; -------------------------------------------------------------------------------- ; @Title: DRA7xx On-Chip Peripherals ; @Props: Released ; @Author: KAM, JON ; @Changelog: 2013-06-27 KAM ; 2022-05-13 JON ; @Manufacturer: TI - Texas Instruments ; @Doc: XML generated (TIXML2PER 2.1.2), based on: DRA7xx.xml (Ver. 1.0) ; @Core: Cortex-M4 ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perdra7xxipu.per 17736 2024-04-08 09:26:07Z kwisniewski $ ; ; WARNING: EXPORT NOTICE ; ; Recipient agrees to not knowingly export or re-export, directly or ; indirectly, any product or technical data (as defined by the U.S., EU, and ; other Export Administration Regulations) including software, or any ; controlled product restricted by other applicable national regulations, ; received from Disclosing party under this Agreement, or any direct ; product of such technology, to any destination to which such export or ; re-export is restricted or prohibited by U.S. or other applicable laws, ; without obtaining prior authorisation from U.S. Department of Commerce ; and other competent Government authorities to the extent required by ; those laws. This provision shall survive termination or expiration of this ; Agreement. ; ; According to our best knowledge of the state and end-use of this ; product or technology, and in compliance with the export control ; regulations of dual-use goods in force in the origin and exporting ; countries, this technology is classified as follows: ; ; US ECCN: 3E991 ; EU ECCN: EAR99 ; ; And may require export or re-export license for shipping it in compliance ; with the applicable regulations of certain countries. ; tree.close "Core Registers (Cortex-M4)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end config 16. 8. AUTOINDENT.ON center tree tree.open "_32_kHz_Synchronized_Timer" tree "L4_WKUP_COUNTER_32K" base ad:0x4AE04000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION,This register contains the sync counter IP revision code" group.long 0x10++0x03 line.long 0x00 "SYSCONFIG,This register is used for idle modes only" hexmask.long 0x00 5.--31. 1. "Reserved,Reads return 0" bitfld.long 0x00 3.--4. "IDLEMODE,Power management REQ/ACK control" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 1.--2. "Reserved,Reads return 0" "0,1,2,3" bitfld.long 0x00 0. "SYNCMODE,Synchronization scheme - 0x0 Gray synchronization scheme" "0,1" rgroup.long 0x30++0x03 line.long 0x00 "CR,This register contains the 32-kHz sync counter value" tree.end tree.end tree.open "ATL" tree "ATL" base ad:0x4843C000 rgroup.long 0x00++0x03 line.long 0x00 "ATL_REVID,ATL IP revision" group.long 0x200++0x0B line.long 0x00 "ATL_PPMR0,Parts per million register for the first ATL instance" bitfld.long 0x00 15. "PPM_SLOWDOWN,Part-Per-Million Slowdown" "PPM_SLOWDOWN_0,PPM_SLOWDOWN_1" hexmask.long.word 0x00 0.--8. 1. "PPM_SETTING,PPM_SETTING PPM adjustment = PPMR[8:0] / 2" line.long 0x04 "ATL_BBSR0,Baseband sample register for the first ATL instance" hexmask.long.word 0x04 0.--15. 1. "SAMPLE_COUNT,The measuring circuit produces a 16- bit Sample Count that is stored in the BBSR register" line.long 0x08 "ATL_ATLCR0,ATL configuration register for first ATL instance" bitfld.long 0x08 0.--4. "ATL_INTERNAL_DIVIDER,ATL Internal Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x0F line.long 0x00 "ATL_SWEN0,Software enable bit for the first ATL instance" bitfld.long 0x00 0. "SWEN,Software enable bit" "SWEN_0,SWEN_1" line.long 0x04 "ATL_BWSMUX0,Select source for BWS input to first ATL instance" bitfld.long 0x04 0.--3. "BWSMUX,Baseband Word Select Mux" "BWSMUX_0,BWSMUX_1,BWSMUX_2,BWSMUX_3,BWSMUX_4,BWSMUX_5,BWSMUX_6,BWSMUX_7,BWSMUX_8,BWSMUX_9,BWSMUX_10,BWSMUX_11,BWSMUX_12,BWSMUX_13,BWSMUX_14,BWSMUX_15" line.long 0x08 "ATL_AWSMUX0,Select source for AWS input to the first ATL instance" bitfld.long 0x08 0.--3. "AWSMUX,Audio Word Select Mux" "AWSMUX_0,AWSMUX_1,AWSMUX_2,AWSMUX_3,AWSMUX_4,AWSMUX_5,AWSMUX_6,AWSMUX_7,AWSMUX_8,AWSMUX_9,AWSMUX_10,AWSMUX_11,AWSMUX_12,AWSMUX_13,AWSMUX_14,AWSMUX_15" line.long 0x0C "ATL_PCLKMUX0,Select source for ATLPCLK input to the first ATL instance" bitfld.long 0x0C 0. "PCLKMUX,ATLPCLK Selection Register Mux" "PCLKMUX_0,PCLKMUX_1" group.long 0x280++0x0B line.long 0x00 "ATL_PPMR1,Parts per million register for the second ATL instance" bitfld.long 0x00 15. "PPM_SLOWDOWN,Part-Per-Million Slowdown" "PPM_SLOWDOWN_0,PPM_SLOWDOWN_1" hexmask.long.word 0x00 0.--8. 1. "PPM_SETTING,PPM_SETTING PPM adjustment = PPMR[8:0] / 2" line.long 0x04 "ATL_BBSR1,Baseband sample register for the second ATL instance" hexmask.long.word 0x04 0.--15. 1. "SAMPLE_COUNT,The measuring circuit produces a 16- bit Sample Count that is stored in the BBSR register" line.long 0x08 "ATL_ATLCR1,ATL configuration register for the second ATL instance" bitfld.long 0x08 0.--4. "ATL_INTERNAL_DIVIDER,ATL Internal Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x290++0x0F line.long 0x00 "ATL_SWEN1,Software enable bit for the second ATL instance" bitfld.long 0x00 0. "SWEN,Software enable bit" "SWEN_0,SWEN_1" line.long 0x04 "ATL_BWSMUX1,Select source for BWS input to the second ATL instance" bitfld.long 0x04 0.--3. "BWSMUX,Baseband Word Select Mux" "BWSMUX_0,BWSMUX_1,BWSMUX_2,BWSMUX_3,BWSMUX_4,BWSMUX_5,BWSMUX_6,BWSMUX_7,BWSMUX_8,BWSMUX_9,BWSMUX_10,BWSMUX_11,BWSMUX_12,BWSMUX_13,BWSMUX_14,BWSMUX_15" line.long 0x08 "ATL_AWSMUX1,Select source for AWS input to the second ATL instance" bitfld.long 0x08 0.--3. "AWSMUX,Audio Word Select Mux" "AWSMUX_0,AWSMUX_1,AWSMUX_2,AWSMUX_3,AWSMUX_4,AWSMUX_5,AWSMUX_6,AWSMUX_7,AWSMUX_8,AWSMUX_9,AWSMUX_10,AWSMUX_11,AWSMUX_12,AWSMUX_13,AWSMUX_14,AWSMUX_15" line.long 0x0C "ATL_PCLKMUX1,Select source for ATLPCLK input to the second ATL instance" bitfld.long 0x0C 0. "PCLKMUX,ATLPCLK Selection Register Mux" "PCLKMUX_0,PCLKMUX_1" group.long 0x300++0x0B line.long 0x00 "ATL_PPMR2,Parts per million register for the third ATL instance" bitfld.long 0x00 15. "PPM_SLOWDOWN,Part-Per-Million Slowdown" "PPM_SLOWDOWN_0,PPM_SLOWDOWN_1" hexmask.long.word 0x00 0.--8. 1. "PPM_SETTING,PPM_SETTING PPM adjustment = PPMR[8:0] / 2" line.long 0x04 "ATL_BBSR2,Baseband sample register for third ATL instance" hexmask.long.word 0x04 0.--15. 1. "SAMPLE_COUNT,The measuring circuit produces a 16- bit Sample Count that is stored in the BBSR register" line.long 0x08 "ATL_ATLCR2,ATL configuration register for the third ATL instance" bitfld.long 0x08 0.--4. "ATL_INTERNAL_DIVIDER,ATL Internal Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x0F line.long 0x00 "ATL_SWEN2,Software enable bit for the third ATL instance" bitfld.long 0x00 0. "SWEN,Software enable bit" "SWEN_0,SWEN_1" line.long 0x04 "ATL_BWSMUX2,Select source for BWS input to to the third ATL instance" bitfld.long 0x04 0.--3. "BWSMUX,Baseband Word Select Mux" "BWSMUX_0,BWSMUX_1,BWSMUX_2,BWSMUX_3,BWSMUX_4,BWSMUX_5,BWSMUX_6,BWSMUX_7,BWSMUX_8,BWSMUX_9,BWSMUX_10,BWSMUX_11,BWSMUX_12,BWSMUX_13,BWSMUX_14,BWSMUX_15" line.long 0x08 "ATL_AWSMUX2,Select source for AWS input to the third ATL instance" bitfld.long 0x08 0.--3. "AWSMUX,Audio Word Select Mux" "AWSMUX_0,AWSMUX_1,AWSMUX_2,AWSMUX_3,AWSMUX_4,AWSMUX_5,AWSMUX_6,AWSMUX_7,AWSMUX_8,AWSMUX_9,AWSMUX_10,AWSMUX_11,AWSMUX_12,AWSMUX_13,AWSMUX_14,AWSMUX_15" line.long 0x0C "ATL_PCLKMUX2,Select source for ATLPCLK input to the third ATL instance" bitfld.long 0x0C 0. "PCLKMUX,ATLPCLK Selection Register Mux" "PCLKMUX_0,PCLKMUX_1" group.long 0x380++0x0B line.long 0x00 "ATL_PPMR3,Parts per million register fourth ATL instance" bitfld.long 0x00 15. "PPM_SLOWDOWN,Part-Per-Million Slowdown" "PPM_SLOWDOWN_0,PPM_SLOWDOWN_1" hexmask.long.word 0x00 0.--8. 1. "PPM_SETTING,PPM_SETTING PPM adjustment = PPMR[8:0] / 2" line.long 0x04 "ATL_BBSR3,Baseband sample register fourth ATL instance" hexmask.long.word 0x04 0.--15. 1. "SAMPLE_COUNT,The measuring circuit produces a 16- bit Sample Count that is stored in the BBSR register" line.long 0x08 "ATL_ATLCR3,ATL configuration register fourth ATL instance" bitfld.long 0x08 0.--4. "ATL_INTERNAL_DIVIDER,ATL Internal Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x390++0x0F line.long 0x00 "ATL_SWEN3,Software enable bit for fourth ATL instance" bitfld.long 0x00 0. "SWEN,Software enable bit" "SWEN_0,SWEN_1" line.long 0x04 "ATL_BWSMUX3,Select source for BWS input to fourth instance ATL" bitfld.long 0x04 0.--3. "BWSMUX,Baseband Word Select Mux" "BWSMUX_0,BWSMUX_1,BWSMUX_2,BWSMUX_3,BWSMUX_4,BWSMUX_5,BWSMUX_6,BWSMUX_7,BWSMUX_8,BWSMUX_9,BWSMUX_10,BWSMUX_11,BWSMUX_12,BWSMUX_13,BWSMUX_14,BWSMUX_15" line.long 0x08 "ATL_AWSMUX3,Select source for AWS input to fourth instance ATL" bitfld.long 0x08 0.--3. "AWSMUX,Audio Word Select Mux" "AWSMUX_0,AWSMUX_1,AWSMUX_2,AWSMUX_3,AWSMUX_4,AWSMUX_5,AWSMUX_6,AWSMUX_7,AWSMUX_8,AWSMUX_9,AWSMUX_10,AWSMUX_11,AWSMUX_12,AWSMUX_13,AWSMUX_14,AWSMUX_15" line.long 0x0C "ATL_PCLKMUX3,Select source for ATLPCLK input to fourth instance ATL" bitfld.long 0x0C 0. "PCLKMUX,ATLPCLK Selection Register Mux" "PCLKMUX_0,PCLKMUX_1" tree.end tree.end tree.open "BB2D_Overview" tree "BB2D" base ad:0x59000000 group.long 0x00++0x37 line.long 0x00 "AQHICLOCKCONTROL,Clock control register" bitfld.long 0x00 24.--27. "MULTI_PIPE_USE_SINGLE_AXI,Force all the transactions to go to one AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "MULTI_PIPE_REG_SELECT,Determines which HI/MC to use while reading registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "ISOLATE_GPU,Isolate GPU bit" "0,1" rbitfld.long 0x00 18. "IDLE_VG,VG pipe is idle" "0,1" newline rbitfld.long 0x00 17. "IDLE2_D,2D pipe is idle" "0,1" rbitfld.long 0x00 16. "IDLE3_D,3D pipe is idle" "0,1" newline bitfld.long 0x00 12. "SOFT_RESET,Soft resets the subsystem" "0,1" bitfld.long 0x00 11. "DISABLE_DEBUG_REGISTERS,Disable debug registers" "0,1" newline bitfld.long 0x00 10. "DISABLE_RAM_CLOCK_GATING,Disables clock gating for RAMs" "0,1" bitfld.long 0x00 9. "FSCALE_CMD_LOAD," "0,1" newline hexmask.long.byte 0x00 2.--8. 1. "FSCALE_VAL," bitfld.long 0x00 1. "CLK2D_DIS,Disable 2D clock" "0,1" newline bitfld.long 0x00 0. "CLK3D_DIS,Disable 3D clock" "0,1" line.long 0x04 "AQHIIDLE,Idle status register" bitfld.long 0x04 31. "AXI_LP,AXI is in low power mode" "0,1" bitfld.long 0x04 11. "IDLE_TS,TS is idle" "0,1" newline bitfld.long 0x04 10. "IDLE_FP,FP is idle" "0,1" bitfld.long 0x04 9. "IDLE_IM,IM is idle" "0,1" newline bitfld.long 0x04 8. "IDLE_VG,VG is idle" "0,1" bitfld.long 0x04 7. "IDLE_TX,TX is idle" "0,1" newline bitfld.long 0x04 6. "IDLE_RA,RA is idle" "0,1" bitfld.long 0x04 5. "IDLE_SE,SE is idle" "0,1" newline bitfld.long 0x04 4. "IDLE_PA,PA is idle" "0,1" bitfld.long 0x04 3. "IDLE_SH,SH is idle" "0,1" newline bitfld.long 0x04 2. "IDLE_PE,PE is idle" "0,1" bitfld.long 0x04 1. "IDLE_DE,DE is idle" "0,1" newline bitfld.long 0x04 0. "IDLE_FE,FE is idle" "0,1" line.long 0x08 "AQAXICONFIG,AXI config" bitfld.long 0x08 12.--15. "ARCACHE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. "AWCACHE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 4.--7. "ARID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "AWID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "AQAXISTATUS,AXI status" bitfld.long 0x0C 9. "DET_RD_ERR," "0,1" bitfld.long 0x0C 8. "DET_WR_ERR," "0,1" newline bitfld.long 0x0C 4.--7. "RD_ERR_ID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "WR_ERR_ID," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "AQINTRACKNOWLEDGE,Interrupt acknowledge register" line.long 0x14 "AQINTRENBL,Interrupt enable register" line.long 0x18 "AQIDENT,Identification register" hexmask.long.byte 0x18 24.--31. 1. "FAMILY,Family value" hexmask.long.byte 0x18 16.--23. 1. "PRODUCT,Product value" newline bitfld.long 0x18 12.--15. "REVISION,Revision value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 8.--11. "TECHNOLOGY,Technology value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x18 0.--7. 1. "CUSTOMER,Customer value" line.long 0x1C "GCFEATURES,Shows which features are enabled in current subsystem implementation" bitfld.long 0x1C 31. "FE20_BIT_INDEX,Supports 20 bit index" "0,1" bitfld.long 0x1C 30. "RS_YUV_TARGET,Supports resolveing into YUV target" "0,1" newline bitfld.long 0x1C 29. "BYTE_WRITE_3D,3D PE has byte write capability" "0,1" bitfld.long 0x1C 28. "FE20,FE 2.0 is present" "0,1" newline bitfld.long 0x1C 27. "VGTS,VG tesselator is present" "0,1" bitfld.long 0x1C 26. "PIPE_VG,VG pipe is present" "0,1" newline bitfld.long 0x1C 25. "MEM32_BIT_SUPPORT,32 bit memory address support" "0,1" bitfld.long 0x1C 24. "YUY2_RENDER_TARGET,YUY2 support in PE and YUY2 to RGB conversion in resolve" "0,1" newline bitfld.long 0x1C 23. "HALF_TX_CACHE,TX cache is half" "0,1" bitfld.long 0x1C 22. "HALF_PE_CACHE,PE cache is half" "0,1" newline bitfld.long 0x1C 21. "YUY2_AVERAGING,YUY2 averaging support in resolve" "0,1" bitfld.long 0x1C 20. "NO_SCALER,No 2D scaler" "0,1" newline bitfld.long 0x1C 19. "BYTE_WRITE_2D,Supports byte write in 2D" "0,1" bitfld.long 0x1C 18. "BUFFER_INTERLEAVING,Supports interleaving depth and color buffers" "0,1" newline bitfld.long 0x1C 17. "NO422_TEXTURE,No 422 texture input format" "0,1" bitfld.long 0x1C 16. "NO_EZ,No early-Z" "0,1" newline bitfld.long 0x1C 15. "MIN_AREA,Configured to have minimum area" "0,1" bitfld.long 0x1C 14. "MODULE_CG,Second level clock gating is available" "0,1" newline bitfld.long 0x1C 13. "YUV420_TILER,YUV 4:2:0 tiler is available" "0,1" bitfld.long 0x1C 12. "HIGH_DYNAMIC_RANGE,Shows if there is HDR support" "0,1" newline bitfld.long 0x1C 11. "FAST_SCALER,Shows if there is HD scaler" "0,1" bitfld.long 0x1C 10. "ETC1_TEXTURE_COMPRESSION,ETC1 texture compression" "0,1" newline bitfld.long 0x1C 9. "PIPE_2D,Shows if there is 2D engine" "0,1" bitfld.long 0x1C 8. "DC,Shows if there is a display controller" "0,1" newline bitfld.long 0x1C 7. "MSAA,MSAA support" "0,1" bitfld.long 0x1C 6. "YUV420_FILTER,YUV 4:2:0 support in filter blit" "0,1" newline bitfld.long 0x1C 5. "ZCOMPRESSION,Depth and color compression" "0,1" bitfld.long 0x1C 4. "DEBUG_MODE,Debug registers" "0,1" newline bitfld.long 0x1C 3. "DXT_TEXTURE_COMPRESSION,DXT texture compression" "0,1" bitfld.long 0x1C 2. "PIPE_3D,3D pipe" "0,1" newline bitfld.long 0x1C 1. "SPECIAL_ANTI_ALIASING,Full-screen anti-aliasing" "0,1" bitfld.long 0x1C 0. "FAST_CLEAR,Fast clear" "0,1" line.long 0x20 "GCCHIPID,Shows the ID for the subsystem in BCD" line.long 0x24 "GCCHIPREV,Shows the revision for the subsystem in BCD" line.long 0x28 "GCCHIPDATE,Shows the release date for the subsystem" line.long 0x2C "GCCHIPTIME,Shows the release time for the subsystem" line.long 0x30 "GCCHIPCUSTOMER,Shows the customer and group for the subsystem" hexmask.long.word 0x30 16.--31. 1. "COMPANY,Company" hexmask.long.word 0x30 0.--15. 1. "GROUP,Group" line.long 0x34 "GCMINORFEATURES0,Shows which minor features are enabled in the subsytem" bitfld.long 0x34 31. "ENHANCE_VR,Enhance VR and add a mode to walk 16 pixels in 16-bit mode in vertical pass to improve cache hit rate when rotating 90/270" "0,1" bitfld.long 0x34 30. "CORRECT_STENCIL,Correct stencil behavior in depth only" "0,1" newline bitfld.long 0x34 29. "A8_TARGET_SUPPORT,2D engine supports A8 target" "0,1" bitfld.long 0x34 28. "NEW_TEXTURE,New texture unit is available" "0,1" newline bitfld.long 0x34 27. "HIERARCHICAL_Z,Hierarchiccal Z is supported" "0,1" bitfld.long 0x34 26. "BYPASS_IN_MSAA,Shader supports bypass mode when MSAA is enabled" "0,1" newline bitfld.long 0x34 25. "VAA,VAA is available or not" "0,1" bitfld.long 0x34 24. "BUG_FIXES0," "0,1" newline bitfld.long 0x34 23. "SHADER_MSAA_SIDEBAND,Put the MSAA data into sideband fifo" "0,1" bitfld.long 0x34 22. "MC_20,New style MC with separate paths for color and depth" "0,1" newline bitfld.long 0x34 21. "DEFAULT_REG0,Unavailable registers will return 0" "0,1" bitfld.long 0x34 20. "EXTRA_SHADER_INSTRUCTIONS1,Sqrt sin cos instructions are available" "0,1" newline bitfld.long 0x34 19. "SHADER_GETS_W,W is sent to SH from RA" "0,1" bitfld.long 0x34 18. "VG_21,Minor updates to VG pipe (Event generation from VG TS PE)" "0,1" newline bitfld.long 0x34 17. "VG_FILTER,VG filter is available" "0,1" bitfld.long 0x34 16. "EXTRA_SHADER_INSTRUCTIONS0,Floor ceil and sign instructions are available" "0,1" newline bitfld.long 0x34 15. "COMPRESSION_FIFO_FIXED,If this bit is not set the FIFO counter should be set to 50" "0,1" bitfld.long 0x34 14. "TS_EXTENDED_COMMANDS,New commands added to the tessellator" "0,1" newline bitfld.long 0x34 13. "VG_20,Major updates to VG pipe (TS buffer tiling. State masking.)" "0,1" bitfld.long 0x34 12. "SUPER_TILED_32X32,32 x 32 super tile is available" "0,1" newline bitfld.long 0x34 11. "SEPARATE_TILE_STATUS_WHEN_INTERLEAVED,Use 2 separate tile status buffers in interleaved mode" "0,1" bitfld.long 0x34 10. "TILE_STATUS_2BITS,2 bits are used instead of 4 bits for tile status" "0,1" newline bitfld.long 0x34 9. "RENDER_8K,Supports 8K render target" "0,1" bitfld.long 0x34 8. "CORRECT_AUTO_DISABLE,Reserved" "0,1" newline bitfld.long 0x34 7. "PE20_2D,2D PE 2.0 is present" "0,1" bitfld.long 0x34 6. "FAST_CLEAR_FLUSH,Proper flush is done in fast clear cache" "0,1" newline bitfld.long 0x34 5. "SPECIAL_MSAA_LOD,Special LOD calculation when MSAA is on" "0,1" bitfld.long 0x34 4. "CORRECT_TEXTURE_CONVERTER,Driver hack is not needed" "0,1" newline bitfld.long 0x34 3. "TEXTURE8_K,Supports 8K x 8K textures" "0,1" bitfld.long 0x34 2. "ENDIANNESS_CONFIG,Configurable endianness support" "0,1" newline bitfld.long 0x34 1. "DUAL_RETURN_BUS,Dual Return Bus from HI to clients" "0,1" bitfld.long 0x34 0. "FLIP_Y,Y flipping capability is added to resolve" "0,1" group.long 0x3C++0x2B line.long 0x00 "GCRESETMEMCOUNTERS,Writing 1 will reset the counters and stop counting" bitfld.long 0x00 0. "RESET," "0,1" line.long 0x04 "GCTOTALREADS,Total reads in terms of 64 bits" line.long 0x08 "GCTOTALWRITES,Total writes in terms of 64 bits" line.long 0x0C "GCCHIPSPECS,Specs for the subsystem" bitfld.long 0x0C 28.--31. "VERTEX_OUTPUT_BUFFER_SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 25.--27. "NUM_PIXEL_PIPES," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--24. "NUM_SHADER_CORES," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 12.--16. "VERTEX_CACHE_SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 8.--11. "THREAD_COUNT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 4.--7. "TEMP_REGISTERS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "STREAMS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "GCTOTALWRITEBURSTS,Total write data count in terms of 64 bits" line.long 0x14 "GCTOTALWRITEREQS,Total write request count" line.long 0x18 "GCTOTALWRITELASTS,Total WLAST count" line.long 0x1C "GCTOTALREADBURSTS,Total read data count in terms of 64 bits" line.long 0x20 "GCTOTALREADREQS,Total read request count" line.long 0x24 "GCTOTALREADLASTS,Total RLAST count" line.long 0x28 "GCGPOUT0,General purpose output register" bitfld.long 0x28 0. "GCHOLD," "0,1" group.long 0x70++0x17 line.long 0x00 "GCAXICONTROL,Special handling on AXI Bus" bitfld.long 0x00 0. "WR_FULL_BURST_MODE," "0,1" line.long 0x04 "GCMINORFEATURES1,Shows which features are enabled in the subsystem" bitfld.long 0x04 31. "FC_FLUSH_STALL," "0,1" bitfld.long 0x04 30. "BUG_FIXES6," "0,1" newline bitfld.long 0x04 29. "WIDE_LINE," "0,1" bitfld.long 0x04 28. "MMU," "0,1" newline bitfld.long 0x04 27. "OK_TO_GATE_AXI_CLOCK," "0,1" bitfld.long 0x04 26. "RESOLVE_OFFSET," "0,1" newline bitfld.long 0x04 25. "NEGATIVE_LOG_FIX," "0,1" bitfld.long 0x04 24. "CORRECT_OVERFLOW_VG," "0,1" newline bitfld.long 0x04 23. "HALTI0," "0,1" bitfld.long 0x04 22. "LINEAR_TEXTURE_SUPPORT," "0,1" newline bitfld.long 0x04 21. "NON_POWER_OF_TWO," "0,1" bitfld.long 0x04 20. "TEXTURE_HORIZONTAL_ALIGNMENT_SELECT," "0,1" newline bitfld.long 0x04 19. "NEW_FLOATING_POINT_ARITHMETIC," "0,1" bitfld.long 0x04 18. "NEW_2D," "0,1" newline bitfld.long 0x04 17. "BUG_FIXES5," "0,1" bitfld.long 0x04 16. "DITHER_AND_FILTER_PLUS_ALPHA_2D,Dither and filter+alpha available" "0,1" newline bitfld.long 0x04 15. "CORRECT_MIN_MAX_DEPTH,EEZ and HZ are correct" "0,1" bitfld.long 0x04 14. "EXTENDED_PIXEL_FORMAT," "0,1" newline bitfld.long 0x04 13. "TWO_STENCIL_REFERENCE," "0,1" bitfld.long 0x04 12. "PIXEL_DITHER," "0,1" newline bitfld.long 0x04 11. "HALF_FLOAT_PIPE," "0,1" bitfld.long 0x04 10. "L2_WINDOWING," "0,1" newline bitfld.long 0x04 9. "BUG_FIXES4," "0,1" bitfld.long 0x04 8. "AUTO_RESTART_TS," "0,1" newline bitfld.long 0x04 7. "CORRECT_AUTO_DISABLE," "0,1" bitfld.long 0x04 6. "BUG_FIXES3," "0,1" newline bitfld.long 0x04 5. "TEXTURE_STRIDE,Texture has stride and memory addressing" "0,1" bitfld.long 0x04 4. "BUG_FIXES2," "0,1" newline bitfld.long 0x04 3. "BUG_FIXES1," "0,1" bitfld.long 0x04 2. "VG_DOUBLE_BUFFER,Double buffering support for VG (second TS-->VG semaphore is present)" "0,1" newline bitfld.long 0x04 1. "V2_COMPRESSION,V2 compression" "0,1" bitfld.long 0x04 0. "RSUV_SWIZZLE,Resolve UV swizzle" "0,1" line.long 0x08 "GCTOTALCYCLES,Total cycles" line.long 0x0C "GCTOTALIDLECYCLES,Total cycles where the GPU is idle" line.long 0x10 "GCCHIPSPECS2,Specs for the subsystem" hexmask.long.word 0x10 16.--31. 1. "NUMBER_OF_CONSTANTS," hexmask.long.byte 0x10 8.--15. 1. "INSTRUCTION_COUNT," newline hexmask.long.byte 0x10 0.--7. 1. "BUFFER_SIZE," line.long 0x14 "GCMINORFEATURES2,Shows which features are enabled in the subsystem" bitfld.long 0x14 28. "NO_INDEX_PATTERN," "0,1" bitfld.long 0x14 26. "NOT_USED," "0,1" newline bitfld.long 0x14 25. "MIXED_STREAMS," "0,1" bitfld.long 0x14 24. "INTERLEAVER," "0,1" newline bitfld.long 0x14 23. "FLUSH_FIXED_2D," "0,1" bitfld.long 0x14 22. "YUV_CONVERSION," "0,1" newline bitfld.long 0x14 21. "MULTI_SOURCE_BLT," "0,1" bitfld.long 0x14 20. "YUV_STANDARD," "0,1" newline bitfld.long 0x14 19. "TILE_FILLER," "0,1" bitfld.long 0x14 18. "THREAD_WALKER_IN_PS," "0,1" newline bitfld.long 0x14 17. "ONE_PASS_2D_FILTER," "0,1" bitfld.long 0x14 16. "FULL_DIRECT_FB," "0,1" newline bitfld.long 0x14 15. "TX_FILTER," "0,1" bitfld.long 0x14 14. "DYNAMIC_FREQUENCY_SCALING," "0,1" newline bitfld.long 0x14 13. "TX_YUV_ASSEMBLER," "0,1" bitfld.long 0x14 12. "RGB888," "0,1" newline bitfld.long 0x14 11. "HALTI1," "0,1" bitfld.long 0x14 10. "S1S8," "0,1" newline bitfld.long 0x14 9. "END_EVENT," "0,1" bitfld.long 0x14 8. "PE_SWIZZLE," "0,1" newline bitfld.long 0x14 7. "CORRECT_AUTO_DISABLE_COUNT_WIDTH," "0,1" bitfld.long 0x14 6. "COMPOSITION," "0,1" newline bitfld.long 0x14 5. "RECT_PRIMITIVE," "0,1" bitfld.long 0x14 4. "LINEAR_PE," "0,1" newline bitfld.long 0x14 3. "SUPER_TILED_TEXTURE," "0,1" bitfld.long 0x14 2. "SEAMLESS_CUBE_MAP," "0,1" newline bitfld.long 0x14 1. "LOGIC_OP," "0,1" bitfld.long 0x14 0. "LINE_LOOP," "0,1" group.long 0x100++0x0B line.long 0x00 "GCMODULEPOWERCONTROLS,Control register for module level power controls" hexmask.long.word 0x00 16.--31. 1. "TURN_OFF_COUNTER,Counter value for clock gating the module if the module is idle for this amount of clock cycles" bitfld.long 0x00 4.--7. "TURN_ON_COUNTER,Number of clock cycles to wait after turning on the clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. "DISABLE_STARVE_MODULE_CLOCK_GATING,Disables module level clock gating for starve/idle condition" "0,1" bitfld.long 0x00 1. "DISABLE_STALL_MODULE_CLOCK_GATING,Disables module level clock gating for stall condition" "0,1" newline bitfld.long 0x00 0. "ENABLE_MODULE_CLOCK_GATING,Enables module level clock gating" "0,1" line.long 0x04 "GCMODULEPOWERMODULECONTROL,Module level control registers" bitfld.long 0x04 7. "DISABLE_MODULE_CLOCK_GATING_TX,Disables module level clock gating for starve/idle condition" "0,1" bitfld.long 0x04 6. "DISABLE_MODULE_CLOCK_GATING_RA,Disables module level clock gating for stall condition" "0,1" newline bitfld.long 0x04 5. "DISABLE_MODULE_CLOCK_GATING_SE,Enables module level clock gating" "0,1" bitfld.long 0x04 4. "DISABLE_MODULE_CLOCK_GATING_PA,Counter value for clock gating the module if the module is idle for this amount of clock cycles" "0,1" newline bitfld.long 0x04 3. "DISABLE_MODULE_CLOCK_GATING_SH,Number of clock cycles to wait after turning on the clock" "0,1" bitfld.long 0x04 2. "DISABLE_MODULE_CLOCK_GATING_PE,Disables module level clock gating for starve/idle condition" "0,1" newline bitfld.long 0x04 1. "DISABLE_MODULE_CLOCK_GATING_DE,Disables module level clock gating for stall condition" "0,1" bitfld.long 0x04 0. "DISABLE_MODULE_CLOCK_GATING_FE,Enables module level clock gating" "0,1" line.long 0x08 "GCMODULEPOWERMODULESTATUS,Module level control status" bitfld.long 0x08 7. "MODULE_CLOCK_GATED_TX,Module level clock gating is ON for TX" "0,1" bitfld.long 0x08 6. "MODULE_CLOCK_GATED_RA,Module level clock gating is ON for RA" "0,1" newline bitfld.long 0x08 5. "MODULE_CLOCK_GATED_SE,Module level clock gating is ON for SE" "0,1" bitfld.long 0x08 4. "MODULE_CLOCK_GATED_PA,Module level clock gating is ON for PA" "0,1" newline bitfld.long 0x08 3. "MODULE_CLOCK_GATED_SH,Module level clock gating is ON for SH" "0,1" bitfld.long 0x08 2. "MODULE_CLOCK_GATED_PE,Module level clock gating is ON for PE" "0,1" newline bitfld.long 0x08 1. "MODULE_CLOCK_GATED_DE,Module level clock gating is ON for DE" "0,1" bitfld.long 0x08 0. "MODULE_CLOCK_GATED_FE,Module level clock gating is ON for FE" "0,1" rgroup.long 0x188++0x07 line.long 0x00 "GCREGMMUSTATUS,Status register that holds which MMU generated an exception" bitfld.long 0x00 12.--13. "EXCEPTION3,MMU 3 caused an exception and theGCREGMMUEXCEPTION3 register holds the offending address" "0,1,2,3" bitfld.long 0x00 8.--9. "EXCEPTION2,MMU 2 caused an exception and theGCREGMMUEXCEPTION2 register holds the offending address" "0,1,2,3" newline bitfld.long 0x00 4.--5. "EXCEPTION1,MMU 1 caused an exception and theGCREGMMUEXCEPTION1 register holds the offending address" "0,1,2,3" bitfld.long 0x00 0.--1. "EXCEPTION0,MMU 0 caused an exception and theGCREGMMUEXCEPTION0 holds the offending address" "0,1,2,3" line.long 0x04 "GCREGMMUCONTROL,Control register that enables the MMU (one time shot)" bitfld.long 0x04 0. "ENABLE,Enable the MMU" "0,1" group.long 0x414++0x03 line.long 0x00 "AQMEMORYDEBUG," bitfld.long 0x00 30. "DONT_STALL_WRITES_TO_SAME_ADDRESS," "0,1" bitfld.long 0x00 24.--29. "ZCOMP_LIMIT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. "DISABLE_WRITE_DATA_SPEEDUP," "0,1" bitfld.long 0x00 22. "DISABLE_STALL_READS," "0,1" newline bitfld.long 0x00 19. "LIMIT_CONTROL,Limit control" "0,1" bitfld.long 0x00 17. "INTERLEAVE_BUFFER_LOW_LATENCY_MODE," "0,1" newline bitfld.long 0x00 14. "DISABLE_MINI_MMU_CACHE," "0,1" hexmask.long.byte 0x00 0.--7. 1. "MAX_OUTSTANDING_READS,Limits the total number of outstanding read requests" group.long 0x42C++0x03 line.long 0x00 "AQREGISTERTIMINGCONTROL," bitfld.long 0x00 22. "LIGHT_SLEEP,Light sleep" "0,1" bitfld.long 0x00 21. "DEEP_SLEEP,Deep sleep" "0,1" newline bitfld.long 0x00 20. "POWER_DOWN,Powerdown memory" "0,1" bitfld.long 0x00 18.--19. "FAST_WTC,WTC for fast RAMs" "0,1,2,3" newline bitfld.long 0x00 16.--17. "FAST_RTC,RTC for fast RAMs" "0,1,2,3" hexmask.long.byte 0x00 8.--15. 1. "FOR_RF2P," newline hexmask.long.byte 0x00 0.--7. 1. "FOR_RF1P," group.long 0x434++0x63 line.long 0x00 "GCDISPLAYPRIORITY,Controls the priority of the display controller requests" hexmask.long.byte 0x00 8.--15. 1. "HIGH,'Duty cycle'" hexmask.long.byte 0x00 0.--7. 1. "PERIOD,Period" line.long 0x04 "GCDBGCYCLECOUNTER,Increments every cycle" line.long 0x08 "GCOUTSTANDINGREADS0,Number of outstanding reads per client in multiples of 8 bytes" hexmask.long.byte 0x08 24.--31. 1. "MMU,Number of outstanding MMU reads in multiples of 8 bytes" hexmask.long.byte 0x08 16.--23. 1. "FE,Number of outstanding FE reads in multiples of 8 bytes" newline hexmask.long.byte 0x08 8.--15. 1. "PEZ,Number of outstanding PEZ reads in multiples of 8 bytes" hexmask.long.byte 0x08 0.--7. 1. "PEC,Number of outstanding PEC reads in multiples of 8 bytes" line.long 0x0C "GCOUTSTANDINGREADS1,Number of outstanding reads per client in multiples of 8 bytes" hexmask.long.byte 0x0C 24.--31. 1. "TOTAL,This field keeps the value of total read requests or total requested data (in 64 bits) depending on the value ofAQMEMORYDEBUG[19] LIMIT_CONTROL register field" hexmask.long.byte 0x0C 16.--23. 1. "FC,Number of outstanding FC reads in multiples of 8 bytes" newline hexmask.long.byte 0x0C 8.--15. 1. "TX,Number of outstanding TX reads in multiples of 8 bytes" hexmask.long.byte 0x0C 0.--7. 1. "RA,Number of outstanding RA reads in multiples of 8 bytes" line.long 0x10 "GCOUTSTANDINGWRITES,Number of outstanding writes per client" hexmask.long.byte 0x10 24.--31. 1. "TOTAL,This field keeps the value of total write requests or total requested data (in 64 bits) depending on the value ofAQMEMORYDEBUG[19] LIMIT_CONTROL register field" hexmask.long.byte 0x10 16.--23. 1. "FC,Number of outstanding FC writes in multiples of 8 bytes" newline hexmask.long.byte 0x10 8.--15. 1. "PEZ,Number of outstanding PEZ writes in multiples of 8 bytes" hexmask.long.byte 0x10 0.--7. 1. "PEC,Number of outstanding PEC writes in multiples of 8 bytes" line.long 0x14 "GCDEBUGSIGNALSRA,32 bit debug signal from RA" line.long 0x18 "GCDEBUGSIGNALSTX,32 bit debug signal from TX" line.long 0x1C "GCDEBUGSIGNALSFE,32 bit debug signal from FE" line.long 0x20 "GCDEBUGSIGNALSPE,32 bit debug signal from PE" line.long 0x24 "GCDEBUGSIGNALSDE,32 bit debug signal from DE" line.long 0x28 "GCDEBUGSIGNALSSH,32 bit debug signal from SH" line.long 0x2C "GCDEBUGSIGNALSPA,32 bit debug signal from PA" line.long 0x30 "GCDEBUGSIGNALSSE,32 bit debug signal from SE" line.long 0x34 "GCDEBUGSIGNALSMC,32 bit debug signal from MC" line.long 0x38 "GCDEBUGSIGNALSHI,32 bit debug signal from HI" line.long 0x3C "GCDEBUGCONTROL0," bitfld.long 0x3C 24.--27. "SH,Selects which set of 32 bit data to get from SH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 16.--19. "PE,Selects which set of 32 bit data to get from PE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 8.--11. "DE,Selects which set of 32 bit data to get from DE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 0.--3. "FE,Selects which set of 32 bit data to get from FE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "GCDEBUGCONTROL1," bitfld.long 0x40 24.--27. "TX,Selects which set of 32 bit data to get from TX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 16.--19. "RA,Selects which set of 32 bit data to get from RA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x40 8.--11. "SE,Selects which set of 32 bit data to get from SE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 0.--3. "PA,Selects which set of 32 bit data to get from PA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "GCDEBUGCONTROL2," bitfld.long 0x44 8.--11. "HI,Selects which set of 32 bit data to get from HI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x44 0.--3. "MC,Selects which set of 32 bit data to get from MC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x48 "GCDEBUGCONTROL3," bitfld.long 0x48 8.--11. "PROBE1,Selects which module's output will be put in the MSB 32 bits of 64 bit debug signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x48 0.--3. "PROBE0,Selects which module's output will be put in the LSB 32 bits of 64 bit debug signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x4C "GCBUSCONTROL,Shows which features are enabled in the subsystem" bitfld.long 0x4C 8. "FCC,Select the return bus for FCC" "0,1" bitfld.long 0x4C 7. "TX,Select the return bus for TX" "0,1" newline bitfld.long 0x4C 6. "FC,Select the return bus for FC-Depth" "0,1" bitfld.long 0x4C 5. "MMU,Select the return bus for MMU" "0,1" newline bitfld.long 0x4C 3. "FE,Select the return bus for FE" "0,1" bitfld.long 0x4C 1. "PEZ,Select the return bus for PEZ" "0,1" newline bitfld.long 0x4C 0. "PEC,Select the return bus for PEC" "0,1" line.long 0x50 "GCREGENDIANNESS0," line.long 0x54 "GCREGENDIANNESS1," line.long 0x58 "GCREGENDIANNESS2," line.long 0x5C "GCREGDRAWPRIMITIVESTARTTIMESTAMP," line.long 0x60 "GCREGDRAWPRIMITIVEENDTIMESTAMP," group.long 0x558++0x03 line.long 0x00 "GCREGCONTROL0,Composition trigger" bitfld.long 0x00 26.--31. "MISC1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 16.--25. 1. "OUTSTANDING_READS_PER_CHANNEL," newline hexmask.long.word 0x00 4.--15. 1. "MISC0," bitfld.long 0x00 3. "ENABLE_UNALIGNED_WRITE_MERGE," "0,1" newline bitfld.long 0x00 2. "ENABLE_WRITE_MERGE," "0,1" bitfld.long 0x00 1. "ENABLE_UNALIGNED_MERGE," "0,1" newline bitfld.long 0x00 0. "ENABLE_READ_MERGE," "0,1" group.long 0x654++0x0B line.long 0x00 "AQCMDBUFFERADDR,Base address for the command buffer" bitfld.long 0x00 31. "TYPE," "0,1" hexmask.long 0x00 0.--30. 1. "ADDRESS,ADDRESS" line.long 0x04 "AQCMDBUFFERCTRL,Command buffer control" bitfld.long 0x04 20.--21. "ENDIAN_CONTROL,Endian control" "0,1,2,3" bitfld.long 0x04 16. "ENABLE,Command buffer" "0,1" newline hexmask.long.word 0x04 0.--15. 1. "PREFETCH,Number of 64-bit words to fetch from the command buffer" line.long 0x08 "AQFESTATUS,FE status" bitfld.long 0x08 0. "COMMAND_DATA,Status of the command parser" "0,1" rgroup.long 0x664++0x03 line.long 0x00 "AQFEDEBUGCURCMDADR,This is the command decoder address" hexmask.long 0x00 3.--31. 1. "CUR_CMD_ADR," repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x190)++0x03 line.long 0x00 "GCREGMMUEXCEPTION$1,Holds the original address that generated an exception" repeat.end tree.end tree.end tree.open "Control_Module" tree "CTRL_MODULE_CORE" base ad:0x4A002000 rgroup.long 0x134++0x03 line.long 0x00 "CTRL_CORE_STATUS,Control Module Status Register" bitfld.long 0x00 6.--8. "DEVICE_TYPE,Device type captured at reset time" "0,1,2,3,4,5,6,7" rgroup.long 0x148++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_1,Firewall Error Status functional Register 1" bitfld.long 0x00 29. "EVE2_FW_ERROR,EVE2 firewall" "0,1" newline bitfld.long 0x00 28. "EVE1_FW_ERROR,EVE1 firewall" "0,1" newline bitfld.long 0x00 23. "BB2D_FW_ERROR,BB2D firewall" "0,1" newline bitfld.long 0x00 22. "L4_WAKEUP_FW_ERROR,L4 wakeup firewall" "0,1" newline bitfld.long 0x00 18. "DEBUGSS_FW_ERROR,DebugSS firewall" "0,1" newline bitfld.long 0x00 17. "L4_CONFIG_FW_ERROR,L4 config firewall" "0,1" newline bitfld.long 0x00 16. "L4_PERIPH1_FW_ERROR,L4 periph1 firewall" "0,1" newline bitfld.long 0x00 14. "DSS_FW_ERROR,DSS firewall" "0,1" newline bitfld.long 0x00 13. "GPU_FW_ERROR,GPU firewall" "0,1" newline bitfld.long 0x00 6. "IVAHD_SL2_FW_ERROR,IVAHD SL2 firewall" "0,1" newline bitfld.long 0x00 5. "IPU1_FW_ERROR,IPU1 firewall" "0,1" newline bitfld.long 0x00 4. "IVAHD_FW_ERROR,IVAHD firewall" "0,1" newline bitfld.long 0x00 3. "EMIF_FW_ERROR,EMIF firewall" "0,1" newline bitfld.long 0x00 2. "GPMC_FW_ERROR,GPMC firewall" "0,1" newline bitfld.long 0x00 1. "L3RAM1_FW_ERROR,L3RAM1 firewall" "0,1" group.long 0x150++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_1,Firewall Error Status Debug Register 1" bitfld.long 0x00 29. "EVE2_DBGFW_ERROR,EVE2 firewall" "0,1" newline bitfld.long 0x00 28. "EVE1_DBGFW_ERROR,EVE1 firewall" "0,1" newline bitfld.long 0x00 23. "BB2D_DBGFW_ERROR,BB2D firewall" "0,1" newline bitfld.long 0x00 22. "L4_WAKEUP_DBGFW_ERROR,L4 wakeup firewall" "0,1" newline bitfld.long 0x00 18. "DEBUGSS_DBGFW_ERROR,DebugSS firewall" "0,1" newline bitfld.long 0x00 17. "L4_CONFIG_DBGFW_ERROR,L4 config firewall" "0,1" newline bitfld.long 0x00 16. "L4_PERIPH1_DBGFW_ERROR,L4 periph1 firewall" "0,1" newline bitfld.long 0x00 14. "DSS_DBGFW_ERROR,DSS debug firewall" "0,1" newline bitfld.long 0x00 13. "GPU_DBGFW_ERROR,GPU debug firewall" "0,1" newline bitfld.long 0x00 6. "IVAHD_SL2_DBGFW_ERROR,IVAHD SL2 debug firewall" "0,1" newline bitfld.long 0x00 5. "IPU1_DBGFW_ERROR,IPU1 debug firewall" "0,1" newline bitfld.long 0x00 4. "IVAHD_DBGFW_ERROR,IVAHD debug firewall" "0,1" newline bitfld.long 0x00 3. "EMIF_DBGFW_ERROR,EMIF debug firewall" "0,1" newline bitfld.long 0x00 2. "GPMC_DBGFW_ERROR,GPMC debug firewall" "0,1" newline bitfld.long 0x00 1. "L3RAM1_DBGFW_ERROR,L3RAM1 debug firewall" "0,1" group.long 0x15C++0x03 line.long 0x00 "CTRL_CORE_MPU_FORCEWRNP,FORCE WRITE NON POSTED" bitfld.long 0x00 0. "MPU_FORCEWRNP,Force mpu write non posted transactions" "0,1" rgroup.long 0x194++0x5B line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0,Standard Fuse OPP VDD_GPU [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1,Standard Fuse OPP VDD_GPU [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2,Standard Fuse OPP VDD_GPU [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3,Standard Fuse OPP VDD_GPU [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4,Standard Fuse OPP VDD_GPU [159:128]" line.long 0x14 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5,Standard Fuse OPP VDD_GPU [191:160]" line.long 0x18 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0,Standard Fuse OPP VDD_MPU [31:0]" line.long 0x1C "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1,Standard Fuse OPP VDD_MPU [63:32]" line.long 0x20 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2,Standard Fuse OPP VDD_MPU [95:64]" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3,Standard Fuse OPP VDD_MPU [127:96]" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4,Standard Fuse OPP VDD_MPU [159:128]" line.long 0x2C "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5,Standard Fuse OPP VDD_MPU [191:160]" line.long 0x30 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6,Standard Fuse OPP VDD_MPU [223:192]" line.long 0x34 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7,Standard Fuse OPP VDD_MPU [255:224]" line.long 0x38 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0,Standard Fuse OPP VDD_CORE [31:0]" line.long 0x3C "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1,Standard Fuse OPP VDD_CORE [63:32]" line.long 0x40 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2,Standard Fuse OPP VDD_CORE [95:64]" line.long 0x44 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3,Standard Fuse OPP VDD_CORE [127:96]" line.long 0x48 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4,Standard Fuse OPP VDD_CORE [159:128]" line.long 0x4C "CTRL_CORE_STD_FUSE_OPP_BGAP_GPU,Standard Fuse OPP BGAP" line.long 0x50 "CTRL_CORE_STD_FUSE_OPP_BGAP_MPU,Standard Fuse OPP BGAP" line.long 0x54 "CTRL_CORE_STD_FUSE_OPP_BGAP_CORE,Standard Fuse OPP BGAP" line.long 0x58 "CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23,Standard Fuse OPP BGAP" hexmask.long.word 0x58 16.--31. 1. "STD_FUSE_OPP_BGAP_MPU3," newline hexmask.long.word 0x58 0.--15. 1. "STD_FUSE_OPP_BGAP_MPU2," rgroup.long 0x220++0x57 line.long 0x00 "CTRL_CORE_STD_FUSE_MPK_0,Standard Fuse keys" line.long 0x04 "CTRL_CORE_STD_FUSE_MPK_1,Standard Fuse keys" line.long 0x08 "CTRL_CORE_STD_FUSE_MPK_2,Standard Fuse keys" line.long 0x0C "CTRL_CORE_STD_FUSE_MPK_3,Standard Fuse keys" line.long 0x10 "CTRL_CORE_STD_FUSE_MPK_4,Standard Fuse keys" line.long 0x14 "CTRL_CORE_STD_FUSE_MPK_5,Standard Fuse keys" line.long 0x18 "CTRL_CORE_STD_FUSE_MPK_6,Standard Fuse keys" line.long 0x1C "CTRL_CORE_STD_FUSE_MPK_7,Standard Fuse keys" line.long 0x20 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0,Standard Fuse OPP VDD_GPU [31:0]" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1,Standard Fuse OPP VDD_GPU [63:32]" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2,Standard Fuse OPP VDD_GPU [95:64]" line.long 0x2C "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3,Standard Fuse OPP VDD_GPU [127:96]" line.long 0x30 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4,Standard Fuse OPP VDD_GPU [159:128]" line.long 0x34 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5,Standard Fuse OPP VDD_GPU [191:160]" line.long 0x38 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0,Standard Fuse OPP VDD_MPU [31:0]" line.long 0x3C "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1,Standard Fuse OPP VDD_MPU [63:32]" line.long 0x40 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2,Standard Fuse OPP VDD_MPU [95:64]" line.long 0x44 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3,Standard Fuse OPP VDD_MPU [127:96]" line.long 0x48 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4,Standard Fuse OPP VDD_MPU [159:128]" line.long 0x4C "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5,Standard Fuse OPP VDD_MPU [191:160]" line.long 0x50 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6,Standard Fuse OPP VDD_MPU [223:192]" line.long 0x54 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7,Standard Fuse OPP VDD_MPU [255:224]" rgroup.long 0x2BC++0x1B line.long 0x00 "CTRL_CORE_CUST_FUSE_SWRV_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_CUST_FUSE_SWRV_1,Customer Fuse keys" line.long 0x08 "CTRL_CORE_CUST_FUSE_SWRV_2,Customer Fuse keys" line.long 0x0C "CTRL_CORE_CUST_FUSE_SWRV_3,Customer Fuse keys" line.long 0x10 "CTRL_CORE_CUST_FUSE_SWRV_4,Customer Fuse keys" line.long 0x14 "CTRL_CORE_CUST_FUSE_SWRV_5,Customer Fuse keys" line.long 0x18 "CTRL_CORE_CUST_FUSE_SWRV_6,Customer Fuse keys" group.long 0x2E0++0x0F line.long 0x00 "CTRL_CORE_BREG_SELECTION,DPLL selection" bitfld.long 0x00 14. "SEL_DDR,Selection ddr" "0,1" newline bitfld.long 0x00 13. "SEL_GPU,Selection gpu" "0,1" newline bitfld.long 0x00 12. "SEL_GMAC,Selection gmac" "0,1" newline bitfld.long 0x00 11. "SEL_DSP,Selection dsp" "0,1" newline bitfld.long 0x00 10. "SEL_EVE,Selection eve" "0,1" newline bitfld.long 0x00 9. "SEL_USB,Selection usb" "0,1" newline bitfld.long 0x00 8. "SEL_IVA,Selection iva" "0,1" newline bitfld.long 0x00 7. "SEL_PCIE,Selection pcie" "0,1" newline bitfld.long 0x00 6. "SEL_SATA,Selection sata" "0,1" newline bitfld.long 0x00 5. "SEL_PER,Selection per" "0,1" newline bitfld.long 0x00 4. "SEL_HDMI,Selection hdmi" "0,1" newline bitfld.long 0x00 1. "SEL_CORE,Selection core" "0,1" newline bitfld.long 0x00 0. "SEL_IPU,Selection ipu" "0,1" line.long 0x04 "CTRL_CORE_DPLL_BCLK,DPPL obs" bitfld.long 0x04 1. "BRW,Reset" "0,1" newline bitfld.long 0x04 0. "BCLK,clock" "0,1" line.long 0x08 "CTRL_CORE_DPLL_BADDR_BDATAW,DPLL addr and dataw" bitfld.long 0x08 16.--19. "BADDR,baddr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "BDATAW,bdataw" line.long 0x0C "CTRL_CORE_DPLL_BDATAR,DPLL datar" hexmask.long.word 0x0C 0.--15. 1. "BDATAR,datar" rgroup.long 0x32C++0x0B line.long 0x00 "CTRL_CORE_TEMP_SENSOR_MPU,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x00 11. "BGAP_TMPSOFF_MPU,Temperature sensor and thermal shutdown mode" "0,1" newline bitfld.long 0x00 10. "BGAP_EOCZ_MPU,ADC End of Conversion" "0,1" newline hexmask.long.word 0x00 0.--9. 1. "BGAP_DTEMP_MPU,Temperature data from the ADC" line.long 0x04 "CTRL_CORE_TEMP_SENSOR_GPU,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x04 11. "BGAP_TMPSOFF_GPU,Temperature sensor and thermal shutdown mode" "0,1" newline bitfld.long 0x04 10. "BGAP_EOCZ_GPU,ADC End of Conversion" "0,1" newline hexmask.long.word 0x04 0.--9. 1. "BGAP_DTEMP_GPU,Temperature data from the ADC" line.long 0x08 "CTRL_CORE_TEMP_SENSOR_CORE,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x08 11. "BGAP_TMPSOFF_CORE,Temperature sensor and thermal shutdown mode" "0,1" newline bitfld.long 0x08 10. "BGAP_EOCZ_CORE,ADC End of Conversion" "0,1" newline hexmask.long.word 0x08 0.--9. 1. "BGAP_DTEMP_CORE,Temperature data from the ADC" group.long 0x358++0x1F line.long 0x00 "CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR,Cortex M4 register" hexmask.long.tbyte 0x00 0.--19. 1. "CORTEX_M4_MMUADDRTRANSLTR,Used to save the mmu address boot" line.long 0x04 "CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR," hexmask.long.tbyte 0x04 0.--19. 1. "CORTEX_M4_MMUADDRLOGICTR," line.long 0x08 "CTRL_CORE_HWOBS_CONTROL,HW observability control" bitfld.long 0x08 14.--18. "HWOBS_CLKDIV_SEL_2,Clock divider selection on po_hwobs(2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 9.--13. "HWOBS_CLKDIV_SEL_1,Clock divider selection on po_hwobs(1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 3.--7. "HWOBS_CLKDIV_SEL,Clock divider selection on po_hwobs(0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 2. "HWOBS_ALL_ZERO_MODE,Used to gate observable signals" "0,1" newline bitfld.long 0x08 1. "HWOBS_ALL_ONE_MODE,Used to gate observable signals" "0,1" newline bitfld.long 0x08 0. "HWOBS_MACRO_ENABLE,Used to gate observable signals coming from macros using" "0,1" line.long 0x0C "CTRL_CORE_PCS1,pcs1" hexmask.long.word 0x0C 22.--31. 1. "USB_TEST_TXDATA," newline hexmask.long.word 0x0C 12.--21. 1. "USB_ERR_USB_BIT_EN," newline hexmask.long.byte 0x0C 4.--11. 1. "USB_CFG_HOLDOFF," newline bitfld.long 0x0C 0.--3. "USB_DET_DELAY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "CTRL_CORE_PCS2,pcs2" bitfld.long 0x10 27.--31. "USB_CFG_SYNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 23.--26. "USB_CFG_EQ_FUNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 19.--22. "USB_CFG_EQ_HOLD," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 15.--18. "USB_CFG_EQ_INIT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--14. "USB_TEST_OSEL," "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 10.--11. "USB_RC_DELAY," "0,1,2,3" newline bitfld.long 0x10 9. "USB_TEST_LSEL," "0,1" newline bitfld.long 0x10 6.--7. "USB_ERR_USB_MODE," "0,1,2,3" newline bitfld.long 0x10 5. "USB_L1_SLEEP," "0,1" newline bitfld.long 0x10 4. "USB_TEST_MODE," "0,1" newline bitfld.long 0x10 3. "USB_ERR_USB_LN_EN," "0,1" newline bitfld.long 0x10 0. "USB_SHORT_TIMES," "0,1" line.long 0x14 "CTRL_CORE_PCS_REVISION,pcs_revision" bitfld.long 0x14 29.--31. "USB_REVISION," "0,1,2,3,4,5,6,7" line.long 0x18 "CTRL_CORE_PHY_POWER_USB,phy_power_usb" hexmask.long.word 0x18 22.--31. 1. "USB_PWRCTL_CLK_FREQ," newline hexmask.long.byte 0x18 14.--21. 1. "USB_PWRCTL_CLK_CMD,Powers up/down the USB3_PHY_TX and USB3_PHY_RX modules" line.long 0x1C "CTRL_CORE_PHY_POWER_SATA,phy_power_sata" hexmask.long.word 0x1C 22.--31. 1. "SATA_PWRCTL_CLK_FREQ," newline hexmask.long.byte 0x1C 14.--21. 1. "SATA_PWRCTL_CLK_CMD,Powers up/down the SATA_PHY_TX and SATA_PHY_RX modules" group.long 0x380++0x2F line.long 0x00 "CTRL_CORE_BANDGAP_MASK_1,bgap_mask" bitfld.long 0x00 30.--31. "SIDLEMODE,sidlemode for bandgap" "0,1,2,3" newline bitfld.long 0x00 27.--29. "COUNTER_DELAY,Counter delay" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "FREEZE_CORE,Freeze the FIFO CORE" "0,1" newline bitfld.long 0x00 22. "FREEZE_GPU,Freeze the FIFO GPU" "0,1" newline bitfld.long 0x00 21. "FREEZE_MPU,Freeze the FIFO MPU" "0,1" newline bitfld.long 0x00 20. "CLEAR_CORE,Reset the FIFO CORE" "0,1" newline bitfld.long 0x00 19. "CLEAR_GPU,Reset the FIFO GPU" "0,1" newline bitfld.long 0x00 18. "CLEAR_MPU,Reset the FIFO MPU" "0,1" newline bitfld.long 0x00 17. "CLEAR_ACCUM_CORE,Reset the accumulator CORE" "0,1" newline bitfld.long 0x00 16. "CLEAR_ACCUM_GPU,Reset the accumulator GPU" "0,1" newline bitfld.long 0x00 15. "CLEAR_ACCUM_MPU,Reset the accumulator MPU" "0,1" newline bitfld.long 0x00 5. "MASK_HOT_CORE,Mask for hot event CORE" "0,1" newline bitfld.long 0x00 4. "MASK_COLD_CORE,Mask for cold event CORE" "0,1" newline bitfld.long 0x00 3. "MASK_HOT_GPU,Mask for hot event GPU" "0,1" newline bitfld.long 0x00 2. "MASK_COLD_GPU,Mask for cold event GPU" "0,1" newline bitfld.long 0x00 1. "MASK_HOT_MPU,Mask for hot event MPU" "0,1" newline bitfld.long 0x00 0. "MASK_COLD_MPU,Mask for cold event MPU" "0,1" line.long 0x04 "CTRL_CORE_BANDGAP_THRESHOLD_MPU,BGAP THRESHOLD MPU" hexmask.long.word 0x04 16.--25. 1. "THOLD_HOT_MPU,alert value hot" newline hexmask.long.word 0x04 0.--9. 1. "THOLD_COLD_MPU,alert value cold" line.long 0x08 "CTRL_CORE_BANDGAP_THRESHOLD_GPU,BGAP THRESHOLD MM" hexmask.long.word 0x08 16.--25. 1. "THOLD_HOT_GPU,alert value hot" newline hexmask.long.word 0x08 0.--9. 1. "THOLD_COLD_GPU,alert value cold" line.long 0x0C "CTRL_CORE_BANDGAP_THRESHOLD_CORE,BGAP THRESHOLD CORE" hexmask.long.word 0x0C 16.--25. 1. "THOLD_HOT_CORE,alert value hot" newline hexmask.long.word 0x0C 0.--9. 1. "THOLD_COLD_CORE,alert value cold" line.long 0x10 "CTRL_CORE_BANDGAP_TSHUT_MPU,BGAP TSHUT THRESHOLD MPU" hexmask.long.word 0x10 16.--25. 1. "TSHUT_HOT_MPU,tshut value hot" newline hexmask.long.word 0x10 0.--9. 1. "TSHUT_COLD_MPU,tshut value cold" line.long 0x14 "CTRL_CORE_BANDGAP_TSHUT_GPU,BGAP TSHUT THRESHOLD GPU" hexmask.long.word 0x14 16.--25. 1. "TSHUT_HOT_GPU,tshut value hot" newline hexmask.long.word 0x14 0.--9. 1. "TSHUT_COLD_GPU,tshut value cold" line.long 0x18 "CTRL_CORE_BANDGAP_TSHUT_CORE,BGAP TSHUT THRESHOLD CORE" hexmask.long.word 0x18 16.--25. 1. "TSHUT_HOT_CORE,tshut value hot" newline hexmask.long.word 0x18 0.--9. 1. "TSHUT_COLD_CORE,tshut value cold" line.long 0x1C "CTRL_CORE_BANDGAP_CUMUL_DTEMP_MPU,Temperature accumulator register" line.long 0x20 "CTRL_CORE_BANDGAP_CUMUL_DTEMP_GPU,Temperature accumulator register" line.long 0x24 "CTRL_CORE_BANDGAP_CUMUL_DTEMP_CORE,Temperature accumulator register" line.long 0x28 "CTRL_CORE_BANDGAP_STATUS_1,BGAP STATUS" bitfld.long 0x28 31. "ALERT,Alert temperature when '1'" "0,1" newline bitfld.long 0x28 5. "HOT_CORE,Event for hot temperature mpu bandgap when '1'" "0,1" newline bitfld.long 0x28 4. "COLD_CORE,Event for cold temperature mpu bandgap when '1'" "0,1" newline bitfld.long 0x28 3. "HOT_GPU,Event for hot temperature gpu bandgap when '1'" "0,1" newline bitfld.long 0x28 2. "COLD_GPU,Event for cold temperature gpu bandgap when '1'" "0,1" newline bitfld.long 0x28 1. "HOT_MPU,Event for hot temperature core bandgap when '1'" "0,1" newline bitfld.long 0x28 0. "COLD_MPU,Event for cold temperature core bandgap when '1'" "0,1" line.long 0x2C "CTRL_CORE_SATA_EXT_MODE,SATA EXTENDED MODE" bitfld.long 0x2C 0. "SATA_EXTENDED_MODE,sata extended mode" "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "CTRL_CORE_DTEMP_MPU_0,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_MPU_0,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_MPU_0,temperature" rgroup.long 0x3D0++0x07 line.long 0x00 "CTRL_CORE_DTEMP_MPU_4,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_MPU_4,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_MPU_4,temperature" line.long 0x04 "CTRL_CORE_DTEMP_GPU_0,TAGGED TEMPERATURE GPU DOMAIN" hexmask.long.tbyte 0x04 10.--31. 1. "DTEMP_TAG_GPU_0,tag" newline hexmask.long.word 0x04 0.--9. 1. "DTEMP_TEMPERATURE_GPU_0,temperature" rgroup.long 0x3E4++0x07 line.long 0x00 "CTRL_CORE_DTEMP_GPU_4,TAGGED TEMPERATURE GPU DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_GPU_4,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_GPU_4,temperature" line.long 0x04 "CTRL_CORE_DTEMP_CORE_0,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x04 10.--31. 1. "DTEMP_TAG_CORE_0,tag" newline hexmask.long.word 0x04 0.--9. 1. "DTEMP_TEMPERATURE_CORE_0,temperature" rgroup.long 0x3F8++0x07 line.long 0x00 "CTRL_CORE_DTEMP_CORE_4,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_CORE_4,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_CORE_4,temperature" line.long 0x04 "CTRL_CORE_SMA_SW_0,OCP Spare Register" bitfld.long 0x04 18. "SATA_PLL_SOFT_RESET,Software reset control for SATA PLL" "0,1" rgroup.long 0x414++0x03 line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_FUNC_2,Firewall Error Status functional Register 2" bitfld.long 0x00 26. "TC1_EDMA_FW_ERROR,EDMA TC1 firewall" "0,1" newline bitfld.long 0x00 22. "QSPI_FW_ERROR,QSPI firewall" "0,1" newline bitfld.long 0x00 17. "TPCC_EDMA_FW_ERROR,EDMA TPCC firewall" "0,1" newline bitfld.long 0x00 16. "TC0_EDMA_FW_ERROR,EDMA TC0 firewall" "0,1" newline bitfld.long 0x00 13. "MCASP3_FW_ERROR,McASP3 firewall" "0,1" newline bitfld.long 0x00 12. "MCASP2_FW_ERROR,McASP2 firewall" "0,1" newline bitfld.long 0x00 11. "MCASP1_FW_ERROR,McASP1 firewall" "0,1" newline bitfld.long 0x00 10. "VCP2_FW_ERROR,VCP2 firewall" "0,1" newline bitfld.long 0x00 9. "VCP1_FW_ERROR,VCP1 firewall" "0,1" newline bitfld.long 0x00 8. "PCIESS2_FW_ERROR,PCIeSS2 firewall" "0,1" newline bitfld.long 0x00 7. "PCIESS1_FW_ERROR,PCIeSS1 firewall" "0,1" newline bitfld.long 0x00 6. "IPU2_FW_ERROR,IPU2 firewall" "0,1" newline bitfld.long 0x00 5. "L4_PERIPH3_FW_ERROR,L4 periph3 init firewall" "0,1" newline bitfld.long 0x00 4. "L4_PERIPH2_FW_ERROR,L4 periph2 init firewall" "0,1" newline bitfld.long 0x00 3. "L3RAM3_FW_ERROR,L3RAM3 firewall" "0,1" newline bitfld.long 0x00 2. "L3RAM2_FW_ERROR,L3RAM2 target firewall" "0,1" newline bitfld.long 0x00 1. "DSP2_FW_ERROR,DSP2 firewall" "0,1" newline bitfld.long 0x00 0. "DSP1_FW_ERROR,DSP1 firewall" "0,1" group.long 0x41C++0x1B line.long 0x00 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_2,Firewall Error Status debug Register 2" bitfld.long 0x00 26. "TC1_EDMA_DBGFW_ERROR,EDMA TC1 debug firewall" "0,1" newline bitfld.long 0x00 22. "QSPI_DBGFW_ERROR,QSPI debug firewall" "0,1" newline bitfld.long 0x00 17. "TPCC_EDMA_DBGFW_ERROR,EDMA TPCC debug firewall" "0,1" newline bitfld.long 0x00 16. "TC0_EDMA_DBGFW_ERROR,EDMA TC0 debug firewall" "0,1" newline bitfld.long 0x00 13. "MCASP3_DBGFW_ERROR,McASP3 debug firewall" "0,1" newline bitfld.long 0x00 12. "MCASP2_DBGFW_ERROR,McASP2 debug firewall" "0,1" newline bitfld.long 0x00 11. "MCASP1_DBGFW_ERROR,McASP1 debug firewall" "0,1" newline bitfld.long 0x00 10. "VCP2_DBGFW_ERROR,VCP2 debug firewall" "0,1" newline bitfld.long 0x00 9. "VCP1_DBGFW_ERROR,VCP1 debug firewall" "0,1" newline bitfld.long 0x00 8. "PCIESS2_DBGFW_ERROR,PCIeSS2 debug firewall" "0,1" newline bitfld.long 0x00 7. "PCIESS1_DBGFW_ERROR,PCIeSS1 debug firewall" "0,1" newline bitfld.long 0x00 6. "IPU2_DBGFW_ERROR,IPU2 debug firewall" "0,1" newline bitfld.long 0x00 5. "L4_PERIPH3_DBGFW_ERROR,L4 periph3 init firewall" "0,1" newline bitfld.long 0x00 4. "L4_PERIPH2_DBGFW_ERROR,L4 periph2 init firewall" "0,1" newline bitfld.long 0x00 3. "L3RAM3_DBGFW_ERROR,L3RAM3 firewall" "0,1" newline bitfld.long 0x00 2. "L3RAM2_DBGFW_ERROR,L3RAM2 target debug firewall" "0,1" newline bitfld.long 0x00 1. "DSP2_DBGFW_ERROR,DSP2 firewall" "0,1" newline bitfld.long 0x00 0. "DSP1_DBGFW_ERROR,DSP1 firewall" "0,1" line.long 0x04 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_1,Register for priority settings for EMIF arbitration" bitfld.long 0x04 28.--30. "MPU_EMIF_PRIORITY,MPU priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 16.--18. "DSP1_MDMA_EMIF_PRIORITY,DSP1 MDMA priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "DSP1_CFG_EMIF_PRIORITY,DSP1 CFG priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 8.--10. "DSP1_EDMA_EMIF_PRIORITY,DSP1 EDMA priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 4.--6. "DSP2_EDMA_EMIF_PRIORITY,DSP2 EDMA priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. "DSP2_CFG_EMIF_PRIORITY,DSP2 CFG priority setting" "0,1,2,3,4,5,6,7" line.long 0x08 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_2,Register for priority settings for EMIF arbitration" bitfld.long 0x08 28.--30. "DSP2_MDMA_EMIF_PRIORITY,DSP2 MDMA priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 24.--26. "IVA_ICONT1_EMIF_PRIORITY,IVA ICONT1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 16.--18. "EVE1_TC0_EMIF_PRIORITY,EVE1 TC0 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 12.--14. "EVE2_TC0_EMIF_PRIORITY,EVE2 TC0 priority setting" "0,1,2,3,4,5,6,7" line.long 0x0C "CTRL_CORE_EMIF_INITIATOR_PRIORITY_3,Register for priority settings for EMIF arbitration" bitfld.long 0x0C 16.--18. "IPU1_EMIF_PRIORITY,IPU1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12.--14. "IPU2_EMIF_PRIORITY,IPU2 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 8.--10. "DMA_SYSTEM_EMIF_PRIORITY,DMA SYSTEM priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 0.--2. "EDMA_TC0_EMIF_PRIORITY,EDMA TC0 priority setting" "0,1,2,3,4,5,6,7" line.long 0x10 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_4,Register for priority settings for EMIF arbitration" bitfld.long 0x10 28.--30. "EDMA_TC1_EMIF_PRIORITY,EDMA TC1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24.--26. "DSS_EMIF_PRIORITY,DSS priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "MLB_MMU1_EMIF_PRIORITY,MLB MMU1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 16.--18. "PCIESS1_EMIF_PRIORITY,PCIeSS1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "PCIESS2_EMIF_PRIORITY,PCIeSS2 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--10. "VIP1_P1_P2_EMIF_PRIORITY,VIP1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 4.--6. "VIP2_P1_P2_EMIF_PRIORITY,VIP2 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "VIP3_P1_P2_EMIF_PRIORITY,VIP3 priority setting" "0,1,2,3,4,5,6,7" line.long 0x14 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_5,Register for priority settings for EMIF arbitration" bitfld.long 0x14 28.--30. "VPE_P1_P2_EMIF_PRIORITY,VPE priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24.--26. "MMC1_GPU_P1_EMIF_PRIORITY,MMC1 GPU P1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "MMC2_GPU_P2_EMIF_PRIORITY,MMC2 GPU P2 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 16.--18. "BB2D_P1_P2_EMIF_PRIORITY,BB2D priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "GMAC_SW_EMIF_PRIORITY,GMAC_SW priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--10. "USB1_EMIF_PRIORITY,USB1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 4.--6. "USB2_EMIF_PRIORITY,USB2 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "USB3_EMIF_PRIORITY,USB3 priority setting" "0,1,2,3,4,5,6,7" line.long 0x18 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_6,Register for priority settings for EMIF arbitration" bitfld.long 0x18 28.--30. "USB4_EMIF_PRIORITY,USB4 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "SATA_EMIF_PRIORITY,SATA priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "EVE1_TC1_EMIF_PRIORITY,EVE1 TC1 priority setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 4.--6. "EVE2_TC1_EMIF_PRIORITY,EVE2 TC1 priority setting" "0,1,2,3,4,5,6,7" group.long 0x43C++0x07 line.long 0x00 "CTRL_CORE_L3_INITIATOR_PRESSURE_1,Register for pressure settings for L3 arbitration" bitfld.long 0x00 26.--27. "MPU_L3_PRESSURE,MPU pressure setting" "0,1,2,3" newline bitfld.long 0x00 17.--18. "DSP1_CFG_L3_PRESSURE,DSP1 CFG pressure setting" "0,1,2,3" newline bitfld.long 0x00 9.--10. "DSP2_CFG_L3_PRESSURE,DSP2 CFG pressure setting" "0,1,2,3" line.long 0x04 "CTRL_CORE_L3_INITIATOR_PRESSURE_2,Register for pressure settings for L3 arbitration" bitfld.long 0x04 12.--13. "IPU1_L3_PRESSURE,IPU1 pressure setting" "0,1,2,3" newline bitfld.long 0x04 9.--10. "IPU2_L3_PRESSURE,IPU2 pressure setting" "0,1,2,3" group.long 0x448++0x0B line.long 0x00 "CTRL_CORE_L3_INITIATOR_PRESSURE_4,Register for pressure settings for L3 arbitration" bitfld.long 0x00 23.--24. "GPU_P1_L3_PRESSURE,GPU P1 pressure setting" "0,1,2,3" newline bitfld.long 0x00 20.--21. "GPU_P2_L3_PRESSURE,GPU P2 pressure setting" "0,1,2,3" line.long 0x04 "CTRL_CORE_L3_INITIATOR_PRESSURE_5,Register for pressure settings for L3 arbitration" bitfld.long 0x04 3.--4. "SATA_L3_PRESSURE,SATA pressure setting" "0,1,2,3" newline bitfld.long 0x04 0.--1. "MMC1_L3_PRESSURE,MMC1 pressure setting" "0,1,2,3" line.long 0x08 "CTRL_CORE_L3_INITIATOR_PRESSURE_6,Register for pressure settings for L3 arbitration" bitfld.long 0x08 17.--18. "MMC2_L3_PRESSURE,MMC2 pressure setting" "0,1,2,3" newline bitfld.long 0x08 15.--16. "USB1_L3_PRESSURE,USB1 pressure setting" "0,1,2,3" newline bitfld.long 0x08 12.--13. "USB2_L3_PRESSURE,USB2 pressure setting" "0,1,2,3" newline bitfld.long 0x08 9.--10. "USB3_L3_PRESSURE,USB3 pressure setting" "0,1,2,3" newline bitfld.long 0x08 6.--7. "USB4_L3_PRESSURE,USB4 pressure setting" "0,1,2,3" rgroup.long 0x458++0x1B line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0,Standard Fuse OPP VDD_iva [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1,Standard Fuse OPP VDD_iva [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2,Standard Fuse OPP VDD_iva [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3,Standard Fuse OPP VDD_iva [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4,Standard Fuse OPP VDD_iva [159:128]" line.long 0x14 "CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL,DSPEVE Voltage Body Bias LDO Control register" bitfld.long 0x14 10. "LDOVBBDSPEVE_FBB_MUX_CTRL,Override control of EFUSE Forward Body Bias voltage value" "0,1" newline rbitfld.long 0x14 5.--9. "LDOVBBDSPEVE_FBB_VSET_IN,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "LDOVBBDSPEVE_FBB_VSET_OUT,Override value for Forward Body Bias voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL,IVA Voltage Body Bias LDO Control register" bitfld.long 0x18 10. "LDOVBBIVA_FBB_MUX_CTRL,Override control of EFUSE Forward Body Bias voltage value" "0,1" newline rbitfld.long 0x18 5.--9. "LDOVBBIVA_FBB_VSET_IN,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 0.--4. "LDOVBBIVA_FBB_VSET_OUT,Override value for Forward Body Bias voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x4E8++0x1B line.long 0x00 "CTRL_CORE_CUST_FUSE_UID_0,Customer Fuse keys" line.long 0x04 "CTRL_CORE_CUST_FUSE_UID_1,Customer Fuse keys" line.long 0x08 "CTRL_CORE_CUST_FUSE_UID_2,Customer Fuse keys" line.long 0x0C "CTRL_CORE_CUST_FUSE_UID_3,Customer Fuse keys" line.long 0x10 "CTRL_CORE_CUST_FUSE_UID_4,Customer Fuse keys" line.long 0x14 "CTRL_CORE_CUST_FUSE_UID_5,Customer Fuse keys" line.long 0x18 "CTRL_CORE_CUST_FUSE_UID_6,Customer Fuse keys" rgroup.long 0x510++0x03 line.long 0x00 "CTRL_CORE_CUST_FUSE_PCIE_ID_0,Customer Fuse keys" group.long 0x534++0x07 line.long 0x00 "CTRL_CORE_SMA_SW_1,OCP Spare Register" bitfld.long 0x00 24. "DSS_CH2_IPC,DSS Channel 2 IPC control" "0,1" newline bitfld.long 0x00 23. "DSS_CH1_IPC,DSS Channel 1 IPC control" "0,1" newline bitfld.long 0x00 22. "DSS_CH0_IPC,DSS Channel 0 IPC control" "0,1" newline bitfld.long 0x00 21. "DSS_CH2_ON_OFF,DSS Channel 2 Pixel clock control On/Off" "0,1" newline bitfld.long 0x00 20. "DSS_CH1_ON_OFF,DSS Channel 1 Pixel clock control On/Off" "0,1" newline bitfld.long 0x00 19. "DSS_CH0_ON_OFF,DSS Channel 0 Pixel clock control On/Off" "0,1" newline bitfld.long 0x00 18. "DSS_CH2_RF,DSS Channel 2 Rise/Fall control" "0,1" newline bitfld.long 0x00 17. "DSS_CH1_RF,DSS Channel 1 Rise/Fall control" "0,1" newline bitfld.long 0x00 16. "DSS_CH0_RF,DSS Channel 0 Rise/Fall control" "0,1" newline bitfld.long 0x00 10. "VIP3_CLK_INV_PORT_1A,VIP3 Slice 1 Clock inversion for Port A enable" "0,1" newline bitfld.long 0x00 9. "VIP3_CLK_INV_PORT_2A,VIP3 Slice 0 Clock inversion for Port A enable" "0,1" newline bitfld.long 0x00 8. "VPE_CLK_DIV_BY_2_EN,Selects alternative clock source for VPE" "0,1" newline bitfld.long 0x00 7. "VIP2_CLK_INV_PORT_2B,VIP2 Slice 1 Clock inversion for Port B enable" "0,1" newline bitfld.long 0x00 6. "VIP2_CLK_INV_PORT_1B,VIP2 Slice 0 Clock inversion for Port B enable" "0,1" newline bitfld.long 0x00 5. "VIP2_CLK_INV_PORT_2A,VIP2 Slice 1 Clock inversion for Port A enable" "0,1" newline bitfld.long 0x00 4. "VIP2_CLK_INV_PORT_1A,VIP2 Slice 0 Clock inversion for Port A enable" "0,1" newline bitfld.long 0x00 3. "VIP1_CLK_INV_PORT_2B,VIP1 Slice 1 Clock inversion for Port B enable" "0,1" newline bitfld.long 0x00 2. "VIP1_CLK_INV_PORT_1B,VIP1 Slice 0 Clock inversion for Port B enable" "0,1" newline bitfld.long 0x00 1. "VIP1_CLK_INV_PORT_2A,VIP1 Slice 1 Clock inversion for Port A enable" "0,1" newline bitfld.long 0x00 0. "VIP1_CLK_INV_PORT_1A,VIP1 Slice 0 Clock inversion for Port A enable" "0,1" line.long 0x04 "CTRL_CORE_DSS_PLL_CONTROL,DSS PLLs Mux control register" bitfld.long 0x04 9.--10. "SDVENC_CLK_SELECTION,SDVENC_CLK mux configuration" "0,1,2,3" newline bitfld.long 0x04 7.--8. "DSI1_C_CLK1_SELECTION,DSI1_C_CLK1 mux configuration" "0,1,2,3" newline bitfld.long 0x04 5.--6. "DSI1_B_CLK1_SELECTION,DSI1_B_CLK1 mux configuration" "0,1,2,3" newline bitfld.long 0x04 3.--4. "DSI1_A_CLK1_SELECTION,DSI1_A_CLK1 mux configuration" "0,1,2,3" newline bitfld.long 0x04 2. "PLL_HDMI_DSS_CONTROL_DISABLE,HDMI PLL disable" "0,1" newline bitfld.long 0x04 1. "PLL_VIDEO2_DSS_CONTROL_DISABLE,VIDEO2 PLL disable" "0,1" newline bitfld.long 0x04 0. "PLL_VIDEO1_DSS_CONTROL_DISABLE,VIDEO1 PLL disable" "0,1" group.long 0x540++0x5F line.long 0x00 "CTRL_CORE_MMR_LOCK_1,Register to lock memory region starting at address offset 0x0000 0100 and ending at address offset 0x0000 079F" line.long 0x04 "CTRL_CORE_MMR_LOCK_2,Register to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F" line.long 0x08 "CTRL_CORE_MMR_LOCK_3,Register to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF" line.long 0x0C "CTRL_CORE_MMR_LOCK_4,Register to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF" line.long 0x10 "CTRL_CORE_MMR_LOCK_5,Register to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 1FFF" line.long 0x14 "CTRL_CORE_CONTROL_IO_1,Register to configure some IP level signals" bitfld.long 0x14 20. "MMU2_DISABLE,MMU2 DISABLE setting" "0,1" newline bitfld.long 0x14 16. "MMU1_DISABLE,MMU1 DISABLE setting" "0,1" newline bitfld.long 0x14 12.--13. "TC1_DEFAULT_BURST_SIZE,EDMA TC1 DEFAULT BURST SIZE setting" "0,1,2,3" newline bitfld.long 0x14 8.--9. "TC0_DEFAULT_BURST_SIZE,EDMA TC0 DEFAULT BURST SIZE setting" "0,1,2,3" newline bitfld.long 0x14 4.--5. "GMII2_SEL,GMII2 selection setting" "0,1,2,3" newline bitfld.long 0x14 0.--1. "GMII1_SEL,GMII1 selection setting" "0,1,2,3" line.long 0x18 "CTRL_CORE_CONTROL_IO_2,Register to configure some IP level signals" bitfld.long 0x18 23. "GMAC_RESET_ISOLATION_ENABLE,Reset isolation enable setting" "0,1" newline bitfld.long 0x18 22. "PWMSS3_TBCLKEN,PWMSS3 CLOCK ENABLE setting" "0,1" newline bitfld.long 0x18 21. "PWMSS2_TBCLKEN,PWMSS2 CLOCK ENABLE setting" "0,1" newline bitfld.long 0x18 20. "PWMSS1_TBCLKEN,PWMSS1 CLOCK ENABLE setting" "0,1" newline bitfld.long 0x18 13. "PCIE_1LANE_2LANE_SELECTION,PCIe one or two lane selection setting" "0,1" newline bitfld.long 0x18 8.--10. "QSPI_MEMMAPPED_CS,QSPI CS MAPPING setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 5. "DCAN2_RAMINIT_START,DCAN2 RAM INIT START setting" "0,1" newline bitfld.long 0x18 4. "DSS_DESHDCP_DISABLE,DSS DESHDCP DISABLE setting" "0,1" newline bitfld.long 0x18 3. "DCAN1_RAMINIT_START,DCAN1 RAM INIT START setting" "0,1" newline bitfld.long 0x18 2. "DCAN2_RAMINIT_DONE,DCAN2 RAM INIT DONE status" "0,1" newline bitfld.long 0x18 1. "DCAN1_RAMINIT_DONE,DCAN1 RAM INIT DONE status" "0,1" newline bitfld.long 0x18 0. "DSS_DESHDCP_CLKEN,DSS DESHDCP CLOCK ENABLE setting" "0,1" line.long 0x1C "CTRL_CORE_CONTROL_DSP1_RST_VECT,Register for storing DSP1 reset vector" bitfld.long 0x1C 24.--26. "DSP1_NUM_MM,Number of DSP instances in the SoC" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x1C 0.--21. 1. "DSP1_RST_VECT,DSP1 reset vector address" line.long 0x20 "CTRL_CORE_CONTROL_DSP2_RST_VECT,Register for storing DSP2 reset vector" bitfld.long 0x20 24.--26. "DSP2_NUM_MM,Number of DSP instances in the SoC" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x20 0.--21. 1. "DSP2_RST_VECT,DSP2 reset vector address" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE,Standard Fuse OPP BGAP" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_BGAP_IVA,Standard Fuse OPP BGAP" line.long 0x2C "CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL,DSPEVE SRAM LDO Control register" bitfld.long 0x2C 26. "LDOSRAMDSPEVE_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMDSPEVE_RETMODE_MUX_CTRL_0,LDOSRAMDSPEVE_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x2C 21.--25. "LDOSRAMDSPEVE_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x2C 16.--20. "LDOSRAMDSPEVE_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x2C 10. "LDOSRAMDSPEVE_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_0,LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x2C 5.--9. "LDOSRAMDSPEVE_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x2C 0.--4. "LDOSRAMDSPEVE_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x30 "CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL,IVA SRAM LDO Control register" bitfld.long 0x30 26. "LDOSRAMIVA_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMIVA_RETMODE_MUX_CTRL_0,LDOSRAMIVA_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x30 21.--25. "LDOSRAMIVA_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 16.--20. "LDOSRAMIVA_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 10. "LDOSRAMIVA_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMIVA_ACTMODE_MUX_CTRL_0,LDOSRAMIVA_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x30 5.--9. "LDOSRAMIVA_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0.--4. "LDOSRAMIVA_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x34 "CTRL_CORE_TEMP_SENSOR_DSPEVE,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x34 11. "BGAP_TMPSOFF_DSPEVE,Temperature sensor and thermal shutdown mode" "0,1" newline bitfld.long 0x34 10. "BGAP_EOCZ_DSPEVE,ADC End of Conversion" "0,1" newline hexmask.long.word 0x34 0.--9. 1. "BGAP_DTEMP_DSPEVE,Temperature data from the ADC" line.long 0x38 "CTRL_CORE_TEMP_SENSOR_IVA,Control VBGAPTS temperature sensor and thermal comparator shutdown register" bitfld.long 0x38 11. "BGAP_TMPSOFF_IVA,Temperature sensor and thermal shutdown mode" "0,1" newline bitfld.long 0x38 10. "BGAP_EOCZ_IVA,ADC End of Conversion" "0,1" newline hexmask.long.word 0x38 0.--9. 1. "BGAP_DTEMP_IVA,Temperature data from the ADC" line.long 0x3C "CTRL_CORE_BANDGAP_MASK_2,bgap_mask" bitfld.long 0x3C 22. "FREEZE_IVA,Freeze the FIFO IVA" "0,1" newline bitfld.long 0x3C 21. "FREEZE_DSPEVE,Freeze the FIFO DSPEVE" "0,1" newline bitfld.long 0x3C 19. "CLEAR_IVA,Reset the FIFO IVA" "0,1" newline bitfld.long 0x3C 18. "CLEAR_DSPEVE,Reset the FIFO DSPEVE" "0,1" newline bitfld.long 0x3C 16. "CLEAR_ACCUM_IVA,Reset the accumulator IVA" "0,1" newline bitfld.long 0x3C 15. "CLEAR_ACCUM_DSPEVE,Reset the accumulator DSPEVE" "0,1" newline bitfld.long 0x3C 3. "MASK_HOT_IVA,Mask for hot event IVA" "0,1" newline bitfld.long 0x3C 2. "MASK_COLD_IVA,Mask for cold event IVA" "0,1" newline bitfld.long 0x3C 1. "MASK_HOT_DSPEVE,Mask for hot event DSPEVE" "0,1" newline bitfld.long 0x3C 0. "MASK_COLD_DSPEVE,Mask for cold event DSPEVE" "0,1" line.long 0x40 "CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE,BGAP THRESHOLD DSPEVE" hexmask.long.word 0x40 16.--25. 1. "THOLD_HOT_DSPEVE,alert value hot" newline hexmask.long.word 0x40 0.--9. 1. "THOLD_COLD_DSPEVE,alert value cold" line.long 0x44 "CTRL_CORE_BANDGAP_THRESHOLD_IVA,BGAP THRESHOLD IVA" hexmask.long.word 0x44 16.--25. 1. "THOLD_HOT_IVA,alert value hot" newline hexmask.long.word 0x44 0.--9. 1. "THOLD_COLD_IVA,alert value cold" line.long 0x48 "CTRL_CORE_BANDGAP_TSHUT_DSPEVE,BGAP TSHUT THRESHOLD IVA" hexmask.long.word 0x48 16.--25. 1. "TSHUT_HOT_DSPEVE,tshut value hot" newline hexmask.long.word 0x48 0.--9. 1. "TSHUT_COLD_DSPEVE,tshut value cold" line.long 0x4C "CTRL_CORE_BANDGAP_TSHUT_IVA,BGAP TSHUT THRESHOLD IVA" hexmask.long.word 0x4C 16.--25. 1. "TSHUT_HOT_IVA,tshut value hot" newline hexmask.long.word 0x4C 0.--9. 1. "TSHUT_COLD_IVA,tshut value cold" line.long 0x50 "CTRL_CORE_BANDGAP_CUMUL_DTEMP_DSPEVE,Temperature accumulator register" line.long 0x54 "CTRL_CORE_BANDGAP_CUMUL_DTEMP_IVA,Temperature accumulator register" line.long 0x58 "CTRL_CORE_BANDGAP_STATUS_2,BGAP STATUS" bitfld.long 0x58 3. "HOT_IVA,Event for hot temperature iva bandgap when '1'" "0,1" newline bitfld.long 0x58 2. "COLD_IVA,Event for cold temperature iva bandgap when '1'" "0,1" newline bitfld.long 0x58 1. "HOT_DSPEVE,Event for hot temperature dspeve bandgap when '1'" "0,1" newline bitfld.long 0x58 0. "COLD_DSPEVE,Event for cold temperature dspeve bandgap when '1'" "0,1" line.long 0x5C "CTRL_CORE_DTEMP_DSPEVE_0,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.tbyte 0x5C 10.--31. 1. "DTEMP_TAG_DSPEVE_0,tag" newline hexmask.long.word 0x5C 0.--9. 1. "DTEMP_TEMPERATURE_DSPEVE_0,temperature" rgroup.long 0x5AC++0x07 line.long 0x00 "CTRL_CORE_DTEMP_DSPEVE_4,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_DSPEVE_4,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_DSPEVE_4,temperature" line.long 0x04 "CTRL_CORE_DTEMP_IVA_0,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.tbyte 0x04 10.--31. 1. "DTEMP_TAG_IVA_0,tag" newline hexmask.long.word 0x04 0.--9. 1. "DTEMP_TEMPERATURE_IVA_0,temperature" rgroup.long 0x5C0++0x3F line.long 0x00 "CTRL_CORE_DTEMP_IVA_4,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_IVA_4,tag" newline hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_IVA_4,temperature" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_0,Standard Fuse OPP Vmin_IVA [31:0]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_1,Standard Fuse OPP Vmin_IVA [63:32]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2,Standard Fuse OPP Vmin_IVA [95:64]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3,Standard Fuse OPP Vmin_IVA [127:96]" line.long 0x14 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4,Standard Fuse OPP Vmin_IVA [159:128]" line.long 0x18 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_0,Standard Fuse OPP Vmin_DSPEVE [31:0]" line.long 0x1C "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_1,Standard Fuse OPP Vmin_DSPEVE [63:32]" line.long 0x20 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2,Standard Fuse OPP Vmin_DSPEVE [95:64]" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3,Standard Fuse OPP Vmin_DSPEVE [127:96]" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4,Standard Fuse OPP Vmin_DSPEVE [159:128]" line.long 0x2C "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_0,Standard Fuse OPP Vmin_CORE [31:0]" line.long 0x30 "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_1,Standard Fuse OPP Vmin_CORE [63:32]" line.long 0x34 "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2,Standard Fuse OPP Vmin_CORE [95:64]" line.long 0x38 "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_3,Standard Fuse OPP Vmin_CORE [127:96]" line.long 0x3C "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_4,Standard Fuse OPP Vmin_CORE [159:128]" group.long 0x680++0x07 line.long 0x00 "CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL,CORE 2nd SRAM LDO Control register" bitfld.long 0x00 26. "LDOSRAMCORE_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_2_RETMODE_MUX_CTRL_0,LDOSRAMCORE_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x00 21.--25. "LDOSRAMCORE_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "LDOSRAMCORE_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10. "LDOSRAMCORE_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_2_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x00 5.--9. "LDOSRAMCORE_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "LDOSRAMCORE_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL,CORE 3rd SRAM LDO Control register" bitfld.long 0x04 26. "LDOSRAMCORE_3_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_3_RETMODE_MUX_CTRL_0,LDOSRAMCORE_3_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x04 21.--25. "LDOSRAMCORE_3_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 16.--20. "LDOSRAMCORE_3_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 10. "LDOSRAMCORE_3_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_3_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_3_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x04 5.--9. "LDOSRAMCORE_3_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 0.--4. "LDOSRAMCORE_3_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x68C++0x07 line.long 0x00 "CTRL_CORE_NMI_DESTINATION_1,Register for routing NMI interrupt to respective cores" hexmask.long.byte 0x00 16.--23. 1. "IPU2_C1,Enable IPU2 CORE1 to receive the NMI interrupt" newline hexmask.long.byte 0x00 8.--15. 1. "IPU2_C0,Enable IPU2 CORE0 to receive the NMI interrupt" newline hexmask.long.byte 0x00 0.--7. 1. "IPU1_C1,Enable IPU1 CORE1 to receive the NMI interrupt" line.long 0x04 "CTRL_CORE_NMI_DESTINATION_2,Register for routing NMI interrupt to respective cores" hexmask.long.byte 0x04 24.--31. 1. "IPU1_C0,Enable IPU1 CORE0 to receive the NMI interrupt" newline hexmask.long.byte 0x04 16.--23. 1. "DSP2,Enable DSP2 to receive the NMI interrupt" newline hexmask.long.byte 0x04 8.--15. 1. "DSP1,Enable DSP1 to receive the NMI interrupt" newline hexmask.long.byte 0x04 0.--7. 1. "MPU,Comes from Efuse (MPU_EN)" group.long 0x698++0x03 line.long 0x00 "CTRL_CORE_IP_PRESSURE,Register to override the L3 pressure setting for the MLB module" bitfld.long 0x00 2. "MLB_L3_PRESSURE_ENABLE,Override enable for the MLB L3 pressure setting" "0,1" newline bitfld.long 0x00 0.--1. "MLB_L3_PRESSURE,MLB L3 pressure setting" "0,1,2,3" rgroup.long 0x6A0++0x33 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0,Standard Fuse OPP VDD_DSPEVE [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1,Standard Fuse OPP VDD_DSPEVE [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2,Standard Fuse OPP VDD_DSPEVE [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3,Standard Fuse OPP VDD_DSPEVE [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4,Standard Fuse OPP VDD_DSPEVE [159:128]" line.long 0x14 "CTRL_CORE_CUST_FUSE_SWRV_7,Customer Fuse keys" line.long 0x18 "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0,Standard Fuse Calibration override value [31:0]" line.long 0x1C "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1,Standard Fuse Calibration override value [63:32]" line.long 0x20 "CTRL_CORE_PCIE_POWER_STATE,Register to PCIe related controls" bitfld.long 0x20 31. "BYPASS_EN_APLL_PCIE,Bypass enable bit setting for APLL_PCIe" "0,1" newline bitfld.long 0x20 30. "CLKOOUTEN_APLL_PCIE,Clock output enable bit setting for APLL_PCIe" "0,1" newline hexmask.long.word 0x20 16.--25. 1. "EFUSE_TRIM_ACS_PCIE,MMR override capability for ACS_PCIe efuse trim bits" newline hexmask.long.word 0x20 0.--15. 1. "EFUSE_TRIM_PCIE_PLL,MMR override capability for PCIe PLL efuse trim bits" line.long 0x24 "CTRL_CORE_BOOTSTRAP,Register to view all the sysboot settings" bitfld.long 0x24 15. "DSP_CLOCK_DIVIDER," "0,1" newline bitfld.long 0x24 13. "BOOTDEVICESIZE,Select the size of the flash device on CS0" "0,1" newline bitfld.long 0x24 11.--12. "MUXCS0DEVICE,Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0" "0,1,2,3" newline bitfld.long 0x24 10. "BOOTWAITEN,Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses" "0,1" newline bitfld.long 0x24 8.--9. "SPEEDSELECT,Indicates the selected source of the 32kHz clock" "0,1,2,3" newline bitfld.long 0x24 0.--5. "BOOTMODE,SYSBOOT mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x28 "CTRL_CORE_MLB_SIG_IO_CTRL,Register to set the MLB's SIG IO characteristics" bitfld.long 0x28 16.--21. "SIG_NC_IN,efuse trim for Nmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x28 8.--13. "SIG_PC_IN,efuse trim for Pmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x28 6. "SIG_REMOVE_SKEW,Adjust for skew generated by the receiver due to asymmetric inputs" "0,1" newline bitfld.long 0x28 5. "SIG_PWRDNRX,powerdown receiver active high" "0,1" newline bitfld.long 0x28 4. "SIG_PWRDNTX,powerdown transmitter active high" "0,1" newline bitfld.long 0x28 3. "SIG_EN_EXT_RES,disables internal resistors" "0,1" line.long 0x2C "CTRL_CORE_MLB_DAT_IO_CTRL,Register to set the MLB's DAT IO characteristics" bitfld.long 0x2C 16.--21. "DAT_NC_IN,efuse trim for Nmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x2C 8.--13. "DAT_PC_IN,efuse trim for Pmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x2C 6. "DAT_REMOVE_SKEW,Adjust for skew generated by the receiver due to asymmetric inputs" "0,1" newline bitfld.long 0x2C 5. "DAT_PWRDNRX,powerdown receiver active high" "0,1" newline bitfld.long 0x2C 4. "DAT_PWRDNTX,powerdown transmitter active high" "0,1" newline bitfld.long 0x2C 3. "DAT_EN_EXT_RES,Enable/disable internal resistors" "0,1" line.long 0x30 "CTRL_CORE_MLB_CLK_BG_CTRL,Register to set the MLB's clock receiver IO and bandgap characteristics" bitfld.long 0x30 16. "T_HYSTERISIS_EN,Hysterisis enable" "0,1" newline bitfld.long 0x30 2.--7. "BG_TRIM,Trim values for MLB bandgap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x30 1. "BG_PWRDN,MLB bandgap cell enable" "0,1" newline bitfld.long 0x30 0. "CLK_PWRDN,Enable the MLB differential clock receiver" "0,1" group.long 0x7A0++0x1F line.long 0x00 "CTRL_CORE_EVE1_IRQ_0_1," hexmask.long.word 0x00 16.--24. 1. "EVE1_IRQ_1," newline hexmask.long.word 0x00 0.--8. 1. "EVE1_IRQ_0," line.long 0x04 "CTRL_CORE_EVE1_IRQ_2_3," hexmask.long.word 0x04 16.--24. 1. "EVE1_IRQ_3," newline hexmask.long.word 0x04 0.--8. 1. "EVE1_IRQ_2," line.long 0x08 "CTRL_CORE_EVE1_IRQ_4_5," hexmask.long.word 0x08 16.--24. 1. "EVE1_IRQ_5," newline hexmask.long.word 0x08 0.--8. 1. "EVE1_IRQ_4," line.long 0x0C "CTRL_CORE_EVE1_IRQ_6_7," hexmask.long.word 0x0C 16.--24. 1. "EVE1_IRQ_7," newline hexmask.long.word 0x0C 0.--8. 1. "EVE1_IRQ_6," line.long 0x10 "CTRL_CORE_EVE2_IRQ_0_1," hexmask.long.word 0x10 16.--24. 1. "EVE2_IRQ_1," newline hexmask.long.word 0x10 0.--8. 1. "EVE2_IRQ_0," line.long 0x14 "CTRL_CORE_EVE2_IRQ_2_3," hexmask.long.word 0x14 16.--24. 1. "EVE2_IRQ_3," newline hexmask.long.word 0x14 0.--8. 1. "EVE2_IRQ_2," line.long 0x18 "CTRL_CORE_EVE2_IRQ_4_5," hexmask.long.word 0x18 16.--24. 1. "EVE2_IRQ_5," newline hexmask.long.word 0x18 0.--8. 1. "EVE2_IRQ_4," line.long 0x1C "CTRL_CORE_EVE2_IRQ_6_7," hexmask.long.word 0x1C 16.--24. 1. "EVE2_IRQ_7," newline hexmask.long.word 0x1C 0.--8. 1. "EVE2_IRQ_6," group.long 0x7E0++0xE7 line.long 0x00 "CTRL_CORE_IPU1_IRQ_23_24," hexmask.long.word 0x00 16.--24. 1. "IPU1_IRQ_24," newline hexmask.long.word 0x00 0.--8. 1. "IPU1_IRQ_23," line.long 0x04 "CTRL_CORE_IPU1_IRQ_25_26," hexmask.long.word 0x04 16.--24. 1. "IPU1_IRQ_26," newline hexmask.long.word 0x04 0.--8. 1. "IPU1_IRQ_25," line.long 0x08 "CTRL_CORE_IPU1_IRQ_27_28," hexmask.long.word 0x08 16.--24. 1. "IPU1_IRQ_28," newline hexmask.long.word 0x08 0.--8. 1. "IPU1_IRQ_27," line.long 0x0C "CTRL_CORE_IPU1_IRQ_29_30," hexmask.long.word 0x0C 16.--24. 1. "IPU1_IRQ_30," newline hexmask.long.word 0x0C 0.--8. 1. "IPU1_IRQ_29," line.long 0x10 "CTRL_CORE_IPU1_IRQ_31_32," hexmask.long.word 0x10 16.--24. 1. "IPU1_IRQ_32," newline hexmask.long.word 0x10 0.--8. 1. "IPU1_IRQ_31," line.long 0x14 "CTRL_CORE_IPU1_IRQ_33_34," hexmask.long.word 0x14 16.--24. 1. "IPU1_IRQ_34," newline hexmask.long.word 0x14 0.--8. 1. "IPU1_IRQ_33," line.long 0x18 "CTRL_CORE_IPU1_IRQ_35_36," hexmask.long.word 0x18 16.--24. 1. "IPU1_IRQ_36," newline hexmask.long.word 0x18 0.--8. 1. "IPU1_IRQ_35," line.long 0x1C "CTRL_CORE_IPU1_IRQ_37_38," hexmask.long.word 0x1C 16.--24. 1. "IPU1_IRQ_38," newline hexmask.long.word 0x1C 0.--8. 1. "IPU1_IRQ_37," line.long 0x20 "CTRL_CORE_IPU1_IRQ_39_40," hexmask.long.word 0x20 16.--24. 1. "IPU1_IRQ_40," newline hexmask.long.word 0x20 0.--8. 1. "IPU1_IRQ_39," line.long 0x24 "CTRL_CORE_IPU1_IRQ_41_42," hexmask.long.word 0x24 16.--24. 1. "IPU1_IRQ_42," newline hexmask.long.word 0x24 0.--8. 1. "IPU1_IRQ_41," line.long 0x28 "CTRL_CORE_IPU1_IRQ_43_44," hexmask.long.word 0x28 16.--24. 1. "IPU1_IRQ_44," newline hexmask.long.word 0x28 0.--8. 1. "IPU1_IRQ_43," line.long 0x2C "CTRL_CORE_IPU1_IRQ_45_46," hexmask.long.word 0x2C 16.--24. 1. "IPU1_IRQ_46," newline hexmask.long.word 0x2C 0.--8. 1. "IPU1_IRQ_45," line.long 0x30 "CTRL_CORE_IPU1_IRQ_47_48," hexmask.long.word 0x30 16.--24. 1. "IPU1_IRQ_48," newline hexmask.long.word 0x30 0.--8. 1. "IPU1_IRQ_47," line.long 0x34 "CTRL_CORE_IPU1_IRQ_49_50," hexmask.long.word 0x34 16.--24. 1. "IPU1_IRQ_50," newline hexmask.long.word 0x34 0.--8. 1. "IPU1_IRQ_49," line.long 0x38 "CTRL_CORE_IPU1_IRQ_51_52," hexmask.long.word 0x38 16.--24. 1. "IPU1_IRQ_52," newline hexmask.long.word 0x38 0.--8. 1. "IPU1_IRQ_51," line.long 0x3C "CTRL_CORE_IPU1_IRQ_53_54," hexmask.long.word 0x3C 16.--24. 1. "IPU1_IRQ_54," newline hexmask.long.word 0x3C 0.--8. 1. "IPU1_IRQ_53," line.long 0x40 "CTRL_CORE_IPU1_IRQ_55_56," hexmask.long.word 0x40 16.--24. 1. "IPU1_IRQ_56," newline hexmask.long.word 0x40 0.--8. 1. "IPU1_IRQ_55," line.long 0x44 "CTRL_CORE_IPU1_IRQ_57_58," hexmask.long.word 0x44 16.--24. 1. "IPU1_IRQ_58," newline hexmask.long.word 0x44 0.--8. 1. "IPU1_IRQ_57," line.long 0x48 "CTRL_CORE_IPU1_IRQ_59_60," hexmask.long.word 0x48 16.--24. 1. "IPU1_IRQ_60," newline hexmask.long.word 0x48 0.--8. 1. "IPU1_IRQ_59," line.long 0x4C "CTRL_CORE_IPU1_IRQ_61_62," hexmask.long.word 0x4C 16.--24. 1. "IPU1_IRQ_62," newline hexmask.long.word 0x4C 0.--8. 1. "IPU1_IRQ_61," line.long 0x50 "CTRL_CORE_IPU1_IRQ_63_64," hexmask.long.word 0x50 16.--24. 1. "IPU1_IRQ_64," newline hexmask.long.word 0x50 0.--8. 1. "IPU1_IRQ_63," line.long 0x54 "CTRL_CORE_IPU1_IRQ_65_66," hexmask.long.word 0x54 16.--24. 1. "IPU1_IRQ_66," newline hexmask.long.word 0x54 0.--8. 1. "IPU1_IRQ_65," line.long 0x58 "CTRL_CORE_IPU1_IRQ_67_68," hexmask.long.word 0x58 16.--24. 1. "IPU1_IRQ_68," newline hexmask.long.word 0x58 0.--8. 1. "IPU1_IRQ_67," line.long 0x5C "CTRL_CORE_IPU1_IRQ_69_70," hexmask.long.word 0x5C 16.--24. 1. "IPU1_IRQ_70," newline hexmask.long.word 0x5C 0.--8. 1. "IPU1_IRQ_69," line.long 0x60 "CTRL_CORE_IPU1_IRQ_71_72," hexmask.long.word 0x60 16.--24. 1. "IPU1_IRQ_72," newline hexmask.long.word 0x60 0.--8. 1. "IPU1_IRQ_71," line.long 0x64 "CTRL_CORE_IPU1_IRQ_73_74," hexmask.long.word 0x64 16.--24. 1. "IPU1_IRQ_74," newline hexmask.long.word 0x64 0.--8. 1. "IPU1_IRQ_73," line.long 0x68 "CTRL_CORE_IPU1_IRQ_75_76," hexmask.long.word 0x68 16.--24. 1. "IPU1_IRQ_76," newline hexmask.long.word 0x68 0.--8. 1. "IPU1_IRQ_75," line.long 0x6C "CTRL_CORE_IPU1_IRQ_77_78," hexmask.long.word 0x6C 16.--24. 1. "IPU1_IRQ_78," newline hexmask.long.word 0x6C 0.--8. 1. "IPU1_IRQ_77," line.long 0x70 "CTRL_CORE_IPU1_IRQ_79_80," hexmask.long.word 0x70 0.--8. 1. "IPU1_IRQ_79," line.long 0x74 "CTRL_CORE_IPU2_IRQ_23_24," hexmask.long.word 0x74 16.--24. 1. "IPU2_IRQ_24," newline hexmask.long.word 0x74 0.--8. 1. "IPU2_IRQ_23," line.long 0x78 "CTRL_CORE_IPU2_IRQ_25_26," hexmask.long.word 0x78 16.--24. 1. "IPU2_IRQ_26," newline hexmask.long.word 0x78 0.--8. 1. "IPU2_IRQ_25," line.long 0x7C "CTRL_CORE_IPU2_IRQ_27_28," hexmask.long.word 0x7C 16.--24. 1. "IPU2_IRQ_28," newline hexmask.long.word 0x7C 0.--8. 1. "IPU2_IRQ_27," line.long 0x80 "CTRL_CORE_IPU2_IRQ_29_30," hexmask.long.word 0x80 16.--24. 1. "IPU2_IRQ_30," newline hexmask.long.word 0x80 0.--8. 1. "IPU2_IRQ_29," line.long 0x84 "CTRL_CORE_IPU2_IRQ_31_32," hexmask.long.word 0x84 16.--24. 1. "IPU2_IRQ_32," newline hexmask.long.word 0x84 0.--8. 1. "IPU2_IRQ_31," line.long 0x88 "CTRL_CORE_IPU2_IRQ_33_34," hexmask.long.word 0x88 16.--24. 1. "IPU2_IRQ_34," newline hexmask.long.word 0x88 0.--8. 1. "IPU2_IRQ_33," line.long 0x8C "CTRL_CORE_IPU2_IRQ_35_36," hexmask.long.word 0x8C 16.--24. 1. "IPU2_IRQ_36," newline hexmask.long.word 0x8C 0.--8. 1. "IPU2_IRQ_35," line.long 0x90 "CTRL_CORE_IPU2_IRQ_37_38," hexmask.long.word 0x90 16.--24. 1. "IPU2_IRQ_38," newline hexmask.long.word 0x90 0.--8. 1. "IPU2_IRQ_37," line.long 0x94 "CTRL_CORE_IPU2_IRQ_39_40," hexmask.long.word 0x94 16.--24. 1. "IPU2_IRQ_40," newline hexmask.long.word 0x94 0.--8. 1. "IPU2_IRQ_39," line.long 0x98 "CTRL_CORE_IPU2_IRQ_41_42," hexmask.long.word 0x98 16.--24. 1. "IPU2_IRQ_42," newline hexmask.long.word 0x98 0.--8. 1. "IPU2_IRQ_41," line.long 0x9C "CTRL_CORE_IPU2_IRQ_43_44," hexmask.long.word 0x9C 16.--24. 1. "IPU2_IRQ_44," newline hexmask.long.word 0x9C 0.--8. 1. "IPU2_IRQ_43," line.long 0xA0 "CTRL_CORE_IPU2_IRQ_45_46," hexmask.long.word 0xA0 16.--24. 1. "IPU2_IRQ_46," newline hexmask.long.word 0xA0 0.--8. 1. "IPU2_IRQ_45," line.long 0xA4 "CTRL_CORE_IPU2_IRQ_47_48," hexmask.long.word 0xA4 16.--24. 1. "IPU2_IRQ_48," newline hexmask.long.word 0xA4 0.--8. 1. "IPU2_IRQ_47," line.long 0xA8 "CTRL_CORE_IPU2_IRQ_49_50," hexmask.long.word 0xA8 16.--24. 1. "IPU2_IRQ_50," newline hexmask.long.word 0xA8 0.--8. 1. "IPU2_IRQ_49," line.long 0xAC "CTRL_CORE_IPU2_IRQ_51_52," hexmask.long.word 0xAC 16.--24. 1. "IPU2_IRQ_52," newline hexmask.long.word 0xAC 0.--8. 1. "IPU2_IRQ_51," line.long 0xB0 "CTRL_CORE_IPU2_IRQ_53_54," hexmask.long.word 0xB0 16.--24. 1. "IPU2_IRQ_54," newline hexmask.long.word 0xB0 0.--8. 1. "IPU2_IRQ_53," line.long 0xB4 "CTRL_CORE_IPU2_IRQ_55_56," hexmask.long.word 0xB4 16.--24. 1. "IPU2_IRQ_56," newline hexmask.long.word 0xB4 0.--8. 1. "IPU2_IRQ_55," line.long 0xB8 "CTRL_CORE_IPU2_IRQ_57_58," hexmask.long.word 0xB8 16.--24. 1. "IPU2_IRQ_58," newline hexmask.long.word 0xB8 0.--8. 1. "IPU2_IRQ_57," line.long 0xBC "CTRL_CORE_IPU2_IRQ_59_60," hexmask.long.word 0xBC 16.--24. 1. "IPU2_IRQ_60," newline hexmask.long.word 0xBC 0.--8. 1. "IPU2_IRQ_59," line.long 0xC0 "CTRL_CORE_IPU2_IRQ_61_62," hexmask.long.word 0xC0 16.--24. 1. "IPU2_IRQ_62," newline hexmask.long.word 0xC0 0.--8. 1. "IPU2_IRQ_61," line.long 0xC4 "CTRL_CORE_IPU2_IRQ_63_64," hexmask.long.word 0xC4 16.--24. 1. "IPU2_IRQ_64," newline hexmask.long.word 0xC4 0.--8. 1. "IPU2_IRQ_63," line.long 0xC8 "CTRL_CORE_IPU2_IRQ_65_66," hexmask.long.word 0xC8 16.--24. 1. "IPU2_IRQ_66," newline hexmask.long.word 0xC8 0.--8. 1. "IPU2_IRQ_65," line.long 0xCC "CTRL_CORE_IPU2_IRQ_67_68," hexmask.long.word 0xCC 16.--24. 1. "IPU2_IRQ_68," newline hexmask.long.word 0xCC 0.--8. 1. "IPU2_IRQ_67," line.long 0xD0 "CTRL_CORE_IPU2_IRQ_69_70," hexmask.long.word 0xD0 16.--24. 1. "IPU2_IRQ_70," newline hexmask.long.word 0xD0 0.--8. 1. "IPU2_IRQ_69," line.long 0xD4 "CTRL_CORE_IPU2_IRQ_71_72," hexmask.long.word 0xD4 16.--24. 1. "IPU2_IRQ_72," newline hexmask.long.word 0xD4 0.--8. 1. "IPU2_IRQ_71," line.long 0xD8 "CTRL_CORE_IPU2_IRQ_73_74," hexmask.long.word 0xD8 16.--24. 1. "IPU2_IRQ_74," newline hexmask.long.word 0xD8 0.--8. 1. "IPU2_IRQ_73," line.long 0xDC "CTRL_CORE_IPU2_IRQ_75_76," hexmask.long.word 0xDC 16.--24. 1. "IPU2_IRQ_76," newline hexmask.long.word 0xDC 0.--8. 1. "IPU2_IRQ_75," line.long 0xE0 "CTRL_CORE_IPU2_IRQ_77_78," hexmask.long.word 0xE0 16.--24. 1. "IPU2_IRQ_78," newline hexmask.long.word 0xE0 0.--8. 1. "IPU2_IRQ_77," line.long 0xE4 "CTRL_CORE_IPU2_IRQ_79_80," hexmask.long.word 0xE4 0.--8. 1. "IPU2_IRQ_79," group.long 0x948++0x3FF line.long 0x00 "CTRL_CORE_DSP1_IRQ_32_33," hexmask.long.word 0x00 16.--24. 1. "DSP1_IRQ_33," newline hexmask.long.word 0x00 0.--8. 1. "DSP1_IRQ_32," line.long 0x04 "CTRL_CORE_DSP1_IRQ_34_35," hexmask.long.word 0x04 16.--24. 1. "DSP1_IRQ_35," newline hexmask.long.word 0x04 0.--8. 1. "DSP1_IRQ_34," line.long 0x08 "CTRL_CORE_DSP1_IRQ_36_37," hexmask.long.word 0x08 16.--24. 1. "DSP1_IRQ_37," newline hexmask.long.word 0x08 0.--8. 1. "DSP1_IRQ_36," line.long 0x0C "CTRL_CORE_DSP1_IRQ_38_39," hexmask.long.word 0x0C 16.--24. 1. "DSP1_IRQ_39," newline hexmask.long.word 0x0C 0.--8. 1. "DSP1_IRQ_38," line.long 0x10 "CTRL_CORE_DSP1_IRQ_40_41," hexmask.long.word 0x10 16.--24. 1. "DSP1_IRQ_41," newline hexmask.long.word 0x10 0.--8. 1. "DSP1_IRQ_40," line.long 0x14 "CTRL_CORE_DSP1_IRQ_42_43," hexmask.long.word 0x14 16.--24. 1. "DSP1_IRQ_43," newline hexmask.long.word 0x14 0.--8. 1. "DSP1_IRQ_42," line.long 0x18 "CTRL_CORE_DSP1_IRQ_44_45," hexmask.long.word 0x18 16.--24. 1. "DSP1_IRQ_45," newline hexmask.long.word 0x18 0.--8. 1. "DSP1_IRQ_44," line.long 0x1C "CTRL_CORE_DSP1_IRQ_46_47," hexmask.long.word 0x1C 16.--24. 1. "DSP1_IRQ_47," newline hexmask.long.word 0x1C 0.--8. 1. "DSP1_IRQ_46," line.long 0x20 "CTRL_CORE_DSP1_IRQ_48_49," hexmask.long.word 0x20 16.--24. 1. "DSP1_IRQ_49," newline hexmask.long.word 0x20 0.--8. 1. "DSP1_IRQ_48," line.long 0x24 "CTRL_CORE_DSP1_IRQ_50_51," hexmask.long.word 0x24 16.--24. 1. "DSP1_IRQ_51," newline hexmask.long.word 0x24 0.--8. 1. "DSP1_IRQ_50," line.long 0x28 "CTRL_CORE_DSP1_IRQ_52_53," hexmask.long.word 0x28 16.--24. 1. "DSP1_IRQ_53," newline hexmask.long.word 0x28 0.--8. 1. "DSP1_IRQ_52," line.long 0x2C "CTRL_CORE_DSP1_IRQ_54_55," hexmask.long.word 0x2C 16.--24. 1. "DSP1_IRQ_55," newline hexmask.long.word 0x2C 0.--8. 1. "DSP1_IRQ_54," line.long 0x30 "CTRL_CORE_DSP1_IRQ_56_57," hexmask.long.word 0x30 16.--24. 1. "DSP1_IRQ_57," newline hexmask.long.word 0x30 0.--8. 1. "DSP1_IRQ_56," line.long 0x34 "CTRL_CORE_DSP1_IRQ_58_59," hexmask.long.word 0x34 16.--24. 1. "DSP1_IRQ_59," newline hexmask.long.word 0x34 0.--8. 1. "DSP1_IRQ_58," line.long 0x38 "CTRL_CORE_DSP1_IRQ_60_61," hexmask.long.word 0x38 16.--24. 1. "DSP1_IRQ_61," newline hexmask.long.word 0x38 0.--8. 1. "DSP1_IRQ_60," line.long 0x3C "CTRL_CORE_DSP1_IRQ_62_63," hexmask.long.word 0x3C 16.--24. 1. "DSP1_IRQ_63," newline hexmask.long.word 0x3C 0.--8. 1. "DSP1_IRQ_62," line.long 0x40 "CTRL_CORE_DSP1_IRQ_64_65," hexmask.long.word 0x40 16.--24. 1. "DSP1_IRQ_65," newline hexmask.long.word 0x40 0.--8. 1. "DSP1_IRQ_64," line.long 0x44 "CTRL_CORE_DSP1_IRQ_66_67," hexmask.long.word 0x44 16.--24. 1. "DSP1_IRQ_67," newline hexmask.long.word 0x44 0.--8. 1. "DSP1_IRQ_66," line.long 0x48 "CTRL_CORE_DSP1_IRQ_68_69," hexmask.long.word 0x48 16.--24. 1. "DSP1_IRQ_69," newline hexmask.long.word 0x48 0.--8. 1. "DSP1_IRQ_68," line.long 0x4C "CTRL_CORE_DSP1_IRQ_70_71," hexmask.long.word 0x4C 16.--24. 1. "DSP1_IRQ_71," newline hexmask.long.word 0x4C 0.--8. 1. "DSP1_IRQ_70," line.long 0x50 "CTRL_CORE_DSP1_IRQ_72_73," hexmask.long.word 0x50 16.--24. 1. "DSP1_IRQ_73," newline hexmask.long.word 0x50 0.--8. 1. "DSP1_IRQ_72," line.long 0x54 "CTRL_CORE_DSP1_IRQ_74_75," hexmask.long.word 0x54 16.--24. 1. "DSP1_IRQ_75," newline hexmask.long.word 0x54 0.--8. 1. "DSP1_IRQ_74," line.long 0x58 "CTRL_CORE_DSP1_IRQ_76_77," hexmask.long.word 0x58 16.--24. 1. "DSP1_IRQ_77," newline hexmask.long.word 0x58 0.--8. 1. "DSP1_IRQ_76," line.long 0x5C "CTRL_CORE_DSP1_IRQ_78_79," hexmask.long.word 0x5C 16.--24. 1. "DSP1_IRQ_79," newline hexmask.long.word 0x5C 0.--8. 1. "DSP1_IRQ_78," line.long 0x60 "CTRL_CORE_DSP1_IRQ_80_81," hexmask.long.word 0x60 16.--24. 1. "DSP1_IRQ_81," newline hexmask.long.word 0x60 0.--8. 1. "DSP1_IRQ_80," line.long 0x64 "CTRL_CORE_DSP1_IRQ_82_83," hexmask.long.word 0x64 16.--24. 1. "DSP1_IRQ_83," newline hexmask.long.word 0x64 0.--8. 1. "DSP1_IRQ_82," line.long 0x68 "CTRL_CORE_DSP1_IRQ_84_85," hexmask.long.word 0x68 16.--24. 1. "DSP1_IRQ_85," newline hexmask.long.word 0x68 0.--8. 1. "DSP1_IRQ_84," line.long 0x6C "CTRL_CORE_DSP1_IRQ_86_87," hexmask.long.word 0x6C 16.--24. 1. "DSP1_IRQ_87," newline hexmask.long.word 0x6C 0.--8. 1. "DSP1_IRQ_86," line.long 0x70 "CTRL_CORE_DSP1_IRQ_88_89," hexmask.long.word 0x70 16.--24. 1. "DSP1_IRQ_89," newline hexmask.long.word 0x70 0.--8. 1. "DSP1_IRQ_88," line.long 0x74 "CTRL_CORE_DSP1_IRQ_90_91," hexmask.long.word 0x74 16.--24. 1. "DSP1_IRQ_91," newline hexmask.long.word 0x74 0.--8. 1. "DSP1_IRQ_90," line.long 0x78 "CTRL_CORE_DSP1_IRQ_92_93," hexmask.long.word 0x78 16.--24. 1. "DSP1_IRQ_93," newline hexmask.long.word 0x78 0.--8. 1. "DSP1_IRQ_92," line.long 0x7C "CTRL_CORE_DSP1_IRQ_94_95," hexmask.long.word 0x7C 16.--24. 1. "DSP1_IRQ_95," newline hexmask.long.word 0x7C 0.--8. 1. "DSP1_IRQ_94," line.long 0x80 "CTRL_CORE_DSP2_IRQ_32_33," hexmask.long.word 0x80 16.--24. 1. "DSP2_IRQ_33," newline hexmask.long.word 0x80 0.--8. 1. "DSP2_IRQ_32," line.long 0x84 "CTRL_CORE_DSP2_IRQ_34_35," hexmask.long.word 0x84 16.--24. 1. "DSP2_IRQ_35," newline hexmask.long.word 0x84 0.--8. 1. "DSP2_IRQ_34," line.long 0x88 "CTRL_CORE_DSP2_IRQ_36_37," hexmask.long.word 0x88 16.--24. 1. "DSP2_IRQ_37," newline hexmask.long.word 0x88 0.--8. 1. "DSP2_IRQ_36," line.long 0x8C "CTRL_CORE_DSP2_IRQ_38_39," hexmask.long.word 0x8C 16.--24. 1. "DSP2_IRQ_39," newline hexmask.long.word 0x8C 0.--8. 1. "DSP2_IRQ_38," line.long 0x90 "CTRL_CORE_DSP2_IRQ_40_41," hexmask.long.word 0x90 16.--24. 1. "DSP2_IRQ_41," newline hexmask.long.word 0x90 0.--8. 1. "DSP2_IRQ_40," line.long 0x94 "CTRL_CORE_DSP2_IRQ_42_43," hexmask.long.word 0x94 16.--24. 1. "DSP2_IRQ_43," newline hexmask.long.word 0x94 0.--8. 1. "DSP2_IRQ_42," line.long 0x98 "CTRL_CORE_DSP2_IRQ_44_45," hexmask.long.word 0x98 16.--24. 1. "DSP2_IRQ_45," newline hexmask.long.word 0x98 0.--8. 1. "DSP2_IRQ_44," line.long 0x9C "CTRL_CORE_DSP2_IRQ_46_47," hexmask.long.word 0x9C 16.--24. 1. "DSP2_IRQ_47," newline hexmask.long.word 0x9C 0.--8. 1. "DSP2_IRQ_46," line.long 0xA0 "CTRL_CORE_DSP2_IRQ_48_49," hexmask.long.word 0xA0 16.--24. 1. "DSP2_IRQ_49," newline hexmask.long.word 0xA0 0.--8. 1. "DSP2_IRQ_48," line.long 0xA4 "CTRL_CORE_DSP2_IRQ_50_51," hexmask.long.word 0xA4 16.--24. 1. "DSP2_IRQ_51," newline hexmask.long.word 0xA4 0.--8. 1. "DSP2_IRQ_50," line.long 0xA8 "CTRL_CORE_DSP2_IRQ_52_53," hexmask.long.word 0xA8 16.--24. 1. "DSP2_IRQ_53," newline hexmask.long.word 0xA8 0.--8. 1. "DSP2_IRQ_52," line.long 0xAC "CTRL_CORE_DSP2_IRQ_54_55," hexmask.long.word 0xAC 16.--24. 1. "DSP2_IRQ_55," newline hexmask.long.word 0xAC 0.--8. 1. "DSP2_IRQ_54," line.long 0xB0 "CTRL_CORE_DSP2_IRQ_56_57," hexmask.long.word 0xB0 16.--24. 1. "DSP2_IRQ_57," newline hexmask.long.word 0xB0 0.--8. 1. "DSP2_IRQ_56," line.long 0xB4 "CTRL_CORE_DSP2_IRQ_58_59," hexmask.long.word 0xB4 16.--24. 1. "DSP2_IRQ_59," newline hexmask.long.word 0xB4 0.--8. 1. "DSP2_IRQ_58," line.long 0xB8 "CTRL_CORE_DSP2_IRQ_60_61," hexmask.long.word 0xB8 16.--24. 1. "DSP2_IRQ_61," newline hexmask.long.word 0xB8 0.--8. 1. "DSP2_IRQ_60," line.long 0xBC "CTRL_CORE_DSP2_IRQ_62_63," hexmask.long.word 0xBC 16.--24. 1. "DSP2_IRQ_63," newline hexmask.long.word 0xBC 0.--8. 1. "DSP2_IRQ_62," line.long 0xC0 "CTRL_CORE_DSP2_IRQ_64_65," hexmask.long.word 0xC0 16.--24. 1. "DSP2_IRQ_65," newline hexmask.long.word 0xC0 0.--8. 1. "DSP2_IRQ_64," line.long 0xC4 "CTRL_CORE_DSP2_IRQ_66_67," hexmask.long.word 0xC4 16.--24. 1. "DSP2_IRQ_67," newline hexmask.long.word 0xC4 0.--8. 1. "DSP2_IRQ_66," line.long 0xC8 "CTRL_CORE_DSP2_IRQ_68_69," hexmask.long.word 0xC8 16.--24. 1. "DSP2_IRQ_69," newline hexmask.long.word 0xC8 0.--8. 1. "DSP2_IRQ_68," line.long 0xCC "CTRL_CORE_DSP2_IRQ_70_71," hexmask.long.word 0xCC 16.--24. 1. "DSP2_IRQ_71," newline hexmask.long.word 0xCC 0.--8. 1. "DSP2_IRQ_70," line.long 0xD0 "CTRL_CORE_DSP2_IRQ_72_73," hexmask.long.word 0xD0 16.--24. 1. "DSP2_IRQ_73," newline hexmask.long.word 0xD0 0.--8. 1. "DSP2_IRQ_72," line.long 0xD4 "CTRL_CORE_DSP2_IRQ_74_75," hexmask.long.word 0xD4 16.--24. 1. "DSP2_IRQ_75," newline hexmask.long.word 0xD4 0.--8. 1. "DSP2_IRQ_74," line.long 0xD8 "CTRL_CORE_DSP2_IRQ_76_77," hexmask.long.word 0xD8 16.--24. 1. "DSP2_IRQ_77," newline hexmask.long.word 0xD8 0.--8. 1. "DSP2_IRQ_76," line.long 0xDC "CTRL_CORE_DSP2_IRQ_78_79," hexmask.long.word 0xDC 16.--24. 1. "DSP2_IRQ_79," newline hexmask.long.word 0xDC 0.--8. 1. "DSP2_IRQ_78," line.long 0xE0 "CTRL_CORE_DSP2_IRQ_80_81," hexmask.long.word 0xE0 16.--24. 1. "DSP2_IRQ_81," newline hexmask.long.word 0xE0 0.--8. 1. "DSP2_IRQ_80," line.long 0xE4 "CTRL_CORE_DSP2_IRQ_82_83," hexmask.long.word 0xE4 16.--24. 1. "DSP2_IRQ_83," newline hexmask.long.word 0xE4 0.--8. 1. "DSP2_IRQ_82," line.long 0xE8 "CTRL_CORE_DSP2_IRQ_84_85," hexmask.long.word 0xE8 16.--24. 1. "DSP2_IRQ_85," newline hexmask.long.word 0xE8 0.--8. 1. "DSP2_IRQ_84," line.long 0xEC "CTRL_CORE_DSP2_IRQ_86_87," hexmask.long.word 0xEC 16.--24. 1. "DSP2_IRQ_87," newline hexmask.long.word 0xEC 0.--8. 1. "DSP2_IRQ_86," line.long 0xF0 "CTRL_CORE_DSP2_IRQ_88_89," hexmask.long.word 0xF0 16.--24. 1. "DSP2_IRQ_89," newline hexmask.long.word 0xF0 0.--8. 1. "DSP2_IRQ_88," line.long 0xF4 "CTRL_CORE_DSP2_IRQ_90_91," hexmask.long.word 0xF4 16.--24. 1. "DSP2_IRQ_91," newline hexmask.long.word 0xF4 0.--8. 1. "DSP2_IRQ_90," line.long 0xF8 "CTRL_CORE_DSP2_IRQ_92_93," hexmask.long.word 0xF8 16.--24. 1. "DSP2_IRQ_93," newline hexmask.long.word 0xF8 0.--8. 1. "DSP2_IRQ_92," line.long 0xFC "CTRL_CORE_DSP2_IRQ_94_95," hexmask.long.word 0xFC 16.--24. 1. "DSP2_IRQ_95," newline hexmask.long.word 0xFC 0.--8. 1. "DSP2_IRQ_94," line.long 0x100 "CTRL_CORE_MPU_IRQ_4_5," hexmask.long.word 0x100 16.--24. 1. "MPU_IRQ_7," newline hexmask.long.word 0x100 0.--8. 1. "MPU_IRQ_4," line.long 0x104 "CTRL_CORE_MPU_IRQ_8_9," hexmask.long.word 0x104 16.--24. 1. "MPU_IRQ_9," newline hexmask.long.word 0x104 0.--8. 1. "MPU_IRQ_8," line.long 0x108 "CTRL_CORE_MPU_IRQ_10_11," hexmask.long.word 0x108 16.--24. 1. "MPU_IRQ_11," newline hexmask.long.word 0x108 0.--8. 1. "MPU_IRQ_10," line.long 0x10C "CTRL_CORE_MPU_IRQ_12_13," hexmask.long.word 0x10C 16.--24. 1. "MPU_IRQ_13," newline hexmask.long.word 0x10C 0.--8. 1. "MPU_IRQ_12," line.long 0x110 "CTRL_CORE_MPU_IRQ_14_15," hexmask.long.word 0x110 16.--24. 1. "MPU_IRQ_15," newline hexmask.long.word 0x110 0.--8. 1. "MPU_IRQ_14," line.long 0x114 "CTRL_CORE_MPU_IRQ_16_17," hexmask.long.word 0x114 16.--24. 1. "MPU_IRQ_17," newline hexmask.long.word 0x114 0.--8. 1. "MPU_IRQ_16," line.long 0x118 "CTRL_CORE_MPU_IRQ_18_19," hexmask.long.word 0x118 16.--24. 1. "MPU_IRQ_19," newline hexmask.long.word 0x118 0.--8. 1. "MPU_IRQ_18," line.long 0x11C "CTRL_CORE_MPU_IRQ_20_21," hexmask.long.word 0x11C 16.--24. 1. "MPU_IRQ_21," newline hexmask.long.word 0x11C 0.--8. 1. "MPU_IRQ_20," line.long 0x120 "CTRL_CORE_MPU_IRQ_22_23," hexmask.long.word 0x120 16.--24. 1. "MPU_IRQ_23," newline hexmask.long.word 0x120 0.--8. 1. "MPU_IRQ_22," line.long 0x124 "CTRL_CORE_MPU_IRQ_24_25," hexmask.long.word 0x124 16.--24. 1. "MPU_IRQ_25," newline hexmask.long.word 0x124 0.--8. 1. "MPU_IRQ_24," line.long 0x128 "CTRL_CORE_MPU_IRQ_26_27," hexmask.long.word 0x128 16.--24. 1. "MPU_IRQ_27," newline hexmask.long.word 0x128 0.--8. 1. "MPU_IRQ_26," line.long 0x12C "CTRL_CORE_MPU_IRQ_28_29," hexmask.long.word 0x12C 16.--24. 1. "MPU_IRQ_29," newline hexmask.long.word 0x12C 0.--8. 1. "MPU_IRQ_28," line.long 0x130 "CTRL_CORE_MPU_IRQ_30_31," hexmask.long.word 0x130 16.--24. 1. "MPU_IRQ_31," newline hexmask.long.word 0x130 0.--8. 1. "MPU_IRQ_30," line.long 0x134 "CTRL_CORE_MPU_IRQ_32_33," hexmask.long.word 0x134 16.--24. 1. "MPU_IRQ_33," newline hexmask.long.word 0x134 0.--8. 1. "MPU_IRQ_32," line.long 0x138 "CTRL_CORE_MPU_IRQ_34_35," hexmask.long.word 0x138 16.--24. 1. "MPU_IRQ_35," newline hexmask.long.word 0x138 0.--8. 1. "MPU_IRQ_34," line.long 0x13C "CTRL_CORE_MPU_IRQ_36_37," hexmask.long.word 0x13C 16.--24. 1. "MPU_IRQ_37," newline hexmask.long.word 0x13C 0.--8. 1. "MPU_IRQ_36," line.long 0x140 "CTRL_CORE_MPU_IRQ_38_39," hexmask.long.word 0x140 16.--24. 1. "MPU_IRQ_39," newline hexmask.long.word 0x140 0.--8. 1. "MPU_IRQ_38," line.long 0x144 "CTRL_CORE_MPU_IRQ_40_41," hexmask.long.word 0x144 16.--24. 1. "MPU_IRQ_41," newline hexmask.long.word 0x144 0.--8. 1. "MPU_IRQ_40," line.long 0x148 "CTRL_CORE_MPU_IRQ_42_43," hexmask.long.word 0x148 16.--24. 1. "MPU_IRQ_43," newline hexmask.long.word 0x148 0.--8. 1. "MPU_IRQ_42," line.long 0x14C "CTRL_CORE_MPU_IRQ_44_45," hexmask.long.word 0x14C 16.--24. 1. "MPU_IRQ_45," newline hexmask.long.word 0x14C 0.--8. 1. "MPU_IRQ_44," line.long 0x150 "CTRL_CORE_MPU_IRQ_46_47," hexmask.long.word 0x150 16.--24. 1. "MPU_IRQ_47," newline hexmask.long.word 0x150 0.--8. 1. "MPU_IRQ_46," line.long 0x154 "CTRL_CORE_MPU_IRQ_48_49," hexmask.long.word 0x154 16.--24. 1. "MPU_IRQ_49," newline hexmask.long.word 0x154 0.--8. 1. "MPU_IRQ_48," line.long 0x158 "CTRL_CORE_MPU_IRQ_50_51," hexmask.long.word 0x158 16.--24. 1. "MPU_IRQ_51," newline hexmask.long.word 0x158 0.--8. 1. "MPU_IRQ_50," line.long 0x15C "CTRL_CORE_MPU_IRQ_52_53," hexmask.long.word 0x15C 16.--24. 1. "MPU_IRQ_53," newline hexmask.long.word 0x15C 0.--8. 1. "MPU_IRQ_52," line.long 0x160 "CTRL_CORE_MPU_IRQ_54_55," hexmask.long.word 0x160 16.--24. 1. "MPU_IRQ_55," newline hexmask.long.word 0x160 0.--8. 1. "MPU_IRQ_54," line.long 0x164 "CTRL_CORE_MPU_IRQ_56_57," hexmask.long.word 0x164 16.--24. 1. "MPU_IRQ_57," newline hexmask.long.word 0x164 0.--8. 1. "MPU_IRQ_56," line.long 0x168 "CTRL_CORE_MPU_IRQ_58_59," hexmask.long.word 0x168 16.--24. 1. "MPU_IRQ_59," newline hexmask.long.word 0x168 0.--8. 1. "MPU_IRQ_58," line.long 0x16C "CTRL_CORE_MPU_IRQ_60_61," hexmask.long.word 0x16C 16.--24. 1. "MPU_IRQ_61," newline hexmask.long.word 0x16C 0.--8. 1. "MPU_IRQ_60," line.long 0x170 "CTRL_CORE_MPU_IRQ_62_63," hexmask.long.word 0x170 16.--24. 1. "MPU_IRQ_63," newline hexmask.long.word 0x170 0.--8. 1. "MPU_IRQ_62," line.long 0x174 "CTRL_CORE_MPU_IRQ_64_65," hexmask.long.word 0x174 16.--24. 1. "MPU_IRQ_65," newline hexmask.long.word 0x174 0.--8. 1. "MPU_IRQ_64," line.long 0x178 "CTRL_CORE_MPU_IRQ_66_67," hexmask.long.word 0x178 16.--24. 1. "MPU_IRQ_67," newline hexmask.long.word 0x178 0.--8. 1. "MPU_IRQ_66," line.long 0x17C "CTRL_CORE_MPU_IRQ_68_69," hexmask.long.word 0x17C 16.--24. 1. "MPU_IRQ_69," newline hexmask.long.word 0x17C 0.--8. 1. "MPU_IRQ_68," line.long 0x180 "CTRL_CORE_MPU_IRQ_70_71," hexmask.long.word 0x180 16.--24. 1. "MPU_IRQ_71," newline hexmask.long.word 0x180 0.--8. 1. "MPU_IRQ_70," line.long 0x184 "CTRL_CORE_MPU_IRQ_72_73," hexmask.long.word 0x184 16.--24. 1. "MPU_IRQ_73," newline hexmask.long.word 0x184 0.--8. 1. "MPU_IRQ_72," line.long 0x188 "CTRL_CORE_MPU_IRQ_74_75," hexmask.long.word 0x188 16.--24. 1. "MPU_IRQ_75," newline hexmask.long.word 0x188 0.--8. 1. "MPU_IRQ_74," line.long 0x18C "CTRL_CORE_MPU_IRQ_76_77," hexmask.long.word 0x18C 16.--24. 1. "MPU_IRQ_77," newline hexmask.long.word 0x18C 0.--8. 1. "MPU_IRQ_76," line.long 0x190 "CTRL_CORE_MPU_IRQ_78_79," hexmask.long.word 0x190 16.--24. 1. "MPU_IRQ_79," newline hexmask.long.word 0x190 0.--8. 1. "MPU_IRQ_78," line.long 0x194 "CTRL_CORE_MPU_IRQ_80_81," hexmask.long.word 0x194 16.--24. 1. "MPU_IRQ_81," newline hexmask.long.word 0x194 0.--8. 1. "MPU_IRQ_80," line.long 0x198 "CTRL_CORE_MPU_IRQ_82_83," hexmask.long.word 0x198 16.--24. 1. "MPU_IRQ_83," newline hexmask.long.word 0x198 0.--8. 1. "MPU_IRQ_82," line.long 0x19C "CTRL_CORE_MPU_IRQ_84_85," hexmask.long.word 0x19C 16.--24. 1. "MPU_IRQ_85," newline hexmask.long.word 0x19C 0.--8. 1. "MPU_IRQ_84," line.long 0x1A0 "CTRL_CORE_MPU_IRQ_86_87," hexmask.long.word 0x1A0 16.--24. 1. "MPU_IRQ_87," newline hexmask.long.word 0x1A0 0.--8. 1. "MPU_IRQ_86," line.long 0x1A4 "CTRL_CORE_MPU_IRQ_88_89," hexmask.long.word 0x1A4 16.--24. 1. "MPU_IRQ_89," newline hexmask.long.word 0x1A4 0.--8. 1. "MPU_IRQ_88," line.long 0x1A8 "CTRL_CORE_MPU_IRQ_90_91," hexmask.long.word 0x1A8 16.--24. 1. "MPU_IRQ_91," newline hexmask.long.word 0x1A8 0.--8. 1. "MPU_IRQ_90," line.long 0x1AC "CTRL_CORE_MPU_IRQ_92_93," hexmask.long.word 0x1AC 16.--24. 1. "MPU_IRQ_93," newline hexmask.long.word 0x1AC 0.--8. 1. "MPU_IRQ_92," line.long 0x1B0 "CTRL_CORE_MPU_IRQ_94_95," hexmask.long.word 0x1B0 16.--24. 1. "MPU_IRQ_95," newline hexmask.long.word 0x1B0 0.--8. 1. "MPU_IRQ_94," line.long 0x1B4 "CTRL_CORE_MPU_IRQ_96_97," hexmask.long.word 0x1B4 16.--24. 1. "MPU_IRQ_97," newline hexmask.long.word 0x1B4 0.--8. 1. "MPU_IRQ_96," line.long 0x1B8 "CTRL_CORE_MPU_IRQ_98_99," hexmask.long.word 0x1B8 16.--24. 1. "MPU_IRQ_99," newline hexmask.long.word 0x1B8 0.--8. 1. "MPU_IRQ_98," line.long 0x1BC "CTRL_CORE_MPU_IRQ_100_101," hexmask.long.word 0x1BC 16.--24. 1. "MPU_IRQ_101," newline hexmask.long.word 0x1BC 0.--8. 1. "MPU_IRQ_100," line.long 0x1C0 "CTRL_CORE_MPU_IRQ_102_103," hexmask.long.word 0x1C0 16.--24. 1. "MPU_IRQ_103," newline hexmask.long.word 0x1C0 0.--8. 1. "MPU_IRQ_102," line.long 0x1C4 "CTRL_CORE_MPU_IRQ_104_105," hexmask.long.word 0x1C4 16.--24. 1. "MPU_IRQ_105," newline hexmask.long.word 0x1C4 0.--8. 1. "MPU_IRQ_104," line.long 0x1C8 "CTRL_CORE_MPU_IRQ_106_107," hexmask.long.word 0x1C8 16.--24. 1. "MPU_IRQ_107," newline hexmask.long.word 0x1C8 0.--8. 1. "MPU_IRQ_106," line.long 0x1CC "CTRL_CORE_MPU_IRQ_108_109," hexmask.long.word 0x1CC 16.--24. 1. "MPU_IRQ_109," newline hexmask.long.word 0x1CC 0.--8. 1. "MPU_IRQ_108," line.long 0x1D0 "CTRL_CORE_MPU_IRQ_110_111," hexmask.long.word 0x1D0 16.--24. 1. "MPU_IRQ_111," newline hexmask.long.word 0x1D0 0.--8. 1. "MPU_IRQ_110," line.long 0x1D4 "CTRL_CORE_MPU_IRQ_112_113," hexmask.long.word 0x1D4 16.--24. 1. "MPU_IRQ_113," newline hexmask.long.word 0x1D4 0.--8. 1. "MPU_IRQ_112," line.long 0x1D8 "CTRL_CORE_MPU_IRQ_114_115," hexmask.long.word 0x1D8 16.--24. 1. "MPU_IRQ_115," newline hexmask.long.word 0x1D8 0.--8. 1. "MPU_IRQ_114," line.long 0x1DC "CTRL_CORE_MPU_IRQ_116_117," hexmask.long.word 0x1DC 16.--24. 1. "MPU_IRQ_117," newline hexmask.long.word 0x1DC 0.--8. 1. "MPU_IRQ_116," line.long 0x1E0 "CTRL_CORE_MPU_IRQ_118_119," hexmask.long.word 0x1E0 16.--24. 1. "MPU_IRQ_119," newline hexmask.long.word 0x1E0 0.--8. 1. "MPU_IRQ_118," line.long 0x1E4 "CTRL_CORE_MPU_IRQ_120_121," hexmask.long.word 0x1E4 16.--24. 1. "MPU_IRQ_121," newline hexmask.long.word 0x1E4 0.--8. 1. "MPU_IRQ_120," line.long 0x1E8 "CTRL_CORE_MPU_IRQ_122_123," hexmask.long.word 0x1E8 16.--24. 1. "MPU_IRQ_123," newline hexmask.long.word 0x1E8 0.--8. 1. "MPU_IRQ_122," line.long 0x1EC "CTRL_CORE_MPU_IRQ_124_125," hexmask.long.word 0x1EC 16.--24. 1. "MPU_IRQ_125," newline hexmask.long.word 0x1EC 0.--8. 1. "MPU_IRQ_124," line.long 0x1F0 "CTRL_CORE_MPU_IRQ_126_127," hexmask.long.word 0x1F0 16.--24. 1. "MPU_IRQ_127," newline hexmask.long.word 0x1F0 0.--8. 1. "MPU_IRQ_126," line.long 0x1F4 "CTRL_CORE_MPU_IRQ_128_129," hexmask.long.word 0x1F4 16.--24. 1. "MPU_IRQ_129," newline hexmask.long.word 0x1F4 0.--8. 1. "MPU_IRQ_128," line.long 0x1F8 "CTRL_CORE_MPU_IRQ_130_131," hexmask.long.word 0x1F8 16.--24. 1. "MPU_IRQ_133," newline hexmask.long.word 0x1F8 0.--8. 1. "MPU_IRQ_130," line.long 0x1FC "CTRL_CORE_MPU_IRQ_134_135," hexmask.long.word 0x1FC 16.--24. 1. "MPU_IRQ_135," newline hexmask.long.word 0x1FC 0.--8. 1. "MPU_IRQ_134," line.long 0x200 "CTRL_CORE_MPU_IRQ_136_137," hexmask.long.word 0x200 16.--24. 1. "MPU_IRQ_137," newline hexmask.long.word 0x200 0.--8. 1. "MPU_IRQ_136," line.long 0x204 "CTRL_CORE_MPU_IRQ_138_139," hexmask.long.word 0x204 16.--24. 1. "MPU_IRQ_139," newline hexmask.long.word 0x204 0.--8. 1. "MPU_IRQ_138," line.long 0x208 "CTRL_CORE_MPU_IRQ_140_141," hexmask.long.word 0x208 16.--24. 1. "MPU_IRQ_141," newline hexmask.long.word 0x208 0.--8. 1. "MPU_IRQ_140," line.long 0x20C "CTRL_CORE_MPU_IRQ_142_143," hexmask.long.word 0x20C 16.--24. 1. "MPU_IRQ_143," newline hexmask.long.word 0x20C 0.--8. 1. "MPU_IRQ_142," line.long 0x210 "CTRL_CORE_MPU_IRQ_144_145," hexmask.long.word 0x210 16.--24. 1. "MPU_IRQ_145," newline hexmask.long.word 0x210 0.--8. 1. "MPU_IRQ_144," line.long 0x214 "CTRL_CORE_MPU_IRQ_146_147," hexmask.long.word 0x214 16.--24. 1. "MPU_IRQ_147," newline hexmask.long.word 0x214 0.--8. 1. "MPU_IRQ_146," line.long 0x218 "CTRL_CORE_MPU_IRQ_148_149," hexmask.long.word 0x218 16.--24. 1. "MPU_IRQ_149," newline hexmask.long.word 0x218 0.--8. 1. "MPU_IRQ_148," line.long 0x21C "CTRL_CORE_MPU_IRQ_150_151," hexmask.long.word 0x21C 16.--24. 1. "MPU_IRQ_151," newline hexmask.long.word 0x21C 0.--8. 1. "MPU_IRQ_150," line.long 0x220 "CTRL_CORE_MPU_IRQ_152_153," hexmask.long.word 0x220 16.--24. 1. "MPU_IRQ_153," newline hexmask.long.word 0x220 0.--8. 1. "MPU_IRQ_152," line.long 0x224 "CTRL_CORE_MPU_IRQ_154_155," hexmask.long.word 0x224 16.--24. 1. "MPU_IRQ_155," newline hexmask.long.word 0x224 0.--8. 1. "MPU_IRQ_154," line.long 0x228 "CTRL_CORE_MPU_IRQ_156_157," hexmask.long.word 0x228 16.--24. 1. "MPU_IRQ_157," newline hexmask.long.word 0x228 0.--8. 1. "MPU_IRQ_156," line.long 0x22C "CTRL_CORE_MPU_IRQ_158_159," hexmask.long.word 0x22C 16.--24. 1. "MPU_IRQ_159," newline hexmask.long.word 0x22C 0.--8. 1. "MPU_IRQ_158," line.long 0x230 "CTRL_CORE_DMA_SYSTEM_DREQ_0_1," hexmask.long.byte 0x230 16.--23. 1. "DMA_SYSTEM_DREQ_1_IRQ_1," newline hexmask.long.byte 0x230 0.--7. 1. "DMA_SYSTEM_DREQ_0_IRQ_0," line.long 0x234 "CTRL_CORE_DMA_SYSTEM_DREQ_2_3," hexmask.long.byte 0x234 16.--23. 1. "DMA_SYSTEM_DREQ_3_IRQ_3," newline hexmask.long.byte 0x234 0.--7. 1. "DMA_SYSTEM_DREQ_2_IRQ_2," line.long 0x238 "CTRL_CORE_DMA_SYSTEM_DREQ_4_5," hexmask.long.byte 0x238 16.--23. 1. "DMA_SYSTEM_DREQ_5_IRQ_5," newline hexmask.long.byte 0x238 0.--7. 1. "DMA_SYSTEM_DREQ_4_IRQ_4," line.long 0x23C "CTRL_CORE_DMA_SYSTEM_DREQ_6_7," hexmask.long.byte 0x23C 16.--23. 1. "DMA_SYSTEM_DREQ_7_IRQ_7," newline hexmask.long.byte 0x23C 0.--7. 1. "DMA_SYSTEM_DREQ_6_IRQ_6," line.long 0x240 "CTRL_CORE_DMA_SYSTEM_DREQ_8_9," hexmask.long.byte 0x240 16.--23. 1. "DMA_SYSTEM_DREQ_9_IRQ_9," newline hexmask.long.byte 0x240 0.--7. 1. "DMA_SYSTEM_DREQ_8_IRQ_8," line.long 0x244 "CTRL_CORE_DMA_SYSTEM_DREQ_10_11," hexmask.long.byte 0x244 16.--23. 1. "DMA_SYSTEM_DREQ_11_IRQ_11," newline hexmask.long.byte 0x244 0.--7. 1. "DMA_SYSTEM_DREQ_10_IRQ_10," line.long 0x248 "CTRL_CORE_DMA_SYSTEM_DREQ_12_13," hexmask.long.byte 0x248 16.--23. 1. "DMA_SYSTEM_DREQ_13_IRQ_13," newline hexmask.long.byte 0x248 0.--7. 1. "DMA_SYSTEM_DREQ_12_IRQ_12," line.long 0x24C "CTRL_CORE_DMA_SYSTEM_DREQ_14_15," hexmask.long.byte 0x24C 16.--23. 1. "DMA_SYSTEM_DREQ_15_IRQ_15," newline hexmask.long.byte 0x24C 0.--7. 1. "DMA_SYSTEM_DREQ_14_IRQ_14," line.long 0x250 "CTRL_CORE_DMA_SYSTEM_DREQ_16_17," hexmask.long.byte 0x250 16.--23. 1. "DMA_SYSTEM_DREQ_17_IRQ_17," newline hexmask.long.byte 0x250 0.--7. 1. "DMA_SYSTEM_DREQ_16_IRQ_16," line.long 0x254 "CTRL_CORE_DMA_SYSTEM_DREQ_18_19," hexmask.long.byte 0x254 16.--23. 1. "DMA_SYSTEM_DREQ_19_IRQ_19," newline hexmask.long.byte 0x254 0.--7. 1. "DMA_SYSTEM_DREQ_18_IRQ_18," line.long 0x258 "CTRL_CORE_DMA_SYSTEM_DREQ_20_21," hexmask.long.byte 0x258 16.--23. 1. "DMA_SYSTEM_DREQ_21_IRQ_21," newline hexmask.long.byte 0x258 0.--7. 1. "DMA_SYSTEM_DREQ_20_IRQ_20," line.long 0x25C "CTRL_CORE_DMA_SYSTEM_DREQ_22_23," hexmask.long.byte 0x25C 16.--23. 1. "DMA_SYSTEM_DREQ_23_IRQ_23," newline hexmask.long.byte 0x25C 0.--7. 1. "DMA_SYSTEM_DREQ_22_IRQ_22," line.long 0x260 "CTRL_CORE_DMA_SYSTEM_DREQ_24_25," hexmask.long.byte 0x260 16.--23. 1. "DMA_SYSTEM_DREQ_25_IRQ_25," newline hexmask.long.byte 0x260 0.--7. 1. "DMA_SYSTEM_DREQ_24_IRQ_24," line.long 0x264 "CTRL_CORE_DMA_SYSTEM_DREQ_26_27," hexmask.long.byte 0x264 16.--23. 1. "DMA_SYSTEM_DREQ_27_IRQ_27," newline hexmask.long.byte 0x264 0.--7. 1. "DMA_SYSTEM_DREQ_26_IRQ_26," line.long 0x268 "CTRL_CORE_DMA_SYSTEM_DREQ_28_29," hexmask.long.byte 0x268 16.--23. 1. "DMA_SYSTEM_DREQ_29_IRQ_29," newline hexmask.long.byte 0x268 0.--7. 1. "DMA_SYSTEM_DREQ_28_IRQ_28," line.long 0x26C "CTRL_CORE_DMA_SYSTEM_DREQ_30_31," hexmask.long.byte 0x26C 16.--23. 1. "DMA_SYSTEM_DREQ_31_IRQ_31," newline hexmask.long.byte 0x26C 0.--7. 1. "DMA_SYSTEM_DREQ_30_IRQ_30," line.long 0x270 "CTRL_CORE_DMA_SYSTEM_DREQ_32_33," hexmask.long.byte 0x270 16.--23. 1. "DMA_SYSTEM_DREQ_33_IRQ_33," newline hexmask.long.byte 0x270 0.--7. 1. "DMA_SYSTEM_DREQ_32_IRQ_32," line.long 0x274 "CTRL_CORE_DMA_SYSTEM_DREQ_34_35," hexmask.long.byte 0x274 16.--23. 1. "DMA_SYSTEM_DREQ_35_IRQ_35," newline hexmask.long.byte 0x274 0.--7. 1. "DMA_SYSTEM_DREQ_34_IRQ_34," line.long 0x278 "CTRL_CORE_DMA_SYSTEM_DREQ_36_37," hexmask.long.byte 0x278 16.--23. 1. "DMA_SYSTEM_DREQ_37_IRQ_37," newline hexmask.long.byte 0x278 0.--7. 1. "DMA_SYSTEM_DREQ_36_IRQ_36," line.long 0x27C "CTRL_CORE_DMA_SYSTEM_DREQ_38_39," hexmask.long.byte 0x27C 16.--23. 1. "DMA_SYSTEM_DREQ_39_IRQ_39," newline hexmask.long.byte 0x27C 0.--7. 1. "DMA_SYSTEM_DREQ_38_IRQ_38," line.long 0x280 "CTRL_CORE_DMA_SYSTEM_DREQ_40_41," hexmask.long.byte 0x280 16.--23. 1. "DMA_SYSTEM_DREQ_41_IRQ_41," newline hexmask.long.byte 0x280 0.--7. 1. "DMA_SYSTEM_DREQ_40_IRQ_40," line.long 0x284 "CTRL_CORE_DMA_SYSTEM_DREQ_42_43," hexmask.long.byte 0x284 16.--23. 1. "DMA_SYSTEM_DREQ_43_IRQ_43," newline hexmask.long.byte 0x284 0.--7. 1. "DMA_SYSTEM_DREQ_42_IRQ_42," line.long 0x288 "CTRL_CORE_DMA_SYSTEM_DREQ_44_45," hexmask.long.byte 0x288 16.--23. 1. "DMA_SYSTEM_DREQ_45_IRQ_45," newline hexmask.long.byte 0x288 0.--7. 1. "DMA_SYSTEM_DREQ_44_IRQ_44," line.long 0x28C "CTRL_CORE_DMA_SYSTEM_DREQ_46_47," hexmask.long.byte 0x28C 16.--23. 1. "DMA_SYSTEM_DREQ_47_IRQ_47," newline hexmask.long.byte 0x28C 0.--7. 1. "DMA_SYSTEM_DREQ_46_IRQ_46," line.long 0x290 "CTRL_CORE_DMA_SYSTEM_DREQ_48_49," hexmask.long.byte 0x290 16.--23. 1. "DMA_SYSTEM_DREQ_49_IRQ_49," newline hexmask.long.byte 0x290 0.--7. 1. "DMA_SYSTEM_DREQ_48_IRQ_48," line.long 0x294 "CTRL_CORE_DMA_SYSTEM_DREQ_50_51," hexmask.long.byte 0x294 16.--23. 1. "DMA_SYSTEM_DREQ_51_IRQ_51," newline hexmask.long.byte 0x294 0.--7. 1. "DMA_SYSTEM_DREQ_50_IRQ_50," line.long 0x298 "CTRL_CORE_DMA_SYSTEM_DREQ_52_53," hexmask.long.byte 0x298 16.--23. 1. "DMA_SYSTEM_DREQ_53_IRQ_53," newline hexmask.long.byte 0x298 0.--7. 1. "DMA_SYSTEM_DREQ_52_IRQ_52," line.long 0x29C "CTRL_CORE_DMA_SYSTEM_DREQ_54_55," hexmask.long.byte 0x29C 16.--23. 1. "DMA_SYSTEM_DREQ_55_IRQ_55," newline hexmask.long.byte 0x29C 0.--7. 1. "DMA_SYSTEM_DREQ_54_IRQ_54," line.long 0x2A0 "CTRL_CORE_DMA_SYSTEM_DREQ_56_57," hexmask.long.byte 0x2A0 16.--23. 1. "DMA_SYSTEM_DREQ_57_IRQ_57," newline hexmask.long.byte 0x2A0 0.--7. 1. "DMA_SYSTEM_DREQ_56_IRQ_56," line.long 0x2A4 "CTRL_CORE_DMA_SYSTEM_DREQ_58_59," hexmask.long.byte 0x2A4 16.--23. 1. "DMA_SYSTEM_DREQ_59_IRQ_59," newline hexmask.long.byte 0x2A4 0.--7. 1. "DMA_SYSTEM_DREQ_58_IRQ_58," line.long 0x2A8 "CTRL_CORE_DMA_SYSTEM_DREQ_60_61," hexmask.long.byte 0x2A8 16.--23. 1. "DMA_SYSTEM_DREQ_61_IRQ_61," newline hexmask.long.byte 0x2A8 0.--7. 1. "DMA_SYSTEM_DREQ_60_IRQ_60," line.long 0x2AC "CTRL_CORE_DMA_SYSTEM_DREQ_62_63," hexmask.long.byte 0x2AC 16.--23. 1. "DMA_SYSTEM_DREQ_63_IRQ_63," newline hexmask.long.byte 0x2AC 0.--7. 1. "DMA_SYSTEM_DREQ_62_IRQ_62," line.long 0x2B0 "CTRL_CORE_DMA_SYSTEM_DREQ_64_65," hexmask.long.byte 0x2B0 16.--23. 1. "DMA_SYSTEM_DREQ_65_IRQ_65," newline hexmask.long.byte 0x2B0 0.--7. 1. "DMA_SYSTEM_DREQ_64_IRQ_64," line.long 0x2B4 "CTRL_CORE_DMA_SYSTEM_DREQ_66_67," hexmask.long.byte 0x2B4 16.--23. 1. "DMA_SYSTEM_DREQ_67_IRQ_67," newline hexmask.long.byte 0x2B4 0.--7. 1. "DMA_SYSTEM_DREQ_66_IRQ_66," line.long 0x2B8 "CTRL_CORE_DMA_SYSTEM_DREQ_68_69," hexmask.long.byte 0x2B8 16.--23. 1. "DMA_SYSTEM_DREQ_69_IRQ_69," newline hexmask.long.byte 0x2B8 0.--7. 1. "DMA_SYSTEM_DREQ_68_IRQ_68," line.long 0x2BC "CTRL_CORE_DMA_SYSTEM_DREQ_70_71," hexmask.long.byte 0x2BC 16.--23. 1. "DMA_SYSTEM_DREQ_71_IRQ_71," newline hexmask.long.byte 0x2BC 0.--7. 1. "DMA_SYSTEM_DREQ_70_IRQ_70," line.long 0x2C0 "CTRL_CORE_DMA_SYSTEM_DREQ_72_73," hexmask.long.byte 0x2C0 16.--23. 1. "DMA_SYSTEM_DREQ_73_IRQ_73," newline hexmask.long.byte 0x2C0 0.--7. 1. "DMA_SYSTEM_DREQ_72_IRQ_72," line.long 0x2C4 "CTRL_CORE_DMA_SYSTEM_DREQ_74_75," hexmask.long.byte 0x2C4 16.--23. 1. "DMA_SYSTEM_DREQ_75_IRQ_75," newline hexmask.long.byte 0x2C4 0.--7. 1. "DMA_SYSTEM_DREQ_74_IRQ_74," line.long 0x2C8 "CTRL_CORE_DMA_SYSTEM_DREQ_76_77," hexmask.long.byte 0x2C8 16.--23. 1. "DMA_SYSTEM_DREQ_77_IRQ_77," newline hexmask.long.byte 0x2C8 0.--7. 1. "DMA_SYSTEM_DREQ_76_IRQ_76," line.long 0x2CC "CTRL_CORE_DMA_SYSTEM_DREQ_78_79," hexmask.long.byte 0x2CC 16.--23. 1. "DMA_SYSTEM_DREQ_79_IRQ_79," newline hexmask.long.byte 0x2CC 0.--7. 1. "DMA_SYSTEM_DREQ_78_IRQ_78," line.long 0x2D0 "CTRL_CORE_DMA_SYSTEM_DREQ_80_81," hexmask.long.byte 0x2D0 16.--23. 1. "DMA_SYSTEM_DREQ_81_IRQ_81," newline hexmask.long.byte 0x2D0 0.--7. 1. "DMA_SYSTEM_DREQ_80_IRQ_80," line.long 0x2D4 "CTRL_CORE_DMA_SYSTEM_DREQ_82_83," hexmask.long.byte 0x2D4 16.--23. 1. "DMA_SYSTEM_DREQ_83_IRQ_83," newline hexmask.long.byte 0x2D4 0.--7. 1. "DMA_SYSTEM_DREQ_82_IRQ_82," line.long 0x2D8 "CTRL_CORE_DMA_SYSTEM_DREQ_84_85," hexmask.long.byte 0x2D8 16.--23. 1. "DMA_SYSTEM_DREQ_85_IRQ_85," newline hexmask.long.byte 0x2D8 0.--7. 1. "DMA_SYSTEM_DREQ_84_IRQ_84," line.long 0x2DC "CTRL_CORE_DMA_SYSTEM_DREQ_86_87," hexmask.long.byte 0x2DC 16.--23. 1. "DMA_SYSTEM_DREQ_87_IRQ_87," newline hexmask.long.byte 0x2DC 0.--7. 1. "DMA_SYSTEM_DREQ_86_IRQ_86," line.long 0x2E0 "CTRL_CORE_DMA_SYSTEM_DREQ_88_89," hexmask.long.byte 0x2E0 16.--23. 1. "DMA_SYSTEM_DREQ_89_IRQ_89," newline hexmask.long.byte 0x2E0 0.--7. 1. "DMA_SYSTEM_DREQ_88_IRQ_88," line.long 0x2E4 "CTRL_CORE_DMA_SYSTEM_DREQ_90_91," hexmask.long.byte 0x2E4 16.--23. 1. "DMA_SYSTEM_DREQ_91_IRQ_91," newline hexmask.long.byte 0x2E4 0.--7. 1. "DMA_SYSTEM_DREQ_90_IRQ_90," line.long 0x2E8 "CTRL_CORE_DMA_SYSTEM_DREQ_92_93," hexmask.long.byte 0x2E8 16.--23. 1. "DMA_SYSTEM_DREQ_93_IRQ_93," newline hexmask.long.byte 0x2E8 0.--7. 1. "DMA_SYSTEM_DREQ_92_IRQ_92," line.long 0x2EC "CTRL_CORE_DMA_SYSTEM_DREQ_94_95," hexmask.long.byte 0x2EC 16.--23. 1. "DMA_SYSTEM_DREQ_95_IRQ_95," newline hexmask.long.byte 0x2EC 0.--7. 1. "DMA_SYSTEM_DREQ_94_IRQ_94," line.long 0x2F0 "CTRL_CORE_DMA_SYSTEM_DREQ_96_97," hexmask.long.byte 0x2F0 16.--23. 1. "DMA_SYSTEM_DREQ_97_IRQ_97," newline hexmask.long.byte 0x2F0 0.--7. 1. "DMA_SYSTEM_DREQ_96_IRQ_96," line.long 0x2F4 "CTRL_CORE_DMA_SYSTEM_DREQ_98_99," hexmask.long.byte 0x2F4 16.--23. 1. "DMA_SYSTEM_DREQ_99_IRQ_99," newline hexmask.long.byte 0x2F4 0.--7. 1. "DMA_SYSTEM_DREQ_98_IRQ_98," line.long 0x2F8 "CTRL_CORE_DMA_SYSTEM_DREQ_100_101," hexmask.long.byte 0x2F8 16.--23. 1. "DMA_SYSTEM_DREQ_101_IRQ_101," newline hexmask.long.byte 0x2F8 0.--7. 1. "DMA_SYSTEM_DREQ_100_IRQ_100," line.long 0x2FC "CTRL_CORE_DMA_SYSTEM_DREQ_102_103," hexmask.long.byte 0x2FC 16.--23. 1. "DMA_SYSTEM_DREQ_103_IRQ_103," newline hexmask.long.byte 0x2FC 0.--7. 1. "DMA_SYSTEM_DREQ_102_IRQ_102," line.long 0x300 "CTRL_CORE_DMA_SYSTEM_DREQ_104_105," hexmask.long.byte 0x300 16.--23. 1. "DMA_SYSTEM_DREQ_105_IRQ_105," newline hexmask.long.byte 0x300 0.--7. 1. "DMA_SYSTEM_DREQ_104_IRQ_104," line.long 0x304 "CTRL_CORE_DMA_SYSTEM_DREQ_106_107," hexmask.long.byte 0x304 16.--23. 1. "DMA_SYSTEM_DREQ_107_IRQ_107," newline hexmask.long.byte 0x304 0.--7. 1. "DMA_SYSTEM_DREQ_106_IRQ_106," line.long 0x308 "CTRL_CORE_DMA_SYSTEM_DREQ_108_109," hexmask.long.byte 0x308 16.--23. 1. "DMA_SYSTEM_DREQ_109_IRQ_109," newline hexmask.long.byte 0x308 0.--7. 1. "DMA_SYSTEM_DREQ_108_IRQ_108," line.long 0x30C "CTRL_CORE_DMA_SYSTEM_DREQ_110_111," hexmask.long.byte 0x30C 16.--23. 1. "DMA_SYSTEM_DREQ_111_IRQ_111," newline hexmask.long.byte 0x30C 0.--7. 1. "DMA_SYSTEM_DREQ_110_IRQ_110," line.long 0x310 "CTRL_CORE_DMA_SYSTEM_DREQ_112_113," hexmask.long.byte 0x310 16.--23. 1. "DMA_SYSTEM_DREQ_113_IRQ_113," newline hexmask.long.byte 0x310 0.--7. 1. "DMA_SYSTEM_DREQ_112_IRQ_112," line.long 0x314 "CTRL_CORE_DMA_SYSTEM_DREQ_114_115," hexmask.long.byte 0x314 16.--23. 1. "DMA_SYSTEM_DREQ_115_IRQ_115," newline hexmask.long.byte 0x314 0.--7. 1. "DMA_SYSTEM_DREQ_114_IRQ_114," line.long 0x318 "CTRL_CORE_DMA_SYSTEM_DREQ_116_117," hexmask.long.byte 0x318 16.--23. 1. "DMA_SYSTEM_DREQ_117_IRQ_117," newline hexmask.long.byte 0x318 0.--7. 1. "DMA_SYSTEM_DREQ_116_IRQ_116," line.long 0x31C "CTRL_CORE_DMA_SYSTEM_DREQ_118_119," hexmask.long.byte 0x31C 16.--23. 1. "DMA_SYSTEM_DREQ_119_IRQ_119," newline hexmask.long.byte 0x31C 0.--7. 1. "DMA_SYSTEM_DREQ_118_IRQ_118," line.long 0x320 "CTRL_CORE_DMA_SYSTEM_DREQ_120_121," hexmask.long.byte 0x320 16.--23. 1. "DMA_SYSTEM_DREQ_121_IRQ_121," newline hexmask.long.byte 0x320 0.--7. 1. "DMA_SYSTEM_DREQ_120_IRQ_120," line.long 0x324 "CTRL_CORE_DMA_SYSTEM_DREQ_122_123," hexmask.long.byte 0x324 16.--23. 1. "DMA_SYSTEM_DREQ_123_IRQ_123," newline hexmask.long.byte 0x324 0.--7. 1. "DMA_SYSTEM_DREQ_122_IRQ_122," line.long 0x328 "CTRL_CORE_DMA_SYSTEM_DREQ_124_125," hexmask.long.byte 0x328 16.--23. 1. "DMA_SYSTEM_DREQ_125_IRQ_125," newline hexmask.long.byte 0x328 0.--7. 1. "DMA_SYSTEM_DREQ_124_IRQ_124," line.long 0x32C "CTRL_CORE_DMA_SYSTEM_DREQ_126_127," hexmask.long.byte 0x32C 0.--7. 1. "DMA_SYSTEM_DREQ_126_IRQ_126," line.long 0x330 "CTRL_CORE_DMA_EDMA_DREQ_0_1," hexmask.long.byte 0x330 16.--23. 1. "DMA_EDMA_DREQ_1_IRQ_1," newline hexmask.long.byte 0x330 0.--7. 1. "DMA_EDMA_DREQ_0_IRQ_0," line.long 0x334 "CTRL_CORE_DMA_EDMA_DREQ_2_3," hexmask.long.byte 0x334 16.--23. 1. "DMA_EDMA_DREQ_3_IRQ_3," newline hexmask.long.byte 0x334 0.--7. 1. "DMA_EDMA_DREQ_2_IRQ_2," line.long 0x338 "CTRL_CORE_DMA_EDMA_DREQ_4_5," hexmask.long.byte 0x338 16.--23. 1. "DMA_EDMA_DREQ_5_IRQ_5," newline hexmask.long.byte 0x338 0.--7. 1. "DMA_EDMA_DREQ_4_IRQ_4," line.long 0x33C "CTRL_CORE_DMA_EDMA_DREQ_6_7," hexmask.long.byte 0x33C 16.--23. 1. "DMA_EDMA_DREQ_7_IRQ_7," newline hexmask.long.byte 0x33C 0.--7. 1. "DMA_EDMA_DREQ_6_IRQ_6," line.long 0x340 "CTRL_CORE_DMA_EDMA_DREQ_8_9," hexmask.long.byte 0x340 16.--23. 1. "DMA_EDMA_DREQ_9_IRQ_9," newline hexmask.long.byte 0x340 0.--7. 1. "DMA_EDMA_DREQ_8_IRQ_8," line.long 0x344 "CTRL_CORE_DMA_EDMA_DREQ_10_11," hexmask.long.byte 0x344 16.--23. 1. "DMA_EDMA_DREQ_11_IRQ_11," newline hexmask.long.byte 0x344 0.--7. 1. "DMA_EDMA_DREQ_10_IRQ_10," line.long 0x348 "CTRL_CORE_DMA_EDMA_DREQ_12_13," hexmask.long.byte 0x348 16.--23. 1. "DMA_EDMA_DREQ_13_IRQ_13," newline hexmask.long.byte 0x348 0.--7. 1. "DMA_EDMA_DREQ_12_IRQ_12," line.long 0x34C "CTRL_CORE_DMA_EDMA_DREQ_14_15," hexmask.long.byte 0x34C 16.--23. 1. "DMA_EDMA_DREQ_15_IRQ_15," newline hexmask.long.byte 0x34C 0.--7. 1. "DMA_EDMA_DREQ_14_IRQ_14," line.long 0x350 "CTRL_CORE_DMA_EDMA_DREQ_16_17," hexmask.long.byte 0x350 16.--23. 1. "DMA_EDMA_DREQ_17_IRQ_17," newline hexmask.long.byte 0x350 0.--7. 1. "DMA_EDMA_DREQ_16_IRQ_16," line.long 0x354 "CTRL_CORE_DMA_EDMA_DREQ_18_19," hexmask.long.byte 0x354 16.--23. 1. "DMA_EDMA_DREQ_19_IRQ_19," newline hexmask.long.byte 0x354 0.--7. 1. "DMA_EDMA_DREQ_18_IRQ_18," line.long 0x358 "CTRL_CORE_DMA_EDMA_DREQ_20_21," hexmask.long.byte 0x358 16.--23. 1. "DMA_EDMA_DREQ_21_IRQ_21," newline hexmask.long.byte 0x358 0.--7. 1. "DMA_EDMA_DREQ_20_IRQ_20," line.long 0x35C "CTRL_CORE_DMA_EDMA_DREQ_22_23," hexmask.long.byte 0x35C 16.--23. 1. "DMA_EDMA_DREQ_23_IRQ_23," newline hexmask.long.byte 0x35C 0.--7. 1. "DMA_EDMA_DREQ_22_IRQ_22," line.long 0x360 "CTRL_CORE_DMA_EDMA_DREQ_24_25," hexmask.long.byte 0x360 16.--23. 1. "DMA_EDMA_DREQ_25_IRQ_25," newline hexmask.long.byte 0x360 0.--7. 1. "DMA_EDMA_DREQ_24_IRQ_24," line.long 0x364 "CTRL_CORE_DMA_EDMA_DREQ_26_27," hexmask.long.byte 0x364 16.--23. 1. "DMA_EDMA_DREQ_27_IRQ_27," newline hexmask.long.byte 0x364 0.--7. 1. "DMA_EDMA_DREQ_26_IRQ_26," line.long 0x368 "CTRL_CORE_DMA_EDMA_DREQ_28_29," hexmask.long.byte 0x368 16.--23. 1. "DMA_EDMA_DREQ_29_IRQ_29," newline hexmask.long.byte 0x368 0.--7. 1. "DMA_EDMA_DREQ_28_IRQ_28," line.long 0x36C "CTRL_CORE_DMA_EDMA_DREQ_30_31," hexmask.long.byte 0x36C 16.--23. 1. "DMA_EDMA_DREQ_31_IRQ_31," newline hexmask.long.byte 0x36C 0.--7. 1. "DMA_EDMA_DREQ_30_IRQ_30," line.long 0x370 "CTRL_CORE_DMA_EDMA_DREQ_32_33," hexmask.long.byte 0x370 16.--23. 1. "DMA_EDMA_DREQ_33_IRQ_33," newline hexmask.long.byte 0x370 0.--7. 1. "DMA_EDMA_DREQ_32_IRQ_32," line.long 0x374 "CTRL_CORE_DMA_EDMA_DREQ_34_35," hexmask.long.byte 0x374 16.--23. 1. "DMA_EDMA_DREQ_35_IRQ_35," newline hexmask.long.byte 0x374 0.--7. 1. "DMA_EDMA_DREQ_34_IRQ_34," line.long 0x378 "CTRL_CORE_DMA_EDMA_DREQ_36_37," hexmask.long.byte 0x378 16.--23. 1. "DMA_EDMA_DREQ_37_IRQ_37," newline hexmask.long.byte 0x378 0.--7. 1. "DMA_EDMA_DREQ_36_IRQ_36," line.long 0x37C "CTRL_CORE_DMA_EDMA_DREQ_38_39," hexmask.long.byte 0x37C 16.--23. 1. "DMA_EDMA_DREQ_39_IRQ_39," newline hexmask.long.byte 0x37C 0.--7. 1. "DMA_EDMA_DREQ_38_IRQ_38," line.long 0x380 "CTRL_CORE_DMA_EDMA_DREQ_40_41," hexmask.long.byte 0x380 16.--23. 1. "DMA_EDMA_DREQ_41_IRQ_41," newline hexmask.long.byte 0x380 0.--7. 1. "DMA_EDMA_DREQ_40_IRQ_40," line.long 0x384 "CTRL_CORE_DMA_EDMA_DREQ_42_43," hexmask.long.byte 0x384 16.--23. 1. "DMA_EDMA_DREQ_43_IRQ_43," newline hexmask.long.byte 0x384 0.--7. 1. "DMA_EDMA_DREQ_42_IRQ_42," line.long 0x388 "CTRL_CORE_DMA_EDMA_DREQ_44_45," hexmask.long.byte 0x388 16.--23. 1. "DMA_EDMA_DREQ_45_IRQ_45," newline hexmask.long.byte 0x388 0.--7. 1. "DMA_EDMA_DREQ_44_IRQ_44," line.long 0x38C "CTRL_CORE_DMA_EDMA_DREQ_46_47," hexmask.long.byte 0x38C 16.--23. 1. "DMA_EDMA_DREQ_47_IRQ_47," newline hexmask.long.byte 0x38C 0.--7. 1. "DMA_EDMA_DREQ_46_IRQ_46," line.long 0x390 "CTRL_CORE_DMA_EDMA_DREQ_48_49," hexmask.long.byte 0x390 16.--23. 1. "DMA_EDMA_DREQ_49_IRQ_49," newline hexmask.long.byte 0x390 0.--7. 1. "DMA_EDMA_DREQ_48_IRQ_48," line.long 0x394 "CTRL_CORE_DMA_EDMA_DREQ_50_51," hexmask.long.byte 0x394 16.--23. 1. "DMA_EDMA_DREQ_51_IRQ_51," newline hexmask.long.byte 0x394 0.--7. 1. "DMA_EDMA_DREQ_50_IRQ_50," line.long 0x398 "CTRL_CORE_DMA_EDMA_DREQ_52_53," hexmask.long.byte 0x398 16.--23. 1. "DMA_EDMA_DREQ_53_IRQ_53," newline hexmask.long.byte 0x398 0.--7. 1. "DMA_EDMA_DREQ_52_IRQ_52," line.long 0x39C "CTRL_CORE_DMA_EDMA_DREQ_54_55," hexmask.long.byte 0x39C 16.--23. 1. "DMA_EDMA_DREQ_55_IRQ_55," newline hexmask.long.byte 0x39C 0.--7. 1. "DMA_EDMA_DREQ_54_IRQ_54," line.long 0x3A0 "CTRL_CORE_DMA_EDMA_DREQ_56_57," hexmask.long.byte 0x3A0 16.--23. 1. "DMA_EDMA_DREQ_57_IRQ_57," newline hexmask.long.byte 0x3A0 0.--7. 1. "DMA_EDMA_DREQ_56_IRQ_56," line.long 0x3A4 "CTRL_CORE_DMA_EDMA_DREQ_58_59," hexmask.long.byte 0x3A4 16.--23. 1. "DMA_EDMA_DREQ_59_IRQ_59," newline hexmask.long.byte 0x3A4 0.--7. 1. "DMA_EDMA_DREQ_58_IRQ_58," line.long 0x3A8 "CTRL_CORE_DMA_EDMA_DREQ_60_61," hexmask.long.byte 0x3A8 16.--23. 1. "DMA_EDMA_DREQ_61_IRQ_61," newline hexmask.long.byte 0x3A8 0.--7. 1. "DMA_EDMA_DREQ_60_IRQ_60," line.long 0x3AC "CTRL_CORE_DMA_EDMA_DREQ_62_63," hexmask.long.byte 0x3AC 16.--23. 1. "DMA_EDMA_DREQ_63_IRQ_63," newline hexmask.long.byte 0x3AC 0.--7. 1. "DMA_EDMA_DREQ_62_IRQ_62," line.long 0x3B0 "CTRL_CORE_DMA_DSP1_DREQ_0_1," hexmask.long.byte 0x3B0 16.--23. 1. "DMA_DSP1_DREQ_1_IRQ_1," newline hexmask.long.byte 0x3B0 0.--7. 1. "DMA_DSP1_DREQ_0_IRQ_0," line.long 0x3B4 "CTRL_CORE_DMA_DSP1_DREQ_2_3," hexmask.long.byte 0x3B4 16.--23. 1. "DMA_DSP1_DREQ_3_IRQ_3," newline hexmask.long.byte 0x3B4 0.--7. 1. "DMA_DSP1_DREQ_2_IRQ_2," line.long 0x3B8 "CTRL_CORE_DMA_DSP1_DREQ_4_5," hexmask.long.byte 0x3B8 16.--23. 1. "DMA_DSP1_DREQ_5_IRQ_5," newline hexmask.long.byte 0x3B8 0.--7. 1. "DMA_DSP1_DREQ_4_IRQ_4," line.long 0x3BC "CTRL_CORE_DMA_DSP1_DREQ_6_7," hexmask.long.byte 0x3BC 16.--23. 1. "DMA_DSP1_DREQ_7_IRQ_7," newline hexmask.long.byte 0x3BC 0.--7. 1. "DMA_DSP1_DREQ_6_IRQ_6," line.long 0x3C0 "CTRL_CORE_DMA_DSP1_DREQ_8_9," hexmask.long.byte 0x3C0 16.--23. 1. "DMA_DSP1_DREQ_9_IRQ_9," newline hexmask.long.byte 0x3C0 0.--7. 1. "DMA_DSP1_DREQ_8_IRQ_8," line.long 0x3C4 "CTRL_CORE_DMA_DSP1_DREQ_10_11," hexmask.long.byte 0x3C4 16.--23. 1. "DMA_DSP1_DREQ_11_IRQ_11," newline hexmask.long.byte 0x3C4 0.--7. 1. "DMA_DSP1_DREQ_10_IRQ_10," line.long 0x3C8 "CTRL_CORE_DMA_DSP1_DREQ_12_13," hexmask.long.byte 0x3C8 16.--23. 1. "DMA_DSP1_DREQ_13_IRQ_13," newline hexmask.long.byte 0x3C8 0.--7. 1. "DMA_DSP1_DREQ_12_IRQ_12," line.long 0x3CC "CTRL_CORE_DMA_DSP1_DREQ_14_15," hexmask.long.byte 0x3CC 16.--23. 1. "DMA_DSP1_DREQ_15_IRQ_15," newline hexmask.long.byte 0x3CC 0.--7. 1. "DMA_DSP1_DREQ_14_IRQ_14," line.long 0x3D0 "CTRL_CORE_DMA_DSP1_DREQ_16_17," hexmask.long.byte 0x3D0 16.--23. 1. "DMA_DSP1_DREQ_17_IRQ_17," newline hexmask.long.byte 0x3D0 0.--7. 1. "DMA_DSP1_DREQ_16_IRQ_16," line.long 0x3D4 "CTRL_CORE_DMA_DSP1_DREQ_18_19," hexmask.long.byte 0x3D4 16.--23. 1. "DMA_DSP1_DREQ_19_IRQ_19," newline hexmask.long.byte 0x3D4 0.--7. 1. "DMA_DSP1_DREQ_18_IRQ_18," line.long 0x3D8 "CTRL_CORE_DMA_DSP2_DREQ_0_1," hexmask.long.byte 0x3D8 16.--23. 1. "DMA_DSP2_DREQ_1_IRQ_1," newline hexmask.long.byte 0x3D8 0.--7. 1. "DMA_DSP2_DREQ_0_IRQ_0," line.long 0x3DC "CTRL_CORE_DMA_DSP2_DREQ_2_3," hexmask.long.byte 0x3DC 16.--23. 1. "DMA_DSP2_DREQ_3_IRQ_3," newline hexmask.long.byte 0x3DC 0.--7. 1. "DMA_DSP2_DREQ_2_IRQ_2," line.long 0x3E0 "CTRL_CORE_DMA_DSP2_DREQ_4_5," hexmask.long.byte 0x3E0 16.--23. 1. "DMA_DSP2_DREQ_5_IRQ_5," newline hexmask.long.byte 0x3E0 0.--7. 1. "DMA_DSP2_DREQ_4_IRQ_4," line.long 0x3E4 "CTRL_CORE_DMA_DSP2_DREQ_6_7," hexmask.long.byte 0x3E4 16.--23. 1. "DMA_DSP2_DREQ_7_IRQ_7," newline hexmask.long.byte 0x3E4 0.--7. 1. "DMA_DSP2_DREQ_6_IRQ_6," line.long 0x3E8 "CTRL_CORE_DMA_DSP2_DREQ_8_9," hexmask.long.byte 0x3E8 16.--23. 1. "DMA_DSP2_DREQ_9_IRQ_9," newline hexmask.long.byte 0x3E8 0.--7. 1. "DMA_DSP2_DREQ_8_IRQ_8," line.long 0x3EC "CTRL_CORE_DMA_DSP2_DREQ_10_11," hexmask.long.byte 0x3EC 16.--23. 1. "DMA_DSP2_DREQ_11_IRQ_11," newline hexmask.long.byte 0x3EC 0.--7. 1. "DMA_DSP2_DREQ_10_IRQ_10," line.long 0x3F0 "CTRL_CORE_DMA_DSP2_DREQ_12_13," hexmask.long.byte 0x3F0 16.--23. 1. "DMA_DSP2_DREQ_13_IRQ_13," newline hexmask.long.byte 0x3F0 0.--7. 1. "DMA_DSP2_DREQ_12_IRQ_12," line.long 0x3F4 "CTRL_CORE_DMA_DSP2_DREQ_14_15," hexmask.long.byte 0x3F4 16.--23. 1. "DMA_DSP2_DREQ_15_IRQ_15," newline hexmask.long.byte 0x3F4 0.--7. 1. "DMA_DSP2_DREQ_14_IRQ_14," line.long 0x3F8 "CTRL_CORE_DMA_DSP2_DREQ_16_17," hexmask.long.byte 0x3F8 16.--23. 1. "DMA_DSP2_DREQ_17_IRQ_17," newline hexmask.long.byte 0x3F8 0.--7. 1. "DMA_DSP2_DREQ_16_IRQ_16," line.long 0x3FC "CTRL_CORE_DMA_DSP2_DREQ_18_19," hexmask.long.byte 0x3FC 16.--23. 1. "DMA_DSP2_DREQ_19_IRQ_19," newline hexmask.long.byte 0x3FC 0.--7. 1. "DMA_DSP2_DREQ_18_IRQ_18," group.long 0xD4C++0x07 line.long 0x00 "CTRL_CORE_OVS_DMARQ_IO_MUX," hexmask.long.byte 0x00 8.--15. 1. "OVS_DMARQ_IO_MUX_2," newline hexmask.long.byte 0x00 0.--7. 1. "OVS_DMARQ_IO_MUX_1," line.long 0x04 "CTRL_CORE_OVS_IRQ_IO_MUX," hexmask.long.word 0x04 9.--17. 1. "OVS_IRQ_IO_MUX_2," newline hexmask.long.word 0x04 0.--8. 1. "OVS_IRQ_IO_MUX_1," group.long 0xE00++0x07 line.long 0x00 "CTRL_CORE_CONTROL_PBIAS,PBIASLITE control" bitfld.long 0x00 27. "SDCARD_BIAS_PWRDNZ,PWRDNZ control to SDCARD BIAS" "0,1" newline bitfld.long 0x00 26. "SDCARD_IO_PWRDNZ,PWRDNZ control to SDCARD IO" "0,1" newline bitfld.long 0x00 25. "SDCARD_BIAS_HIZ_MODE,HIZ_MODE from SDCARD PBIAS" "0,1" newline rbitfld.long 0x00 24. "SDCARD_BIAS_SUPPLY_HI_OUT,SUPPLY_HI_OUT from SDCARD PBIAS" "0,1" newline rbitfld.long 0x00 23. "SDCARD_BIAS_VMODE_ERROR,VMODE ERROR from SDCARD PBIAS" "0,1" newline bitfld.long 0x00 21. "SDCARD_BIAS_VMODE,VMODE control to SDCARD PBIAS" "0,1" line.long 0x04 "CTRL_CORE_CONTROL_I2C_0,I2C pads control 0" bitfld.long 0x04 31. "I2C4_SDA_GLFENB,Active_high glitch free operation enable pin for i2c4 receiver - DISABLE" "I2C4_SDA_GLFENB_0,I2C4_SDA_GLFENB_1" newline bitfld.long 0x04 30. "I2C4_SDA_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c4 - ENABLE" "I2C4_SDA_PULLUPRESX_0,I2C4_SDA_PULLUPRESX_1" newline bitfld.long 0x04 29. "I2C3_SDA_GLFENB,Active_high glitch free operation enable pin for i2c3 receiver - DISABLE" "I2C3_SDA_GLFENB_0,I2C3_SDA_GLFENB_1" newline bitfld.long 0x04 28. "I2C3_SDA_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c3 - ENABLE" "I2C3_SDA_PULLUPRESX_0,I2C3_SDA_PULLUPRESX_1" newline bitfld.long 0x04 27. "I2C2_SDA_GLFENB,Active_high glitch free operation enable pin for i2c2 receiver - DISABLE" "I2C2_SDA_GLFENB_0,I2C2_SDA_GLFENB_1" newline bitfld.long 0x04 26. "I2C2_SDA_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c2 - ENABLE" "I2C2_SDA_PULLUPRESX_0,I2C2_SDA_PULLUPRESX_1" newline bitfld.long 0x04 25. "I2C1_PMIC_SDA_GLFENB,Active_high glitch free operation enable pin for i2c1 receiver - DISABLE" "I2C1_PMIC_SDA_GLFENB_0,I2C1_PMIC_SDA_GLFENB_1" newline bitfld.long 0x04 24. "I2C1_PMIC_SDA_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c1 - ENABLE" "I2C1_PMIC_SDA_PULLUPRESX_0,I2C1_PMIC_SDA_PULLUPRESX_1" newline bitfld.long 0x04 23. "I2C4_SCL_GLFENB,Active_high glitch free operation enable pin for i2c4 receiver - DISABLE" "I2C4_SCL_GLFENB_0,I2C4_SCL_GLFENB_1" newline bitfld.long 0x04 22. "I2C4_SCL_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c4 - ENABLE" "I2C4_SCL_PULLUPRESX_0,I2C4_SCL_PULLUPRESX_1" newline bitfld.long 0x04 21. "I2C3_SCL_GLFENB,Active_high glitch free operation enable pin for i2c3 receiver - DISABLE" "I2C3_SCL_GLFENB_0,I2C3_SCL_GLFENB_1" newline bitfld.long 0x04 20. "I2C3_SCL_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c3 - ENABLE" "I2C3_SCL_PULLUPRESX_0,I2C3_SCL_PULLUPRESX_1" newline bitfld.long 0x04 19. "I2C2_SCL_GLFENB,Active_high glitch free operation enable pin for i2c2 receiver - DISABLE" "I2C2_SCL_GLFENB_0,I2C2_SCL_GLFENB_1" newline bitfld.long 0x04 18. "I2C2_SCL_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c2 - ENABLE" "I2C2_SCL_PULLUPRESX_0,I2C2_SCL_PULLUPRESX_1" newline bitfld.long 0x04 17. "I2C1_PMIC_SCL_GLFENB,Active_high glitch free operation enable pin for i2c1_pmic receiver - DISABLE" "I2C1_PMIC_SCL_GLFENB_0,I2C1_PMIC_SCL_GLFENB_1" newline bitfld.long 0x04 16. "I2C1_PMIC_SCL_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c1_pmic - ENABLE" "I2C1_PMIC_SCL_PULLUPRESX_0,I2C1_PMIC_SCL_PULLUPRESX_1" newline bitfld.long 0x04 15. "I2C5_SDA_GLFENB,Active_high glitch free operation enable pin for i2c5 receiver - DISABLE" "I2C5_SDA_GLFENB_0,I2C5_SDA_GLFENB_1" newline bitfld.long 0x04 14. "I2C5_SDA_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c5 - ENABLE" "I2C5_SDA_PULLUPRESX_0,I2C5_SDA_PULLUPRESX_1" newline bitfld.long 0x04 13. "I2C5_SCL_GLFENB,Active_high glitch free operation enable pin for i2c5 receiver - DISABLE" "I2C5_SCL_GLFENB_0,I2C5_SCL_GLFENB_1" newline bitfld.long 0x04 12. "I2C5_SCL_PULLUPRESX,Active_low internal pull_up resistor enabled for i2c5 - ENABLE" "I2C5_SCL_PULLUPRESX_0,I2C5_SCL_PULLUPRESX_1" group.long 0xE0C++0x03 line.long 0x00 "CTRL_CORE_CONTROL_HDMI_TX_PHY,HDMI TX PHY control" bitfld.long 0x00 30. "HDMITXPHY_TXVALID," "0,1" newline bitfld.long 0x00 29. "HDMITXPHY_ENBYPASSCLK," "0,1" newline bitfld.long 0x00 28. "HDMITXPHY_PD_PULLUPDET," "0,1" group.long 0xE1C++0x07 line.long 0x00 "CTRL_CORE_CONTROL_USB2PHYCORE,USB2PHYCORE control" bitfld.long 0x00 31. "USB2PHY_AUTORESUME_EN,Auto resume enable" "0,1" newline bitfld.long 0x00 30. "USB2PHY_DISCHGDET,Disable charger detect" "0,1" newline bitfld.long 0x00 29. "USB2PHY_GPIOMODE,GPIO mode" "0,1" newline bitfld.long 0x00 28. "USB2PHY_CHG_DET_EXT_CTL,Charge detect external control" "0,1" newline bitfld.long 0x00 27. "USB2PHY_RDM_PD_CHGDET_EN,DM Pull down control" "0,1" newline bitfld.long 0x00 26. "USB2PHY_RDP_PU_CHGDET_EN,DP Pull up control" "0,1" newline bitfld.long 0x00 25. "USB2PHY_CHG_VSRC_EN,VSRC enable on DP line:Host charger case" "0,1" newline bitfld.long 0x00 24. "USB2PHY_CHG_ISINK_EN,ISINK enable on DM line:Host charger case" "0,1" newline rbitfld.long 0x00 21.--23. "USB2PHY_CHG_DET_STATUS,Status of charger detection" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x00 20. "USB2PHY_CHG_DET_DM_COMP,Output of the comparator on DM during the resistor host detect protocol" "0,1" newline rbitfld.long 0x00 19. "USB2PHY_CHG_DET_DP_COMP,Output of the comparator on DP during the resistor host detect protocol" "0,1" newline rbitfld.long 0x00 18. "USB2PHY_DATADET,Output of the charger detect comparator" "0,1" newline bitfld.long 0x00 17. "USB2PHY_SINKONDP,When '1' current sink is connected to DP instead of DM" "0,1" newline bitfld.long 0x00 16. "USB2PHY_SRCONDM,When '1' voltage source is connected to DP instead of DM" "0,1" newline bitfld.long 0x00 15. "USB2PHY_RESTARTCHGDET,restartchgdet = '1' for 1 msec cause the CD_START to reset" "0,1" newline rbitfld.long 0x00 14. "USB2PHY_CHGDETDONE,Status indicates that charger detection protocol is over" "0,1" newline rbitfld.long 0x00 13. "USB2PHY_CHGDETECTED,Output of the charger detection protocol" "0,1" newline bitfld.long 0x00 12. "USB2PHY_MCPCPUEN,MCPC Pull up enable" "0,1" newline bitfld.long 0x00 11. "USB2PHY_MCPCMODEEN,MCPC Mode enable" "0,1" newline rbitfld.long 0x00 10. "USB2PHY_RESETDONEMCLK,OCP reset status" "0,1" newline rbitfld.long 0x00 9. "USB2PHY_UTMIRESETDONE,UTMI FSM reset status" "0,1" newline bitfld.long 0x00 7. "USB2PHY_DATAPOLARITYN,Data polarity" "0,1" newline rbitfld.long 0x00 6. "USBDPLL_FREQLOCK,Status from USB DPLL" "0,1" newline rbitfld.long 0x00 5. "USB2PHY_RESETDONETCLK,resetdonetclk status from USB2PHY" "0,1" line.long 0x04 "CTRL_CORE_CONTROL_HDMI_1,HDMI pads control 1" bitfld.long 0x04 31. "HDMI_DDC_SDA_GLFENB,Active_high glitch free operation enable pin for hdmi_ddc_sda receiver - DISABLE" "HDMI_DDC_SDA_GLFENB_0,HDMI_DDC_SDA_GLFENB_1" newline bitfld.long 0x04 30. "HDMI_DDC_SDA_PULLUPRESX,Active_low internal pull_up resistor enabled for hdmi_ddc_sda - ENABLE" "HDMI_DDC_SDA_PULLUPRESX_0,HDMI_DDC_SDA_PULLUPRESX_1" newline bitfld.long 0x04 29. "HDMI_DDC_SCL_GLFENB,Active_high glitch free operation enable pin for hdmi_ddc_scl receiver - DISABLE" "HDMI_DDC_SCL_GLFENB_0,HDMI_DDC_SCL_GLFENB_1" newline bitfld.long 0x04 28. "HDMI_DDC_SCL_PULLUPRESX,Active_low internal pull_up resistor enabled for hdmi_ddc_scl - ENABLE" "HDMI_DDC_SCL_PULLUPRESX_0,HDMI_DDC_SCL_PULLUPRESX_1" newline bitfld.long 0x04 27. "HDMI_DDC_SDA_HSMODE,Active-high selection for I2C High-Speed mode - DISABLE" "HDMI_DDC_SDA_HSMODE_0,HDMI_DDC_SDA_HSMODE_1" newline bitfld.long 0x04 26. "HDMI_DDC_SCL_HSMODE,Active-high selection for I2C High-Speed mode - DISABLE" "HDMI_DDC_SCL_HSMODE_0,HDMI_DDC_SCL_HSMODE_1" group.long 0xE30++0x1B line.long 0x00 "CTRL_CORE_CONTROL_DDRCACH1_0,ddrcaCH1 control" bitfld.long 0x00 29.--31. "DDRCH1_PART0_I,PART0 Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 26.--28. "DDRCH1_PART0_SR,PART0 Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24.--25. "DDRCH1_PART0_WD,PART0 Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x00 21.--23. "DDRCH1_PART5A_I,PART5A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. "DDRCH1_PART5A_SR,PART5A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--17. "DDRCH1_PART5A_WD,PART5A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x00 13.--15. "DDRCH1_PART5B_I,PART5B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--12. "DDRCH1_PART5B_SR,PART5B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--9. "DDRCH1_PART5B_WD,PART5B Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x00 5.--7. "DDRCH1_PART6_I,PART6 Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2.--4. "DDRCH1_PART6_SR,PART6 Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--1. "DDRCH1_PART6_WD,PART6 Weak driver control WD[1:0]" "0,1,2,3" line.long 0x04 "CTRL_CORE_CONTROL_DDRCACH2_0,ddrcaCH2 control" bitfld.long 0x04 29.--31. "DDRCH2_PART0_I,PART0 Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 26.--28. "DDRCH2_PART0_SR,PART0 Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 24.--25. "DDRCH2_PART0_WD,PART0 Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x04 21.--23. "DDRCH2_PART5A_I,PART5A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 18.--20. "DDRCH2_PART5A_SR,PART5A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 16.--17. "DDRCH2_PART5A_WD,PART5A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x04 13.--15. "DDRCH2_PART5B_I,PART5B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 10.--12. "DDRCH2_PART5B_SR,PART5B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 8.--9. "DDRCH2_PART5B_WD,PART5B Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x04 5.--7. "DDRCH2_PART6_I,PART6 Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 2.--4. "DDRCH2_PART6_SR,PART6 Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--1. "DDRCH2_PART6_WD,PART6 Weak driver control WD[1:0]" "0,1,2,3" line.long 0x08 "CTRL_CORE_CONTROL_DDRCH1_0,DDRCH1 control 0" bitfld.long 0x08 29.--31. "DDRCH1_PART1A_I,PART1A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 26.--28. "DDRCH1_PART1A_SR,PART1A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 24.--25. "DDRCH1_PART1A_WD,PART1A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x08 21.--23. "DDRCH1_PART1B_I,PART1B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 18.--20. "DDRCH1_PART1B_SR,PART1B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 16.--17. "DDRCH1_PART1B_WD,PART1B Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x08 13.--15. "DDRCH1_PART2A_I,PART2A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 10.--12. "DDRCH1_PART2A_SR,PART2A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 8.--9. "DDRCH1_PART2A_WD,PART2A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x08 5.--7. "DDRCH1_PART2B_I,PART2B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 2.--4. "DDRCH1_PART2B_SR,PART2B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0.--1. "DDRCH1_PART2B_WD,PART2B Weak driver control WD[1:0]" "0,1,2,3" line.long 0x0C "CTRL_CORE_CONTROL_DDRCH1_1,DDRCH1 control 1" bitfld.long 0x0C 29.--31. "DDRCH1_PART3A_I,PART3A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 26.--28. "DDRCH1_PART3A_SR,PART3A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 24.--25. "DDRCH1_PART3A_WD,PART3A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x0C 21.--23. "DDRCH1_PART3B_I,PART3B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 18.--20. "DDRCH1_PART3B_SR,PART3B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 16.--17. "DDRCH1_PART3B_WD,PART3B Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x0C 13.--15. "DDRCH1_PART4A_I,PART4A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--12. "DDRCH1_PART4A_SR,PART4A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 8.--9. "DDRCH1_PART4A_WD,PART4A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x0C 5.--7. "DDRCH1_PART4B_I,PART4B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 2.--4. "DDRCH1_PART4B_SR,PART4B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 0.--1. "DDRCH1_PART4B_WD,PART4B Weak driver control WD[1:0]" "0,1,2,3" line.long 0x10 "CTRL_CORE_CONTROL_DDRCH2_0,DDRCH2 control 0" bitfld.long 0x10 29.--31. "DDRCH2_PART1A_I,PART1A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 26.--28. "DDRCH2_PART1A_SR,PART1A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24.--25. "DDRCH2_PART1A_WD,PART1A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x10 21.--23. "DDRCH2_PART1B_I,PART1B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 18.--20. "DDRCH2_PART1B_SR,PART1B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 16.--17. "DDRCH2_PART1B_WD,PART1B Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x10 13.--15. "DDRCH2_PART2A_I,PART2A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 10.--12. "DDRCH2_PART2A_SR,PART2A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8.--9. "DDRCH2_PART2A_WD,PART2A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x10 5.--7. "DDRCH2_PART2B_I,PART2B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 2.--4. "DDRCH2_PART2B_SR,PART2B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--1. "DDRCH2_PART2B_WD,PART2B Weak driver control WD[1:0]" "0,1,2,3" line.long 0x14 "CTRL_CORE_CONTROL_DDRCH2_1,DDRCH2 control 1" bitfld.long 0x14 29.--31. "DDRCH2_PART3A_I,PART3A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 26.--28. "DDRCH2_PART3A_SR,PART3A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 24.--25. "DDRCH2_PART3A_WD,PART3A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x14 21.--23. "DDRCH2_PART3B_I,PART3B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 18.--20. "DDRCH2_PART3B_SR,PART3B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 16.--17. "DDRCH2_PART3B_WD,PART3B Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x14 13.--15. "DDRCH2_PART4A_I,PART4A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 10.--12. "DDRCH2_PART4A_SR,PART4A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8.--9. "DDRCH2_PART4A_WD,PART4A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x14 5.--7. "DDRCH2_PART4B_I,PART4B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 2.--4. "DDRCH2_PART4B_SR,PART4B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--1. "DDRCH2_PART4B_WD,PART4B Weak driver control WD[1:0]" "0,1,2,3" line.long 0x18 "CTRL_CORE_CONTROL_DDRCH1_2," bitfld.long 0x18 21.--23. "DDRCH1_PART7A_I,PART7A Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 18.--20. "DDRCH1_PART7A_SR,PART7A Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 16.--17. "DDRCH1_PART7A_WD,PART7A Weak driver control WD[1:0]" "0,1,2,3" newline bitfld.long 0x18 13.--15. "DDRCH1_PART7B_I,PART7B Impedence control I[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 10.--12. "DDRCH1_PART7B_SR,PART7B Slew Rate control SR[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--9. "DDRCH1_PART7B_WD,PART7B Weak driver control WD[1:0]" "0,1,2,3" group.long 0xE50++0x07 line.long 0x00 "CTRL_CORE_CONTROL_DDRIO_0," bitfld.long 0x00 19. "DDRCH1_VREF_DQ0_INT_CCAP0,Selection for coupling cap connection - DISABLE" "DDRCH1_VREF_DQ0_INT_CCAP0_0,DDRCH1_VREF_DQ0_INT_CCAP0_1" newline bitfld.long 0x00 18. "DDRCH1_VREF_DQ0_INT_CCAP1,Selection for coupling cap connection - DISABLE" "DDRCH1_VREF_DQ0_INT_CCAP1_0,DDRCH1_VREF_DQ0_INT_CCAP1_1" newline bitfld.long 0x00 17. "DDRCH1_VREF_DQ0_INT_TAP0,Selection for internal reference voltage drive - DISABLE" "DDRCH1_VREF_DQ0_INT_TAP0_0,DDRCH1_VREF_DQ0_INT_TAP0_1" newline bitfld.long 0x00 16. "DDRCH1_VREF_DQ0_INT_TAP1,Selection for internal reference voltage drive - DISABLE" "DDRCH1_VREF_DQ0_INT_TAP1_0,DDRCH1_VREF_DQ0_INT_TAP1_1" newline bitfld.long 0x00 15. "DDRCH1_VREF_DQ0_INT_EN,Enable - DISABLE" "DDRCH1_VREF_DQ0_INT_EN_0,DDRCH1_VREF_DQ0_INT_EN_1" newline bitfld.long 0x00 14. "DDRCH1_VREF_DQ1_INT_CCAP0,Selection for coupling cap connection - DISABLE" "DDRCH1_VREF_DQ1_INT_CCAP0_0,DDRCH1_VREF_DQ1_INT_CCAP0_1" newline bitfld.long 0x00 13. "DDRCH1_VREF_DQ1_INT_CCAP1,Selection for coupling cap connection - DISABLE" "DDRCH1_VREF_DQ1_INT_CCAP1_0,DDRCH1_VREF_DQ1_INT_CCAP1_1" newline bitfld.long 0x00 12. "DDRCH1_VREF_DQ1_INT_TAP0,Selection for internal reference voltage drive - DISABLE" "DDRCH1_VREF_DQ1_INT_TAP0_0,DDRCH1_VREF_DQ1_INT_TAP0_1" newline bitfld.long 0x00 11. "DDRCH1_VREF_DQ1_INT_TAP1,Selection for internal reference voltage drive - DISABLE" "DDRCH1_VREF_DQ1_INT_TAP1_0,DDRCH1_VREF_DQ1_INT_TAP1_1" newline bitfld.long 0x00 10. "DDRCH1_VREF_DQ1_INT_EN,Enable - DISABLE" "DDRCH1_VREF_DQ1_INT_EN_0,DDRCH1_VREF_DQ1_INT_EN_1" line.long 0x04 "CTRL_CORE_CONTROL_DDRIO_1," bitfld.long 0x04 26. "DDRCH2_VREF_DQ0_INT_CCAP0,Selection for coupling cap connection - DISABLE" "DDRCH2_VREF_DQ0_INT_CCAP0_0,DDRCH2_VREF_DQ0_INT_CCAP0_1" newline bitfld.long 0x04 25. "DDRCH2_VREF_DQ0_INT_CCAP1,Selection for coupling cap connection - DISABLE" "DDRCH2_VREF_DQ0_INT_CCAP1_0,DDRCH2_VREF_DQ0_INT_CCAP1_1" newline bitfld.long 0x04 24. "DDRCH2_VREF_DQ0_INT_TAP0,Selection for internal reference voltage drive - DISABLE" "DDRCH2_VREF_DQ0_INT_TAP0_0,DDRCH2_VREF_DQ0_INT_TAP0_1" newline bitfld.long 0x04 23. "DDRCH2_VREF_DQ0_INT_TAP1,Selection for internal reference voltage drive - DISABLE" "DDRCH2_VREF_DQ0_INT_TAP1_0,DDRCH2_VREF_DQ0_INT_TAP1_1" newline bitfld.long 0x04 22. "DDRCH2_VREF_DQ0_INT_EN,Enable - DISABLE" "DDRCH2_VREF_DQ0_INT_EN_0,DDRCH2_VREF_DQ0_INT_EN_1" newline bitfld.long 0x04 21. "DDRCH2_VREF_DQ1_INT_CCAP0,Selection for coupling cap connection - DISABLE" "DDRCH2_VREF_DQ1_INT_CCAP0_0,DDRCH2_VREF_DQ1_INT_CCAP0_1" newline bitfld.long 0x04 20. "DDRCH2_VREF_DQ1_INT_CCAP1,Selection for coupling cap connection - DISABLE" "DDRCH2_VREF_DQ1_INT_CCAP1_0,DDRCH2_VREF_DQ1_INT_CCAP1_1" newline bitfld.long 0x04 19. "DDRCH2_VREF_DQ1_INT_TAP0,Selection for internal reference voltage drive - DISABLE" "DDRCH2_VREF_DQ1_INT_TAP0_0,DDRCH2_VREF_DQ1_INT_TAP0_1" newline bitfld.long 0x04 18. "DDRCH2_VREF_DQ1_INT_TAP1,Selection for internal reference voltage drive - DISABLE" "DDRCH2_VREF_DQ1_INT_TAP1_0,DDRCH2_VREF_DQ1_INT_TAP1_1" newline bitfld.long 0x04 17. "DDRCH2_VREF_DQ1_INT_EN,Enable - DISABLE" "DDRCH2_VREF_DQ1_INT_EN_0,DDRCH2_VREF_DQ1_INT_EN_1" group.long 0xE5C++0x03 line.long 0x00 "CTRL_CORE_CONTROL_HYST_1,Register for hysteresis control of the MMC1 pads" bitfld.long 0x00 31. "SDCARD_HYST,hysteresis control for sdcard" "0,1" newline bitfld.long 0x00 29.--30. "SDCARD_IC,Drive strength control for MMC1 pads In 3V signaling mode" "0,1,2,3" group.long 0xE74++0x07 line.long 0x00 "CTRL_CORE_SRCOMP_NORTH_SIDE," bitfld.long 0x00 30. "USB2PHY_AUTORESUME_EN," "0,1" newline bitfld.long 0x00 29. "USB2PHY_DISCHGDET," "0,1" newline bitfld.long 0x00 28. "USB2PHY_PD," "0,1" newline rbitfld.long 0x00 20. "USB2PHY_CHG_DET_DM_COMP," "0,1" newline rbitfld.long 0x00 19. "USB2PHY_CHG_DET_DP_COMP," "0,1" newline rbitfld.long 0x00 18. "USB2PHY_DATADET," "0,1" newline rbitfld.long 0x00 17. "USB2PHY_CHGDETDONE," "0,1" newline rbitfld.long 0x00 16. "USB2PHY_CHGDETECTED," "0,1" newline rbitfld.long 0x00 15. "USB2PHY_RESETDONEMCLK," "0,1" newline rbitfld.long 0x00 14. "USB2PHY_UTMIRESETDONE," "0,1" newline rbitfld.long 0x00 13. "USBDPLL_FREQLOCK," "0,1" newline rbitfld.long 0x00 12. "USB2PHY_RESETDONETCLK," "0,1" newline bitfld.long 0x00 11. "USB2PHY_GPIOMODE," "0,1" newline bitfld.long 0x00 10. "USB2PHY_CHG_DET_EXT_CTL," "0,1" newline bitfld.long 0x00 9. "USB2PHY_RDM_PD_CHGDET_EN," "0,1" newline bitfld.long 0x00 8. "USB2PHY_RDP_PU_CHGDET_EN," "0,1" newline bitfld.long 0x00 7. "USB2PHY_CHG_VSRC_EN," "0,1" newline bitfld.long 0x00 6. "USB2PHY_CHG_ISINK_EN," "0,1" newline bitfld.long 0x00 5. "USB2PHY_SINKONDP," "0,1" newline bitfld.long 0x00 4. "USB2PHY_SRCONDM," "0,1" newline bitfld.long 0x00 3. "USB2PHY_RESTARTCHGDET," "0,1" newline bitfld.long 0x00 2. "USB2PHY_MCPCPUEN," "0,1" newline bitfld.long 0x00 1. "USB2PHY_MCPCMODEEN," "0,1" newline bitfld.long 0x00 0. "USB2PHY_DATAPOLARITYN," "0,1" line.long 0x04 "CTRL_CORE_SRCOMP_SOUTH_SIDE," bitfld.long 0x04 12.--14. "USB2PHY_CHG_DET_STATUS," "0,1,2,3,4,5,6,7" group.long 0x1400++0x3D7 line.long 0x00 "CTRL_CORE_PAD_GPMC_AD0," rbitfld.long 0x00 25. "GPMC_AD0_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD0_WAKEUPEVENT_0,GPMC_AD0_WAKEUPEVENT_1" newline bitfld.long 0x00 24. "GPMC_AD0_WAKEUPENABLE,- DISABLE" "GPMC_AD0_WAKEUPENABLE_0,GPMC_AD0_WAKEUPENABLE_1" newline bitfld.long 0x00 19. "GPMC_AD0_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD0_SLEWCONTROL_0,GPMC_AD0_SLEWCONTROL_1" newline bitfld.long 0x00 18. "GPMC_AD0_INPUTENABLE,- DISABLE" "GPMC_AD0_INPUTENABLE_0,GPMC_AD0_INPUTENABLE_1" newline bitfld.long 0x00 17. "GPMC_AD0_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD0_PULLTYPESELECT_0,GPMC_AD0_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "GPMC_AD0_PULLUDENABLE,- DISABLE" "GPMC_AD0_PULLUDENABLE_0,GPMC_AD0_PULLUDENABLE_1" newline bitfld.long 0x00 8. "GPMC_AD0_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD0_MODESELECT_0,GPMC_AD0_MODESELECT_1" newline bitfld.long 0x00 4.--7. "GPMC_AD0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "GPMC_AD0_MUXMODE,- SYSBOOT0_15" "GPMC_AD0_MUXMODE_0,?,GPMC_AD0_MUXMODE_2,GPMC_AD0_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD0_MUXMODE_14,GPMC_AD0_MUXMODE_15" line.long 0x04 "CTRL_CORE_PAD_GPMC_AD1," rbitfld.long 0x04 25. "GPMC_AD1_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD1_WAKEUPEVENT_0,GPMC_AD1_WAKEUPEVENT_1" newline bitfld.long 0x04 24. "GPMC_AD1_WAKEUPENABLE,- DISABLE" "GPMC_AD1_WAKEUPENABLE_0,GPMC_AD1_WAKEUPENABLE_1" newline bitfld.long 0x04 19. "GPMC_AD1_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD1_SLEWCONTROL_0,GPMC_AD1_SLEWCONTROL_1" newline bitfld.long 0x04 18. "GPMC_AD1_INPUTENABLE,- DISABLE" "GPMC_AD1_INPUTENABLE_0,GPMC_AD1_INPUTENABLE_1" newline bitfld.long 0x04 17. "GPMC_AD1_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD1_PULLTYPESELECT_0,GPMC_AD1_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "GPMC_AD1_PULLUDENABLE,- DISABLE" "GPMC_AD1_PULLUDENABLE_0,GPMC_AD1_PULLUDENABLE_1" newline bitfld.long 0x04 8. "GPMC_AD1_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD1_MODESELECT_0,GPMC_AD1_MODESELECT_1" newline bitfld.long 0x04 4.--7. "GPMC_AD1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "GPMC_AD1_MUXMODE,- SYSBOOT1_15" "GPMC_AD1_MUXMODE_0,?,GPMC_AD1_MUXMODE_2,GPMC_AD1_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD1_MUXMODE_14,GPMC_AD1_MUXMODE_15" line.long 0x08 "CTRL_CORE_PAD_GPMC_AD2," rbitfld.long 0x08 25. "GPMC_AD2_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD2_WAKEUPEVENT_0,GPMC_AD2_WAKEUPEVENT_1" newline bitfld.long 0x08 24. "GPMC_AD2_WAKEUPENABLE,- DISABLE" "GPMC_AD2_WAKEUPENABLE_0,GPMC_AD2_WAKEUPENABLE_1" newline bitfld.long 0x08 19. "GPMC_AD2_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD2_SLEWCONTROL_0,GPMC_AD2_SLEWCONTROL_1" newline bitfld.long 0x08 18. "GPMC_AD2_INPUTENABLE,- DISABLE" "GPMC_AD2_INPUTENABLE_0,GPMC_AD2_INPUTENABLE_1" newline bitfld.long 0x08 17. "GPMC_AD2_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD2_PULLTYPESELECT_0,GPMC_AD2_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "GPMC_AD2_PULLUDENABLE,- DISABLE" "GPMC_AD2_PULLUDENABLE_0,GPMC_AD2_PULLUDENABLE_1" newline bitfld.long 0x08 8. "GPMC_AD2_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD2_MODESELECT_0,GPMC_AD2_MODESELECT_1" newline bitfld.long 0x08 4.--7. "GPMC_AD2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "GPMC_AD2_MUXMODE,- SYSBOOT2_15" "GPMC_AD2_MUXMODE_0,?,GPMC_AD2_MUXMODE_2,GPMC_AD2_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD2_MUXMODE_14,GPMC_AD2_MUXMODE_15" line.long 0x0C "CTRL_CORE_PAD_GPMC_AD3," rbitfld.long 0x0C 25. "GPMC_AD3_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD3_WAKEUPEVENT_0,GPMC_AD3_WAKEUPEVENT_1" newline bitfld.long 0x0C 24. "GPMC_AD3_WAKEUPENABLE,- DISABLE" "GPMC_AD3_WAKEUPENABLE_0,GPMC_AD3_WAKEUPENABLE_1" newline bitfld.long 0x0C 19. "GPMC_AD3_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD3_SLEWCONTROL_0,GPMC_AD3_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "GPMC_AD3_INPUTENABLE,- DISABLE" "GPMC_AD3_INPUTENABLE_0,GPMC_AD3_INPUTENABLE_1" newline bitfld.long 0x0C 17. "GPMC_AD3_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD3_PULLTYPESELECT_0,GPMC_AD3_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "GPMC_AD3_PULLUDENABLE,- DISABLE" "GPMC_AD3_PULLUDENABLE_0,GPMC_AD3_PULLUDENABLE_1" newline bitfld.long 0x0C 8. "GPMC_AD3_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD3_MODESELECT_0,GPMC_AD3_MODESELECT_1" newline bitfld.long 0x0C 4.--7. "GPMC_AD3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "GPMC_AD3_MUXMODE,- SYSBOOT3_15" "GPMC_AD3_MUXMODE_0,?,GPMC_AD3_MUXMODE_2,GPMC_AD3_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD3_MUXMODE_14,GPMC_AD3_MUXMODE_15" line.long 0x10 "CTRL_CORE_PAD_GPMC_AD4," rbitfld.long 0x10 25. "GPMC_AD4_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD4_WAKEUPEVENT_0,GPMC_AD4_WAKEUPEVENT_1" newline bitfld.long 0x10 24. "GPMC_AD4_WAKEUPENABLE,- DISABLE" "GPMC_AD4_WAKEUPENABLE_0,GPMC_AD4_WAKEUPENABLE_1" newline bitfld.long 0x10 19. "GPMC_AD4_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD4_SLEWCONTROL_0,GPMC_AD4_SLEWCONTROL_1" newline bitfld.long 0x10 18. "GPMC_AD4_INPUTENABLE,- DISABLE" "GPMC_AD4_INPUTENABLE_0,GPMC_AD4_INPUTENABLE_1" newline bitfld.long 0x10 17. "GPMC_AD4_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD4_PULLTYPESELECT_0,GPMC_AD4_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "GPMC_AD4_PULLUDENABLE,- DISABLE" "GPMC_AD4_PULLUDENABLE_0,GPMC_AD4_PULLUDENABLE_1" newline bitfld.long 0x10 8. "GPMC_AD4_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD4_MODESELECT_0,GPMC_AD4_MODESELECT_1" newline bitfld.long 0x10 4.--7. "GPMC_AD4_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. "GPMC_AD4_MUXMODE,- SYSBOOT4_15" "GPMC_AD4_MUXMODE_0,?,GPMC_AD4_MUXMODE_2,GPMC_AD4_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD4_MUXMODE_14,GPMC_AD4_MUXMODE_15" line.long 0x14 "CTRL_CORE_PAD_GPMC_AD5," rbitfld.long 0x14 25. "GPMC_AD5_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD5_WAKEUPEVENT_0,GPMC_AD5_WAKEUPEVENT_1" newline bitfld.long 0x14 24. "GPMC_AD5_WAKEUPENABLE,- DISABLE" "GPMC_AD5_WAKEUPENABLE_0,GPMC_AD5_WAKEUPENABLE_1" newline bitfld.long 0x14 19. "GPMC_AD5_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD5_SLEWCONTROL_0,GPMC_AD5_SLEWCONTROL_1" newline bitfld.long 0x14 18. "GPMC_AD5_INPUTENABLE,- DISABLE" "GPMC_AD5_INPUTENABLE_0,GPMC_AD5_INPUTENABLE_1" newline bitfld.long 0x14 17. "GPMC_AD5_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD5_PULLTYPESELECT_0,GPMC_AD5_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "GPMC_AD5_PULLUDENABLE,- DISABLE" "GPMC_AD5_PULLUDENABLE_0,GPMC_AD5_PULLUDENABLE_1" newline bitfld.long 0x14 8. "GPMC_AD5_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD5_MODESELECT_0,GPMC_AD5_MODESELECT_1" newline bitfld.long 0x14 4.--7. "GPMC_AD5_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0.--3. "GPMC_AD5_MUXMODE,- SYSBOOT5_15" "GPMC_AD5_MUXMODE_0,?,GPMC_AD5_MUXMODE_2,GPMC_AD5_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD5_MUXMODE_14,GPMC_AD5_MUXMODE_15" line.long 0x18 "CTRL_CORE_PAD_GPMC_AD6," rbitfld.long 0x18 25. "GPMC_AD6_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD6_WAKEUPEVENT_0,GPMC_AD6_WAKEUPEVENT_1" newline bitfld.long 0x18 24. "GPMC_AD6_WAKEUPENABLE,- DISABLE" "GPMC_AD6_WAKEUPENABLE_0,GPMC_AD6_WAKEUPENABLE_1" newline bitfld.long 0x18 19. "GPMC_AD6_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD6_SLEWCONTROL_0,GPMC_AD6_SLEWCONTROL_1" newline bitfld.long 0x18 18. "GPMC_AD6_INPUTENABLE,- DISABLE" "GPMC_AD6_INPUTENABLE_0,GPMC_AD6_INPUTENABLE_1" newline bitfld.long 0x18 17. "GPMC_AD6_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD6_PULLTYPESELECT_0,GPMC_AD6_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "GPMC_AD6_PULLUDENABLE,- DISABLE" "GPMC_AD6_PULLUDENABLE_0,GPMC_AD6_PULLUDENABLE_1" newline bitfld.long 0x18 8. "GPMC_AD6_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD6_MODESELECT_0,GPMC_AD6_MODESELECT_1" newline bitfld.long 0x18 4.--7. "GPMC_AD6_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--3. "GPMC_AD6_MUXMODE,- SYSBOOT6_15" "GPMC_AD6_MUXMODE_0,?,GPMC_AD6_MUXMODE_2,GPMC_AD6_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD6_MUXMODE_14,GPMC_AD6_MUXMODE_15" line.long 0x1C "CTRL_CORE_PAD_GPMC_AD7," rbitfld.long 0x1C 25. "GPMC_AD7_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD7_WAKEUPEVENT_0,GPMC_AD7_WAKEUPEVENT_1" newline bitfld.long 0x1C 24. "GPMC_AD7_WAKEUPENABLE,- DISABLE" "GPMC_AD7_WAKEUPENABLE_0,GPMC_AD7_WAKEUPENABLE_1" newline bitfld.long 0x1C 19. "GPMC_AD7_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD7_SLEWCONTROL_0,GPMC_AD7_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "GPMC_AD7_INPUTENABLE,- DISABLE" "GPMC_AD7_INPUTENABLE_0,GPMC_AD7_INPUTENABLE_1" newline bitfld.long 0x1C 17. "GPMC_AD7_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD7_PULLTYPESELECT_0,GPMC_AD7_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "GPMC_AD7_PULLUDENABLE,- DISABLE" "GPMC_AD7_PULLUDENABLE_0,GPMC_AD7_PULLUDENABLE_1" newline bitfld.long 0x1C 8. "GPMC_AD7_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD7_MODESELECT_0,GPMC_AD7_MODESELECT_1" newline bitfld.long 0x1C 4.--7. "GPMC_AD7_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 0.--3. "GPMC_AD7_MUXMODE,- SYSBOOT7_15" "GPMC_AD7_MUXMODE_0,?,GPMC_AD7_MUXMODE_2,GPMC_AD7_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD7_MUXMODE_14,GPMC_AD7_MUXMODE_15" line.long 0x20 "CTRL_CORE_PAD_GPMC_AD8," rbitfld.long 0x20 25. "GPMC_AD8_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD8_WAKEUPEVENT_0,GPMC_AD8_WAKEUPEVENT_1" newline bitfld.long 0x20 24. "GPMC_AD8_WAKEUPENABLE,- DISABLE" "GPMC_AD8_WAKEUPENABLE_0,GPMC_AD8_WAKEUPENABLE_1" newline bitfld.long 0x20 19. "GPMC_AD8_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD8_SLEWCONTROL_0,GPMC_AD8_SLEWCONTROL_1" newline bitfld.long 0x20 18. "GPMC_AD8_INPUTENABLE,- DISABLE" "GPMC_AD8_INPUTENABLE_0,GPMC_AD8_INPUTENABLE_1" newline bitfld.long 0x20 17. "GPMC_AD8_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD8_PULLTYPESELECT_0,GPMC_AD8_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "GPMC_AD8_PULLUDENABLE,- DISABLE" "GPMC_AD8_PULLUDENABLE_0,GPMC_AD8_PULLUDENABLE_1" newline bitfld.long 0x20 8. "GPMC_AD8_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD8_MODESELECT_0,GPMC_AD8_MODESELECT_1" newline bitfld.long 0x20 4.--7. "GPMC_AD8_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20 0.--3. "GPMC_AD8_MUXMODE,- SYSBOOT8_15" "GPMC_AD8_MUXMODE_0,?,GPMC_AD8_MUXMODE_2,GPMC_AD8_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD8_MUXMODE_14,GPMC_AD8_MUXMODE_15" line.long 0x24 "CTRL_CORE_PAD_GPMC_AD9," rbitfld.long 0x24 25. "GPMC_AD9_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD9_WAKEUPEVENT_0,GPMC_AD9_WAKEUPEVENT_1" newline bitfld.long 0x24 24. "GPMC_AD9_WAKEUPENABLE,- DISABLE" "GPMC_AD9_WAKEUPENABLE_0,GPMC_AD9_WAKEUPENABLE_1" newline bitfld.long 0x24 19. "GPMC_AD9_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD9_SLEWCONTROL_0,GPMC_AD9_SLEWCONTROL_1" newline bitfld.long 0x24 18. "GPMC_AD9_INPUTENABLE,- DISABLE" "GPMC_AD9_INPUTENABLE_0,GPMC_AD9_INPUTENABLE_1" newline bitfld.long 0x24 17. "GPMC_AD9_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD9_PULLTYPESELECT_0,GPMC_AD9_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "GPMC_AD9_PULLUDENABLE,- DISABLE" "GPMC_AD9_PULLUDENABLE_0,GPMC_AD9_PULLUDENABLE_1" newline bitfld.long 0x24 8. "GPMC_AD9_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD9_MODESELECT_0,GPMC_AD9_MODESELECT_1" newline bitfld.long 0x24 4.--7. "GPMC_AD9_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x24 0.--3. "GPMC_AD9_MUXMODE,- SYSBOOT9_15" "GPMC_AD9_MUXMODE_0,?,GPMC_AD9_MUXMODE_2,GPMC_AD9_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD9_MUXMODE_14,GPMC_AD9_MUXMODE_15" line.long 0x28 "CTRL_CORE_PAD_GPMC_AD10," rbitfld.long 0x28 25. "GPMC_AD10_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD10_WAKEUPEVENT_0,GPMC_AD10_WAKEUPEVENT_1" newline bitfld.long 0x28 24. "GPMC_AD10_WAKEUPENABLE,- DISABLE" "GPMC_AD10_WAKEUPENABLE_0,GPMC_AD10_WAKEUPENABLE_1" newline bitfld.long 0x28 19. "GPMC_AD10_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD10_SLEWCONTROL_0,GPMC_AD10_SLEWCONTROL_1" newline bitfld.long 0x28 18. "GPMC_AD10_INPUTENABLE,- DISABLE" "GPMC_AD10_INPUTENABLE_0,GPMC_AD10_INPUTENABLE_1" newline bitfld.long 0x28 17. "GPMC_AD10_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD10_PULLTYPESELECT_0,GPMC_AD10_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "GPMC_AD10_PULLUDENABLE,- DISABLE" "GPMC_AD10_PULLUDENABLE_0,GPMC_AD10_PULLUDENABLE_1" newline bitfld.long 0x28 8. "GPMC_AD10_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD10_MODESELECT_0,GPMC_AD10_MODESELECT_1" newline bitfld.long 0x28 4.--7. "GPMC_AD10_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 0.--3. "GPMC_AD10_MUXMODE,- SYSBOOT10_15" "GPMC_AD10_MUXMODE_0,?,GPMC_AD10_MUXMODE_2,GPMC_AD10_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD10_MUXMODE_14,GPMC_AD10_MUXMODE_15" line.long 0x2C "CTRL_CORE_PAD_GPMC_AD11," rbitfld.long 0x2C 25. "GPMC_AD11_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD11_WAKEUPEVENT_0,GPMC_AD11_WAKEUPEVENT_1" newline bitfld.long 0x2C 24. "GPMC_AD11_WAKEUPENABLE,- DISABLE" "GPMC_AD11_WAKEUPENABLE_0,GPMC_AD11_WAKEUPENABLE_1" newline bitfld.long 0x2C 19. "GPMC_AD11_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD11_SLEWCONTROL_0,GPMC_AD11_SLEWCONTROL_1" newline bitfld.long 0x2C 18. "GPMC_AD11_INPUTENABLE,- DISABLE" "GPMC_AD11_INPUTENABLE_0,GPMC_AD11_INPUTENABLE_1" newline bitfld.long 0x2C 17. "GPMC_AD11_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD11_PULLTYPESELECT_0,GPMC_AD11_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "GPMC_AD11_PULLUDENABLE,- DISABLE" "GPMC_AD11_PULLUDENABLE_0,GPMC_AD11_PULLUDENABLE_1" newline bitfld.long 0x2C 8. "GPMC_AD11_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD11_MODESELECT_0,GPMC_AD11_MODESELECT_1" newline bitfld.long 0x2C 4.--7. "GPMC_AD11_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 0.--3. "GPMC_AD11_MUXMODE,- SYSBOOT11_15" "GPMC_AD11_MUXMODE_0,?,GPMC_AD11_MUXMODE_2,GPMC_AD11_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD11_MUXMODE_14,GPMC_AD11_MUXMODE_15" line.long 0x30 "CTRL_CORE_PAD_GPMC_AD12," rbitfld.long 0x30 25. "GPMC_AD12_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD12_WAKEUPEVENT_0,GPMC_AD12_WAKEUPEVENT_1" newline bitfld.long 0x30 24. "GPMC_AD12_WAKEUPENABLE,- DISABLE" "GPMC_AD12_WAKEUPENABLE_0,GPMC_AD12_WAKEUPENABLE_1" newline bitfld.long 0x30 19. "GPMC_AD12_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD12_SLEWCONTROL_0,GPMC_AD12_SLEWCONTROL_1" newline bitfld.long 0x30 18. "GPMC_AD12_INPUTENABLE,- DISABLE" "GPMC_AD12_INPUTENABLE_0,GPMC_AD12_INPUTENABLE_1" newline bitfld.long 0x30 17. "GPMC_AD12_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD12_PULLTYPESELECT_0,GPMC_AD12_PULLTYPESELECT_1" newline bitfld.long 0x30 16. "GPMC_AD12_PULLUDENABLE,- DISABLE" "GPMC_AD12_PULLUDENABLE_0,GPMC_AD12_PULLUDENABLE_1" newline bitfld.long 0x30 8. "GPMC_AD12_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD12_MODESELECT_0,GPMC_AD12_MODESELECT_1" newline bitfld.long 0x30 4.--7. "GPMC_AD12_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 0.--3. "GPMC_AD12_MUXMODE,- SYSBOOT12_15" "GPMC_AD12_MUXMODE_0,?,GPMC_AD12_MUXMODE_2,GPMC_AD12_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD12_MUXMODE_14,GPMC_AD12_MUXMODE_15" line.long 0x34 "CTRL_CORE_PAD_GPMC_AD13," rbitfld.long 0x34 25. "GPMC_AD13_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD13_WAKEUPEVENT_0,GPMC_AD13_WAKEUPEVENT_1" newline bitfld.long 0x34 24. "GPMC_AD13_WAKEUPENABLE,- DISABLE" "GPMC_AD13_WAKEUPENABLE_0,GPMC_AD13_WAKEUPENABLE_1" newline bitfld.long 0x34 19. "GPMC_AD13_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD13_SLEWCONTROL_0,GPMC_AD13_SLEWCONTROL_1" newline bitfld.long 0x34 18. "GPMC_AD13_INPUTENABLE,- DISABLE" "GPMC_AD13_INPUTENABLE_0,GPMC_AD13_INPUTENABLE_1" newline bitfld.long 0x34 17. "GPMC_AD13_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD13_PULLTYPESELECT_0,GPMC_AD13_PULLTYPESELECT_1" newline bitfld.long 0x34 16. "GPMC_AD13_PULLUDENABLE,- DISABLE" "GPMC_AD13_PULLUDENABLE_0,GPMC_AD13_PULLUDENABLE_1" newline bitfld.long 0x34 8. "GPMC_AD13_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD13_MODESELECT_0,GPMC_AD13_MODESELECT_1" newline bitfld.long 0x34 4.--7. "GPMC_AD13_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x34 0.--3. "GPMC_AD13_MUXMODE,- SYSBOOT13_15" "GPMC_AD13_MUXMODE_0,?,GPMC_AD13_MUXMODE_2,GPMC_AD13_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD13_MUXMODE_14,GPMC_AD13_MUXMODE_15" line.long 0x38 "CTRL_CORE_PAD_GPMC_AD14," rbitfld.long 0x38 25. "GPMC_AD14_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD14_WAKEUPEVENT_0,GPMC_AD14_WAKEUPEVENT_1" newline bitfld.long 0x38 24. "GPMC_AD14_WAKEUPENABLE,- DISABLE" "GPMC_AD14_WAKEUPENABLE_0,GPMC_AD14_WAKEUPENABLE_1" newline bitfld.long 0x38 19. "GPMC_AD14_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD14_SLEWCONTROL_0,GPMC_AD14_SLEWCONTROL_1" newline bitfld.long 0x38 18. "GPMC_AD14_INPUTENABLE,- DISABLE" "GPMC_AD14_INPUTENABLE_0,GPMC_AD14_INPUTENABLE_1" newline bitfld.long 0x38 17. "GPMC_AD14_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD14_PULLTYPESELECT_0,GPMC_AD14_PULLTYPESELECT_1" newline bitfld.long 0x38 16. "GPMC_AD14_PULLUDENABLE,- DISABLE" "GPMC_AD14_PULLUDENABLE_0,GPMC_AD14_PULLUDENABLE_1" newline bitfld.long 0x38 8. "GPMC_AD14_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD14_MODESELECT_0,GPMC_AD14_MODESELECT_1" newline bitfld.long 0x38 4.--7. "GPMC_AD14_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38 0.--3. "GPMC_AD14_MUXMODE,- SYSBOOT14_15" "GPMC_AD14_MUXMODE_0,?,GPMC_AD14_MUXMODE_2,GPMC_AD14_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD14_MUXMODE_14,GPMC_AD14_MUXMODE_15" line.long 0x3C "CTRL_CORE_PAD_GPMC_AD15," rbitfld.long 0x3C 25. "GPMC_AD15_WAKEUPEVENT,- NOWAKEUP" "GPMC_AD15_WAKEUPEVENT_0,GPMC_AD15_WAKEUPEVENT_1" newline bitfld.long 0x3C 24. "GPMC_AD15_WAKEUPENABLE,- DISABLE" "GPMC_AD15_WAKEUPENABLE_0,GPMC_AD15_WAKEUPENABLE_1" newline bitfld.long 0x3C 19. "GPMC_AD15_SLEWCONTROL,- SLOW_SLEW" "GPMC_AD15_SLEWCONTROL_0,GPMC_AD15_SLEWCONTROL_1" newline bitfld.long 0x3C 18. "GPMC_AD15_INPUTENABLE,- DISABLE" "GPMC_AD15_INPUTENABLE_0,GPMC_AD15_INPUTENABLE_1" newline bitfld.long 0x3C 17. "GPMC_AD15_PULLTYPESELECT,- PULL_DOWN" "GPMC_AD15_PULLTYPESELECT_0,GPMC_AD15_PULLTYPESELECT_1" newline bitfld.long 0x3C 16. "GPMC_AD15_PULLUDENABLE,- DISABLE" "GPMC_AD15_PULLUDENABLE_0,GPMC_AD15_PULLUDENABLE_1" newline bitfld.long 0x3C 8. "GPMC_AD15_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_AD15_MODESELECT_0,GPMC_AD15_MODESELECT_1" newline bitfld.long 0x3C 4.--7. "GPMC_AD15_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C 0.--3. "GPMC_AD15_MUXMODE,- SYSBOOT15_15" "GPMC_AD15_MUXMODE_0,?,GPMC_AD15_MUXMODE_2,GPMC_AD15_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,GPMC_AD15_MUXMODE_14,GPMC_AD15_MUXMODE_15" line.long 0x40 "CTRL_CORE_PAD_GPMC_A0," rbitfld.long 0x40 25. "GPMC_A0_WAKEUPEVENT,- NOWAKEUP" "GPMC_A0_WAKEUPEVENT_0,GPMC_A0_WAKEUPEVENT_1" newline bitfld.long 0x40 24. "GPMC_A0_WAKEUPENABLE,- DISABLE" "GPMC_A0_WAKEUPENABLE_0,GPMC_A0_WAKEUPENABLE_1" newline bitfld.long 0x40 19. "GPMC_A0_SLEWCONTROL,- SLOW_SLEW" "GPMC_A0_SLEWCONTROL_0,GPMC_A0_SLEWCONTROL_1" newline bitfld.long 0x40 18. "GPMC_A0_INPUTENABLE,- DISABLE" "GPMC_A0_INPUTENABLE_0,GPMC_A0_INPUTENABLE_1" newline bitfld.long 0x40 17. "GPMC_A0_PULLTYPESELECT,- PULL_DOWN" "GPMC_A0_PULLTYPESELECT_0,GPMC_A0_PULLTYPESELECT_1" newline bitfld.long 0x40 16. "GPMC_A0_PULLUDENABLE,- DISABLE" "GPMC_A0_PULLUDENABLE_0,GPMC_A0_PULLUDENABLE_1" newline bitfld.long 0x40 8. "GPMC_A0_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A0_MODESELECT_0,GPMC_A0_MODESELECT_1" newline bitfld.long 0x40 4.--7. "GPMC_A0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x40 0.--3. "GPMC_A0_MUXMODE,- VIN4B_D0_6" "GPMC_A0_MUXMODE_0,?,GPMC_A0_MUXMODE_2,GPMC_A0_MUXMODE_3,GPMC_A0_MUXMODE_4,GPMC_A0_MUXMODE_5,GPMC_A0_MUXMODE_6,GPMC_A0_MUXMODE_7,GPMC_A0_MUXMODE_8,?,?,?,?,?,GPMC_A0_MUXMODE_14,?" line.long 0x44 "CTRL_CORE_PAD_GPMC_A1," rbitfld.long 0x44 25. "GPMC_A1_WAKEUPEVENT,- NOWAKEUP" "GPMC_A1_WAKEUPEVENT_0,GPMC_A1_WAKEUPEVENT_1" newline bitfld.long 0x44 24. "GPMC_A1_WAKEUPENABLE,- DISABLE" "GPMC_A1_WAKEUPENABLE_0,GPMC_A1_WAKEUPENABLE_1" newline bitfld.long 0x44 19. "GPMC_A1_SLEWCONTROL,- SLOW_SLEW" "GPMC_A1_SLEWCONTROL_0,GPMC_A1_SLEWCONTROL_1" newline bitfld.long 0x44 18. "GPMC_A1_INPUTENABLE,- DISABLE" "GPMC_A1_INPUTENABLE_0,GPMC_A1_INPUTENABLE_1" newline bitfld.long 0x44 17. "GPMC_A1_PULLTYPESELECT,- PULL_DOWN" "GPMC_A1_PULLTYPESELECT_0,GPMC_A1_PULLTYPESELECT_1" newline bitfld.long 0x44 16. "GPMC_A1_PULLUDENABLE,- DISABLE" "GPMC_A1_PULLUDENABLE_0,GPMC_A1_PULLUDENABLE_1" newline bitfld.long 0x44 8. "GPMC_A1_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A1_MODESELECT_0,GPMC_A1_MODESELECT_1" newline bitfld.long 0x44 4.--7. "GPMC_A1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x44 0.--3. "GPMC_A1_MUXMODE,- VIN4B_D1_6" "GPMC_A1_MUXMODE_0,?,GPMC_A1_MUXMODE_2,GPMC_A1_MUXMODE_3,GPMC_A1_MUXMODE_4,GPMC_A1_MUXMODE_5,GPMC_A1_MUXMODE_6,GPMC_A1_MUXMODE_7,GPMC_A1_MUXMODE_8,?,?,?,?,?,GPMC_A1_MUXMODE_14,?" line.long 0x48 "CTRL_CORE_PAD_GPMC_A2," rbitfld.long 0x48 25. "GPMC_A2_WAKEUPEVENT,- NOWAKEUP" "GPMC_A2_WAKEUPEVENT_0,GPMC_A2_WAKEUPEVENT_1" newline bitfld.long 0x48 24. "GPMC_A2_WAKEUPENABLE,- DISABLE" "GPMC_A2_WAKEUPENABLE_0,GPMC_A2_WAKEUPENABLE_1" newline bitfld.long 0x48 19. "GPMC_A2_SLEWCONTROL,- SLOW_SLEW" "GPMC_A2_SLEWCONTROL_0,GPMC_A2_SLEWCONTROL_1" newline bitfld.long 0x48 18. "GPMC_A2_INPUTENABLE,- DISABLE" "GPMC_A2_INPUTENABLE_0,GPMC_A2_INPUTENABLE_1" newline bitfld.long 0x48 17. "GPMC_A2_PULLTYPESELECT,- PULL_DOWN" "GPMC_A2_PULLTYPESELECT_0,GPMC_A2_PULLTYPESELECT_1" newline bitfld.long 0x48 16. "GPMC_A2_PULLUDENABLE,- DISABLE" "GPMC_A2_PULLUDENABLE_0,GPMC_A2_PULLUDENABLE_1" newline bitfld.long 0x48 8. "GPMC_A2_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A2_MODESELECT_0,GPMC_A2_MODESELECT_1" newline bitfld.long 0x48 4.--7. "GPMC_A2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x48 0.--3. "GPMC_A2_MUXMODE,- VIN4B_D2_6" "GPMC_A2_MUXMODE_0,?,GPMC_A2_MUXMODE_2,GPMC_A2_MUXMODE_3,GPMC_A2_MUXMODE_4,GPMC_A2_MUXMODE_5,GPMC_A2_MUXMODE_6,GPMC_A2_MUXMODE_7,GPMC_A2_MUXMODE_8,?,?,?,?,?,GPMC_A2_MUXMODE_14,?" line.long 0x4C "CTRL_CORE_PAD_GPMC_A3," rbitfld.long 0x4C 25. "GPMC_A3_WAKEUPEVENT,- NOWAKEUP" "GPMC_A3_WAKEUPEVENT_0,GPMC_A3_WAKEUPEVENT_1" newline bitfld.long 0x4C 24. "GPMC_A3_WAKEUPENABLE,- DISABLE" "GPMC_A3_WAKEUPENABLE_0,GPMC_A3_WAKEUPENABLE_1" newline bitfld.long 0x4C 19. "GPMC_A3_SLEWCONTROL,- SLOW_SLEW" "GPMC_A3_SLEWCONTROL_0,GPMC_A3_SLEWCONTROL_1" newline bitfld.long 0x4C 18. "GPMC_A3_INPUTENABLE,- DISABLE" "GPMC_A3_INPUTENABLE_0,GPMC_A3_INPUTENABLE_1" newline bitfld.long 0x4C 17. "GPMC_A3_PULLTYPESELECT,- PULL_DOWN" "GPMC_A3_PULLTYPESELECT_0,GPMC_A3_PULLTYPESELECT_1" newline bitfld.long 0x4C 16. "GPMC_A3_PULLUDENABLE,- DISABLE" "GPMC_A3_PULLUDENABLE_0,GPMC_A3_PULLUDENABLE_1" newline bitfld.long 0x4C 8. "GPMC_A3_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A3_MODESELECT_0,GPMC_A3_MODESELECT_1" newline bitfld.long 0x4C 4.--7. "GPMC_A3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x4C 0.--3. "GPMC_A3_MUXMODE,- VIN4B_D3_6" "GPMC_A3_MUXMODE_0,GPMC_A3_MUXMODE_1,GPMC_A3_MUXMODE_2,GPMC_A3_MUXMODE_3,GPMC_A3_MUXMODE_4,GPMC_A3_MUXMODE_5,GPMC_A3_MUXMODE_6,GPMC_A3_MUXMODE_7,GPMC_A3_MUXMODE_8,?,?,?,?,?,GPMC_A3_MUXMODE_14,?" line.long 0x50 "CTRL_CORE_PAD_GPMC_A4," rbitfld.long 0x50 25. "GPMC_A4_WAKEUPEVENT,- NOWAKEUP" "GPMC_A4_WAKEUPEVENT_0,GPMC_A4_WAKEUPEVENT_1" newline bitfld.long 0x50 24. "GPMC_A4_WAKEUPENABLE,- DISABLE" "GPMC_A4_WAKEUPENABLE_0,GPMC_A4_WAKEUPENABLE_1" newline bitfld.long 0x50 19. "GPMC_A4_SLEWCONTROL,- SLOW_SLEW" "GPMC_A4_SLEWCONTROL_0,GPMC_A4_SLEWCONTROL_1" newline bitfld.long 0x50 18. "GPMC_A4_INPUTENABLE,- DISABLE" "GPMC_A4_INPUTENABLE_0,GPMC_A4_INPUTENABLE_1" newline bitfld.long 0x50 17. "GPMC_A4_PULLTYPESELECT,- PULL_DOWN" "GPMC_A4_PULLTYPESELECT_0,GPMC_A4_PULLTYPESELECT_1" newline bitfld.long 0x50 16. "GPMC_A4_PULLUDENABLE,- DISABLE" "GPMC_A4_PULLUDENABLE_0,GPMC_A4_PULLUDENABLE_1" newline bitfld.long 0x50 8. "GPMC_A4_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A4_MODESELECT_0,GPMC_A4_MODESELECT_1" newline bitfld.long 0x50 4.--7. "GPMC_A4_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x50 0.--3. "GPMC_A4_MUXMODE,- VIN4B_D4_6" "GPMC_A4_MUXMODE_0,GPMC_A4_MUXMODE_1,GPMC_A4_MUXMODE_2,GPMC_A4_MUXMODE_3,GPMC_A4_MUXMODE_4,GPMC_A4_MUXMODE_5,GPMC_A4_MUXMODE_6,GPMC_A4_MUXMODE_7,GPMC_A4_MUXMODE_8,?,?,?,?,?,GPMC_A4_MUXMODE_14,?" line.long 0x54 "CTRL_CORE_PAD_GPMC_A5," rbitfld.long 0x54 25. "GPMC_A5_WAKEUPEVENT,- NOWAKEUP" "GPMC_A5_WAKEUPEVENT_0,GPMC_A5_WAKEUPEVENT_1" newline bitfld.long 0x54 24. "GPMC_A5_WAKEUPENABLE,- DISABLE" "GPMC_A5_WAKEUPENABLE_0,GPMC_A5_WAKEUPENABLE_1" newline bitfld.long 0x54 19. "GPMC_A5_SLEWCONTROL,- SLOW_SLEW" "GPMC_A5_SLEWCONTROL_0,GPMC_A5_SLEWCONTROL_1" newline bitfld.long 0x54 18. "GPMC_A5_INPUTENABLE,- DISABLE" "GPMC_A5_INPUTENABLE_0,GPMC_A5_INPUTENABLE_1" newline bitfld.long 0x54 17. "GPMC_A5_PULLTYPESELECT,- PULL_DOWN" "GPMC_A5_PULLTYPESELECT_0,GPMC_A5_PULLTYPESELECT_1" newline bitfld.long 0x54 16. "GPMC_A5_PULLUDENABLE,- DISABLE" "GPMC_A5_PULLUDENABLE_0,GPMC_A5_PULLUDENABLE_1" newline bitfld.long 0x54 8. "GPMC_A5_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A5_MODESELECT_0,GPMC_A5_MODESELECT_1" newline bitfld.long 0x54 4.--7. "GPMC_A5_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x54 0.--3. "GPMC_A5_MUXMODE,- VIN4B_D5_6" "GPMC_A5_MUXMODE_0,GPMC_A5_MUXMODE_1,GPMC_A5_MUXMODE_2,GPMC_A5_MUXMODE_3,GPMC_A5_MUXMODE_4,GPMC_A5_MUXMODE_5,GPMC_A5_MUXMODE_6,GPMC_A5_MUXMODE_7,GPMC_A5_MUXMODE_8,?,?,?,?,?,GPMC_A5_MUXMODE_14,?" line.long 0x58 "CTRL_CORE_PAD_GPMC_A6," rbitfld.long 0x58 25. "GPMC_A6_WAKEUPEVENT,- NOWAKEUP" "GPMC_A6_WAKEUPEVENT_0,GPMC_A6_WAKEUPEVENT_1" newline bitfld.long 0x58 24. "GPMC_A6_WAKEUPENABLE,- DISABLE" "GPMC_A6_WAKEUPENABLE_0,GPMC_A6_WAKEUPENABLE_1" newline bitfld.long 0x58 19. "GPMC_A6_SLEWCONTROL,- SLOW_SLEW" "GPMC_A6_SLEWCONTROL_0,GPMC_A6_SLEWCONTROL_1" newline bitfld.long 0x58 18. "GPMC_A6_INPUTENABLE,- DISABLE" "GPMC_A6_INPUTENABLE_0,GPMC_A6_INPUTENABLE_1" newline bitfld.long 0x58 17. "GPMC_A6_PULLTYPESELECT,- PULL_DOWN" "GPMC_A6_PULLTYPESELECT_0,GPMC_A6_PULLTYPESELECT_1" newline bitfld.long 0x58 16. "GPMC_A6_PULLUDENABLE,- DISABLE" "GPMC_A6_PULLUDENABLE_0,GPMC_A6_PULLUDENABLE_1" newline bitfld.long 0x58 8. "GPMC_A6_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A6_MODESELECT_0,GPMC_A6_MODESELECT_1" newline bitfld.long 0x58 4.--7. "GPMC_A6_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x58 0.--3. "GPMC_A6_MUXMODE,- VIN4B_D6_6" "GPMC_A6_MUXMODE_0,GPMC_A6_MUXMODE_1,GPMC_A6_MUXMODE_2,GPMC_A6_MUXMODE_3,GPMC_A6_MUXMODE_4,GPMC_A6_MUXMODE_5,GPMC_A6_MUXMODE_6,GPMC_A6_MUXMODE_7,GPMC_A6_MUXMODE_8,?,?,?,?,?,GPMC_A6_MUXMODE_14,?" line.long 0x5C "CTRL_CORE_PAD_GPMC_A7," rbitfld.long 0x5C 25. "GPMC_A7_WAKEUPEVENT,- NOWAKEUP" "GPMC_A7_WAKEUPEVENT_0,GPMC_A7_WAKEUPEVENT_1" newline bitfld.long 0x5C 24. "GPMC_A7_WAKEUPENABLE,- DISABLE" "GPMC_A7_WAKEUPENABLE_0,GPMC_A7_WAKEUPENABLE_1" newline bitfld.long 0x5C 19. "GPMC_A7_SLEWCONTROL,- SLOW_SLEW" "GPMC_A7_SLEWCONTROL_0,GPMC_A7_SLEWCONTROL_1" newline bitfld.long 0x5C 18. "GPMC_A7_INPUTENABLE,- DISABLE" "GPMC_A7_INPUTENABLE_0,GPMC_A7_INPUTENABLE_1" newline bitfld.long 0x5C 17. "GPMC_A7_PULLTYPESELECT,- PULL_DOWN" "GPMC_A7_PULLTYPESELECT_0,GPMC_A7_PULLTYPESELECT_1" newline bitfld.long 0x5C 16. "GPMC_A7_PULLUDENABLE,- DISABLE" "GPMC_A7_PULLUDENABLE_0,GPMC_A7_PULLUDENABLE_1" newline bitfld.long 0x5C 8. "GPMC_A7_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A7_MODESELECT_0,GPMC_A7_MODESELECT_1" newline bitfld.long 0x5C 4.--7. "GPMC_A7_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x5C 0.--3. "GPMC_A7_MUXMODE,- VIN4B_D7_6" "GPMC_A7_MUXMODE_0,GPMC_A7_MUXMODE_1,GPMC_A7_MUXMODE_2,GPMC_A7_MUXMODE_3,GPMC_A7_MUXMODE_4,GPMC_A7_MUXMODE_5,GPMC_A7_MUXMODE_6,GPMC_A7_MUXMODE_7,GPMC_A7_MUXMODE_8,?,?,?,?,?,GPMC_A7_MUXMODE_14,?" line.long 0x60 "CTRL_CORE_PAD_GPMC_A8," rbitfld.long 0x60 25. "GPMC_A8_WAKEUPEVENT,- NOWAKEUP" "GPMC_A8_WAKEUPEVENT_0,GPMC_A8_WAKEUPEVENT_1" newline bitfld.long 0x60 24. "GPMC_A8_WAKEUPENABLE,- DISABLE" "GPMC_A8_WAKEUPENABLE_0,GPMC_A8_WAKEUPENABLE_1" newline bitfld.long 0x60 19. "GPMC_A8_SLEWCONTROL,- SLOW_SLEW" "GPMC_A8_SLEWCONTROL_0,GPMC_A8_SLEWCONTROL_1" newline bitfld.long 0x60 18. "GPMC_A8_INPUTENABLE,- DISABLE" "GPMC_A8_INPUTENABLE_0,GPMC_A8_INPUTENABLE_1" newline bitfld.long 0x60 17. "GPMC_A8_PULLTYPESELECT,- PULL_DOWN" "GPMC_A8_PULLTYPESELECT_0,GPMC_A8_PULLTYPESELECT_1" newline bitfld.long 0x60 16. "GPMC_A8_PULLUDENABLE,- DISABLE" "GPMC_A8_PULLUDENABLE_0,GPMC_A8_PULLUDENABLE_1" newline bitfld.long 0x60 8. "GPMC_A8_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A8_MODESELECT_0,GPMC_A8_MODESELECT_1" newline bitfld.long 0x60 4.--7. "GPMC_A8_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x60 0.--3. "GPMC_A8_MUXMODE,- VIN4B_HSYNC1_6" "GPMC_A8_MUXMODE_0,GPMC_A8_MUXMODE_1,GPMC_A8_MUXMODE_2,GPMC_A8_MUXMODE_3,?,GPMC_A8_MUXMODE_5,GPMC_A8_MUXMODE_6,GPMC_A8_MUXMODE_7,GPMC_A8_MUXMODE_8,?,?,?,?,?,GPMC_A8_MUXMODE_14,?" line.long 0x64 "CTRL_CORE_PAD_GPMC_A9," rbitfld.long 0x64 25. "GPMC_A9_WAKEUPEVENT,- NOWAKEUP" "GPMC_A9_WAKEUPEVENT_0,GPMC_A9_WAKEUPEVENT_1" newline bitfld.long 0x64 24. "GPMC_A9_WAKEUPENABLE,- DISABLE" "GPMC_A9_WAKEUPENABLE_0,GPMC_A9_WAKEUPENABLE_1" newline bitfld.long 0x64 19. "GPMC_A9_SLEWCONTROL,- SLOW_SLEW" "GPMC_A9_SLEWCONTROL_0,GPMC_A9_SLEWCONTROL_1" newline bitfld.long 0x64 18. "GPMC_A9_INPUTENABLE,- DISABLE" "GPMC_A9_INPUTENABLE_0,GPMC_A9_INPUTENABLE_1" newline bitfld.long 0x64 17. "GPMC_A9_PULLTYPESELECT,- PULL_DOWN" "GPMC_A9_PULLTYPESELECT_0,GPMC_A9_PULLTYPESELECT_1" newline bitfld.long 0x64 16. "GPMC_A9_PULLUDENABLE,- DISABLE" "GPMC_A9_PULLUDENABLE_0,GPMC_A9_PULLUDENABLE_1" newline bitfld.long 0x64 8. "GPMC_A9_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A9_MODESELECT_0,GPMC_A9_MODESELECT_1" newline bitfld.long 0x64 4.--7. "GPMC_A9_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x64 0.--3. "GPMC_A9_MUXMODE,- VIN4B_VSYNC1_6" "GPMC_A9_MUXMODE_0,GPMC_A9_MUXMODE_1,GPMC_A9_MUXMODE_2,GPMC_A9_MUXMODE_3,?,GPMC_A9_MUXMODE_5,GPMC_A9_MUXMODE_6,GPMC_A9_MUXMODE_7,GPMC_A9_MUXMODE_8,?,?,?,?,?,GPMC_A9_MUXMODE_14,?" line.long 0x68 "CTRL_CORE_PAD_GPMC_A10," rbitfld.long 0x68 25. "GPMC_A10_WAKEUPEVENT,- NOWAKEUP" "GPMC_A10_WAKEUPEVENT_0,GPMC_A10_WAKEUPEVENT_1" newline bitfld.long 0x68 24. "GPMC_A10_WAKEUPENABLE,- DISABLE" "GPMC_A10_WAKEUPENABLE_0,GPMC_A10_WAKEUPENABLE_1" newline bitfld.long 0x68 19. "GPMC_A10_SLEWCONTROL,- SLOW_SLEW" "GPMC_A10_SLEWCONTROL_0,GPMC_A10_SLEWCONTROL_1" newline bitfld.long 0x68 18. "GPMC_A10_INPUTENABLE,- DISABLE" "GPMC_A10_INPUTENABLE_0,GPMC_A10_INPUTENABLE_1" newline bitfld.long 0x68 17. "GPMC_A10_PULLTYPESELECT,- PULL_DOWN" "GPMC_A10_PULLTYPESELECT_0,GPMC_A10_PULLTYPESELECT_1" newline bitfld.long 0x68 16. "GPMC_A10_PULLUDENABLE,- DISABLE" "GPMC_A10_PULLUDENABLE_0,GPMC_A10_PULLUDENABLE_1" newline bitfld.long 0x68 8. "GPMC_A10_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A10_MODESELECT_0,GPMC_A10_MODESELECT_1" newline bitfld.long 0x68 4.--7. "GPMC_A10_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x68 0.--3. "GPMC_A10_MUXMODE,- VIN4B_CLK1_6" "GPMC_A10_MUXMODE_0,GPMC_A10_MUXMODE_1,GPMC_A10_MUXMODE_2,GPMC_A10_MUXMODE_3,?,GPMC_A10_MUXMODE_5,GPMC_A10_MUXMODE_6,GPMC_A10_MUXMODE_7,GPMC_A10_MUXMODE_8,?,?,?,?,?,GPMC_A10_MUXMODE_14,?" line.long 0x6C "CTRL_CORE_PAD_GPMC_A11," rbitfld.long 0x6C 25. "GPMC_A11_WAKEUPEVENT,- NOWAKEUP" "GPMC_A11_WAKEUPEVENT_0,GPMC_A11_WAKEUPEVENT_1" newline bitfld.long 0x6C 24. "GPMC_A11_WAKEUPENABLE,- DISABLE" "GPMC_A11_WAKEUPENABLE_0,GPMC_A11_WAKEUPENABLE_1" newline bitfld.long 0x6C 19. "GPMC_A11_SLEWCONTROL,- SLOW_SLEW" "GPMC_A11_SLEWCONTROL_0,GPMC_A11_SLEWCONTROL_1" newline bitfld.long 0x6C 18. "GPMC_A11_INPUTENABLE,- DISABLE" "GPMC_A11_INPUTENABLE_0,GPMC_A11_INPUTENABLE_1" newline bitfld.long 0x6C 17. "GPMC_A11_PULLTYPESELECT,- PULL_DOWN" "GPMC_A11_PULLTYPESELECT_0,GPMC_A11_PULLTYPESELECT_1" newline bitfld.long 0x6C 16. "GPMC_A11_PULLUDENABLE,- DISABLE" "GPMC_A11_PULLUDENABLE_0,GPMC_A11_PULLUDENABLE_1" newline bitfld.long 0x6C 8. "GPMC_A11_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A11_MODESELECT_0,GPMC_A11_MODESELECT_1" newline bitfld.long 0x6C 4.--7. "GPMC_A11_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x6C 0.--3. "GPMC_A11_MUXMODE,- VIN4B_DE1_6" "GPMC_A11_MUXMODE_0,GPMC_A11_MUXMODE_1,GPMC_A11_MUXMODE_2,GPMC_A11_MUXMODE_3,GPMC_A11_MUXMODE_4,GPMC_A11_MUXMODE_5,GPMC_A11_MUXMODE_6,GPMC_A11_MUXMODE_7,GPMC_A11_MUXMODE_8,?,?,?,?,?,GPMC_A11_MUXMODE_14,?" line.long 0x70 "CTRL_CORE_PAD_GPMC_A12," rbitfld.long 0x70 25. "GPMC_A12_WAKEUPEVENT,- NOWAKEUP" "GPMC_A12_WAKEUPEVENT_0,GPMC_A12_WAKEUPEVENT_1" newline bitfld.long 0x70 24. "GPMC_A12_WAKEUPENABLE,- DISABLE" "GPMC_A12_WAKEUPENABLE_0,GPMC_A12_WAKEUPENABLE_1" newline bitfld.long 0x70 19. "GPMC_A12_SLEWCONTROL,- SLOW_SLEW" "GPMC_A12_SLEWCONTROL_0,GPMC_A12_SLEWCONTROL_1" newline bitfld.long 0x70 18. "GPMC_A12_INPUTENABLE,- DISABLE" "GPMC_A12_INPUTENABLE_0,GPMC_A12_INPUTENABLE_1" newline bitfld.long 0x70 17. "GPMC_A12_PULLTYPESELECT,- PULL_DOWN" "GPMC_A12_PULLTYPESELECT_0,GPMC_A12_PULLTYPESELECT_1" newline bitfld.long 0x70 16. "GPMC_A12_PULLUDENABLE,- DISABLE" "GPMC_A12_PULLUDENABLE_0,GPMC_A12_PULLUDENABLE_1" newline bitfld.long 0x70 8. "GPMC_A12_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A12_MODESELECT_0,GPMC_A12_MODESELECT_1" newline bitfld.long 0x70 4.--7. "GPMC_A12_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x70 0.--3. "GPMC_A12_MUXMODE,- VIN4B_FLD1_6" "GPMC_A12_MUXMODE_0,GPMC_A12_MUXMODE_1,?,?,GPMC_A12_MUXMODE_4,GPMC_A12_MUXMODE_5,GPMC_A12_MUXMODE_6,GPMC_A12_MUXMODE_7,GPMC_A12_MUXMODE_8,GPMC_A12_MUXMODE_9,?,?,?,?,GPMC_A12_MUXMODE_14,?" line.long 0x74 "CTRL_CORE_PAD_GPMC_A13," rbitfld.long 0x74 25. "GPMC_A13_WAKEUPEVENT,- NOWAKEUP" "GPMC_A13_WAKEUPEVENT_0,GPMC_A13_WAKEUPEVENT_1" newline bitfld.long 0x74 24. "GPMC_A13_WAKEUPENABLE,- DISABLE" "GPMC_A13_WAKEUPENABLE_0,GPMC_A13_WAKEUPENABLE_1" newline bitfld.long 0x74 19. "GPMC_A13_SLEWCONTROL,- SLOW_SLEW" "GPMC_A13_SLEWCONTROL_0,GPMC_A13_SLEWCONTROL_1" newline bitfld.long 0x74 18. "GPMC_A13_INPUTENABLE,- DISABLE" "GPMC_A13_INPUTENABLE_0,GPMC_A13_INPUTENABLE_1" newline bitfld.long 0x74 17. "GPMC_A13_PULLTYPESELECT,- PULL_DOWN" "GPMC_A13_PULLTYPESELECT_0,GPMC_A13_PULLTYPESELECT_1" newline bitfld.long 0x74 16. "GPMC_A13_PULLUDENABLE,- DISABLE" "GPMC_A13_PULLUDENABLE_0,GPMC_A13_PULLUDENABLE_1" newline bitfld.long 0x74 8. "GPMC_A13_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A13_MODESELECT_0,GPMC_A13_MODESELECT_1" newline bitfld.long 0x74 4.--7. "GPMC_A13_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x74 0.--3. "GPMC_A13_MUXMODE,- QSPI1_RTCLK_1" "GPMC_A13_MUXMODE_0,GPMC_A13_MUXMODE_1,?,?,GPMC_A13_MUXMODE_4,?,?,GPMC_A13_MUXMODE_7,GPMC_A13_MUXMODE_8,GPMC_A13_MUXMODE_9,?,?,?,?,GPMC_A13_MUXMODE_14,?" line.long 0x78 "CTRL_CORE_PAD_GPMC_A14," rbitfld.long 0x78 25. "GPMC_A14_WAKEUPEVENT,- NOWAKEUP" "GPMC_A14_WAKEUPEVENT_0,GPMC_A14_WAKEUPEVENT_1" newline bitfld.long 0x78 24. "GPMC_A14_WAKEUPENABLE,- DISABLE" "GPMC_A14_WAKEUPENABLE_0,GPMC_A14_WAKEUPENABLE_1" newline bitfld.long 0x78 19. "GPMC_A14_SLEWCONTROL,- SLOW_SLEW" "GPMC_A14_SLEWCONTROL_0,GPMC_A14_SLEWCONTROL_1" newline bitfld.long 0x78 18. "GPMC_A14_INPUTENABLE,- DISABLE" "GPMC_A14_INPUTENABLE_0,GPMC_A14_INPUTENABLE_1" newline bitfld.long 0x78 17. "GPMC_A14_PULLTYPESELECT,- PULL_DOWN" "GPMC_A14_PULLTYPESELECT_0,GPMC_A14_PULLTYPESELECT_1" newline bitfld.long 0x78 16. "GPMC_A14_PULLUDENABLE,- DISABLE" "GPMC_A14_PULLUDENABLE_0,GPMC_A14_PULLUDENABLE_1" newline bitfld.long 0x78 8. "GPMC_A14_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A14_MODESELECT_0,GPMC_A14_MODESELECT_1" newline bitfld.long 0x78 4.--7. "GPMC_A14_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x78 0.--3. "GPMC_A14_MUXMODE,- QSPI1_D3_1" "GPMC_A14_MUXMODE_0,GPMC_A14_MUXMODE_1,?,?,GPMC_A14_MUXMODE_4,?,?,GPMC_A14_MUXMODE_7,GPMC_A14_MUXMODE_8,?,?,?,?,?,GPMC_A14_MUXMODE_14,?" line.long 0x7C "CTRL_CORE_PAD_GPMC_A15," rbitfld.long 0x7C 25. "GPMC_A15_WAKEUPEVENT,- NOWAKEUP" "GPMC_A15_WAKEUPEVENT_0,GPMC_A15_WAKEUPEVENT_1" newline bitfld.long 0x7C 24. "GPMC_A15_WAKEUPENABLE,- DISABLE" "GPMC_A15_WAKEUPENABLE_0,GPMC_A15_WAKEUPENABLE_1" newline bitfld.long 0x7C 19. "GPMC_A15_SLEWCONTROL,- SLOW_SLEW" "GPMC_A15_SLEWCONTROL_0,GPMC_A15_SLEWCONTROL_1" newline bitfld.long 0x7C 18. "GPMC_A15_INPUTENABLE,- DISABLE" "GPMC_A15_INPUTENABLE_0,GPMC_A15_INPUTENABLE_1" newline bitfld.long 0x7C 17. "GPMC_A15_PULLTYPESELECT,- PULL_DOWN" "GPMC_A15_PULLTYPESELECT_0,GPMC_A15_PULLTYPESELECT_1" newline bitfld.long 0x7C 16. "GPMC_A15_PULLUDENABLE,- DISABLE" "GPMC_A15_PULLUDENABLE_0,GPMC_A15_PULLUDENABLE_1" newline bitfld.long 0x7C 8. "GPMC_A15_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A15_MODESELECT_0,GPMC_A15_MODESELECT_1" newline bitfld.long 0x7C 4.--7. "GPMC_A15_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x7C 0.--3. "GPMC_A15_MUXMODE,- GPMC_A15_0" "GPMC_A15_MUXMODE_0,GPMC_A15_MUXMODE_1,?,?,GPMC_A15_MUXMODE_4,?,?,GPMC_A15_MUXMODE_7,?,?,?,?,?,?,GPMC_A15_MUXMODE_14,?" line.long 0x80 "CTRL_CORE_PAD_GPMC_A16," rbitfld.long 0x80 25. "GPMC_A16_WAKEUPEVENT,- NOWAKEUP" "GPMC_A16_WAKEUPEVENT_0,GPMC_A16_WAKEUPEVENT_1" newline bitfld.long 0x80 24. "GPMC_A16_WAKEUPENABLE,- DISABLE" "GPMC_A16_WAKEUPENABLE_0,GPMC_A16_WAKEUPENABLE_1" newline bitfld.long 0x80 19. "GPMC_A16_SLEWCONTROL,- SLOW_SLEW" "GPMC_A16_SLEWCONTROL_0,GPMC_A16_SLEWCONTROL_1" newline bitfld.long 0x80 18. "GPMC_A16_INPUTENABLE,- DISABLE" "GPMC_A16_INPUTENABLE_0,GPMC_A16_INPUTENABLE_1" newline bitfld.long 0x80 17. "GPMC_A16_PULLTYPESELECT,- PULL_DOWN" "GPMC_A16_PULLTYPESELECT_0,GPMC_A16_PULLTYPESELECT_1" newline bitfld.long 0x80 16. "GPMC_A16_PULLUDENABLE,- DISABLE" "GPMC_A16_PULLUDENABLE_0,GPMC_A16_PULLUDENABLE_1" newline bitfld.long 0x80 8. "GPMC_A16_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A16_MODESELECT_0,GPMC_A16_MODESELECT_1" newline bitfld.long 0x80 4.--7. "GPMC_A16_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x80 0.--3. "GPMC_A16_MUXMODE,- GPMC_A16_0" "GPMC_A16_MUXMODE_0,GPMC_A16_MUXMODE_1,?,?,GPMC_A16_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_A16_MUXMODE_14,?" line.long 0x84 "CTRL_CORE_PAD_GPMC_A17," rbitfld.long 0x84 25. "GPMC_A17_WAKEUPEVENT,- NOWAKEUP" "GPMC_A17_WAKEUPEVENT_0,GPMC_A17_WAKEUPEVENT_1" newline bitfld.long 0x84 24. "GPMC_A17_WAKEUPENABLE,- DISABLE" "GPMC_A17_WAKEUPENABLE_0,GPMC_A17_WAKEUPENABLE_1" newline bitfld.long 0x84 19. "GPMC_A17_SLEWCONTROL,- SLOW_SLEW" "GPMC_A17_SLEWCONTROL_0,GPMC_A17_SLEWCONTROL_1" newline bitfld.long 0x84 18. "GPMC_A17_INPUTENABLE,- DISABLE" "GPMC_A17_INPUTENABLE_0,GPMC_A17_INPUTENABLE_1" newline bitfld.long 0x84 17. "GPMC_A17_PULLTYPESELECT,- PULL_DOWN" "GPMC_A17_PULLTYPESELECT_0,GPMC_A17_PULLTYPESELECT_1" newline bitfld.long 0x84 16. "GPMC_A17_PULLUDENABLE,- DISABLE" "GPMC_A17_PULLUDENABLE_0,GPMC_A17_PULLUDENABLE_1" newline bitfld.long 0x84 8. "GPMC_A17_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A17_MODESELECT_0,GPMC_A17_MODESELECT_1" newline bitfld.long 0x84 4.--7. "GPMC_A17_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x84 0.--3. "GPMC_A17_MUXMODE,- GPMC_A17_0" "GPMC_A17_MUXMODE_0,GPMC_A17_MUXMODE_1,?,?,GPMC_A17_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_A17_MUXMODE_14,?" line.long 0x88 "CTRL_CORE_PAD_GPMC_A18," rbitfld.long 0x88 25. "GPMC_A18_WAKEUPEVENT,- NOWAKEUP" "GPMC_A18_WAKEUPEVENT_0,GPMC_A18_WAKEUPEVENT_1" newline bitfld.long 0x88 24. "GPMC_A18_WAKEUPENABLE,- DISABLE" "GPMC_A18_WAKEUPENABLE_0,GPMC_A18_WAKEUPENABLE_1" newline bitfld.long 0x88 19. "GPMC_A18_SLEWCONTROL,- SLOW_SLEW" "GPMC_A18_SLEWCONTROL_0,GPMC_A18_SLEWCONTROL_1" newline bitfld.long 0x88 18. "GPMC_A18_INPUTENABLE,- DISABLE" "GPMC_A18_INPUTENABLE_0,GPMC_A18_INPUTENABLE_1" newline bitfld.long 0x88 17. "GPMC_A18_PULLTYPESELECT,- PULL_DOWN" "GPMC_A18_PULLTYPESELECT_0,GPMC_A18_PULLTYPESELECT_1" newline bitfld.long 0x88 16. "GPMC_A18_PULLUDENABLE,- DISABLE" "GPMC_A18_PULLUDENABLE_0,GPMC_A18_PULLUDENABLE_1" newline bitfld.long 0x88 8. "GPMC_A18_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A18_MODESELECT_0,GPMC_A18_MODESELECT_1" newline bitfld.long 0x88 4.--7. "GPMC_A18_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x88 0.--3. "GPMC_A18_MUXMODE,- GPMC_A18_0" "GPMC_A18_MUXMODE_0,GPMC_A18_MUXMODE_1,?,?,GPMC_A18_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_A18_MUXMODE_14,?" line.long 0x8C "CTRL_CORE_PAD_GPMC_A19," rbitfld.long 0x8C 25. "GPMC_A19_WAKEUPEVENT,- NOWAKEUP" "GPMC_A19_WAKEUPEVENT_0,GPMC_A19_WAKEUPEVENT_1" newline bitfld.long 0x8C 24. "GPMC_A19_WAKEUPENABLE,- DISABLE" "GPMC_A19_WAKEUPENABLE_0,GPMC_A19_WAKEUPENABLE_1" newline bitfld.long 0x8C 19. "GPMC_A19_SLEWCONTROL,- SLOW_SLEW" "GPMC_A19_SLEWCONTROL_0,GPMC_A19_SLEWCONTROL_1" newline bitfld.long 0x8C 18. "GPMC_A19_INPUTENABLE,- DISABLE" "GPMC_A19_INPUTENABLE_0,GPMC_A19_INPUTENABLE_1" newline bitfld.long 0x8C 17. "GPMC_A19_PULLTYPESELECT,- PULL_DOWN" "GPMC_A19_PULLTYPESELECT_0,GPMC_A19_PULLTYPESELECT_1" newline bitfld.long 0x8C 16. "GPMC_A19_PULLUDENABLE,- DISABLE" "GPMC_A19_PULLUDENABLE_0,GPMC_A19_PULLUDENABLE_1" newline bitfld.long 0x8C 8. "GPMC_A19_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A19_MODESELECT_0,GPMC_A19_MODESELECT_1" newline bitfld.long 0x8C 4.--7. "GPMC_A19_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x8C 0.--3. "GPMC_A19_MUXMODE,- VIN3B_D0_6" "GPMC_A19_MUXMODE_0,GPMC_A19_MUXMODE_1,GPMC_A19_MUXMODE_2,?,GPMC_A19_MUXMODE_4,?,GPMC_A19_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A19_MUXMODE_14,?" line.long 0x90 "CTRL_CORE_PAD_GPMC_A20," rbitfld.long 0x90 25. "GPMC_A20_WAKEUPEVENT,- NOWAKEUP" "GPMC_A20_WAKEUPEVENT_0,GPMC_A20_WAKEUPEVENT_1" newline bitfld.long 0x90 24. "GPMC_A20_WAKEUPENABLE,- DISABLE" "GPMC_A20_WAKEUPENABLE_0,GPMC_A20_WAKEUPENABLE_1" newline bitfld.long 0x90 19. "GPMC_A20_SLEWCONTROL,- SLOW_SLEW" "GPMC_A20_SLEWCONTROL_0,GPMC_A20_SLEWCONTROL_1" newline bitfld.long 0x90 18. "GPMC_A20_INPUTENABLE,- DISABLE" "GPMC_A20_INPUTENABLE_0,GPMC_A20_INPUTENABLE_1" newline bitfld.long 0x90 17. "GPMC_A20_PULLTYPESELECT,- PULL_DOWN" "GPMC_A20_PULLTYPESELECT_0,GPMC_A20_PULLTYPESELECT_1" newline bitfld.long 0x90 16. "GPMC_A20_PULLUDENABLE,- DISABLE" "GPMC_A20_PULLUDENABLE_0,GPMC_A20_PULLUDENABLE_1" newline bitfld.long 0x90 8. "GPMC_A20_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A20_MODESELECT_0,GPMC_A20_MODESELECT_1" newline bitfld.long 0x90 4.--7. "GPMC_A20_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x90 0.--3. "GPMC_A20_MUXMODE,- VIN3B_D1_6" "GPMC_A20_MUXMODE_0,GPMC_A20_MUXMODE_1,GPMC_A20_MUXMODE_2,?,GPMC_A20_MUXMODE_4,?,GPMC_A20_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A20_MUXMODE_14,?" line.long 0x94 "CTRL_CORE_PAD_GPMC_A21," rbitfld.long 0x94 25. "GPMC_A21_WAKEUPEVENT,- NOWAKEUP" "GPMC_A21_WAKEUPEVENT_0,GPMC_A21_WAKEUPEVENT_1" newline bitfld.long 0x94 24. "GPMC_A21_WAKEUPENABLE,- DISABLE" "GPMC_A21_WAKEUPENABLE_0,GPMC_A21_WAKEUPENABLE_1" newline bitfld.long 0x94 19. "GPMC_A21_SLEWCONTROL,- SLOW_SLEW" "GPMC_A21_SLEWCONTROL_0,GPMC_A21_SLEWCONTROL_1" newline bitfld.long 0x94 18. "GPMC_A21_INPUTENABLE,- DISABLE" "GPMC_A21_INPUTENABLE_0,GPMC_A21_INPUTENABLE_1" newline bitfld.long 0x94 17. "GPMC_A21_PULLTYPESELECT,- PULL_DOWN" "GPMC_A21_PULLTYPESELECT_0,GPMC_A21_PULLTYPESELECT_1" newline bitfld.long 0x94 16. "GPMC_A21_PULLUDENABLE,- DISABLE" "GPMC_A21_PULLUDENABLE_0,GPMC_A21_PULLUDENABLE_1" newline bitfld.long 0x94 8. "GPMC_A21_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A21_MODESELECT_0,GPMC_A21_MODESELECT_1" newline bitfld.long 0x94 4.--7. "GPMC_A21_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x94 0.--3. "GPMC_A21_MUXMODE,- VIN3B_D2_6" "GPMC_A21_MUXMODE_0,GPMC_A21_MUXMODE_1,GPMC_A21_MUXMODE_2,?,GPMC_A21_MUXMODE_4,?,GPMC_A21_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A21_MUXMODE_14,?" line.long 0x98 "CTRL_CORE_PAD_GPMC_A22," rbitfld.long 0x98 25. "GPMC_A22_WAKEUPEVENT,- NOWAKEUP" "GPMC_A22_WAKEUPEVENT_0,GPMC_A22_WAKEUPEVENT_1" newline bitfld.long 0x98 24. "GPMC_A22_WAKEUPENABLE,- DISABLE" "GPMC_A22_WAKEUPENABLE_0,GPMC_A22_WAKEUPENABLE_1" newline bitfld.long 0x98 19. "GPMC_A22_SLEWCONTROL,- SLOW_SLEW" "GPMC_A22_SLEWCONTROL_0,GPMC_A22_SLEWCONTROL_1" newline bitfld.long 0x98 18. "GPMC_A22_INPUTENABLE,- DISABLE" "GPMC_A22_INPUTENABLE_0,GPMC_A22_INPUTENABLE_1" newline bitfld.long 0x98 17. "GPMC_A22_PULLTYPESELECT,- PULL_DOWN" "GPMC_A22_PULLTYPESELECT_0,GPMC_A22_PULLTYPESELECT_1" newline bitfld.long 0x98 16. "GPMC_A22_PULLUDENABLE,- DISABLE" "GPMC_A22_PULLUDENABLE_0,GPMC_A22_PULLUDENABLE_1" newline bitfld.long 0x98 8. "GPMC_A22_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A22_MODESELECT_0,GPMC_A22_MODESELECT_1" newline bitfld.long 0x98 4.--7. "GPMC_A22_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x98 0.--3. "GPMC_A22_MUXMODE,- VIN3B_D3_6" "GPMC_A22_MUXMODE_0,GPMC_A22_MUXMODE_1,GPMC_A22_MUXMODE_2,?,GPMC_A22_MUXMODE_4,?,GPMC_A22_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A22_MUXMODE_14,?" line.long 0x9C "CTRL_CORE_PAD_GPMC_A23," rbitfld.long 0x9C 25. "GPMC_A23_WAKEUPEVENT,- NOWAKEUP" "GPMC_A23_WAKEUPEVENT_0,GPMC_A23_WAKEUPEVENT_1" newline bitfld.long 0x9C 24. "GPMC_A23_WAKEUPENABLE,- DISABLE" "GPMC_A23_WAKEUPENABLE_0,GPMC_A23_WAKEUPENABLE_1" newline bitfld.long 0x9C 19. "GPMC_A23_SLEWCONTROL,- SLOW_SLEW" "GPMC_A23_SLEWCONTROL_0,GPMC_A23_SLEWCONTROL_1" newline bitfld.long 0x9C 18. "GPMC_A23_INPUTENABLE,- DISABLE" "GPMC_A23_INPUTENABLE_0,GPMC_A23_INPUTENABLE_1" newline bitfld.long 0x9C 17. "GPMC_A23_PULLTYPESELECT,- PULL_DOWN" "GPMC_A23_PULLTYPESELECT_0,GPMC_A23_PULLTYPESELECT_1" newline bitfld.long 0x9C 16. "GPMC_A23_PULLUDENABLE,- DISABLE" "GPMC_A23_PULLUDENABLE_0,GPMC_A23_PULLUDENABLE_1" newline bitfld.long 0x9C 8. "GPMC_A23_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A23_MODESELECT_0,GPMC_A23_MODESELECT_1" newline bitfld.long 0x9C 4.--7. "GPMC_A23_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x9C 0.--3. "GPMC_A23_MUXMODE,- VIN3B_D4_6" "GPMC_A23_MUXMODE_0,GPMC_A23_MUXMODE_1,GPMC_A23_MUXMODE_2,?,GPMC_A23_MUXMODE_4,?,GPMC_A23_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A23_MUXMODE_14,?" line.long 0xA0 "CTRL_CORE_PAD_GPMC_A24," rbitfld.long 0xA0 25. "GPMC_A24_WAKEUPEVENT,- NOWAKEUP" "GPMC_A24_WAKEUPEVENT_0,GPMC_A24_WAKEUPEVENT_1" newline bitfld.long 0xA0 24. "GPMC_A24_WAKEUPENABLE,- DISABLE" "GPMC_A24_WAKEUPENABLE_0,GPMC_A24_WAKEUPENABLE_1" newline bitfld.long 0xA0 19. "GPMC_A24_SLEWCONTROL,- SLOW_SLEW" "GPMC_A24_SLEWCONTROL_0,GPMC_A24_SLEWCONTROL_1" newline bitfld.long 0xA0 18. "GPMC_A24_INPUTENABLE,- DISABLE" "GPMC_A24_INPUTENABLE_0,GPMC_A24_INPUTENABLE_1" newline bitfld.long 0xA0 17. "GPMC_A24_PULLTYPESELECT,- PULL_DOWN" "GPMC_A24_PULLTYPESELECT_0,GPMC_A24_PULLTYPESELECT_1" newline bitfld.long 0xA0 16. "GPMC_A24_PULLUDENABLE,- DISABLE" "GPMC_A24_PULLUDENABLE_0,GPMC_A24_PULLUDENABLE_1" newline bitfld.long 0xA0 8. "GPMC_A24_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A24_MODESELECT_0,GPMC_A24_MODESELECT_1" newline bitfld.long 0xA0 4.--7. "GPMC_A24_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xA0 0.--3. "GPMC_A24_MUXMODE,- VIN3B_D5_6" "GPMC_A24_MUXMODE_0,GPMC_A24_MUXMODE_1,GPMC_A24_MUXMODE_2,?,GPMC_A24_MUXMODE_4,?,GPMC_A24_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A24_MUXMODE_14,?" line.long 0xA4 "CTRL_CORE_PAD_GPMC_A25," rbitfld.long 0xA4 25. "GPMC_A25_WAKEUPEVENT,- NOWAKEUP" "GPMC_A25_WAKEUPEVENT_0,GPMC_A25_WAKEUPEVENT_1" newline bitfld.long 0xA4 24. "GPMC_A25_WAKEUPENABLE,- DISABLE" "GPMC_A25_WAKEUPENABLE_0,GPMC_A25_WAKEUPENABLE_1" newline bitfld.long 0xA4 19. "GPMC_A25_SLEWCONTROL,- SLOW_SLEW" "GPMC_A25_SLEWCONTROL_0,GPMC_A25_SLEWCONTROL_1" newline bitfld.long 0xA4 18. "GPMC_A25_INPUTENABLE,- DISABLE" "GPMC_A25_INPUTENABLE_0,GPMC_A25_INPUTENABLE_1" newline bitfld.long 0xA4 17. "GPMC_A25_PULLTYPESELECT,- PULL_DOWN" "GPMC_A25_PULLTYPESELECT_0,GPMC_A25_PULLTYPESELECT_1" newline bitfld.long 0xA4 16. "GPMC_A25_PULLUDENABLE,- DISABLE" "GPMC_A25_PULLUDENABLE_0,GPMC_A25_PULLUDENABLE_1" newline bitfld.long 0xA4 8. "GPMC_A25_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A25_MODESELECT_0,GPMC_A25_MODESELECT_1" newline bitfld.long 0xA4 4.--7. "GPMC_A25_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xA4 0.--3. "GPMC_A25_MUXMODE,- VIN3B_D6_6" "GPMC_A25_MUXMODE_0,GPMC_A25_MUXMODE_1,GPMC_A25_MUXMODE_2,?,GPMC_A25_MUXMODE_4,?,GPMC_A25_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A25_MUXMODE_14,?" line.long 0xA8 "CTRL_CORE_PAD_GPMC_A26," rbitfld.long 0xA8 25. "GPMC_A26_WAKEUPEVENT,- NOWAKEUP" "GPMC_A26_WAKEUPEVENT_0,GPMC_A26_WAKEUPEVENT_1" newline bitfld.long 0xA8 24. "GPMC_A26_WAKEUPENABLE,- DISABLE" "GPMC_A26_WAKEUPENABLE_0,GPMC_A26_WAKEUPENABLE_1" newline bitfld.long 0xA8 19. "GPMC_A26_SLEWCONTROL,- SLOW_SLEW" "GPMC_A26_SLEWCONTROL_0,GPMC_A26_SLEWCONTROL_1" newline bitfld.long 0xA8 18. "GPMC_A26_INPUTENABLE,- DISABLE" "GPMC_A26_INPUTENABLE_0,GPMC_A26_INPUTENABLE_1" newline bitfld.long 0xA8 17. "GPMC_A26_PULLTYPESELECT,- PULL_DOWN" "GPMC_A26_PULLTYPESELECT_0,GPMC_A26_PULLTYPESELECT_1" newline bitfld.long 0xA8 16. "GPMC_A26_PULLUDENABLE,- DISABLE" "GPMC_A26_PULLUDENABLE_0,GPMC_A26_PULLUDENABLE_1" newline bitfld.long 0xA8 8. "GPMC_A26_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A26_MODESELECT_0,GPMC_A26_MODESELECT_1" newline bitfld.long 0xA8 4.--7. "GPMC_A26_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xA8 0.--3. "GPMC_A26_MUXMODE,- VIN3B_D7_6" "GPMC_A26_MUXMODE_0,GPMC_A26_MUXMODE_1,GPMC_A26_MUXMODE_2,?,GPMC_A26_MUXMODE_4,?,GPMC_A26_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A26_MUXMODE_14,?" line.long 0xAC "CTRL_CORE_PAD_GPMC_A27," rbitfld.long 0xAC 25. "GPMC_A27_WAKEUPEVENT,- NOWAKEUP" "GPMC_A27_WAKEUPEVENT_0,GPMC_A27_WAKEUPEVENT_1" newline bitfld.long 0xAC 24. "GPMC_A27_WAKEUPENABLE,- DISABLE" "GPMC_A27_WAKEUPENABLE_0,GPMC_A27_WAKEUPENABLE_1" newline bitfld.long 0xAC 19. "GPMC_A27_SLEWCONTROL,- SLOW_SLEW" "GPMC_A27_SLEWCONTROL_0,GPMC_A27_SLEWCONTROL_1" newline bitfld.long 0xAC 18. "GPMC_A27_INPUTENABLE,- DISABLE" "GPMC_A27_INPUTENABLE_0,GPMC_A27_INPUTENABLE_1" newline bitfld.long 0xAC 17. "GPMC_A27_PULLTYPESELECT,- PULL_DOWN" "GPMC_A27_PULLTYPESELECT_0,GPMC_A27_PULLTYPESELECT_1" newline bitfld.long 0xAC 16. "GPMC_A27_PULLUDENABLE,- DISABLE" "GPMC_A27_PULLUDENABLE_0,GPMC_A27_PULLUDENABLE_1" newline bitfld.long 0xAC 8. "GPMC_A27_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_A27_MODESELECT_0,GPMC_A27_MODESELECT_1" newline bitfld.long 0xAC 4.--7. "GPMC_A27_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xAC 0.--3. "GPMC_A27_MUXMODE,- VIN3B_HSYNC1_6" "GPMC_A27_MUXMODE_0,GPMC_A27_MUXMODE_1,GPMC_A27_MUXMODE_2,?,GPMC_A27_MUXMODE_4,?,GPMC_A27_MUXMODE_6,?,?,?,?,?,?,?,GPMC_A27_MUXMODE_14,?" line.long 0xB0 "CTRL_CORE_PAD_GPMC_CS1," rbitfld.long 0xB0 25. "GPMC_CS1_WAKEUPEVENT,- NOWAKEUP" "GPMC_CS1_WAKEUPEVENT_0,GPMC_CS1_WAKEUPEVENT_1" newline bitfld.long 0xB0 24. "GPMC_CS1_WAKEUPENABLE,- DISABLE" "GPMC_CS1_WAKEUPENABLE_0,GPMC_CS1_WAKEUPENABLE_1" newline bitfld.long 0xB0 19. "GPMC_CS1_SLEWCONTROL,- SLOW_SLEW" "GPMC_CS1_SLEWCONTROL_0,GPMC_CS1_SLEWCONTROL_1" newline bitfld.long 0xB0 18. "GPMC_CS1_INPUTENABLE,- DISABLE" "GPMC_CS1_INPUTENABLE_0,GPMC_CS1_INPUTENABLE_1" newline bitfld.long 0xB0 17. "GPMC_CS1_PULLTYPESELECT,- PULL_DOWN" "GPMC_CS1_PULLTYPESELECT_0,GPMC_CS1_PULLTYPESELECT_1" newline bitfld.long 0xB0 16. "GPMC_CS1_PULLUDENABLE,- DISABLE" "GPMC_CS1_PULLUDENABLE_0,GPMC_CS1_PULLUDENABLE_1" newline bitfld.long 0xB0 8. "GPMC_CS1_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_CS1_MODESELECT_0,GPMC_CS1_MODESELECT_1" newline bitfld.long 0xB0 4.--7. "GPMC_CS1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xB0 0.--3. "GPMC_CS1_MUXMODE,- VIN3B_VSYNC1_6" "GPMC_CS1_MUXMODE_0,GPMC_CS1_MUXMODE_1,GPMC_CS1_MUXMODE_2,?,GPMC_CS1_MUXMODE_4,?,GPMC_CS1_MUXMODE_6,?,?,?,?,?,?,?,GPMC_CS1_MUXMODE_14,?" line.long 0xB4 "CTRL_CORE_PAD_GPMC_CS0," rbitfld.long 0xB4 25. "GPMC_CS0_WAKEUPEVENT,- NOWAKEUP" "GPMC_CS0_WAKEUPEVENT_0,GPMC_CS0_WAKEUPEVENT_1" newline bitfld.long 0xB4 24. "GPMC_CS0_WAKEUPENABLE,- DISABLE" "GPMC_CS0_WAKEUPENABLE_0,GPMC_CS0_WAKEUPENABLE_1" newline bitfld.long 0xB4 19. "GPMC_CS0_SLEWCONTROL,- SLOW_SLEW" "GPMC_CS0_SLEWCONTROL_0,GPMC_CS0_SLEWCONTROL_1" newline bitfld.long 0xB4 18. "GPMC_CS0_INPUTENABLE,- DISABLE" "GPMC_CS0_INPUTENABLE_0,GPMC_CS0_INPUTENABLE_1" newline bitfld.long 0xB4 17. "GPMC_CS0_PULLTYPESELECT,- PULL_DOWN" "GPMC_CS0_PULLTYPESELECT_0,GPMC_CS0_PULLTYPESELECT_1" newline bitfld.long 0xB4 16. "GPMC_CS0_PULLUDENABLE,- DISABLE" "GPMC_CS0_PULLUDENABLE_0,GPMC_CS0_PULLUDENABLE_1" newline bitfld.long 0xB4 8. "GPMC_CS0_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_CS0_MODESELECT_0,GPMC_CS0_MODESELECT_1" newline bitfld.long 0xB4 4.--7. "GPMC_CS0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xB4 0.--3. "GPMC_CS0_MUXMODE,- GPMC_CS0_0" "GPMC_CS0_MUXMODE_0,?,?,?,GPMC_CS0_MUXMODE_4,?,?,?,?,?,?,?,?,?,GPMC_CS0_MUXMODE_14,?" line.long 0xB8 "CTRL_CORE_PAD_GPMC_CS2," rbitfld.long 0xB8 25. "GPMC_CS2_WAKEUPEVENT,- NOWAKEUP" "GPMC_CS2_WAKEUPEVENT_0,GPMC_CS2_WAKEUPEVENT_1" newline bitfld.long 0xB8 24. "GPMC_CS2_WAKEUPENABLE,- DISABLE" "GPMC_CS2_WAKEUPENABLE_0,GPMC_CS2_WAKEUPENABLE_1" newline bitfld.long 0xB8 19. "GPMC_CS2_SLEWCONTROL,- SLOW_SLEW" "GPMC_CS2_SLEWCONTROL_0,GPMC_CS2_SLEWCONTROL_1" newline bitfld.long 0xB8 18. "GPMC_CS2_INPUTENABLE,- DISABLE" "GPMC_CS2_INPUTENABLE_0,GPMC_CS2_INPUTENABLE_1" newline bitfld.long 0xB8 17. "GPMC_CS2_PULLTYPESELECT,- PULL_DOWN" "GPMC_CS2_PULLTYPESELECT_0,GPMC_CS2_PULLTYPESELECT_1" newline bitfld.long 0xB8 16. "GPMC_CS2_PULLUDENABLE,- DISABLE" "GPMC_CS2_PULLUDENABLE_0,GPMC_CS2_PULLUDENABLE_1" newline bitfld.long 0xB8 8. "GPMC_CS2_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_CS2_MODESELECT_0,GPMC_CS2_MODESELECT_1" newline bitfld.long 0xB8 4.--7. "GPMC_CS2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xB8 0.--3. "GPMC_CS2_MUXMODE,- GPMC_CS2_0" "GPMC_CS2_MUXMODE_0,GPMC_CS2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_CS2_MUXMODE_14,?" line.long 0xBC "CTRL_CORE_PAD_GPMC_CS3," rbitfld.long 0xBC 25. "GPMC_CS3_WAKEUPEVENT,- NOWAKEUP" "GPMC_CS3_WAKEUPEVENT_0,GPMC_CS3_WAKEUPEVENT_1" newline bitfld.long 0xBC 24. "GPMC_CS3_WAKEUPENABLE,- DISABLE" "GPMC_CS3_WAKEUPENABLE_0,GPMC_CS3_WAKEUPENABLE_1" newline bitfld.long 0xBC 19. "GPMC_CS3_SLEWCONTROL,- SLOW_SLEW" "GPMC_CS3_SLEWCONTROL_0,GPMC_CS3_SLEWCONTROL_1" newline bitfld.long 0xBC 18. "GPMC_CS3_INPUTENABLE,- DISABLE" "GPMC_CS3_INPUTENABLE_0,GPMC_CS3_INPUTENABLE_1" newline bitfld.long 0xBC 17. "GPMC_CS3_PULLTYPESELECT,- PULL_DOWN" "GPMC_CS3_PULLTYPESELECT_0,GPMC_CS3_PULLTYPESELECT_1" newline bitfld.long 0xBC 16. "GPMC_CS3_PULLUDENABLE,- DISABLE" "GPMC_CS3_PULLUDENABLE_0,GPMC_CS3_PULLUDENABLE_1" newline bitfld.long 0xBC 8. "GPMC_CS3_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_CS3_MODESELECT_0,GPMC_CS3_MODESELECT_1" newline bitfld.long 0xBC 4.--7. "GPMC_CS3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xBC 0.--3. "GPMC_CS3_MUXMODE,- QSPI1_CS1_1" "GPMC_CS3_MUXMODE_0,GPMC_CS3_MUXMODE_1,GPMC_CS3_MUXMODE_2,GPMC_CS3_MUXMODE_3,GPMC_CS3_MUXMODE_4,GPMC_CS3_MUXMODE_5,?,?,?,?,?,?,?,?,GPMC_CS3_MUXMODE_14,?" line.long 0xC0 "CTRL_CORE_PAD_GPMC_CLK," rbitfld.long 0xC0 25. "GPMC_CLK_WAKEUPEVENT,- NOWAKEUP" "GPMC_CLK_WAKEUPEVENT_0,GPMC_CLK_WAKEUPEVENT_1" newline bitfld.long 0xC0 24. "GPMC_CLK_WAKEUPENABLE,- DISABLE" "GPMC_CLK_WAKEUPENABLE_0,GPMC_CLK_WAKEUPENABLE_1" newline bitfld.long 0xC0 19. "GPMC_CLK_SLEWCONTROL,- SLOW_SLEW" "GPMC_CLK_SLEWCONTROL_0,GPMC_CLK_SLEWCONTROL_1" newline bitfld.long 0xC0 18. "GPMC_CLK_INPUTENABLE,- DISABLE" "GPMC_CLK_INPUTENABLE_0,GPMC_CLK_INPUTENABLE_1" newline bitfld.long 0xC0 17. "GPMC_CLK_PULLTYPESELECT,- PULL_DOWN" "GPMC_CLK_PULLTYPESELECT_0,GPMC_CLK_PULLTYPESELECT_1" newline bitfld.long 0xC0 16. "GPMC_CLK_PULLUDENABLE,- DISABLE" "GPMC_CLK_PULLUDENABLE_0,GPMC_CLK_PULLUDENABLE_1" newline bitfld.long 0xC0 8. "GPMC_CLK_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_CLK_MODESELECT_0,GPMC_CLK_MODESELECT_1" newline bitfld.long 0xC0 4.--7. "GPMC_CLK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xC0 0.--3. "GPMC_CLK_MUXMODE,- VIN3B_CLK1_6" "GPMC_CLK_MUXMODE_0,GPMC_CLK_MUXMODE_1,GPMC_CLK_MUXMODE_2,GPMC_CLK_MUXMODE_3,GPMC_CLK_MUXMODE_4,GPMC_CLK_MUXMODE_5,GPMC_CLK_MUXMODE_6,GPMC_CLK_MUXMODE_7,GPMC_CLK_MUXMODE_8,GPMC_CLK_MUXMODE_9,?,?,?,?,GPMC_CLK_MUXMODE_14,?" line.long 0xC4 "CTRL_CORE_PAD_GPMC_ADVN_ALE," rbitfld.long 0xC4 25. "GPMC_ADVN_ALE_WAKEUPEVENT,- NOWAKEUP" "GPMC_ADVN_ALE_WAKEUPEVENT_0,GPMC_ADVN_ALE_WAKEUPEVENT_1" newline bitfld.long 0xC4 24. "GPMC_ADVN_ALE_WAKEUPENABLE,- DISABLE" "GPMC_ADVN_ALE_WAKEUPENABLE_0,GPMC_ADVN_ALE_WAKEUPENABLE_1" newline bitfld.long 0xC4 19. "GPMC_ADVN_ALE_SLEWCONTROL,- SLOW_SLEW" "GPMC_ADVN_ALE_SLEWCONTROL_0,GPMC_ADVN_ALE_SLEWCONTROL_1" newline bitfld.long 0xC4 18. "GPMC_ADVN_ALE_INPUTENABLE,- DISABLE" "GPMC_ADVN_ALE_INPUTENABLE_0,GPMC_ADVN_ALE_INPUTENABLE_1" newline bitfld.long 0xC4 17. "GPMC_ADVN_ALE_PULLTYPESELECT,- PULL_DOWN" "GPMC_ADVN_ALE_PULLTYPESELECT_0,GPMC_ADVN_ALE_PULLTYPESELECT_1" newline bitfld.long 0xC4 16. "GPMC_ADVN_ALE_PULLUDENABLE,- DISABLE" "GPMC_ADVN_ALE_PULLUDENABLE_0,GPMC_ADVN_ALE_PULLUDENABLE_1" newline bitfld.long 0xC4 8. "GPMC_ADVN_ALE_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_ADVN_ALE_MODESELECT_0,GPMC_ADVN_ALE_MODESELECT_1" newline bitfld.long 0xC4 4.--7. "GPMC_ADVN_ALE_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xC4 0.--3. "GPMC_ADVN_ALE_MUXMODE,- GPMC_A23_6" "GPMC_ADVN_ALE_MUXMODE_0,GPMC_ADVN_ALE_MUXMODE_1,GPMC_ADVN_ALE_MUXMODE_2,GPMC_ADVN_ALE_MUXMODE_3,GPMC_ADVN_ALE_MUXMODE_4,GPMC_ADVN_ALE_MUXMODE_5,GPMC_ADVN_ALE_MUXMODE_6,GPMC_ADVN_ALE_MUXMODE_7,GPMC_ADVN_ALE_MUXMODE_8,GPMC_ADVN_ALE_MUXMODE_9,?,?,?,?,GPMC_ADVN_ALE_MUXMODE_14,?" line.long 0xC8 "CTRL_CORE_PAD_GPMC_OEN_REN," rbitfld.long 0xC8 25. "GPMC_OEN_REN_WAKEUPEVENT,- NOWAKEUP" "GPMC_OEN_REN_WAKEUPEVENT_0,GPMC_OEN_REN_WAKEUPEVENT_1" newline bitfld.long 0xC8 24. "GPMC_OEN_REN_WAKEUPENABLE,- DISABLE" "GPMC_OEN_REN_WAKEUPENABLE_0,GPMC_OEN_REN_WAKEUPENABLE_1" newline bitfld.long 0xC8 19. "GPMC_OEN_REN_SLEWCONTROL,- SLOW_SLEW" "GPMC_OEN_REN_SLEWCONTROL_0,GPMC_OEN_REN_SLEWCONTROL_1" newline bitfld.long 0xC8 18. "GPMC_OEN_REN_INPUTENABLE,- DISABLE" "GPMC_OEN_REN_INPUTENABLE_0,GPMC_OEN_REN_INPUTENABLE_1" newline bitfld.long 0xC8 17. "GPMC_OEN_REN_PULLTYPESELECT,- PULL_DOWN" "GPMC_OEN_REN_PULLTYPESELECT_0,GPMC_OEN_REN_PULLTYPESELECT_1" newline bitfld.long 0xC8 16. "GPMC_OEN_REN_PULLUDENABLE,- DISABLE" "GPMC_OEN_REN_PULLUDENABLE_0,GPMC_OEN_REN_PULLUDENABLE_1" newline bitfld.long 0xC8 8. "GPMC_OEN_REN_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_OEN_REN_MODESELECT_0,GPMC_OEN_REN_MODESELECT_1" newline bitfld.long 0xC8 4.--7. "GPMC_OEN_REN_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xC8 0.--3. "GPMC_OEN_REN_MUXMODE,- GPMC_OEN_REN_0" "GPMC_OEN_REN_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_OEN_REN_MUXMODE_14,?" line.long 0xCC "CTRL_CORE_PAD_GPMC_WEN," rbitfld.long 0xCC 25. "GPMC_WEN_WAKEUPEVENT,- NOWAKEUP" "GPMC_WEN_WAKEUPEVENT_0,GPMC_WEN_WAKEUPEVENT_1" newline bitfld.long 0xCC 24. "GPMC_WEN_WAKEUPENABLE,- DISABLE" "GPMC_WEN_WAKEUPENABLE_0,GPMC_WEN_WAKEUPENABLE_1" newline bitfld.long 0xCC 19. "GPMC_WEN_SLEWCONTROL,- SLOW_SLEW" "GPMC_WEN_SLEWCONTROL_0,GPMC_WEN_SLEWCONTROL_1" newline bitfld.long 0xCC 18. "GPMC_WEN_INPUTENABLE,- DISABLE" "GPMC_WEN_INPUTENABLE_0,GPMC_WEN_INPUTENABLE_1" newline bitfld.long 0xCC 17. "GPMC_WEN_PULLTYPESELECT,- PULL_DOWN" "GPMC_WEN_PULLTYPESELECT_0,GPMC_WEN_PULLTYPESELECT_1" newline bitfld.long 0xCC 16. "GPMC_WEN_PULLUDENABLE,- DISABLE" "GPMC_WEN_PULLUDENABLE_0,GPMC_WEN_PULLUDENABLE_1" newline bitfld.long 0xCC 8. "GPMC_WEN_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_WEN_MODESELECT_0,GPMC_WEN_MODESELECT_1" newline bitfld.long 0xCC 4.--7. "GPMC_WEN_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xCC 0.--3. "GPMC_WEN_MUXMODE,- GPMC_WEN_0" "GPMC_WEN_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_WEN_MUXMODE_14,?" line.long 0xD0 "CTRL_CORE_PAD_GPMC_BEN0," rbitfld.long 0xD0 25. "GPMC_BEN0_WAKEUPEVENT,- NOWAKEUP" "GPMC_BEN0_WAKEUPEVENT_0,GPMC_BEN0_WAKEUPEVENT_1" newline bitfld.long 0xD0 24. "GPMC_BEN0_WAKEUPENABLE,- DISABLE" "GPMC_BEN0_WAKEUPENABLE_0,GPMC_BEN0_WAKEUPENABLE_1" newline bitfld.long 0xD0 19. "GPMC_BEN0_SLEWCONTROL,- SLOW_SLEW" "GPMC_BEN0_SLEWCONTROL_0,GPMC_BEN0_SLEWCONTROL_1" newline bitfld.long 0xD0 18. "GPMC_BEN0_INPUTENABLE,- DISABLE" "GPMC_BEN0_INPUTENABLE_0,GPMC_BEN0_INPUTENABLE_1" newline bitfld.long 0xD0 17. "GPMC_BEN0_PULLTYPESELECT,- PULL_DOWN" "GPMC_BEN0_PULLTYPESELECT_0,GPMC_BEN0_PULLTYPESELECT_1" newline bitfld.long 0xD0 16. "GPMC_BEN0_PULLUDENABLE,- DISABLE" "GPMC_BEN0_PULLUDENABLE_0,GPMC_BEN0_PULLUDENABLE_1" newline bitfld.long 0xD0 8. "GPMC_BEN0_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_BEN0_MODESELECT_0,GPMC_BEN0_MODESELECT_1" newline bitfld.long 0xD0 4.--7. "GPMC_BEN0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xD0 0.--3. "GPMC_BEN0_MUXMODE,- VIN3B_DE1_6" "GPMC_BEN0_MUXMODE_0,GPMC_BEN0_MUXMODE_1,?,GPMC_BEN0_MUXMODE_3,?,?,GPMC_BEN0_MUXMODE_6,GPMC_BEN0_MUXMODE_7,?,GPMC_BEN0_MUXMODE_9,?,?,?,?,GPMC_BEN0_MUXMODE_14,?" line.long 0xD4 "CTRL_CORE_PAD_GPMC_BEN1," rbitfld.long 0xD4 25. "GPMC_BEN1_WAKEUPEVENT,- NOWAKEUP" "GPMC_BEN1_WAKEUPEVENT_0,GPMC_BEN1_WAKEUPEVENT_1" newline bitfld.long 0xD4 24. "GPMC_BEN1_WAKEUPENABLE,- DISABLE" "GPMC_BEN1_WAKEUPENABLE_0,GPMC_BEN1_WAKEUPENABLE_1" newline bitfld.long 0xD4 19. "GPMC_BEN1_SLEWCONTROL,- SLOW_SLEW" "GPMC_BEN1_SLEWCONTROL_0,GPMC_BEN1_SLEWCONTROL_1" newline bitfld.long 0xD4 18. "GPMC_BEN1_INPUTENABLE,- DISABLE" "GPMC_BEN1_INPUTENABLE_0,GPMC_BEN1_INPUTENABLE_1" newline bitfld.long 0xD4 17. "GPMC_BEN1_PULLTYPESELECT,- PULL_DOWN" "GPMC_BEN1_PULLTYPESELECT_0,GPMC_BEN1_PULLTYPESELECT_1" newline bitfld.long 0xD4 16. "GPMC_BEN1_PULLUDENABLE,- DISABLE" "GPMC_BEN1_PULLUDENABLE_0,GPMC_BEN1_PULLUDENABLE_1" newline bitfld.long 0xD4 8. "GPMC_BEN1_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_BEN1_MODESELECT_0,GPMC_BEN1_MODESELECT_1" newline bitfld.long 0xD4 4.--7. "GPMC_BEN1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xD4 0.--3. "GPMC_BEN1_MUXMODE,- VIN3B_FLD1_6" "GPMC_BEN1_MUXMODE_0,GPMC_BEN1_MUXMODE_1,?,GPMC_BEN1_MUXMODE_3,GPMC_BEN1_MUXMODE_4,GPMC_BEN1_MUXMODE_5,GPMC_BEN1_MUXMODE_6,GPMC_BEN1_MUXMODE_7,?,GPMC_BEN1_MUXMODE_9,?,?,?,?,GPMC_BEN1_MUXMODE_14,?" line.long 0xD8 "CTRL_CORE_PAD_GPMC_WAIT0," rbitfld.long 0xD8 25. "GPMC_WAIT0_WAKEUPEVENT,- NOWAKEUP" "GPMC_WAIT0_WAKEUPEVENT_0,GPMC_WAIT0_WAKEUPEVENT_1" newline bitfld.long 0xD8 24. "GPMC_WAIT0_WAKEUPENABLE,- DISABLE" "GPMC_WAIT0_WAKEUPENABLE_0,GPMC_WAIT0_WAKEUPENABLE_1" newline bitfld.long 0xD8 19. "GPMC_WAIT0_SLEWCONTROL,- SLOW_SLEW" "GPMC_WAIT0_SLEWCONTROL_0,GPMC_WAIT0_SLEWCONTROL_1" newline bitfld.long 0xD8 18. "GPMC_WAIT0_INPUTENABLE,- DISABLE" "GPMC_WAIT0_INPUTENABLE_0,GPMC_WAIT0_INPUTENABLE_1" newline bitfld.long 0xD8 17. "GPMC_WAIT0_PULLTYPESELECT,- PULL_DOWN" "GPMC_WAIT0_PULLTYPESELECT_0,GPMC_WAIT0_PULLTYPESELECT_1" newline bitfld.long 0xD8 16. "GPMC_WAIT0_PULLUDENABLE,- DISABLE" "GPMC_WAIT0_PULLUDENABLE_0,GPMC_WAIT0_PULLUDENABLE_1" newline bitfld.long 0xD8 8. "GPMC_WAIT0_MODESELECT,Selects between default and another IO delay different than the default one" "GPMC_WAIT0_MODESELECT_0,GPMC_WAIT0_MODESELECT_1" newline bitfld.long 0xD8 4.--7. "GPMC_WAIT0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xD8 0.--3. "GPMC_WAIT0_MUXMODE,- GPMC_WAIT0_0" "GPMC_WAIT0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,GPMC_WAIT0_MUXMODE_14,?" line.long 0xDC "CTRL_CORE_PAD_VIN1A_CLK0," rbitfld.long 0xDC 25. "VIN1A_CLK0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_CLK0_WAKEUPEVENT_0,VIN1A_CLK0_WAKEUPEVENT_1" newline bitfld.long 0xDC 24. "VIN1A_CLK0_WAKEUPENABLE,- DISABLE" "VIN1A_CLK0_WAKEUPENABLE_0,VIN1A_CLK0_WAKEUPENABLE_1" newline bitfld.long 0xDC 19. "VIN1A_CLK0_SLEWCONTROL,- SLOW_SLEW" "VIN1A_CLK0_SLEWCONTROL_0,VIN1A_CLK0_SLEWCONTROL_1" newline bitfld.long 0xDC 18. "VIN1A_CLK0_INPUTENABLE,- DISABLE" "VIN1A_CLK0_INPUTENABLE_0,VIN1A_CLK0_INPUTENABLE_1" newline bitfld.long 0xDC 17. "VIN1A_CLK0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_CLK0_PULLTYPESELECT_0,VIN1A_CLK0_PULLTYPESELECT_1" newline bitfld.long 0xDC 16. "VIN1A_CLK0_PULLUDENABLE,- DISABLE" "VIN1A_CLK0_PULLUDENABLE_0,VIN1A_CLK0_PULLUDENABLE_1" newline bitfld.long 0xDC 8. "VIN1A_CLK0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_CLK0_MODESELECT_0,VIN1A_CLK0_MODESELECT_1" newline bitfld.long 0xDC 4.--7. "VIN1A_CLK0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xDC 0.--3. "VIN1A_CLK0_MUXMODE,- VIN1A_CLK0_0" "VIN1A_CLK0_MUXMODE_0,?,?,VIN1A_CLK0_MUXMODE_3,VIN1A_CLK0_MUXMODE_4,?,?,?,?,?,?,?,?,?,VIN1A_CLK0_MUXMODE_14,?" line.long 0xE0 "CTRL_CORE_PAD_VIN1B_CLK1," rbitfld.long 0xE0 25. "VIN1B_CLK1_WAKEUPEVENT,- NOWAKEUP" "VIN1B_CLK1_WAKEUPEVENT_0,VIN1B_CLK1_WAKEUPEVENT_1" newline bitfld.long 0xE0 24. "VIN1B_CLK1_WAKEUPENABLE,- DISABLE" "VIN1B_CLK1_WAKEUPENABLE_0,VIN1B_CLK1_WAKEUPENABLE_1" newline bitfld.long 0xE0 19. "VIN1B_CLK1_SLEWCONTROL,- SLOW_SLEW" "VIN1B_CLK1_SLEWCONTROL_0,VIN1B_CLK1_SLEWCONTROL_1" newline bitfld.long 0xE0 18. "VIN1B_CLK1_INPUTENABLE,- DISABLE" "VIN1B_CLK1_INPUTENABLE_0,VIN1B_CLK1_INPUTENABLE_1" newline bitfld.long 0xE0 17. "VIN1B_CLK1_PULLTYPESELECT,- PULL_DOWN" "VIN1B_CLK1_PULLTYPESELECT_0,VIN1B_CLK1_PULLTYPESELECT_1" newline bitfld.long 0xE0 16. "VIN1B_CLK1_PULLUDENABLE,- DISABLE" "VIN1B_CLK1_PULLUDENABLE_0,VIN1B_CLK1_PULLUDENABLE_1" newline bitfld.long 0xE0 8. "VIN1B_CLK1_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1B_CLK1_MODESELECT_0,VIN1B_CLK1_MODESELECT_1" newline bitfld.long 0xE0 4.--7. "VIN1B_CLK1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xE0 0.--3. "VIN1B_CLK1_MUXMODE,- VIN1B_CLK1_0" "VIN1B_CLK1_MUXMODE_0,?,?,?,?,?,VIN1B_CLK1_MUXMODE_6,?,?,?,?,?,?,?,VIN1B_CLK1_MUXMODE_14,?" line.long 0xE4 "CTRL_CORE_PAD_VIN1A_DE0," rbitfld.long 0xE4 25. "VIN1A_DE0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_DE0_WAKEUPEVENT_0,VIN1A_DE0_WAKEUPEVENT_1" newline bitfld.long 0xE4 24. "VIN1A_DE0_WAKEUPENABLE,- DISABLE" "VIN1A_DE0_WAKEUPENABLE_0,VIN1A_DE0_WAKEUPENABLE_1" newline bitfld.long 0xE4 19. "VIN1A_DE0_SLEWCONTROL,- SLOW_SLEW" "VIN1A_DE0_SLEWCONTROL_0,VIN1A_DE0_SLEWCONTROL_1" newline bitfld.long 0xE4 18. "VIN1A_DE0_INPUTENABLE,- DISABLE" "VIN1A_DE0_INPUTENABLE_0,VIN1A_DE0_INPUTENABLE_1" newline bitfld.long 0xE4 17. "VIN1A_DE0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_DE0_PULLTYPESELECT_0,VIN1A_DE0_PULLTYPESELECT_1" newline bitfld.long 0xE4 16. "VIN1A_DE0_PULLUDENABLE,- DISABLE" "VIN1A_DE0_PULLUDENABLE_0,VIN1A_DE0_PULLUDENABLE_1" newline bitfld.long 0xE4 8. "VIN1A_DE0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_DE0_MODESELECT_0,VIN1A_DE0_MODESELECT_1" newline bitfld.long 0xE4 4.--7. "VIN1A_DE0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xE4 0.--3. "VIN1A_DE0_MUXMODE,- VIN1B_HSYNC1_1" "VIN1A_DE0_MUXMODE_0,VIN1A_DE0_MUXMODE_1,?,VIN1A_DE0_MUXMODE_3,VIN1A_DE0_MUXMODE_4,VIN1A_DE0_MUXMODE_5,?,VIN1A_DE0_MUXMODE_7,VIN1A_DE0_MUXMODE_8,VIN1A_DE0_MUXMODE_9,VIN1A_DE0_MUXMODE_10,?,?,?,VIN1A_DE0_MUXMODE_14,?" line.long 0xE8 "CTRL_CORE_PAD_VIN1A_FLD0," rbitfld.long 0xE8 25. "VIN1A_FLD0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_FLD0_WAKEUPEVENT_0,VIN1A_FLD0_WAKEUPEVENT_1" newline bitfld.long 0xE8 24. "VIN1A_FLD0_WAKEUPENABLE,- DISABLE" "VIN1A_FLD0_WAKEUPENABLE_0,VIN1A_FLD0_WAKEUPENABLE_1" newline bitfld.long 0xE8 19. "VIN1A_FLD0_SLEWCONTROL,- SLOW_SLEW" "VIN1A_FLD0_SLEWCONTROL_0,VIN1A_FLD0_SLEWCONTROL_1" newline bitfld.long 0xE8 18. "VIN1A_FLD0_INPUTENABLE,- DISABLE" "VIN1A_FLD0_INPUTENABLE_0,VIN1A_FLD0_INPUTENABLE_1" newline bitfld.long 0xE8 17. "VIN1A_FLD0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_FLD0_PULLTYPESELECT_0,VIN1A_FLD0_PULLTYPESELECT_1" newline bitfld.long 0xE8 16. "VIN1A_FLD0_PULLUDENABLE,- DISABLE" "VIN1A_FLD0_PULLUDENABLE_0,VIN1A_FLD0_PULLUDENABLE_1" newline bitfld.long 0xE8 8. "VIN1A_FLD0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_FLD0_MODESELECT_0,VIN1A_FLD0_MODESELECT_1" newline bitfld.long 0xE8 4.--7. "VIN1A_FLD0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xE8 0.--3. "VIN1A_FLD0_MUXMODE,- VIN1B_VSYNC1_1" "VIN1A_FLD0_MUXMODE_0,VIN1A_FLD0_MUXMODE_1,?,?,VIN1A_FLD0_MUXMODE_4,VIN1A_FLD0_MUXMODE_5,?,VIN1A_FLD0_MUXMODE_7,VIN1A_FLD0_MUXMODE_8,VIN1A_FLD0_MUXMODE_9,VIN1A_FLD0_MUXMODE_10,?,?,?,VIN1A_FLD0_MUXMODE_14,?" line.long 0xEC "CTRL_CORE_PAD_VIN1A_HSYNC0," rbitfld.long 0xEC 25. "VIN1A_HSYNC0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_HSYNC0_WAKEUPEVENT_0,VIN1A_HSYNC0_WAKEUPEVENT_1" newline bitfld.long 0xEC 24. "VIN1A_HSYNC0_WAKEUPENABLE,- DISABLE" "VIN1A_HSYNC0_WAKEUPENABLE_0,VIN1A_HSYNC0_WAKEUPENABLE_1" newline bitfld.long 0xEC 19. "VIN1A_HSYNC0_SLEWCONTROL,- SLOW_SLEW" "VIN1A_HSYNC0_SLEWCONTROL_0,VIN1A_HSYNC0_SLEWCONTROL_1" newline bitfld.long 0xEC 18. "VIN1A_HSYNC0_INPUTENABLE,- DISABLE" "VIN1A_HSYNC0_INPUTENABLE_0,VIN1A_HSYNC0_INPUTENABLE_1" newline bitfld.long 0xEC 17. "VIN1A_HSYNC0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_HSYNC0_PULLTYPESELECT_0,VIN1A_HSYNC0_PULLTYPESELECT_1" newline bitfld.long 0xEC 16. "VIN1A_HSYNC0_PULLUDENABLE,- DISABLE" "VIN1A_HSYNC0_PULLUDENABLE_0,VIN1A_HSYNC0_PULLUDENABLE_1" newline bitfld.long 0xEC 8. "VIN1A_HSYNC0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_HSYNC0_MODESELECT_0,VIN1A_HSYNC0_MODESELECT_1" newline bitfld.long 0xEC 4.--7. "VIN1A_HSYNC0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xEC 0.--3. "VIN1A_HSYNC0_MUXMODE,- VIN1B_FLD1_1" "VIN1A_HSYNC0_MUXMODE_0,VIN1A_HSYNC0_MUXMODE_1,?,?,VIN1A_HSYNC0_MUXMODE_4,VIN1A_HSYNC0_MUXMODE_5,?,VIN1A_HSYNC0_MUXMODE_7,VIN1A_HSYNC0_MUXMODE_8,?,VIN1A_HSYNC0_MUXMODE_10,?,?,?,VIN1A_HSYNC0_MUXMODE_14,?" line.long 0xF0 "CTRL_CORE_PAD_VIN1A_VSYNC0," rbitfld.long 0xF0 25. "VIN1A_VSYNC0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_VSYNC0_WAKEUPEVENT_0,VIN1A_VSYNC0_WAKEUPEVENT_1" newline bitfld.long 0xF0 24. "VIN1A_VSYNC0_WAKEUPENABLE,- DISABLE" "VIN1A_VSYNC0_WAKEUPENABLE_0,VIN1A_VSYNC0_WAKEUPENABLE_1" newline bitfld.long 0xF0 19. "VIN1A_VSYNC0_SLEWCONTROL,- SLOW_SLEW" "VIN1A_VSYNC0_SLEWCONTROL_0,VIN1A_VSYNC0_SLEWCONTROL_1" newline bitfld.long 0xF0 18. "VIN1A_VSYNC0_INPUTENABLE,- DISABLE" "VIN1A_VSYNC0_INPUTENABLE_0,VIN1A_VSYNC0_INPUTENABLE_1" newline bitfld.long 0xF0 17. "VIN1A_VSYNC0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_VSYNC0_PULLTYPESELECT_0,VIN1A_VSYNC0_PULLTYPESELECT_1" newline bitfld.long 0xF0 16. "VIN1A_VSYNC0_PULLUDENABLE,- DISABLE" "VIN1A_VSYNC0_PULLUDENABLE_0,VIN1A_VSYNC0_PULLUDENABLE_1" newline bitfld.long 0xF0 8. "VIN1A_VSYNC0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_VSYNC0_MODESELECT_0,VIN1A_VSYNC0_MODESELECT_1" newline bitfld.long 0xF0 4.--7. "VIN1A_VSYNC0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xF0 0.--3. "VIN1A_VSYNC0_MUXMODE,- VIN1B_DE1_1" "VIN1A_VSYNC0_MUXMODE_0,VIN1A_VSYNC0_MUXMODE_1,?,?,VIN1A_VSYNC0_MUXMODE_4,VIN1A_VSYNC0_MUXMODE_5,?,VIN1A_VSYNC0_MUXMODE_7,VIN1A_VSYNC0_MUXMODE_8,?,VIN1A_VSYNC0_MUXMODE_10,?,?,?,VIN1A_VSYNC0_MUXMODE_14,?" line.long 0xF4 "CTRL_CORE_PAD_VIN1A_D0," rbitfld.long 0xF4 25. "VIN1A_D0_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D0_WAKEUPEVENT_0,VIN1A_D0_WAKEUPEVENT_1" newline bitfld.long 0xF4 24. "VIN1A_D0_WAKEUPENABLE,- DISABLE" "VIN1A_D0_WAKEUPENABLE_0,VIN1A_D0_WAKEUPENABLE_1" newline bitfld.long 0xF4 19. "VIN1A_D0_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D0_SLEWCONTROL_0,VIN1A_D0_SLEWCONTROL_1" newline bitfld.long 0xF4 18. "VIN1A_D0_INPUTENABLE,- DISABLE" "VIN1A_D0_INPUTENABLE_0,VIN1A_D0_INPUTENABLE_1" newline bitfld.long 0xF4 17. "VIN1A_D0_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D0_PULLTYPESELECT_0,VIN1A_D0_PULLTYPESELECT_1" newline bitfld.long 0xF4 16. "VIN1A_D0_PULLUDENABLE,- DISABLE" "VIN1A_D0_PULLUDENABLE_0,VIN1A_D0_PULLUDENABLE_1" newline bitfld.long 0xF4 8. "VIN1A_D0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D0_MODESELECT_0,VIN1A_D0_MODESELECT_1" newline bitfld.long 0xF4 4.--7. "VIN1A_D0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xF4 0.--3. "VIN1A_D0_MUXMODE,- GMII0_TXCLK_7" "VIN1A_D0_MUXMODE_0,?,?,VIN1A_D0_MUXMODE_3,VIN1A_D0_MUXMODE_4,VIN1A_D0_MUXMODE_5,?,VIN1A_D0_MUXMODE_7,?,?,VIN1A_D0_MUXMODE_10,?,?,?,VIN1A_D0_MUXMODE_14,?" line.long 0xF8 "CTRL_CORE_PAD_VIN1A_D1," rbitfld.long 0xF8 25. "VIN1A_D1_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D1_WAKEUPEVENT_0,VIN1A_D1_WAKEUPEVENT_1" newline bitfld.long 0xF8 24. "VIN1A_D1_WAKEUPENABLE,- DISABLE" "VIN1A_D1_WAKEUPENABLE_0,VIN1A_D1_WAKEUPENABLE_1" newline bitfld.long 0xF8 19. "VIN1A_D1_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D1_SLEWCONTROL_0,VIN1A_D1_SLEWCONTROL_1" newline bitfld.long 0xF8 18. "VIN1A_D1_INPUTENABLE,- DISABLE" "VIN1A_D1_INPUTENABLE_0,VIN1A_D1_INPUTENABLE_1" newline bitfld.long 0xF8 17. "VIN1A_D1_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D1_PULLTYPESELECT_0,VIN1A_D1_PULLTYPESELECT_1" newline bitfld.long 0xF8 16. "VIN1A_D1_PULLUDENABLE,- DISABLE" "VIN1A_D1_PULLUDENABLE_0,VIN1A_D1_PULLUDENABLE_1" newline bitfld.long 0xF8 8. "VIN1A_D1_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D1_MODESELECT_0,VIN1A_D1_MODESELECT_1" newline bitfld.long 0xF8 4.--7. "VIN1A_D1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xF8 0.--3. "VIN1A_D1_MUXMODE,- GMII0_COL_7" "VIN1A_D1_MUXMODE_0,?,?,VIN1A_D1_MUXMODE_3,VIN1A_D1_MUXMODE_4,VIN1A_D1_MUXMODE_5,?,VIN1A_D1_MUXMODE_7,?,?,VIN1A_D1_MUXMODE_10,?,?,?,VIN1A_D1_MUXMODE_14,?" line.long 0xFC "CTRL_CORE_PAD_VIN1A_D2," rbitfld.long 0xFC 25. "VIN1A_D2_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D2_WAKEUPEVENT_0,VIN1A_D2_WAKEUPEVENT_1" newline bitfld.long 0xFC 24. "VIN1A_D2_WAKEUPENABLE,- DISABLE" "VIN1A_D2_WAKEUPENABLE_0,VIN1A_D2_WAKEUPENABLE_1" newline bitfld.long 0xFC 19. "VIN1A_D2_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D2_SLEWCONTROL_0,VIN1A_D2_SLEWCONTROL_1" newline bitfld.long 0xFC 18. "VIN1A_D2_INPUTENABLE,- DISABLE" "VIN1A_D2_INPUTENABLE_0,VIN1A_D2_INPUTENABLE_1" newline bitfld.long 0xFC 17. "VIN1A_D2_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D2_PULLTYPESELECT_0,VIN1A_D2_PULLTYPESELECT_1" newline bitfld.long 0xFC 16. "VIN1A_D2_PULLUDENABLE,- DISABLE" "VIN1A_D2_PULLUDENABLE_0,VIN1A_D2_PULLUDENABLE_1" newline bitfld.long 0xFC 8. "VIN1A_D2_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D2_MODESELECT_0,VIN1A_D2_MODESELECT_1" newline bitfld.long 0xFC 4.--7. "VIN1A_D2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0xFC 0.--3. "VIN1A_D2_MUXMODE,- GMII0_CRS_7" "VIN1A_D2_MUXMODE_0,?,?,VIN1A_D2_MUXMODE_3,VIN1A_D2_MUXMODE_4,VIN1A_D2_MUXMODE_5,?,VIN1A_D2_MUXMODE_7,?,?,VIN1A_D2_MUXMODE_10,?,?,?,VIN1A_D2_MUXMODE_14,?" line.long 0x100 "CTRL_CORE_PAD_VIN1A_D3," rbitfld.long 0x100 25. "VIN1A_D3_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D3_WAKEUPEVENT_0,VIN1A_D3_WAKEUPEVENT_1" newline bitfld.long 0x100 24. "VIN1A_D3_WAKEUPENABLE,- DISABLE" "VIN1A_D3_WAKEUPENABLE_0,VIN1A_D3_WAKEUPENABLE_1" newline bitfld.long 0x100 19. "VIN1A_D3_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D3_SLEWCONTROL_0,VIN1A_D3_SLEWCONTROL_1" newline bitfld.long 0x100 18. "VIN1A_D3_INPUTENABLE,- DISABLE" "VIN1A_D3_INPUTENABLE_0,VIN1A_D3_INPUTENABLE_1" newline bitfld.long 0x100 17. "VIN1A_D3_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D3_PULLTYPESELECT_0,VIN1A_D3_PULLTYPESELECT_1" newline bitfld.long 0x100 16. "VIN1A_D3_PULLUDENABLE,- DISABLE" "VIN1A_D3_PULLUDENABLE_0,VIN1A_D3_PULLUDENABLE_1" newline bitfld.long 0x100 8. "VIN1A_D3_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D3_MODESELECT_0,VIN1A_D3_MODESELECT_1" newline bitfld.long 0x100 4.--7. "VIN1A_D3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x100 0.--3. "VIN1A_D3_MUXMODE,- PR1_PRU0_PRU_R300_13" "VIN1A_D3_MUXMODE_0,?,?,VIN1A_D3_MUXMODE_3,VIN1A_D3_MUXMODE_4,VIN1A_D3_MUXMODE_5,?,VIN1A_D3_MUXMODE_7,?,?,VIN1A_D3_MUXMODE_10,?,VIN1A_D3_MUXMODE_12,VIN1A_D3_MUXMODE_13,VIN1A_D3_MUXMODE_14,?" line.long 0x104 "CTRL_CORE_PAD_VIN1A_D4," rbitfld.long 0x104 25. "VIN1A_D4_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D4_WAKEUPEVENT_0,VIN1A_D4_WAKEUPEVENT_1" newline bitfld.long 0x104 24. "VIN1A_D4_WAKEUPENABLE,- DISABLE" "VIN1A_D4_WAKEUPENABLE_0,VIN1A_D4_WAKEUPENABLE_1" newline bitfld.long 0x104 19. "VIN1A_D4_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D4_SLEWCONTROL_0,VIN1A_D4_SLEWCONTROL_1" newline bitfld.long 0x104 18. "VIN1A_D4_INPUTENABLE,- DISABLE" "VIN1A_D4_INPUTENABLE_0,VIN1A_D4_INPUTENABLE_1" newline bitfld.long 0x104 17. "VIN1A_D4_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D4_PULLTYPESELECT_0,VIN1A_D4_PULLTYPESELECT_1" newline bitfld.long 0x104 16. "VIN1A_D4_PULLUDENABLE,- DISABLE" "VIN1A_D4_PULLUDENABLE_0,VIN1A_D4_PULLUDENABLE_1" newline bitfld.long 0x104 8. "VIN1A_D4_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D4_MODESELECT_0,VIN1A_D4_MODESELECT_1" newline bitfld.long 0x104 4.--7. "VIN1A_D4_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x104 0.--3. "VIN1A_D4_MUXMODE,- PR1_PRU0_PRU_R301_13" "VIN1A_D4_MUXMODE_0,?,?,VIN1A_D4_MUXMODE_3,VIN1A_D4_MUXMODE_4,?,?,VIN1A_D4_MUXMODE_7,?,?,VIN1A_D4_MUXMODE_10,?,VIN1A_D4_MUXMODE_12,VIN1A_D4_MUXMODE_13,VIN1A_D4_MUXMODE_14,?" line.long 0x108 "CTRL_CORE_PAD_VIN1A_D5," rbitfld.long 0x108 25. "VIN1A_D5_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D5_WAKEUPEVENT_0,VIN1A_D5_WAKEUPEVENT_1" newline bitfld.long 0x108 24. "VIN1A_D5_WAKEUPENABLE,- DISABLE" "VIN1A_D5_WAKEUPENABLE_0,VIN1A_D5_WAKEUPENABLE_1" newline bitfld.long 0x108 19. "VIN1A_D5_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D5_SLEWCONTROL_0,VIN1A_D5_SLEWCONTROL_1" newline bitfld.long 0x108 18. "VIN1A_D5_INPUTENABLE,- DISABLE" "VIN1A_D5_INPUTENABLE_0,VIN1A_D5_INPUTENABLE_1" newline bitfld.long 0x108 17. "VIN1A_D5_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D5_PULLTYPESELECT_0,VIN1A_D5_PULLTYPESELECT_1" newline bitfld.long 0x108 16. "VIN1A_D5_PULLUDENABLE,- DISABLE" "VIN1A_D5_PULLUDENABLE_0,VIN1A_D5_PULLUDENABLE_1" newline bitfld.long 0x108 8. "VIN1A_D5_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D5_MODESELECT_0,VIN1A_D5_MODESELECT_1" newline bitfld.long 0x108 4.--7. "VIN1A_D5_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x108 0.--3. "VIN1A_D5_MUXMODE,- PR1_PRU0_PRU_R302_13" "VIN1A_D5_MUXMODE_0,?,?,VIN1A_D5_MUXMODE_3,VIN1A_D5_MUXMODE_4,?,?,VIN1A_D5_MUXMODE_7,?,?,VIN1A_D5_MUXMODE_10,?,VIN1A_D5_MUXMODE_12,VIN1A_D5_MUXMODE_13,VIN1A_D5_MUXMODE_14,?" line.long 0x10C "CTRL_CORE_PAD_VIN1A_D6," rbitfld.long 0x10C 25. "VIN1A_D6_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D6_WAKEUPEVENT_0,VIN1A_D6_WAKEUPEVENT_1" newline bitfld.long 0x10C 24. "VIN1A_D6_WAKEUPENABLE,- DISABLE" "VIN1A_D6_WAKEUPENABLE_0,VIN1A_D6_WAKEUPENABLE_1" newline bitfld.long 0x10C 19. "VIN1A_D6_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D6_SLEWCONTROL_0,VIN1A_D6_SLEWCONTROL_1" newline bitfld.long 0x10C 18. "VIN1A_D6_INPUTENABLE,- DISABLE" "VIN1A_D6_INPUTENABLE_0,VIN1A_D6_INPUTENABLE_1" newline bitfld.long 0x10C 17. "VIN1A_D6_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D6_PULLTYPESELECT_0,VIN1A_D6_PULLTYPESELECT_1" newline bitfld.long 0x10C 16. "VIN1A_D6_PULLUDENABLE,- DISABLE" "VIN1A_D6_PULLUDENABLE_0,VIN1A_D6_PULLUDENABLE_1" newline bitfld.long 0x10C 8. "VIN1A_D6_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D6_MODESELECT_0,VIN1A_D6_MODESELECT_1" newline bitfld.long 0x10C 4.--7. "VIN1A_D6_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10C 0.--3. "VIN1A_D6_MUXMODE,- PR1_PRU0_PRU_R303_13" "VIN1A_D6_MUXMODE_0,?,?,VIN1A_D6_MUXMODE_3,VIN1A_D6_MUXMODE_4,?,?,VIN1A_D6_MUXMODE_7,?,?,VIN1A_D6_MUXMODE_10,?,VIN1A_D6_MUXMODE_12,VIN1A_D6_MUXMODE_13,VIN1A_D6_MUXMODE_14,?" line.long 0x110 "CTRL_CORE_PAD_VIN1A_D7," rbitfld.long 0x110 25. "VIN1A_D7_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D7_WAKEUPEVENT_0,VIN1A_D7_WAKEUPEVENT_1" newline bitfld.long 0x110 24. "VIN1A_D7_WAKEUPENABLE,- DISABLE" "VIN1A_D7_WAKEUPENABLE_0,VIN1A_D7_WAKEUPENABLE_1" newline bitfld.long 0x110 19. "VIN1A_D7_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D7_SLEWCONTROL_0,VIN1A_D7_SLEWCONTROL_1" newline bitfld.long 0x110 18. "VIN1A_D7_INPUTENABLE,- DISABLE" "VIN1A_D7_INPUTENABLE_0,VIN1A_D7_INPUTENABLE_1" newline bitfld.long 0x110 17. "VIN1A_D7_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D7_PULLTYPESELECT_0,VIN1A_D7_PULLTYPESELECT_1" newline bitfld.long 0x110 16. "VIN1A_D7_PULLUDENABLE,- DISABLE" "VIN1A_D7_PULLUDENABLE_0,VIN1A_D7_PULLUDENABLE_1" newline bitfld.long 0x110 8. "VIN1A_D7_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D7_MODESELECT_0,VIN1A_D7_MODESELECT_1" newline bitfld.long 0x110 4.--7. "VIN1A_D7_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x110 0.--3. "VIN1A_D7_MUXMODE,- PR1_PRU0_PRU_R304_13" "VIN1A_D7_MUXMODE_0,?,?,VIN1A_D7_MUXMODE_3,VIN1A_D7_MUXMODE_4,?,?,VIN1A_D7_MUXMODE_7,?,?,VIN1A_D7_MUXMODE_10,?,VIN1A_D7_MUXMODE_12,VIN1A_D7_MUXMODE_13,VIN1A_D7_MUXMODE_14,?" line.long 0x114 "CTRL_CORE_PAD_VIN1A_D8," rbitfld.long 0x114 25. "VIN1A_D8_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D8_WAKEUPEVENT_0,VIN1A_D8_WAKEUPEVENT_1" newline bitfld.long 0x114 24. "VIN1A_D8_WAKEUPENABLE,- DISABLE" "VIN1A_D8_WAKEUPENABLE_0,VIN1A_D8_WAKEUPENABLE_1" newline bitfld.long 0x114 19. "VIN1A_D8_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D8_SLEWCONTROL_0,VIN1A_D8_SLEWCONTROL_1" newline bitfld.long 0x114 18. "VIN1A_D8_INPUTENABLE,- DISABLE" "VIN1A_D8_INPUTENABLE_0,VIN1A_D8_INPUTENABLE_1" newline bitfld.long 0x114 17. "VIN1A_D8_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D8_PULLTYPESELECT_0,VIN1A_D8_PULLTYPESELECT_1" newline bitfld.long 0x114 16. "VIN1A_D8_PULLUDENABLE,- DISABLE" "VIN1A_D8_PULLUDENABLE_0,VIN1A_D8_PULLUDENABLE_1" newline bitfld.long 0x114 8. "VIN1A_D8_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D8_MODESELECT_0,VIN1A_D8_MODESELECT_1" newline bitfld.long 0x114 4.--7. "VIN1A_D8_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x114 0.--3. "VIN1A_D8_MUXMODE,- PR1_PRU0_PRU_R305_13" "VIN1A_D8_MUXMODE_0,VIN1A_D8_MUXMODE_1,?,?,VIN1A_D8_MUXMODE_4,?,?,VIN1A_D8_MUXMODE_7,?,VIN1A_D8_MUXMODE_9,VIN1A_D8_MUXMODE_10,?,VIN1A_D8_MUXMODE_12,VIN1A_D8_MUXMODE_13,VIN1A_D8_MUXMODE_14,?" line.long 0x118 "CTRL_CORE_PAD_VIN1A_D9," rbitfld.long 0x118 25. "VIN1A_D9_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D9_WAKEUPEVENT_0,VIN1A_D9_WAKEUPEVENT_1" newline bitfld.long 0x118 24. "VIN1A_D9_WAKEUPENABLE,- DISABLE" "VIN1A_D9_WAKEUPENABLE_0,VIN1A_D9_WAKEUPENABLE_1" newline bitfld.long 0x118 19. "VIN1A_D9_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D9_SLEWCONTROL_0,VIN1A_D9_SLEWCONTROL_1" newline bitfld.long 0x118 18. "VIN1A_D9_INPUTENABLE,- DISABLE" "VIN1A_D9_INPUTENABLE_0,VIN1A_D9_INPUTENABLE_1" newline bitfld.long 0x118 17. "VIN1A_D9_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D9_PULLTYPESELECT_0,VIN1A_D9_PULLTYPESELECT_1" newline bitfld.long 0x118 16. "VIN1A_D9_PULLUDENABLE,- DISABLE" "VIN1A_D9_PULLUDENABLE_0,VIN1A_D9_PULLUDENABLE_1" newline bitfld.long 0x118 8. "VIN1A_D9_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D9_MODESELECT_0,VIN1A_D9_MODESELECT_1" newline bitfld.long 0x118 4.--7. "VIN1A_D9_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x118 0.--3. "VIN1A_D9_MUXMODE,- PR1_PRU0_PRU_R306_13" "VIN1A_D9_MUXMODE_0,VIN1A_D9_MUXMODE_1,?,?,VIN1A_D9_MUXMODE_4,?,?,VIN1A_D9_MUXMODE_7,?,VIN1A_D9_MUXMODE_9,VIN1A_D9_MUXMODE_10,?,VIN1A_D9_MUXMODE_12,VIN1A_D9_MUXMODE_13,VIN1A_D9_MUXMODE_14,?" line.long 0x11C "CTRL_CORE_PAD_VIN1A_D10," rbitfld.long 0x11C 25. "VIN1A_D10_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D10_WAKEUPEVENT_0,VIN1A_D10_WAKEUPEVENT_1" newline bitfld.long 0x11C 24. "VIN1A_D10_WAKEUPENABLE,- DISABLE" "VIN1A_D10_WAKEUPENABLE_0,VIN1A_D10_WAKEUPENABLE_1" newline bitfld.long 0x11C 19. "VIN1A_D10_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D10_SLEWCONTROL_0,VIN1A_D10_SLEWCONTROL_1" newline bitfld.long 0x11C 18. "VIN1A_D10_INPUTENABLE,- DISABLE" "VIN1A_D10_INPUTENABLE_0,VIN1A_D10_INPUTENABLE_1" newline bitfld.long 0x11C 17. "VIN1A_D10_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D10_PULLTYPESELECT_0,VIN1A_D10_PULLTYPESELECT_1" newline bitfld.long 0x11C 16. "VIN1A_D10_PULLUDENABLE,- DISABLE" "VIN1A_D10_PULLUDENABLE_0,VIN1A_D10_PULLUDENABLE_1" newline bitfld.long 0x11C 8. "VIN1A_D10_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D10_MODESELECT_0,VIN1A_D10_MODESELECT_1" newline bitfld.long 0x11C 4.--7. "VIN1A_D10_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x11C 0.--3. "VIN1A_D10_MUXMODE,- PR1_PRU0_PRU_R307_13" "VIN1A_D10_MUXMODE_0,VIN1A_D10_MUXMODE_1,?,?,VIN1A_D10_MUXMODE_4,?,?,VIN1A_D10_MUXMODE_7,?,VIN1A_D10_MUXMODE_9,VIN1A_D10_MUXMODE_10,?,VIN1A_D10_MUXMODE_12,VIN1A_D10_MUXMODE_13,VIN1A_D10_MUXMODE_14,?" line.long 0x120 "CTRL_CORE_PAD_VIN1A_D11," rbitfld.long 0x120 25. "VIN1A_D11_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D11_WAKEUPEVENT_0,VIN1A_D11_WAKEUPEVENT_1" newline bitfld.long 0x120 24. "VIN1A_D11_WAKEUPENABLE,- DISABLE" "VIN1A_D11_WAKEUPENABLE_0,VIN1A_D11_WAKEUPENABLE_1" newline bitfld.long 0x120 19. "VIN1A_D11_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D11_SLEWCONTROL_0,VIN1A_D11_SLEWCONTROL_1" newline bitfld.long 0x120 18. "VIN1A_D11_INPUTENABLE,- DISABLE" "VIN1A_D11_INPUTENABLE_0,VIN1A_D11_INPUTENABLE_1" newline bitfld.long 0x120 17. "VIN1A_D11_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D11_PULLTYPESELECT_0,VIN1A_D11_PULLTYPESELECT_1" newline bitfld.long 0x120 16. "VIN1A_D11_PULLUDENABLE,- DISABLE" "VIN1A_D11_PULLUDENABLE_0,VIN1A_D11_PULLUDENABLE_1" newline bitfld.long 0x120 8. "VIN1A_D11_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D11_MODESELECT_0,VIN1A_D11_MODESELECT_1" newline bitfld.long 0x120 4.--7. "VIN1A_D11_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x120 0.--3. "VIN1A_D11_MUXMODE,- PR1_PRU0_PRU_R308_13" "VIN1A_D11_MUXMODE_0,VIN1A_D11_MUXMODE_1,?,?,VIN1A_D11_MUXMODE_4,VIN1A_D11_MUXMODE_5,?,VIN1A_D11_MUXMODE_7,?,VIN1A_D11_MUXMODE_9,VIN1A_D11_MUXMODE_10,?,VIN1A_D11_MUXMODE_12,VIN1A_D11_MUXMODE_13,VIN1A_D11_MUXMODE_14,?" line.long 0x124 "CTRL_CORE_PAD_VIN1A_D12," rbitfld.long 0x124 25. "VIN1A_D12_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D12_WAKEUPEVENT_0,VIN1A_D12_WAKEUPEVENT_1" newline bitfld.long 0x124 24. "VIN1A_D12_WAKEUPENABLE,- DISABLE" "VIN1A_D12_WAKEUPENABLE_0,VIN1A_D12_WAKEUPENABLE_1" newline bitfld.long 0x124 19. "VIN1A_D12_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D12_SLEWCONTROL_0,VIN1A_D12_SLEWCONTROL_1" newline bitfld.long 0x124 18. "VIN1A_D12_INPUTENABLE,- DISABLE" "VIN1A_D12_INPUTENABLE_0,VIN1A_D12_INPUTENABLE_1" newline bitfld.long 0x124 17. "VIN1A_D12_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D12_PULLTYPESELECT_0,VIN1A_D12_PULLTYPESELECT_1" newline bitfld.long 0x124 16. "VIN1A_D12_PULLUDENABLE,- DISABLE" "VIN1A_D12_PULLUDENABLE_0,VIN1A_D12_PULLUDENABLE_1" newline bitfld.long 0x124 8. "VIN1A_D12_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D12_MODESELECT_0,VIN1A_D12_MODESELECT_1" newline bitfld.long 0x124 4.--7. "VIN1A_D12_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x124 0.--3. "VIN1A_D12_MUXMODE,- PR1_PRU0_PRU_R309_13" "VIN1A_D12_MUXMODE_0,VIN1A_D12_MUXMODE_1,VIN1A_D12_MUXMODE_2,?,VIN1A_D12_MUXMODE_4,VIN1A_D12_MUXMODE_5,?,VIN1A_D12_MUXMODE_7,?,VIN1A_D12_MUXMODE_9,VIN1A_D12_MUXMODE_10,?,VIN1A_D12_MUXMODE_12,VIN1A_D12_MUXMODE_13,VIN1A_D12_MUXMODE_14,?" line.long 0x128 "CTRL_CORE_PAD_VIN1A_D13," rbitfld.long 0x128 25. "VIN1A_D13_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D13_WAKEUPEVENT_0,VIN1A_D13_WAKEUPEVENT_1" newline bitfld.long 0x128 24. "VIN1A_D13_WAKEUPENABLE,- DISABLE" "VIN1A_D13_WAKEUPENABLE_0,VIN1A_D13_WAKEUPENABLE_1" newline bitfld.long 0x128 19. "VIN1A_D13_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D13_SLEWCONTROL_0,VIN1A_D13_SLEWCONTROL_1" newline bitfld.long 0x128 18. "VIN1A_D13_INPUTENABLE,- DISABLE" "VIN1A_D13_INPUTENABLE_0,VIN1A_D13_INPUTENABLE_1" newline bitfld.long 0x128 17. "VIN1A_D13_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D13_PULLTYPESELECT_0,VIN1A_D13_PULLTYPESELECT_1" newline bitfld.long 0x128 16. "VIN1A_D13_PULLUDENABLE,- DISABLE" "VIN1A_D13_PULLUDENABLE_0,VIN1A_D13_PULLUDENABLE_1" newline bitfld.long 0x128 8. "VIN1A_D13_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D13_MODESELECT_0,VIN1A_D13_MODESELECT_1" newline bitfld.long 0x128 4.--7. "VIN1A_D13_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x128 0.--3. "VIN1A_D13_MUXMODE,- PR1_PRU0_PRU_R3010_13" "VIN1A_D13_MUXMODE_0,VIN1A_D13_MUXMODE_1,VIN1A_D13_MUXMODE_2,?,VIN1A_D13_MUXMODE_4,VIN1A_D13_MUXMODE_5,?,VIN1A_D13_MUXMODE_7,?,VIN1A_D13_MUXMODE_9,VIN1A_D13_MUXMODE_10,?,VIN1A_D13_MUXMODE_12,VIN1A_D13_MUXMODE_13,VIN1A_D13_MUXMODE_14,?" line.long 0x12C "CTRL_CORE_PAD_VIN1A_D14," rbitfld.long 0x12C 25. "VIN1A_D14_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D14_WAKEUPEVENT_0,VIN1A_D14_WAKEUPEVENT_1" newline bitfld.long 0x12C 24. "VIN1A_D14_WAKEUPENABLE,- DISABLE" "VIN1A_D14_WAKEUPENABLE_0,VIN1A_D14_WAKEUPENABLE_1" newline bitfld.long 0x12C 19. "VIN1A_D14_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D14_SLEWCONTROL_0,VIN1A_D14_SLEWCONTROL_1" newline bitfld.long 0x12C 18. "VIN1A_D14_INPUTENABLE,- DISABLE" "VIN1A_D14_INPUTENABLE_0,VIN1A_D14_INPUTENABLE_1" newline bitfld.long 0x12C 17. "VIN1A_D14_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D14_PULLTYPESELECT_0,VIN1A_D14_PULLTYPESELECT_1" newline bitfld.long 0x12C 16. "VIN1A_D14_PULLUDENABLE,- DISABLE" "VIN1A_D14_PULLUDENABLE_0,VIN1A_D14_PULLUDENABLE_1" newline bitfld.long 0x12C 8. "VIN1A_D14_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D14_MODESELECT_0,VIN1A_D14_MODESELECT_1" newline bitfld.long 0x12C 4.--7. "VIN1A_D14_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x12C 0.--3. "VIN1A_D14_MUXMODE,- PR1_PRU0_PRU_R3011_13" "VIN1A_D14_MUXMODE_0,VIN1A_D14_MUXMODE_1,VIN1A_D14_MUXMODE_2,?,VIN1A_D14_MUXMODE_4,VIN1A_D14_MUXMODE_5,?,VIN1A_D14_MUXMODE_7,?,VIN1A_D14_MUXMODE_9,VIN1A_D14_MUXMODE_10,?,VIN1A_D14_MUXMODE_12,VIN1A_D14_MUXMODE_13,VIN1A_D14_MUXMODE_14,?" line.long 0x130 "CTRL_CORE_PAD_VIN1A_D15," rbitfld.long 0x130 25. "VIN1A_D15_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D15_WAKEUPEVENT_0,VIN1A_D15_WAKEUPEVENT_1" newline bitfld.long 0x130 24. "VIN1A_D15_WAKEUPENABLE,- DISABLE" "VIN1A_D15_WAKEUPENABLE_0,VIN1A_D15_WAKEUPENABLE_1" newline bitfld.long 0x130 19. "VIN1A_D15_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D15_SLEWCONTROL_0,VIN1A_D15_SLEWCONTROL_1" newline bitfld.long 0x130 18. "VIN1A_D15_INPUTENABLE,- DISABLE" "VIN1A_D15_INPUTENABLE_0,VIN1A_D15_INPUTENABLE_1" newline bitfld.long 0x130 17. "VIN1A_D15_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D15_PULLTYPESELECT_0,VIN1A_D15_PULLTYPESELECT_1" newline bitfld.long 0x130 16. "VIN1A_D15_PULLUDENABLE,- DISABLE" "VIN1A_D15_PULLUDENABLE_0,VIN1A_D15_PULLUDENABLE_1" newline bitfld.long 0x130 8. "VIN1A_D15_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D15_MODESELECT_0,VIN1A_D15_MODESELECT_1" newline bitfld.long 0x130 4.--7. "VIN1A_D15_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x130 0.--3. "VIN1A_D15_MUXMODE,- PR1_PRU0_PRU_R3012_13" "VIN1A_D15_MUXMODE_0,VIN1A_D15_MUXMODE_1,VIN1A_D15_MUXMODE_2,?,VIN1A_D15_MUXMODE_4,VIN1A_D15_MUXMODE_5,?,VIN1A_D15_MUXMODE_7,?,VIN1A_D15_MUXMODE_9,VIN1A_D15_MUXMODE_10,?,VIN1A_D15_MUXMODE_12,VIN1A_D15_MUXMODE_13,VIN1A_D15_MUXMODE_14,?" line.long 0x134 "CTRL_CORE_PAD_VIN1A_D16," rbitfld.long 0x134 25. "VIN1A_D16_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D16_WAKEUPEVENT_0,VIN1A_D16_WAKEUPEVENT_1" newline bitfld.long 0x134 24. "VIN1A_D16_WAKEUPENABLE,- DISABLE" "VIN1A_D16_WAKEUPENABLE_0,VIN1A_D16_WAKEUPENABLE_1" newline bitfld.long 0x134 19. "VIN1A_D16_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D16_SLEWCONTROL_0,VIN1A_D16_SLEWCONTROL_1" newline bitfld.long 0x134 18. "VIN1A_D16_INPUTENABLE,- DISABLE" "VIN1A_D16_INPUTENABLE_0,VIN1A_D16_INPUTENABLE_1" newline bitfld.long 0x134 17. "VIN1A_D16_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D16_PULLTYPESELECT_0,VIN1A_D16_PULLTYPESELECT_1" newline bitfld.long 0x134 16. "VIN1A_D16_PULLUDENABLE,- DISABLE" "VIN1A_D16_PULLUDENABLE_0,VIN1A_D16_PULLUDENABLE_1" newline bitfld.long 0x134 8. "VIN1A_D16_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D16_MODESELECT_0,VIN1A_D16_MODESELECT_1" newline bitfld.long 0x134 4.--7. "VIN1A_D16_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x134 0.--3. "VIN1A_D16_MUXMODE,- PR1_PRU0_PRU_R3013_13" "VIN1A_D16_MUXMODE_0,VIN1A_D16_MUXMODE_1,VIN1A_D16_MUXMODE_2,?,VIN1A_D16_MUXMODE_4,?,VIN1A_D16_MUXMODE_6,VIN1A_D16_MUXMODE_7,?,VIN1A_D16_MUXMODE_9,VIN1A_D16_MUXMODE_10,VIN1A_D16_MUXMODE_11,VIN1A_D16_MUXMODE_12,VIN1A_D16_MUXMODE_13,VIN1A_D16_MUXMODE_14,?" line.long 0x138 "CTRL_CORE_PAD_VIN1A_D17," rbitfld.long 0x138 25. "VIN1A_D17_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D17_WAKEUPEVENT_0,VIN1A_D17_WAKEUPEVENT_1" newline bitfld.long 0x138 24. "VIN1A_D17_WAKEUPENABLE,- DISABLE" "VIN1A_D17_WAKEUPENABLE_0,VIN1A_D17_WAKEUPENABLE_1" newline bitfld.long 0x138 19. "VIN1A_D17_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D17_SLEWCONTROL_0,VIN1A_D17_SLEWCONTROL_1" newline bitfld.long 0x138 18. "VIN1A_D17_INPUTENABLE,- DISABLE" "VIN1A_D17_INPUTENABLE_0,VIN1A_D17_INPUTENABLE_1" newline bitfld.long 0x138 17. "VIN1A_D17_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D17_PULLTYPESELECT_0,VIN1A_D17_PULLTYPESELECT_1" newline bitfld.long 0x138 16. "VIN1A_D17_PULLUDENABLE,- DISABLE" "VIN1A_D17_PULLUDENABLE_0,VIN1A_D17_PULLUDENABLE_1" newline bitfld.long 0x138 8. "VIN1A_D17_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D17_MODESELECT_0,VIN1A_D17_MODESELECT_1" newline bitfld.long 0x138 4.--7. "VIN1A_D17_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x138 0.--3. "VIN1A_D17_MUXMODE,- PR1_PRU0_PRU_R3014_13" "VIN1A_D17_MUXMODE_0,VIN1A_D17_MUXMODE_1,VIN1A_D17_MUXMODE_2,?,VIN1A_D17_MUXMODE_4,?,VIN1A_D17_MUXMODE_6,VIN1A_D17_MUXMODE_7,?,VIN1A_D17_MUXMODE_9,VIN1A_D17_MUXMODE_10,VIN1A_D17_MUXMODE_11,VIN1A_D17_MUXMODE_12,VIN1A_D17_MUXMODE_13,VIN1A_D17_MUXMODE_14,?" line.long 0x13C "CTRL_CORE_PAD_VIN1A_D18," rbitfld.long 0x13C 25. "VIN1A_D18_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D18_WAKEUPEVENT_0,VIN1A_D18_WAKEUPEVENT_1" newline bitfld.long 0x13C 24. "VIN1A_D18_WAKEUPENABLE,- DISABLE" "VIN1A_D18_WAKEUPENABLE_0,VIN1A_D18_WAKEUPENABLE_1" newline bitfld.long 0x13C 19. "VIN1A_D18_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D18_SLEWCONTROL_0,VIN1A_D18_SLEWCONTROL_1" newline bitfld.long 0x13C 18. "VIN1A_D18_INPUTENABLE,- DISABLE" "VIN1A_D18_INPUTENABLE_0,VIN1A_D18_INPUTENABLE_1" newline bitfld.long 0x13C 17. "VIN1A_D18_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D18_PULLTYPESELECT_0,VIN1A_D18_PULLTYPESELECT_1" newline bitfld.long 0x13C 16. "VIN1A_D18_PULLUDENABLE,- DISABLE" "VIN1A_D18_PULLUDENABLE_0,VIN1A_D18_PULLUDENABLE_1" newline bitfld.long 0x13C 8. "VIN1A_D18_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D18_MODESELECT_0,VIN1A_D18_MODESELECT_1" newline bitfld.long 0x13C 4.--7. "VIN1A_D18_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x13C 0.--3. "VIN1A_D18_MUXMODE,- PR1_PRU0_PRU_R3015_13" "VIN1A_D18_MUXMODE_0,VIN1A_D18_MUXMODE_1,VIN1A_D18_MUXMODE_2,?,VIN1A_D18_MUXMODE_4,?,VIN1A_D18_MUXMODE_6,VIN1A_D18_MUXMODE_7,?,VIN1A_D18_MUXMODE_9,VIN1A_D18_MUXMODE_10,VIN1A_D18_MUXMODE_11,VIN1A_D18_MUXMODE_12,VIN1A_D18_MUXMODE_13,VIN1A_D18_MUXMODE_14,?" line.long 0x140 "CTRL_CORE_PAD_VIN1A_D19," rbitfld.long 0x140 25. "VIN1A_D19_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D19_WAKEUPEVENT_0,VIN1A_D19_WAKEUPEVENT_1" newline bitfld.long 0x140 24. "VIN1A_D19_WAKEUPENABLE,- DISABLE" "VIN1A_D19_WAKEUPENABLE_0,VIN1A_D19_WAKEUPENABLE_1" newline bitfld.long 0x140 19. "VIN1A_D19_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D19_SLEWCONTROL_0,VIN1A_D19_SLEWCONTROL_1" newline bitfld.long 0x140 18. "VIN1A_D19_INPUTENABLE,- DISABLE" "VIN1A_D19_INPUTENABLE_0,VIN1A_D19_INPUTENABLE_1" newline bitfld.long 0x140 17. "VIN1A_D19_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D19_PULLTYPESELECT_0,VIN1A_D19_PULLTYPESELECT_1" newline bitfld.long 0x140 16. "VIN1A_D19_PULLUDENABLE,- DISABLE" "VIN1A_D19_PULLUDENABLE_0,VIN1A_D19_PULLUDENABLE_1" newline bitfld.long 0x140 8. "VIN1A_D19_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D19_MODESELECT_0,VIN1A_D19_MODESELECT_1" newline bitfld.long 0x140 4.--7. "VIN1A_D19_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x140 0.--3. "VIN1A_D19_MUXMODE,- PR1_PRU0_PRU_R3016_13" "VIN1A_D19_MUXMODE_0,VIN1A_D19_MUXMODE_1,VIN1A_D19_MUXMODE_2,?,VIN1A_D19_MUXMODE_4,?,VIN1A_D19_MUXMODE_6,VIN1A_D19_MUXMODE_7,?,VIN1A_D19_MUXMODE_9,VIN1A_D19_MUXMODE_10,VIN1A_D19_MUXMODE_11,VIN1A_D19_MUXMODE_12,VIN1A_D19_MUXMODE_13,VIN1A_D19_MUXMODE_14,?" line.long 0x144 "CTRL_CORE_PAD_VIN1A_D20," rbitfld.long 0x144 25. "VIN1A_D20_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D20_WAKEUPEVENT_0,VIN1A_D20_WAKEUPEVENT_1" newline bitfld.long 0x144 24. "VIN1A_D20_WAKEUPENABLE,- DISABLE" "VIN1A_D20_WAKEUPENABLE_0,VIN1A_D20_WAKEUPENABLE_1" newline bitfld.long 0x144 19. "VIN1A_D20_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D20_SLEWCONTROL_0,VIN1A_D20_SLEWCONTROL_1" newline bitfld.long 0x144 18. "VIN1A_D20_INPUTENABLE,- DISABLE" "VIN1A_D20_INPUTENABLE_0,VIN1A_D20_INPUTENABLE_1" newline bitfld.long 0x144 17. "VIN1A_D20_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D20_PULLTYPESELECT_0,VIN1A_D20_PULLTYPESELECT_1" newline bitfld.long 0x144 16. "VIN1A_D20_PULLUDENABLE,- DISABLE" "VIN1A_D20_PULLUDENABLE_0,VIN1A_D20_PULLUDENABLE_1" newline bitfld.long 0x144 8. "VIN1A_D20_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D20_MODESELECT_0,VIN1A_D20_MODESELECT_1" newline bitfld.long 0x144 4.--7. "VIN1A_D20_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x144 0.--3. "VIN1A_D20_MUXMODE,- PR1_PRU0_PRU_R3017_13" "VIN1A_D20_MUXMODE_0,VIN1A_D20_MUXMODE_1,VIN1A_D20_MUXMODE_2,?,VIN1A_D20_MUXMODE_4,?,VIN1A_D20_MUXMODE_6,VIN1A_D20_MUXMODE_7,?,VIN1A_D20_MUXMODE_9,VIN1A_D20_MUXMODE_10,VIN1A_D20_MUXMODE_11,VIN1A_D20_MUXMODE_12,VIN1A_D20_MUXMODE_13,VIN1A_D20_MUXMODE_14,?" line.long 0x148 "CTRL_CORE_PAD_VIN1A_D21," rbitfld.long 0x148 25. "VIN1A_D21_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D21_WAKEUPEVENT_0,VIN1A_D21_WAKEUPEVENT_1" newline bitfld.long 0x148 24. "VIN1A_D21_WAKEUPENABLE,- DISABLE" "VIN1A_D21_WAKEUPENABLE_0,VIN1A_D21_WAKEUPENABLE_1" newline bitfld.long 0x148 19. "VIN1A_D21_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D21_SLEWCONTROL_0,VIN1A_D21_SLEWCONTROL_1" newline bitfld.long 0x148 18. "VIN1A_D21_INPUTENABLE,- DISABLE" "VIN1A_D21_INPUTENABLE_0,VIN1A_D21_INPUTENABLE_1" newline bitfld.long 0x148 17. "VIN1A_D21_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D21_PULLTYPESELECT_0,VIN1A_D21_PULLTYPESELECT_1" newline bitfld.long 0x148 16. "VIN1A_D21_PULLUDENABLE,- DISABLE" "VIN1A_D21_PULLUDENABLE_0,VIN1A_D21_PULLUDENABLE_1" newline bitfld.long 0x148 8. "VIN1A_D21_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D21_MODESELECT_0,VIN1A_D21_MODESELECT_1" newline bitfld.long 0x148 4.--7. "VIN1A_D21_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x148 0.--3. "VIN1A_D21_MUXMODE,- PR1_PRU0_PRU_R3018_13" "VIN1A_D21_MUXMODE_0,VIN1A_D21_MUXMODE_1,VIN1A_D21_MUXMODE_2,?,VIN1A_D21_MUXMODE_4,?,VIN1A_D21_MUXMODE_6,VIN1A_D21_MUXMODE_7,?,VIN1A_D21_MUXMODE_9,VIN1A_D21_MUXMODE_10,VIN1A_D21_MUXMODE_11,VIN1A_D21_MUXMODE_12,VIN1A_D21_MUXMODE_13,VIN1A_D21_MUXMODE_14,?" line.long 0x14C "CTRL_CORE_PAD_VIN1A_D22," rbitfld.long 0x14C 25. "VIN1A_D22_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D22_WAKEUPEVENT_0,VIN1A_D22_WAKEUPEVENT_1" newline bitfld.long 0x14C 24. "VIN1A_D22_WAKEUPENABLE,- DISABLE" "VIN1A_D22_WAKEUPENABLE_0,VIN1A_D22_WAKEUPENABLE_1" newline bitfld.long 0x14C 19. "VIN1A_D22_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D22_SLEWCONTROL_0,VIN1A_D22_SLEWCONTROL_1" newline bitfld.long 0x14C 18. "VIN1A_D22_INPUTENABLE,- DISABLE" "VIN1A_D22_INPUTENABLE_0,VIN1A_D22_INPUTENABLE_1" newline bitfld.long 0x14C 17. "VIN1A_D22_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D22_PULLTYPESELECT_0,VIN1A_D22_PULLTYPESELECT_1" newline bitfld.long 0x14C 16. "VIN1A_D22_PULLUDENABLE,- DISABLE" "VIN1A_D22_PULLUDENABLE_0,VIN1A_D22_PULLUDENABLE_1" newline bitfld.long 0x14C 8. "VIN1A_D22_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D22_MODESELECT_0,VIN1A_D22_MODESELECT_1" newline bitfld.long 0x14C 4.--7. "VIN1A_D22_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14C 0.--3. "VIN1A_D22_MUXMODE,- PR1_PRU0_PRU_R3019_13" "VIN1A_D22_MUXMODE_0,VIN1A_D22_MUXMODE_1,VIN1A_D22_MUXMODE_2,?,VIN1A_D22_MUXMODE_4,?,VIN1A_D22_MUXMODE_6,VIN1A_D22_MUXMODE_7,?,VIN1A_D22_MUXMODE_9,VIN1A_D22_MUXMODE_10,VIN1A_D22_MUXMODE_11,VIN1A_D22_MUXMODE_12,VIN1A_D22_MUXMODE_13,VIN1A_D22_MUXMODE_14,?" line.long 0x150 "CTRL_CORE_PAD_VIN1A_D23," rbitfld.long 0x150 25. "VIN1A_D23_WAKEUPEVENT,- NOWAKEUP" "VIN1A_D23_WAKEUPEVENT_0,VIN1A_D23_WAKEUPEVENT_1" newline bitfld.long 0x150 24. "VIN1A_D23_WAKEUPENABLE,- DISABLE" "VIN1A_D23_WAKEUPENABLE_0,VIN1A_D23_WAKEUPENABLE_1" newline bitfld.long 0x150 19. "VIN1A_D23_SLEWCONTROL,- SLOW_SLEW" "VIN1A_D23_SLEWCONTROL_0,VIN1A_D23_SLEWCONTROL_1" newline bitfld.long 0x150 18. "VIN1A_D23_INPUTENABLE,- DISABLE" "VIN1A_D23_INPUTENABLE_0,VIN1A_D23_INPUTENABLE_1" newline bitfld.long 0x150 17. "VIN1A_D23_PULLTYPESELECT,- PULL_DOWN" "VIN1A_D23_PULLTYPESELECT_0,VIN1A_D23_PULLTYPESELECT_1" newline bitfld.long 0x150 16. "VIN1A_D23_PULLUDENABLE,- DISABLE" "VIN1A_D23_PULLUDENABLE_0,VIN1A_D23_PULLUDENABLE_1" newline bitfld.long 0x150 8. "VIN1A_D23_MODESELECT,Selects between default and another IO delay different than the default one" "VIN1A_D23_MODESELECT_0,VIN1A_D23_MODESELECT_1" newline bitfld.long 0x150 4.--7. "VIN1A_D23_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x150 0.--3. "VIN1A_D23_MUXMODE,- PR1_PRU0_PRU_R3020_13" "VIN1A_D23_MUXMODE_0,VIN1A_D23_MUXMODE_1,VIN1A_D23_MUXMODE_2,?,VIN1A_D23_MUXMODE_4,?,VIN1A_D23_MUXMODE_6,VIN1A_D23_MUXMODE_7,?,VIN1A_D23_MUXMODE_9,VIN1A_D23_MUXMODE_10,VIN1A_D23_MUXMODE_11,VIN1A_D23_MUXMODE_12,VIN1A_D23_MUXMODE_13,VIN1A_D23_MUXMODE_14,?" line.long 0x154 "CTRL_CORE_PAD_VIN2A_CLK0," rbitfld.long 0x154 25. "VIN2A_CLK0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_CLK0_WAKEUPEVENT_0,VIN2A_CLK0_WAKEUPEVENT_1" newline bitfld.long 0x154 24. "VIN2A_CLK0_WAKEUPENABLE,- DISABLE" "VIN2A_CLK0_WAKEUPENABLE_0,VIN2A_CLK0_WAKEUPENABLE_1" newline bitfld.long 0x154 19. "VIN2A_CLK0_SLEWCONTROL,- SLOW_SLEW" "VIN2A_CLK0_SLEWCONTROL_0,VIN2A_CLK0_SLEWCONTROL_1" newline bitfld.long 0x154 18. "VIN2A_CLK0_INPUTENABLE,- DISABLE" "VIN2A_CLK0_INPUTENABLE_0,VIN2A_CLK0_INPUTENABLE_1" newline bitfld.long 0x154 17. "VIN2A_CLK0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_CLK0_PULLTYPESELECT_0,VIN2A_CLK0_PULLTYPESELECT_1" newline bitfld.long 0x154 16. "VIN2A_CLK0_PULLUDENABLE,- DISABLE" "VIN2A_CLK0_PULLUDENABLE_0,VIN2A_CLK0_PULLUDENABLE_1" newline bitfld.long 0x154 8. "VIN2A_CLK0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_CLK0_MODESELECT_0,VIN2A_CLK0_MODESELECT_1" newline bitfld.long 0x154 4.--7. "VIN2A_CLK0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x154 0.--3. "VIN2A_CLK0_MUXMODE,- PR1_EDIO_DATA_OUT0_13" "VIN2A_CLK0_MUXMODE_0,?,?,?,VIN2A_CLK0_MUXMODE_4,VIN2A_CLK0_MUXMODE_5,?,?,?,VIN2A_CLK0_MUXMODE_9,VIN2A_CLK0_MUXMODE_10,?,VIN2A_CLK0_MUXMODE_12,VIN2A_CLK0_MUXMODE_13,VIN2A_CLK0_MUXMODE_14,?" line.long 0x158 "CTRL_CORE_PAD_VIN2A_DE0," rbitfld.long 0x158 25. "VIN2A_DE0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_DE0_WAKEUPEVENT_0,VIN2A_DE0_WAKEUPEVENT_1" newline bitfld.long 0x158 24. "VIN2A_DE0_WAKEUPENABLE,- DISABLE" "VIN2A_DE0_WAKEUPENABLE_0,VIN2A_DE0_WAKEUPENABLE_1" newline bitfld.long 0x158 19. "VIN2A_DE0_SLEWCONTROL,- SLOW_SLEW" "VIN2A_DE0_SLEWCONTROL_0,VIN2A_DE0_SLEWCONTROL_1" newline bitfld.long 0x158 18. "VIN2A_DE0_INPUTENABLE,- DISABLE" "VIN2A_DE0_INPUTENABLE_0,VIN2A_DE0_INPUTENABLE_1" newline bitfld.long 0x158 17. "VIN2A_DE0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_DE0_PULLTYPESELECT_0,VIN2A_DE0_PULLTYPESELECT_1" newline bitfld.long 0x158 16. "VIN2A_DE0_PULLUDENABLE,- DISABLE" "VIN2A_DE0_PULLUDENABLE_0,VIN2A_DE0_PULLUDENABLE_1" newline bitfld.long 0x158 8. "VIN2A_DE0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_DE0_MODESELECT_0,VIN2A_DE0_MODESELECT_1" newline bitfld.long 0x158 4.--7. "VIN2A_DE0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x158 0.--3. "VIN2A_DE0_MUXMODE,- PR1_EDIO_DATA_OUT1_13" "VIN2A_DE0_MUXMODE_0,VIN2A_DE0_MUXMODE_1,VIN2A_DE0_MUXMODE_2,VIN2A_DE0_MUXMODE_3,VIN2A_DE0_MUXMODE_4,VIN2A_DE0_MUXMODE_5,?,VIN2A_DE0_MUXMODE_7,?,VIN2A_DE0_MUXMODE_9,VIN2A_DE0_MUXMODE_10,?,VIN2A_DE0_MUXMODE_12,VIN2A_DE0_MUXMODE_13,VIN2A_DE0_MUXMODE_14,?" line.long 0x15C "CTRL_CORE_PAD_VIN2A_FLD0," rbitfld.long 0x15C 25. "VIN2A_FLD0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_FLD0_WAKEUPEVENT_0,VIN2A_FLD0_WAKEUPEVENT_1" newline bitfld.long 0x15C 24. "VIN2A_FLD0_WAKEUPENABLE,- DISABLE" "VIN2A_FLD0_WAKEUPENABLE_0,VIN2A_FLD0_WAKEUPENABLE_1" newline bitfld.long 0x15C 19. "VIN2A_FLD0_SLEWCONTROL,- SLOW_SLEW" "VIN2A_FLD0_SLEWCONTROL_0,VIN2A_FLD0_SLEWCONTROL_1" newline bitfld.long 0x15C 18. "VIN2A_FLD0_INPUTENABLE,- DISABLE" "VIN2A_FLD0_INPUTENABLE_0,VIN2A_FLD0_INPUTENABLE_1" newline bitfld.long 0x15C 17. "VIN2A_FLD0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_FLD0_PULLTYPESELECT_0,VIN2A_FLD0_PULLTYPESELECT_1" newline bitfld.long 0x15C 16. "VIN2A_FLD0_PULLUDENABLE,- DISABLE" "VIN2A_FLD0_PULLUDENABLE_0,VIN2A_FLD0_PULLUDENABLE_1" newline bitfld.long 0x15C 8. "VIN2A_FLD0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_FLD0_MODESELECT_0,VIN2A_FLD0_MODESELECT_1" newline bitfld.long 0x15C 4.--7. "VIN2A_FLD0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x15C 0.--3. "VIN2A_FLD0_MUXMODE,- PR1_EDIO_DATA_OUT2_13" "VIN2A_FLD0_MUXMODE_0,?,VIN2A_FLD0_MUXMODE_2,?,VIN2A_FLD0_MUXMODE_4,VIN2A_FLD0_MUXMODE_5,?,VIN2A_FLD0_MUXMODE_7,?,?,VIN2A_FLD0_MUXMODE_10,?,VIN2A_FLD0_MUXMODE_12,VIN2A_FLD0_MUXMODE_13,VIN2A_FLD0_MUXMODE_14,?" line.long 0x160 "CTRL_CORE_PAD_VIN2A_HSYNC0," rbitfld.long 0x160 25. "VIN2A_HSYNC0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_HSYNC0_WAKEUPEVENT_0,VIN2A_HSYNC0_WAKEUPEVENT_1" newline bitfld.long 0x160 24. "VIN2A_HSYNC0_WAKEUPENABLE,- DISABLE" "VIN2A_HSYNC0_WAKEUPENABLE_0,VIN2A_HSYNC0_WAKEUPENABLE_1" newline bitfld.long 0x160 19. "VIN2A_HSYNC0_SLEWCONTROL,- SLOW_SLEW" "VIN2A_HSYNC0_SLEWCONTROL_0,VIN2A_HSYNC0_SLEWCONTROL_1" newline bitfld.long 0x160 18. "VIN2A_HSYNC0_INPUTENABLE,- DISABLE" "VIN2A_HSYNC0_INPUTENABLE_0,VIN2A_HSYNC0_INPUTENABLE_1" newline bitfld.long 0x160 17. "VIN2A_HSYNC0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_HSYNC0_PULLTYPESELECT_0,VIN2A_HSYNC0_PULLTYPESELECT_1" newline bitfld.long 0x160 16. "VIN2A_HSYNC0_PULLUDENABLE,- DISABLE" "VIN2A_HSYNC0_PULLUDENABLE_0,VIN2A_HSYNC0_PULLUDENABLE_1" newline bitfld.long 0x160 8. "VIN2A_HSYNC0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_HSYNC0_MODESELECT_0,VIN2A_HSYNC0_MODESELECT_1" newline bitfld.long 0x160 4.--7. "VIN2A_HSYNC0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x160 0.--3. "VIN2A_HSYNC0_MUXMODE,- PR1_EDIO_DATA_OUT3_13" "VIN2A_HSYNC0_MUXMODE_0,?,?,VIN2A_HSYNC0_MUXMODE_3,VIN2A_HSYNC0_MUXMODE_4,VIN2A_HSYNC0_MUXMODE_5,?,VIN2A_HSYNC0_MUXMODE_7,VIN2A_HSYNC0_MUXMODE_8,VIN2A_HSYNC0_MUXMODE_9,VIN2A_HSYNC0_MUXMODE_10,VIN2A_HSYNC0_MUXMODE_11,VIN2A_HSYNC0_MUXMODE_12,VIN2A_HSYNC0_MUXMODE_13,VIN2A_HSYNC0_MUXMODE_14,?" line.long 0x164 "CTRL_CORE_PAD_VIN2A_VSYNC0," rbitfld.long 0x164 25. "VIN2A_VSYNC0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_VSYNC0_WAKEUPEVENT_0,VIN2A_VSYNC0_WAKEUPEVENT_1" newline bitfld.long 0x164 24. "VIN2A_VSYNC0_WAKEUPENABLE,- DISABLE" "VIN2A_VSYNC0_WAKEUPENABLE_0,VIN2A_VSYNC0_WAKEUPENABLE_1" newline bitfld.long 0x164 19. "VIN2A_VSYNC0_SLEWCONTROL,- SLOW_SLEW" "VIN2A_VSYNC0_SLEWCONTROL_0,VIN2A_VSYNC0_SLEWCONTROL_1" newline bitfld.long 0x164 18. "VIN2A_VSYNC0_INPUTENABLE,- DISABLE" "VIN2A_VSYNC0_INPUTENABLE_0,VIN2A_VSYNC0_INPUTENABLE_1" newline bitfld.long 0x164 17. "VIN2A_VSYNC0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_VSYNC0_PULLTYPESELECT_0,VIN2A_VSYNC0_PULLTYPESELECT_1" newline bitfld.long 0x164 16. "VIN2A_VSYNC0_PULLUDENABLE,- DISABLE" "VIN2A_VSYNC0_PULLUDENABLE_0,VIN2A_VSYNC0_PULLUDENABLE_1" newline bitfld.long 0x164 8. "VIN2A_VSYNC0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_VSYNC0_MODESELECT_0,VIN2A_VSYNC0_MODESELECT_1" newline bitfld.long 0x164 4.--7. "VIN2A_VSYNC0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x164 0.--3. "VIN2A_VSYNC0_MUXMODE,- PR1_EDIO_DATA_OUT4_13" "VIN2A_VSYNC0_MUXMODE_0,?,?,VIN2A_VSYNC0_MUXMODE_3,VIN2A_VSYNC0_MUXMODE_4,VIN2A_VSYNC0_MUXMODE_5,?,VIN2A_VSYNC0_MUXMODE_7,VIN2A_VSYNC0_MUXMODE_8,VIN2A_VSYNC0_MUXMODE_9,VIN2A_VSYNC0_MUXMODE_10,VIN2A_VSYNC0_MUXMODE_11,VIN2A_VSYNC0_MUXMODE_12,VIN2A_VSYNC0_MUXMODE_13,VIN2A_VSYNC0_MUXMODE_14,?" line.long 0x168 "CTRL_CORE_PAD_VIN2A_D0," rbitfld.long 0x168 25. "VIN2A_D0_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D0_WAKEUPEVENT_0,VIN2A_D0_WAKEUPEVENT_1" newline bitfld.long 0x168 24. "VIN2A_D0_WAKEUPENABLE,- DISABLE" "VIN2A_D0_WAKEUPENABLE_0,VIN2A_D0_WAKEUPENABLE_1" newline bitfld.long 0x168 19. "VIN2A_D0_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D0_SLEWCONTROL_0,VIN2A_D0_SLEWCONTROL_1" newline bitfld.long 0x168 18. "VIN2A_D0_INPUTENABLE,- DISABLE" "VIN2A_D0_INPUTENABLE_0,VIN2A_D0_INPUTENABLE_1" newline bitfld.long 0x168 17. "VIN2A_D0_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D0_PULLTYPESELECT_0,VIN2A_D0_PULLTYPESELECT_1" newline bitfld.long 0x168 16. "VIN2A_D0_PULLUDENABLE,- DISABLE" "VIN2A_D0_PULLUDENABLE_0,VIN2A_D0_PULLUDENABLE_1" newline bitfld.long 0x168 8. "VIN2A_D0_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D0_MODESELECT_0,VIN2A_D0_MODESELECT_1" newline bitfld.long 0x168 4.--7. "VIN2A_D0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x168 0.--3. "VIN2A_D0_MUXMODE,- PR1_EDIO_DATA_OUT5_13" "VIN2A_D0_MUXMODE_0,?,?,?,VIN2A_D0_MUXMODE_4,VIN2A_D0_MUXMODE_5,?,VIN2A_D0_MUXMODE_7,VIN2A_D0_MUXMODE_8,VIN2A_D0_MUXMODE_9,VIN2A_D0_MUXMODE_10,VIN2A_D0_MUXMODE_11,VIN2A_D0_MUXMODE_12,VIN2A_D0_MUXMODE_13,VIN2A_D0_MUXMODE_14,?" line.long 0x16C "CTRL_CORE_PAD_VIN2A_D1," rbitfld.long 0x16C 25. "VIN2A_D1_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D1_WAKEUPEVENT_0,VIN2A_D1_WAKEUPEVENT_1" newline bitfld.long 0x16C 24. "VIN2A_D1_WAKEUPENABLE,- DISABLE" "VIN2A_D1_WAKEUPENABLE_0,VIN2A_D1_WAKEUPENABLE_1" newline bitfld.long 0x16C 19. "VIN2A_D1_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D1_SLEWCONTROL_0,VIN2A_D1_SLEWCONTROL_1" newline bitfld.long 0x16C 18. "VIN2A_D1_INPUTENABLE,- DISABLE" "VIN2A_D1_INPUTENABLE_0,VIN2A_D1_INPUTENABLE_1" newline bitfld.long 0x16C 17. "VIN2A_D1_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D1_PULLTYPESELECT_0,VIN2A_D1_PULLTYPESELECT_1" newline bitfld.long 0x16C 16. "VIN2A_D1_PULLUDENABLE,- DISABLE" "VIN2A_D1_PULLUDENABLE_0,VIN2A_D1_PULLUDENABLE_1" newline bitfld.long 0x16C 8. "VIN2A_D1_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D1_MODESELECT_0,VIN2A_D1_MODESELECT_1" newline bitfld.long 0x16C 4.--7. "VIN2A_D1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x16C 0.--3. "VIN2A_D1_MUXMODE,- PR1_EDIO_DATA_OUT6_13" "VIN2A_D1_MUXMODE_0,?,?,?,VIN2A_D1_MUXMODE_4,VIN2A_D1_MUXMODE_5,?,VIN2A_D1_MUXMODE_7,VIN2A_D1_MUXMODE_8,VIN2A_D1_MUXMODE_9,VIN2A_D1_MUXMODE_10,VIN2A_D1_MUXMODE_11,VIN2A_D1_MUXMODE_12,VIN2A_D1_MUXMODE_13,VIN2A_D1_MUXMODE_14,?" line.long 0x170 "CTRL_CORE_PAD_VIN2A_D2," rbitfld.long 0x170 25. "VIN2A_D2_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D2_WAKEUPEVENT_0,VIN2A_D2_WAKEUPEVENT_1" newline bitfld.long 0x170 24. "VIN2A_D2_WAKEUPENABLE,- DISABLE" "VIN2A_D2_WAKEUPENABLE_0,VIN2A_D2_WAKEUPENABLE_1" newline bitfld.long 0x170 19. "VIN2A_D2_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D2_SLEWCONTROL_0,VIN2A_D2_SLEWCONTROL_1" newline bitfld.long 0x170 18. "VIN2A_D2_INPUTENABLE,- DISABLE" "VIN2A_D2_INPUTENABLE_0,VIN2A_D2_INPUTENABLE_1" newline bitfld.long 0x170 17. "VIN2A_D2_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D2_PULLTYPESELECT_0,VIN2A_D2_PULLTYPESELECT_1" newline bitfld.long 0x170 16. "VIN2A_D2_PULLUDENABLE,- DISABLE" "VIN2A_D2_PULLUDENABLE_0,VIN2A_D2_PULLUDENABLE_1" newline bitfld.long 0x170 8. "VIN2A_D2_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D2_MODESELECT_0,VIN2A_D2_MODESELECT_1" newline bitfld.long 0x170 4.--7. "VIN2A_D2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x170 0.--3. "VIN2A_D2_MUXMODE,- PR1_EDIO_DATA_OUT7_13" "VIN2A_D2_MUXMODE_0,?,?,?,VIN2A_D2_MUXMODE_4,VIN2A_D2_MUXMODE_5,?,VIN2A_D2_MUXMODE_7,VIN2A_D2_MUXMODE_8,VIN2A_D2_MUXMODE_9,VIN2A_D2_MUXMODE_10,VIN2A_D2_MUXMODE_11,VIN2A_D2_MUXMODE_12,VIN2A_D2_MUXMODE_13,VIN2A_D2_MUXMODE_14,?" line.long 0x174 "CTRL_CORE_PAD_VIN2A_D3," rbitfld.long 0x174 25. "VIN2A_D3_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D3_WAKEUPEVENT_0,VIN2A_D3_WAKEUPEVENT_1" newline bitfld.long 0x174 24. "VIN2A_D3_WAKEUPENABLE,- DISABLE" "VIN2A_D3_WAKEUPENABLE_0,VIN2A_D3_WAKEUPENABLE_1" newline bitfld.long 0x174 19. "VIN2A_D3_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D3_SLEWCONTROL_0,VIN2A_D3_SLEWCONTROL_1" newline bitfld.long 0x174 18. "VIN2A_D3_INPUTENABLE,- DISABLE" "VIN2A_D3_INPUTENABLE_0,VIN2A_D3_INPUTENABLE_1" newline bitfld.long 0x174 17. "VIN2A_D3_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D3_PULLTYPESELECT_0,VIN2A_D3_PULLTYPESELECT_1" newline bitfld.long 0x174 16. "VIN2A_D3_PULLUDENABLE,- DISABLE" "VIN2A_D3_PULLUDENABLE_0,VIN2A_D3_PULLUDENABLE_1" newline bitfld.long 0x174 8. "VIN2A_D3_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D3_MODESELECT_0,VIN2A_D3_MODESELECT_1" newline bitfld.long 0x174 4.--7. "VIN2A_D3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x174 0.--3. "VIN2A_D3_MUXMODE,- PR1_PRU1_PRU_R300_13" "VIN2A_D3_MUXMODE_0,?,?,?,VIN2A_D3_MUXMODE_4,VIN2A_D3_MUXMODE_5,?,VIN2A_D3_MUXMODE_7,VIN2A_D3_MUXMODE_8,VIN2A_D3_MUXMODE_9,VIN2A_D3_MUXMODE_10,VIN2A_D3_MUXMODE_11,VIN2A_D3_MUXMODE_12,VIN2A_D3_MUXMODE_13,VIN2A_D3_MUXMODE_14,?" line.long 0x178 "CTRL_CORE_PAD_VIN2A_D4," rbitfld.long 0x178 25. "VIN2A_D4_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D4_WAKEUPEVENT_0,VIN2A_D4_WAKEUPEVENT_1" newline bitfld.long 0x178 24. "VIN2A_D4_WAKEUPENABLE,- DISABLE" "VIN2A_D4_WAKEUPENABLE_0,VIN2A_D4_WAKEUPENABLE_1" newline bitfld.long 0x178 19. "VIN2A_D4_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D4_SLEWCONTROL_0,VIN2A_D4_SLEWCONTROL_1" newline bitfld.long 0x178 18. "VIN2A_D4_INPUTENABLE,- DISABLE" "VIN2A_D4_INPUTENABLE_0,VIN2A_D4_INPUTENABLE_1" newline bitfld.long 0x178 17. "VIN2A_D4_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D4_PULLTYPESELECT_0,VIN2A_D4_PULLTYPESELECT_1" newline bitfld.long 0x178 16. "VIN2A_D4_PULLUDENABLE,- DISABLE" "VIN2A_D4_PULLUDENABLE_0,VIN2A_D4_PULLUDENABLE_1" newline bitfld.long 0x178 8. "VIN2A_D4_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D4_MODESELECT_0,VIN2A_D4_MODESELECT_1" newline bitfld.long 0x178 4.--7. "VIN2A_D4_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x178 0.--3. "VIN2A_D4_MUXMODE,- PR1_PRU1_PRU_R301_13" "VIN2A_D4_MUXMODE_0,?,?,?,VIN2A_D4_MUXMODE_4,VIN2A_D4_MUXMODE_5,?,VIN2A_D4_MUXMODE_7,VIN2A_D4_MUXMODE_8,VIN2A_D4_MUXMODE_9,VIN2A_D4_MUXMODE_10,VIN2A_D4_MUXMODE_11,VIN2A_D4_MUXMODE_12,VIN2A_D4_MUXMODE_13,VIN2A_D4_MUXMODE_14,?" line.long 0x17C "CTRL_CORE_PAD_VIN2A_D5," rbitfld.long 0x17C 25. "VIN2A_D5_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D5_WAKEUPEVENT_0,VIN2A_D5_WAKEUPEVENT_1" newline bitfld.long 0x17C 24. "VIN2A_D5_WAKEUPENABLE,- DISABLE" "VIN2A_D5_WAKEUPENABLE_0,VIN2A_D5_WAKEUPENABLE_1" newline bitfld.long 0x17C 19. "VIN2A_D5_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D5_SLEWCONTROL_0,VIN2A_D5_SLEWCONTROL_1" newline bitfld.long 0x17C 18. "VIN2A_D5_INPUTENABLE,- DISABLE" "VIN2A_D5_INPUTENABLE_0,VIN2A_D5_INPUTENABLE_1" newline bitfld.long 0x17C 17. "VIN2A_D5_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D5_PULLTYPESELECT_0,VIN2A_D5_PULLTYPESELECT_1" newline bitfld.long 0x17C 16. "VIN2A_D5_PULLUDENABLE,- DISABLE" "VIN2A_D5_PULLUDENABLE_0,VIN2A_D5_PULLUDENABLE_1" newline bitfld.long 0x17C 8. "VIN2A_D5_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D5_MODESELECT_0,VIN2A_D5_MODESELECT_1" newline bitfld.long 0x17C 4.--7. "VIN2A_D5_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x17C 0.--3. "VIN2A_D5_MUXMODE,- PR1_PRU1_PRU_R302_13" "VIN2A_D5_MUXMODE_0,?,?,?,VIN2A_D5_MUXMODE_4,VIN2A_D5_MUXMODE_5,?,VIN2A_D5_MUXMODE_7,VIN2A_D5_MUXMODE_8,VIN2A_D5_MUXMODE_9,VIN2A_D5_MUXMODE_10,VIN2A_D5_MUXMODE_11,VIN2A_D5_MUXMODE_12,VIN2A_D5_MUXMODE_13,VIN2A_D5_MUXMODE_14,?" line.long 0x180 "CTRL_CORE_PAD_VIN2A_D6," rbitfld.long 0x180 25. "VIN2A_D6_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D6_WAKEUPEVENT_0,VIN2A_D6_WAKEUPEVENT_1" newline bitfld.long 0x180 24. "VIN2A_D6_WAKEUPENABLE,- DISABLE" "VIN2A_D6_WAKEUPENABLE_0,VIN2A_D6_WAKEUPENABLE_1" newline bitfld.long 0x180 19. "VIN2A_D6_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D6_SLEWCONTROL_0,VIN2A_D6_SLEWCONTROL_1" newline bitfld.long 0x180 18. "VIN2A_D6_INPUTENABLE,- DISABLE" "VIN2A_D6_INPUTENABLE_0,VIN2A_D6_INPUTENABLE_1" newline bitfld.long 0x180 17. "VIN2A_D6_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D6_PULLTYPESELECT_0,VIN2A_D6_PULLTYPESELECT_1" newline bitfld.long 0x180 16. "VIN2A_D6_PULLUDENABLE,- DISABLE" "VIN2A_D6_PULLUDENABLE_0,VIN2A_D6_PULLUDENABLE_1" newline bitfld.long 0x180 8. "VIN2A_D6_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D6_MODESELECT_0,VIN2A_D6_MODESELECT_1" newline bitfld.long 0x180 4.--7. "VIN2A_D6_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x180 0.--3. "VIN2A_D6_MUXMODE,- PR1_PRU1_PRU_R303_13" "VIN2A_D6_MUXMODE_0,?,?,?,VIN2A_D6_MUXMODE_4,VIN2A_D6_MUXMODE_5,?,VIN2A_D6_MUXMODE_7,VIN2A_D6_MUXMODE_8,VIN2A_D6_MUXMODE_9,VIN2A_D6_MUXMODE_10,VIN2A_D6_MUXMODE_11,VIN2A_D6_MUXMODE_12,VIN2A_D6_MUXMODE_13,VIN2A_D6_MUXMODE_14,?" line.long 0x184 "CTRL_CORE_PAD_VIN2A_D7," rbitfld.long 0x184 25. "VIN2A_D7_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D7_WAKEUPEVENT_0,VIN2A_D7_WAKEUPEVENT_1" newline bitfld.long 0x184 24. "VIN2A_D7_WAKEUPENABLE,- DISABLE" "VIN2A_D7_WAKEUPENABLE_0,VIN2A_D7_WAKEUPENABLE_1" newline bitfld.long 0x184 19. "VIN2A_D7_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D7_SLEWCONTROL_0,VIN2A_D7_SLEWCONTROL_1" newline bitfld.long 0x184 18. "VIN2A_D7_INPUTENABLE,- DISABLE" "VIN2A_D7_INPUTENABLE_0,VIN2A_D7_INPUTENABLE_1" newline bitfld.long 0x184 17. "VIN2A_D7_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D7_PULLTYPESELECT_0,VIN2A_D7_PULLTYPESELECT_1" newline bitfld.long 0x184 16. "VIN2A_D7_PULLUDENABLE,- DISABLE" "VIN2A_D7_PULLUDENABLE_0,VIN2A_D7_PULLUDENABLE_1" newline bitfld.long 0x184 8. "VIN2A_D7_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D7_MODESELECT_0,VIN2A_D7_MODESELECT_1" newline bitfld.long 0x184 4.--7. "VIN2A_D7_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x184 0.--3. "VIN2A_D7_MUXMODE,- PR1_PRU1_PRU_R304_13" "VIN2A_D7_MUXMODE_0,?,?,?,VIN2A_D7_MUXMODE_4,VIN2A_D7_MUXMODE_5,?,VIN2A_D7_MUXMODE_7,VIN2A_D7_MUXMODE_8,VIN2A_D7_MUXMODE_9,VIN2A_D7_MUXMODE_10,VIN2A_D7_MUXMODE_11,VIN2A_D7_MUXMODE_12,VIN2A_D7_MUXMODE_13,VIN2A_D7_MUXMODE_14,?" line.long 0x188 "CTRL_CORE_PAD_VIN2A_D8," rbitfld.long 0x188 25. "VIN2A_D8_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D8_WAKEUPEVENT_0,VIN2A_D8_WAKEUPEVENT_1" newline bitfld.long 0x188 24. "VIN2A_D8_WAKEUPENABLE,- DISABLE" "VIN2A_D8_WAKEUPENABLE_0,VIN2A_D8_WAKEUPENABLE_1" newline bitfld.long 0x188 19. "VIN2A_D8_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D8_SLEWCONTROL_0,VIN2A_D8_SLEWCONTROL_1" newline bitfld.long 0x188 18. "VIN2A_D8_INPUTENABLE,- DISABLE" "VIN2A_D8_INPUTENABLE_0,VIN2A_D8_INPUTENABLE_1" newline bitfld.long 0x188 17. "VIN2A_D8_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D8_PULLTYPESELECT_0,VIN2A_D8_PULLTYPESELECT_1" newline bitfld.long 0x188 16. "VIN2A_D8_PULLUDENABLE,- DISABLE" "VIN2A_D8_PULLUDENABLE_0,VIN2A_D8_PULLUDENABLE_1" newline bitfld.long 0x188 8. "VIN2A_D8_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D8_MODESELECT_0,VIN2A_D8_MODESELECT_1" newline bitfld.long 0x188 4.--7. "VIN2A_D8_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x188 0.--3. "VIN2A_D8_MUXMODE,- PR1_PRU1_PRU_R305_13" "VIN2A_D8_MUXMODE_0,?,?,?,VIN2A_D8_MUXMODE_4,VIN2A_D8_MUXMODE_5,?,VIN2A_D8_MUXMODE_7,VIN2A_D8_MUXMODE_8,VIN2A_D8_MUXMODE_9,VIN2A_D8_MUXMODE_10,VIN2A_D8_MUXMODE_11,VIN2A_D8_MUXMODE_12,VIN2A_D8_MUXMODE_13,VIN2A_D8_MUXMODE_14,?" line.long 0x18C "CTRL_CORE_PAD_VIN2A_D9," rbitfld.long 0x18C 25. "VIN2A_D9_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D9_WAKEUPEVENT_0,VIN2A_D9_WAKEUPEVENT_1" newline bitfld.long 0x18C 24. "VIN2A_D9_WAKEUPENABLE,- DISABLE" "VIN2A_D9_WAKEUPENABLE_0,VIN2A_D9_WAKEUPENABLE_1" newline bitfld.long 0x18C 19. "VIN2A_D9_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D9_SLEWCONTROL_0,VIN2A_D9_SLEWCONTROL_1" newline bitfld.long 0x18C 18. "VIN2A_D9_INPUTENABLE,- DISABLE" "VIN2A_D9_INPUTENABLE_0,VIN2A_D9_INPUTENABLE_1" newline bitfld.long 0x18C 17. "VIN2A_D9_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D9_PULLTYPESELECT_0,VIN2A_D9_PULLTYPESELECT_1" newline bitfld.long 0x18C 16. "VIN2A_D9_PULLUDENABLE,- DISABLE" "VIN2A_D9_PULLUDENABLE_0,VIN2A_D9_PULLUDENABLE_1" newline bitfld.long 0x18C 8. "VIN2A_D9_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D9_MODESELECT_0,VIN2A_D9_MODESELECT_1" newline bitfld.long 0x18C 4.--7. "VIN2A_D9_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18C 0.--3. "VIN2A_D9_MUXMODE,- PR1_PRU1_PRU_R306_13" "VIN2A_D9_MUXMODE_0,?,?,?,VIN2A_D9_MUXMODE_4,VIN2A_D9_MUXMODE_5,?,VIN2A_D9_MUXMODE_7,VIN2A_D9_MUXMODE_8,VIN2A_D9_MUXMODE_9,VIN2A_D9_MUXMODE_10,VIN2A_D9_MUXMODE_11,VIN2A_D9_MUXMODE_12,VIN2A_D9_MUXMODE_13,VIN2A_D9_MUXMODE_14,?" line.long 0x190 "CTRL_CORE_PAD_VIN2A_D10," rbitfld.long 0x190 25. "VIN2A_D10_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D10_WAKEUPEVENT_0,VIN2A_D10_WAKEUPEVENT_1" newline bitfld.long 0x190 24. "VIN2A_D10_WAKEUPENABLE,- DISABLE" "VIN2A_D10_WAKEUPENABLE_0,VIN2A_D10_WAKEUPENABLE_1" newline bitfld.long 0x190 19. "VIN2A_D10_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D10_SLEWCONTROL_0,VIN2A_D10_SLEWCONTROL_1" newline bitfld.long 0x190 18. "VIN2A_D10_INPUTENABLE,- DISABLE" "VIN2A_D10_INPUTENABLE_0,VIN2A_D10_INPUTENABLE_1" newline bitfld.long 0x190 17. "VIN2A_D10_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D10_PULLTYPESELECT_0,VIN2A_D10_PULLTYPESELECT_1" newline bitfld.long 0x190 16. "VIN2A_D10_PULLUDENABLE,- DISABLE" "VIN2A_D10_PULLUDENABLE_0,VIN2A_D10_PULLUDENABLE_1" newline bitfld.long 0x190 8. "VIN2A_D10_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D10_MODESELECT_0,VIN2A_D10_MODESELECT_1" newline bitfld.long 0x190 4.--7. "VIN2A_D10_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x190 0.--3. "VIN2A_D10_MUXMODE,- PR1_PRU1_PRU_R307_13" "VIN2A_D10_MUXMODE_0,?,?,VIN2A_D10_MUXMODE_3,VIN2A_D10_MUXMODE_4,?,?,VIN2A_D10_MUXMODE_7,?,VIN2A_D10_MUXMODE_9,VIN2A_D10_MUXMODE_10,VIN2A_D10_MUXMODE_11,VIN2A_D10_MUXMODE_12,VIN2A_D10_MUXMODE_13,VIN2A_D10_MUXMODE_14,?" line.long 0x194 "CTRL_CORE_PAD_VIN2A_D11," rbitfld.long 0x194 25. "VIN2A_D11_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D11_WAKEUPEVENT_0,VIN2A_D11_WAKEUPEVENT_1" newline bitfld.long 0x194 24. "VIN2A_D11_WAKEUPENABLE,- DISABLE" "VIN2A_D11_WAKEUPENABLE_0,VIN2A_D11_WAKEUPENABLE_1" newline bitfld.long 0x194 19. "VIN2A_D11_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D11_SLEWCONTROL_0,VIN2A_D11_SLEWCONTROL_1" newline bitfld.long 0x194 18. "VIN2A_D11_INPUTENABLE,- DISABLE" "VIN2A_D11_INPUTENABLE_0,VIN2A_D11_INPUTENABLE_1" newline bitfld.long 0x194 17. "VIN2A_D11_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D11_PULLTYPESELECT_0,VIN2A_D11_PULLTYPESELECT_1" newline bitfld.long 0x194 16. "VIN2A_D11_PULLUDENABLE,- DISABLE" "VIN2A_D11_PULLUDENABLE_0,VIN2A_D11_PULLUDENABLE_1" newline bitfld.long 0x194 8. "VIN2A_D11_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D11_MODESELECT_0,VIN2A_D11_MODESELECT_1" newline bitfld.long 0x194 4.--7. "VIN2A_D11_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x194 0.--3. "VIN2A_D11_MUXMODE,- PR1_PRU1_PRU_R308_13" "VIN2A_D11_MUXMODE_0,?,?,VIN2A_D11_MUXMODE_3,VIN2A_D11_MUXMODE_4,?,?,VIN2A_D11_MUXMODE_7,?,VIN2A_D11_MUXMODE_9,VIN2A_D11_MUXMODE_10,VIN2A_D11_MUXMODE_11,VIN2A_D11_MUXMODE_12,VIN2A_D11_MUXMODE_13,VIN2A_D11_MUXMODE_14,?" line.long 0x198 "CTRL_CORE_PAD_VIN2A_D12," rbitfld.long 0x198 25. "VIN2A_D12_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D12_WAKEUPEVENT_0,VIN2A_D12_WAKEUPEVENT_1" newline bitfld.long 0x198 24. "VIN2A_D12_WAKEUPENABLE,- DISABLE" "VIN2A_D12_WAKEUPENABLE_0,VIN2A_D12_WAKEUPENABLE_1" newline bitfld.long 0x198 19. "VIN2A_D12_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D12_SLEWCONTROL_0,VIN2A_D12_SLEWCONTROL_1" newline bitfld.long 0x198 18. "VIN2A_D12_INPUTENABLE,- DISABLE" "VIN2A_D12_INPUTENABLE_0,VIN2A_D12_INPUTENABLE_1" newline bitfld.long 0x198 17. "VIN2A_D12_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D12_PULLTYPESELECT_0,VIN2A_D12_PULLTYPESELECT_1" newline bitfld.long 0x198 16. "VIN2A_D12_PULLUDENABLE,- DISABLE" "VIN2A_D12_PULLUDENABLE_0,VIN2A_D12_PULLUDENABLE_1" newline bitfld.long 0x198 8. "VIN2A_D12_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D12_MODESELECT_0,VIN2A_D12_MODESELECT_1" newline bitfld.long 0x198 4.--7. "VIN2A_D12_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x198 0.--3. "VIN2A_D12_MUXMODE,- PR1_PRU1_PRU_R309_13" "VIN2A_D12_MUXMODE_0,?,?,VIN2A_D12_MUXMODE_3,VIN2A_D12_MUXMODE_4,?,?,VIN2A_D12_MUXMODE_7,VIN2A_D12_MUXMODE_8,VIN2A_D12_MUXMODE_9,VIN2A_D12_MUXMODE_10,VIN2A_D12_MUXMODE_11,VIN2A_D12_MUXMODE_12,VIN2A_D12_MUXMODE_13,VIN2A_D12_MUXMODE_14,?" line.long 0x19C "CTRL_CORE_PAD_VIN2A_D13," rbitfld.long 0x19C 25. "VIN2A_D13_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D13_WAKEUPEVENT_0,VIN2A_D13_WAKEUPEVENT_1" newline bitfld.long 0x19C 24. "VIN2A_D13_WAKEUPENABLE,- DISABLE" "VIN2A_D13_WAKEUPENABLE_0,VIN2A_D13_WAKEUPENABLE_1" newline bitfld.long 0x19C 19. "VIN2A_D13_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D13_SLEWCONTROL_0,VIN2A_D13_SLEWCONTROL_1" newline bitfld.long 0x19C 18. "VIN2A_D13_INPUTENABLE,- DISABLE" "VIN2A_D13_INPUTENABLE_0,VIN2A_D13_INPUTENABLE_1" newline bitfld.long 0x19C 17. "VIN2A_D13_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D13_PULLTYPESELECT_0,VIN2A_D13_PULLTYPESELECT_1" newline bitfld.long 0x19C 16. "VIN2A_D13_PULLUDENABLE,- DISABLE" "VIN2A_D13_PULLUDENABLE_0,VIN2A_D13_PULLUDENABLE_1" newline bitfld.long 0x19C 8. "VIN2A_D13_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D13_MODESELECT_0,VIN2A_D13_MODESELECT_1" newline bitfld.long 0x19C 4.--7. "VIN2A_D13_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x19C 0.--3. "VIN2A_D13_MUXMODE,- PR1_PRU1_PRU_R3010_13" "VIN2A_D13_MUXMODE_0,?,?,VIN2A_D13_MUXMODE_3,VIN2A_D13_MUXMODE_4,?,?,VIN2A_D13_MUXMODE_7,VIN2A_D13_MUXMODE_8,VIN2A_D13_MUXMODE_9,VIN2A_D13_MUXMODE_10,VIN2A_D13_MUXMODE_11,VIN2A_D13_MUXMODE_12,VIN2A_D13_MUXMODE_13,VIN2A_D13_MUXMODE_14,?" line.long 0x1A0 "CTRL_CORE_PAD_VIN2A_D14," rbitfld.long 0x1A0 25. "VIN2A_D14_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D14_WAKEUPEVENT_0,VIN2A_D14_WAKEUPEVENT_1" newline bitfld.long 0x1A0 24. "VIN2A_D14_WAKEUPENABLE,- DISABLE" "VIN2A_D14_WAKEUPENABLE_0,VIN2A_D14_WAKEUPENABLE_1" newline bitfld.long 0x1A0 19. "VIN2A_D14_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D14_SLEWCONTROL_0,VIN2A_D14_SLEWCONTROL_1" newline bitfld.long 0x1A0 18. "VIN2A_D14_INPUTENABLE,- DISABLE" "VIN2A_D14_INPUTENABLE_0,VIN2A_D14_INPUTENABLE_1" newline bitfld.long 0x1A0 17. "VIN2A_D14_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D14_PULLTYPESELECT_0,VIN2A_D14_PULLTYPESELECT_1" newline bitfld.long 0x1A0 16. "VIN2A_D14_PULLUDENABLE,- DISABLE" "VIN2A_D14_PULLUDENABLE_0,VIN2A_D14_PULLUDENABLE_1" newline bitfld.long 0x1A0 8. "VIN2A_D14_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D14_MODESELECT_0,VIN2A_D14_MODESELECT_1" newline bitfld.long 0x1A0 4.--7. "VIN2A_D14_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1A0 0.--3. "VIN2A_D14_MUXMODE,- PR1_PRU1_PRU_R3011_13" "VIN2A_D14_MUXMODE_0,?,?,VIN2A_D14_MUXMODE_3,VIN2A_D14_MUXMODE_4,?,?,VIN2A_D14_MUXMODE_7,VIN2A_D14_MUXMODE_8,?,VIN2A_D14_MUXMODE_10,VIN2A_D14_MUXMODE_11,VIN2A_D14_MUXMODE_12,VIN2A_D14_MUXMODE_13,VIN2A_D14_MUXMODE_14,?" line.long 0x1A4 "CTRL_CORE_PAD_VIN2A_D15," rbitfld.long 0x1A4 25. "VIN2A_D15_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D15_WAKEUPEVENT_0,VIN2A_D15_WAKEUPEVENT_1" newline bitfld.long 0x1A4 24. "VIN2A_D15_WAKEUPENABLE,- DISABLE" "VIN2A_D15_WAKEUPENABLE_0,VIN2A_D15_WAKEUPENABLE_1" newline bitfld.long 0x1A4 19. "VIN2A_D15_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D15_SLEWCONTROL_0,VIN2A_D15_SLEWCONTROL_1" newline bitfld.long 0x1A4 18. "VIN2A_D15_INPUTENABLE,- DISABLE" "VIN2A_D15_INPUTENABLE_0,VIN2A_D15_INPUTENABLE_1" newline bitfld.long 0x1A4 17. "VIN2A_D15_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D15_PULLTYPESELECT_0,VIN2A_D15_PULLTYPESELECT_1" newline bitfld.long 0x1A4 16. "VIN2A_D15_PULLUDENABLE,- DISABLE" "VIN2A_D15_PULLUDENABLE_0,VIN2A_D15_PULLUDENABLE_1" newline bitfld.long 0x1A4 8. "VIN2A_D15_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D15_MODESELECT_0,VIN2A_D15_MODESELECT_1" newline bitfld.long 0x1A4 4.--7. "VIN2A_D15_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1A4 0.--3. "VIN2A_D15_MUXMODE,- PR1_PRU1_PRU_R3012_13" "VIN2A_D15_MUXMODE_0,?,?,VIN2A_D15_MUXMODE_3,VIN2A_D15_MUXMODE_4,?,?,VIN2A_D15_MUXMODE_7,VIN2A_D15_MUXMODE_8,?,VIN2A_D15_MUXMODE_10,VIN2A_D15_MUXMODE_11,VIN2A_D15_MUXMODE_12,VIN2A_D15_MUXMODE_13,VIN2A_D15_MUXMODE_14,?" line.long 0x1A8 "CTRL_CORE_PAD_VIN2A_D16," rbitfld.long 0x1A8 25. "VIN2A_D16_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D16_WAKEUPEVENT_0,VIN2A_D16_WAKEUPEVENT_1" newline bitfld.long 0x1A8 24. "VIN2A_D16_WAKEUPENABLE,- DISABLE" "VIN2A_D16_WAKEUPENABLE_0,VIN2A_D16_WAKEUPENABLE_1" newline bitfld.long 0x1A8 19. "VIN2A_D16_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D16_SLEWCONTROL_0,VIN2A_D16_SLEWCONTROL_1" newline bitfld.long 0x1A8 18. "VIN2A_D16_INPUTENABLE,- DISABLE" "VIN2A_D16_INPUTENABLE_0,VIN2A_D16_INPUTENABLE_1" newline bitfld.long 0x1A8 17. "VIN2A_D16_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D16_PULLTYPESELECT_0,VIN2A_D16_PULLTYPESELECT_1" newline bitfld.long 0x1A8 16. "VIN2A_D16_PULLUDENABLE,- DISABLE" "VIN2A_D16_PULLUDENABLE_0,VIN2A_D16_PULLUDENABLE_1" newline bitfld.long 0x1A8 8. "VIN2A_D16_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D16_MODESELECT_0,VIN2A_D16_MODESELECT_1" newline bitfld.long 0x1A8 4.--7. "VIN2A_D16_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1A8 0.--3. "VIN2A_D16_MUXMODE,- PR1_PRU1_PRU_R3013_13" "VIN2A_D16_MUXMODE_0,?,VIN2A_D16_MUXMODE_2,VIN2A_D16_MUXMODE_3,VIN2A_D16_MUXMODE_4,?,VIN2A_D16_MUXMODE_6,VIN2A_D16_MUXMODE_7,VIN2A_D16_MUXMODE_8,?,VIN2A_D16_MUXMODE_10,VIN2A_D16_MUXMODE_11,VIN2A_D16_MUXMODE_12,VIN2A_D16_MUXMODE_13,VIN2A_D16_MUXMODE_14,?" line.long 0x1AC "CTRL_CORE_PAD_VIN2A_D17," rbitfld.long 0x1AC 25. "VIN2A_D17_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D17_WAKEUPEVENT_0,VIN2A_D17_WAKEUPEVENT_1" newline bitfld.long 0x1AC 24. "VIN2A_D17_WAKEUPENABLE,- DISABLE" "VIN2A_D17_WAKEUPENABLE_0,VIN2A_D17_WAKEUPENABLE_1" newline bitfld.long 0x1AC 19. "VIN2A_D17_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D17_SLEWCONTROL_0,VIN2A_D17_SLEWCONTROL_1" newline bitfld.long 0x1AC 18. "VIN2A_D17_INPUTENABLE,- DISABLE" "VIN2A_D17_INPUTENABLE_0,VIN2A_D17_INPUTENABLE_1" newline bitfld.long 0x1AC 17. "VIN2A_D17_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D17_PULLTYPESELECT_0,VIN2A_D17_PULLTYPESELECT_1" newline bitfld.long 0x1AC 16. "VIN2A_D17_PULLUDENABLE,- DISABLE" "VIN2A_D17_PULLUDENABLE_0,VIN2A_D17_PULLUDENABLE_1" newline bitfld.long 0x1AC 8. "VIN2A_D17_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D17_MODESELECT_0,VIN2A_D17_MODESELECT_1" newline bitfld.long 0x1AC 4.--7. "VIN2A_D17_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1AC 0.--3. "VIN2A_D17_MUXMODE,- PR1_PRU1_PRU_R3014_13" "VIN2A_D17_MUXMODE_0,?,VIN2A_D17_MUXMODE_2,VIN2A_D17_MUXMODE_3,VIN2A_D17_MUXMODE_4,?,VIN2A_D17_MUXMODE_6,VIN2A_D17_MUXMODE_7,VIN2A_D17_MUXMODE_8,?,VIN2A_D17_MUXMODE_10,VIN2A_D17_MUXMODE_11,VIN2A_D17_MUXMODE_12,VIN2A_D17_MUXMODE_13,VIN2A_D17_MUXMODE_14,?" line.long 0x1B0 "CTRL_CORE_PAD_VIN2A_D18," rbitfld.long 0x1B0 25. "VIN2A_D18_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D18_WAKEUPEVENT_0,VIN2A_D18_WAKEUPEVENT_1" newline bitfld.long 0x1B0 24. "VIN2A_D18_WAKEUPENABLE,- DISABLE" "VIN2A_D18_WAKEUPENABLE_0,VIN2A_D18_WAKEUPENABLE_1" newline bitfld.long 0x1B0 19. "VIN2A_D18_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D18_SLEWCONTROL_0,VIN2A_D18_SLEWCONTROL_1" newline bitfld.long 0x1B0 18. "VIN2A_D18_INPUTENABLE,- DISABLE" "VIN2A_D18_INPUTENABLE_0,VIN2A_D18_INPUTENABLE_1" newline bitfld.long 0x1B0 17. "VIN2A_D18_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D18_PULLTYPESELECT_0,VIN2A_D18_PULLTYPESELECT_1" newline bitfld.long 0x1B0 16. "VIN2A_D18_PULLUDENABLE,- DISABLE" "VIN2A_D18_PULLUDENABLE_0,VIN2A_D18_PULLUDENABLE_1" newline bitfld.long 0x1B0 8. "VIN2A_D18_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D18_MODESELECT_0,VIN2A_D18_MODESELECT_1" newline bitfld.long 0x1B0 4.--7. "VIN2A_D18_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1B0 0.--3. "VIN2A_D18_MUXMODE,- PR1_PRU1_PRU_R3015_13" "VIN2A_D18_MUXMODE_0,?,VIN2A_D18_MUXMODE_2,VIN2A_D18_MUXMODE_3,VIN2A_D18_MUXMODE_4,?,VIN2A_D18_MUXMODE_6,VIN2A_D18_MUXMODE_7,VIN2A_D18_MUXMODE_8,?,VIN2A_D18_MUXMODE_10,VIN2A_D18_MUXMODE_11,VIN2A_D18_MUXMODE_12,VIN2A_D18_MUXMODE_13,VIN2A_D18_MUXMODE_14,?" line.long 0x1B4 "CTRL_CORE_PAD_VIN2A_D19," rbitfld.long 0x1B4 25. "VIN2A_D19_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D19_WAKEUPEVENT_0,VIN2A_D19_WAKEUPEVENT_1" newline bitfld.long 0x1B4 24. "VIN2A_D19_WAKEUPENABLE,- DISABLE" "VIN2A_D19_WAKEUPENABLE_0,VIN2A_D19_WAKEUPENABLE_1" newline bitfld.long 0x1B4 19. "VIN2A_D19_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D19_SLEWCONTROL_0,VIN2A_D19_SLEWCONTROL_1" newline bitfld.long 0x1B4 18. "VIN2A_D19_INPUTENABLE,- DISABLE" "VIN2A_D19_INPUTENABLE_0,VIN2A_D19_INPUTENABLE_1" newline bitfld.long 0x1B4 17. "VIN2A_D19_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D19_PULLTYPESELECT_0,VIN2A_D19_PULLTYPESELECT_1" newline bitfld.long 0x1B4 16. "VIN2A_D19_PULLUDENABLE,- DISABLE" "VIN2A_D19_PULLUDENABLE_0,VIN2A_D19_PULLUDENABLE_1" newline bitfld.long 0x1B4 8. "VIN2A_D19_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D19_MODESELECT_0,VIN2A_D19_MODESELECT_1" newline bitfld.long 0x1B4 4.--7. "VIN2A_D19_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1B4 0.--3. "VIN2A_D19_MUXMODE,- PR1_PRU1_PRU_R3016_13" "VIN2A_D19_MUXMODE_0,?,VIN2A_D19_MUXMODE_2,VIN2A_D19_MUXMODE_3,VIN2A_D19_MUXMODE_4,?,VIN2A_D19_MUXMODE_6,VIN2A_D19_MUXMODE_7,VIN2A_D19_MUXMODE_8,?,VIN2A_D19_MUXMODE_10,VIN2A_D19_MUXMODE_11,VIN2A_D19_MUXMODE_12,VIN2A_D19_MUXMODE_13,VIN2A_D19_MUXMODE_14,?" line.long 0x1B8 "CTRL_CORE_PAD_VIN2A_D20," rbitfld.long 0x1B8 25. "VIN2A_D20_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D20_WAKEUPEVENT_0,VIN2A_D20_WAKEUPEVENT_1" newline bitfld.long 0x1B8 24. "VIN2A_D20_WAKEUPENABLE,- DISABLE" "VIN2A_D20_WAKEUPENABLE_0,VIN2A_D20_WAKEUPENABLE_1" newline bitfld.long 0x1B8 19. "VIN2A_D20_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D20_SLEWCONTROL_0,VIN2A_D20_SLEWCONTROL_1" newline bitfld.long 0x1B8 18. "VIN2A_D20_INPUTENABLE,- DISABLE" "VIN2A_D20_INPUTENABLE_0,VIN2A_D20_INPUTENABLE_1" newline bitfld.long 0x1B8 17. "VIN2A_D20_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D20_PULLTYPESELECT_0,VIN2A_D20_PULLTYPESELECT_1" newline bitfld.long 0x1B8 16. "VIN2A_D20_PULLUDENABLE,- DISABLE" "VIN2A_D20_PULLUDENABLE_0,VIN2A_D20_PULLUDENABLE_1" newline bitfld.long 0x1B8 8. "VIN2A_D20_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D20_MODESELECT_0,VIN2A_D20_MODESELECT_1" newline bitfld.long 0x1B8 4.--7. "VIN2A_D20_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1B8 0.--3. "VIN2A_D20_MUXMODE,- PR1_PRU1_PRU_R3017_13" "VIN2A_D20_MUXMODE_0,?,VIN2A_D20_MUXMODE_2,VIN2A_D20_MUXMODE_3,VIN2A_D20_MUXMODE_4,VIN2A_D20_MUXMODE_5,VIN2A_D20_MUXMODE_6,VIN2A_D20_MUXMODE_7,VIN2A_D20_MUXMODE_8,?,VIN2A_D20_MUXMODE_10,VIN2A_D20_MUXMODE_11,VIN2A_D20_MUXMODE_12,VIN2A_D20_MUXMODE_13,VIN2A_D20_MUXMODE_14,?" line.long 0x1BC "CTRL_CORE_PAD_VIN2A_D21," rbitfld.long 0x1BC 25. "VIN2A_D21_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D21_WAKEUPEVENT_0,VIN2A_D21_WAKEUPEVENT_1" newline bitfld.long 0x1BC 24. "VIN2A_D21_WAKEUPENABLE,- DISABLE" "VIN2A_D21_WAKEUPENABLE_0,VIN2A_D21_WAKEUPENABLE_1" newline bitfld.long 0x1BC 19. "VIN2A_D21_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D21_SLEWCONTROL_0,VIN2A_D21_SLEWCONTROL_1" newline bitfld.long 0x1BC 18. "VIN2A_D21_INPUTENABLE,- DISABLE" "VIN2A_D21_INPUTENABLE_0,VIN2A_D21_INPUTENABLE_1" newline bitfld.long 0x1BC 17. "VIN2A_D21_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D21_PULLTYPESELECT_0,VIN2A_D21_PULLTYPESELECT_1" newline bitfld.long 0x1BC 16. "VIN2A_D21_PULLUDENABLE,- DISABLE" "VIN2A_D21_PULLUDENABLE_0,VIN2A_D21_PULLUDENABLE_1" newline bitfld.long 0x1BC 8. "VIN2A_D21_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D21_MODESELECT_0,VIN2A_D21_MODESELECT_1" newline bitfld.long 0x1BC 4.--7. "VIN2A_D21_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1BC 0.--3. "VIN2A_D21_MUXMODE,- PR1_PRU1_PRU_R3018_13" "VIN2A_D21_MUXMODE_0,?,VIN2A_D21_MUXMODE_2,VIN2A_D21_MUXMODE_3,VIN2A_D21_MUXMODE_4,VIN2A_D21_MUXMODE_5,VIN2A_D21_MUXMODE_6,VIN2A_D21_MUXMODE_7,VIN2A_D21_MUXMODE_8,?,?,VIN2A_D21_MUXMODE_11,VIN2A_D21_MUXMODE_12,VIN2A_D21_MUXMODE_13,VIN2A_D21_MUXMODE_14,?" line.long 0x1C0 "CTRL_CORE_PAD_VIN2A_D22," rbitfld.long 0x1C0 25. "VIN2A_D22_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D22_WAKEUPEVENT_0,VIN2A_D22_WAKEUPEVENT_1" newline bitfld.long 0x1C0 24. "VIN2A_D22_WAKEUPENABLE,- DISABLE" "VIN2A_D22_WAKEUPENABLE_0,VIN2A_D22_WAKEUPENABLE_1" newline bitfld.long 0x1C0 19. "VIN2A_D22_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D22_SLEWCONTROL_0,VIN2A_D22_SLEWCONTROL_1" newline bitfld.long 0x1C0 18. "VIN2A_D22_INPUTENABLE,- DISABLE" "VIN2A_D22_INPUTENABLE_0,VIN2A_D22_INPUTENABLE_1" newline bitfld.long 0x1C0 17. "VIN2A_D22_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D22_PULLTYPESELECT_0,VIN2A_D22_PULLTYPESELECT_1" newline bitfld.long 0x1C0 16. "VIN2A_D22_PULLUDENABLE,- DISABLE" "VIN2A_D22_PULLUDENABLE_0,VIN2A_D22_PULLUDENABLE_1" newline bitfld.long 0x1C0 8. "VIN2A_D22_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D22_MODESELECT_0,VIN2A_D22_MODESELECT_1" newline bitfld.long 0x1C0 4.--7. "VIN2A_D22_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C0 0.--3. "VIN2A_D22_MUXMODE,- PR1_PRU1_PRU_R3019_13" "VIN2A_D22_MUXMODE_0,?,VIN2A_D22_MUXMODE_2,VIN2A_D22_MUXMODE_3,VIN2A_D22_MUXMODE_4,VIN2A_D22_MUXMODE_5,VIN2A_D22_MUXMODE_6,VIN2A_D22_MUXMODE_7,VIN2A_D22_MUXMODE_8,?,?,VIN2A_D22_MUXMODE_11,VIN2A_D22_MUXMODE_12,VIN2A_D22_MUXMODE_13,VIN2A_D22_MUXMODE_14,?" line.long 0x1C4 "CTRL_CORE_PAD_VIN2A_D23," rbitfld.long 0x1C4 25. "VIN2A_D23_WAKEUPEVENT,- NOWAKEUP" "VIN2A_D23_WAKEUPEVENT_0,VIN2A_D23_WAKEUPEVENT_1" newline bitfld.long 0x1C4 24. "VIN2A_D23_WAKEUPENABLE,- DISABLE" "VIN2A_D23_WAKEUPENABLE_0,VIN2A_D23_WAKEUPENABLE_1" newline bitfld.long 0x1C4 19. "VIN2A_D23_SLEWCONTROL,- SLOW_SLEW" "VIN2A_D23_SLEWCONTROL_0,VIN2A_D23_SLEWCONTROL_1" newline bitfld.long 0x1C4 18. "VIN2A_D23_INPUTENABLE,- DISABLE" "VIN2A_D23_INPUTENABLE_0,VIN2A_D23_INPUTENABLE_1" newline bitfld.long 0x1C4 17. "VIN2A_D23_PULLTYPESELECT,- PULL_DOWN" "VIN2A_D23_PULLTYPESELECT_0,VIN2A_D23_PULLTYPESELECT_1" newline bitfld.long 0x1C4 16. "VIN2A_D23_PULLUDENABLE,- DISABLE" "VIN2A_D23_PULLUDENABLE_0,VIN2A_D23_PULLUDENABLE_1" newline bitfld.long 0x1C4 8. "VIN2A_D23_MODESELECT,Selects between default and another IO delay different than the default one" "VIN2A_D23_MODESELECT_0,VIN2A_D23_MODESELECT_1" newline bitfld.long 0x1C4 4.--7. "VIN2A_D23_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C4 0.--3. "VIN2A_D23_MUXMODE,- PR1_PRU1_PRU_R3020_13" "VIN2A_D23_MUXMODE_0,?,VIN2A_D23_MUXMODE_2,VIN2A_D23_MUXMODE_3,VIN2A_D23_MUXMODE_4,VIN2A_D23_MUXMODE_5,VIN2A_D23_MUXMODE_6,VIN2A_D23_MUXMODE_7,VIN2A_D23_MUXMODE_8,?,?,VIN2A_D23_MUXMODE_11,VIN2A_D23_MUXMODE_12,VIN2A_D23_MUXMODE_13,VIN2A_D23_MUXMODE_14,?" line.long 0x1C8 "CTRL_CORE_PAD_VOUT1_CLK," rbitfld.long 0x1C8 25. "VOUT1_CLK_WAKEUPEVENT,- NOWAKEUP" "VOUT1_CLK_WAKEUPEVENT_0,VOUT1_CLK_WAKEUPEVENT_1" newline bitfld.long 0x1C8 24. "VOUT1_CLK_WAKEUPENABLE,- DISABLE" "VOUT1_CLK_WAKEUPENABLE_0,VOUT1_CLK_WAKEUPENABLE_1" newline bitfld.long 0x1C8 19. "VOUT1_CLK_SLEWCONTROL,- SLOW_SLEW" "VOUT1_CLK_SLEWCONTROL_0,VOUT1_CLK_SLEWCONTROL_1" newline bitfld.long 0x1C8 18. "VOUT1_CLK_INPUTENABLE,- DISABLE" "VOUT1_CLK_INPUTENABLE_0,VOUT1_CLK_INPUTENABLE_1" newline bitfld.long 0x1C8 17. "VOUT1_CLK_PULLTYPESELECT,- PULL_DOWN" "VOUT1_CLK_PULLTYPESELECT_0,VOUT1_CLK_PULLTYPESELECT_1" newline bitfld.long 0x1C8 16. "VOUT1_CLK_PULLUDENABLE,- DISABLE" "VOUT1_CLK_PULLUDENABLE_0,VOUT1_CLK_PULLUDENABLE_1" newline bitfld.long 0x1C8 8. "VOUT1_CLK_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_CLK_MODESELECT_0,VOUT1_CLK_MODESELECT_1" newline bitfld.long 0x1C8 4.--7. "VOUT1_CLK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C8 0.--3. "VOUT1_CLK_MUXMODE,- SPI3_CS0_8" "VOUT1_CLK_MUXMODE_0,?,?,VOUT1_CLK_MUXMODE_3,VOUT1_CLK_MUXMODE_4,?,?,?,VOUT1_CLK_MUXMODE_8,?,?,?,?,?,VOUT1_CLK_MUXMODE_14,?" line.long 0x1CC "CTRL_CORE_PAD_VOUT1_DE," rbitfld.long 0x1CC 25. "VOUT1_DE_WAKEUPEVENT,- NOWAKEUP" "VOUT1_DE_WAKEUPEVENT_0,VOUT1_DE_WAKEUPEVENT_1" newline bitfld.long 0x1CC 24. "VOUT1_DE_WAKEUPENABLE,- DISABLE" "VOUT1_DE_WAKEUPENABLE_0,VOUT1_DE_WAKEUPENABLE_1" newline bitfld.long 0x1CC 19. "VOUT1_DE_SLEWCONTROL,- SLOW_SLEW" "VOUT1_DE_SLEWCONTROL_0,VOUT1_DE_SLEWCONTROL_1" newline bitfld.long 0x1CC 18. "VOUT1_DE_INPUTENABLE,- DISABLE" "VOUT1_DE_INPUTENABLE_0,VOUT1_DE_INPUTENABLE_1" newline bitfld.long 0x1CC 17. "VOUT1_DE_PULLTYPESELECT,- PULL_DOWN" "VOUT1_DE_PULLTYPESELECT_0,VOUT1_DE_PULLTYPESELECT_1" newline bitfld.long 0x1CC 16. "VOUT1_DE_PULLUDENABLE,- DISABLE" "VOUT1_DE_PULLUDENABLE_0,VOUT1_DE_PULLUDENABLE_1" newline bitfld.long 0x1CC 8. "VOUT1_DE_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_DE_MODESELECT_0,VOUT1_DE_MODESELECT_1" newline bitfld.long 0x1CC 4.--7. "VOUT1_DE_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1CC 0.--3. "VOUT1_DE_MUXMODE,- SPI3_D1_8" "VOUT1_DE_MUXMODE_0,?,?,VOUT1_DE_MUXMODE_3,VOUT1_DE_MUXMODE_4,?,?,?,VOUT1_DE_MUXMODE_8,?,?,?,?,?,VOUT1_DE_MUXMODE_14,?" line.long 0x1D0 "CTRL_CORE_PAD_VOUT1_FLD," rbitfld.long 0x1D0 25. "VOUT1_FLD_WAKEUPEVENT,- NOWAKEUP" "VOUT1_FLD_WAKEUPEVENT_0,VOUT1_FLD_WAKEUPEVENT_1" newline bitfld.long 0x1D0 24. "VOUT1_FLD_WAKEUPENABLE,- DISABLE" "VOUT1_FLD_WAKEUPENABLE_0,VOUT1_FLD_WAKEUPENABLE_1" newline bitfld.long 0x1D0 19. "VOUT1_FLD_SLEWCONTROL,- SLOW_SLEW" "VOUT1_FLD_SLEWCONTROL_0,VOUT1_FLD_SLEWCONTROL_1" newline bitfld.long 0x1D0 18. "VOUT1_FLD_INPUTENABLE,- DISABLE" "VOUT1_FLD_INPUTENABLE_0,VOUT1_FLD_INPUTENABLE_1" newline bitfld.long 0x1D0 17. "VOUT1_FLD_PULLTYPESELECT,- PULL_DOWN" "VOUT1_FLD_PULLTYPESELECT_0,VOUT1_FLD_PULLTYPESELECT_1" newline bitfld.long 0x1D0 16. "VOUT1_FLD_PULLUDENABLE,- DISABLE" "VOUT1_FLD_PULLUDENABLE_0,VOUT1_FLD_PULLUDENABLE_1" newline bitfld.long 0x1D0 8. "VOUT1_FLD_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_FLD_MODESELECT_0,VOUT1_FLD_MODESELECT_1" newline bitfld.long 0x1D0 4.--7. "VOUT1_FLD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1D0 0.--3. "VOUT1_FLD_MUXMODE,- SPI3_CS1_8" "VOUT1_FLD_MUXMODE_0,?,?,VOUT1_FLD_MUXMODE_3,VOUT1_FLD_MUXMODE_4,?,?,?,VOUT1_FLD_MUXMODE_8,?,?,?,?,?,VOUT1_FLD_MUXMODE_14,?" line.long 0x1D4 "CTRL_CORE_PAD_VOUT1_HSYNC," rbitfld.long 0x1D4 25. "VOUT1_HSYNC_WAKEUPEVENT,- NOWAKEUP" "VOUT1_HSYNC_WAKEUPEVENT_0,VOUT1_HSYNC_WAKEUPEVENT_1" newline bitfld.long 0x1D4 24. "VOUT1_HSYNC_WAKEUPENABLE,- DISABLE" "VOUT1_HSYNC_WAKEUPENABLE_0,VOUT1_HSYNC_WAKEUPENABLE_1" newline bitfld.long 0x1D4 19. "VOUT1_HSYNC_SLEWCONTROL,- SLOW_SLEW" "VOUT1_HSYNC_SLEWCONTROL_0,VOUT1_HSYNC_SLEWCONTROL_1" newline bitfld.long 0x1D4 18. "VOUT1_HSYNC_INPUTENABLE,- DISABLE" "VOUT1_HSYNC_INPUTENABLE_0,VOUT1_HSYNC_INPUTENABLE_1" newline bitfld.long 0x1D4 17. "VOUT1_HSYNC_PULLTYPESELECT,- PULL_DOWN" "VOUT1_HSYNC_PULLTYPESELECT_0,VOUT1_HSYNC_PULLTYPESELECT_1" newline bitfld.long 0x1D4 16. "VOUT1_HSYNC_PULLUDENABLE,- DISABLE" "VOUT1_HSYNC_PULLUDENABLE_0,VOUT1_HSYNC_PULLUDENABLE_1" newline bitfld.long 0x1D4 8. "VOUT1_HSYNC_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_HSYNC_MODESELECT_0,VOUT1_HSYNC_MODESELECT_1" newline bitfld.long 0x1D4 4.--7. "VOUT1_HSYNC_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1D4 0.--3. "VOUT1_HSYNC_MUXMODE,- SPI3_D0_8" "VOUT1_HSYNC_MUXMODE_0,?,?,VOUT1_HSYNC_MUXMODE_3,VOUT1_HSYNC_MUXMODE_4,?,?,?,VOUT1_HSYNC_MUXMODE_8,?,?,?,?,?,VOUT1_HSYNC_MUXMODE_14,?" line.long 0x1D8 "CTRL_CORE_PAD_VOUT1_VSYNC," rbitfld.long 0x1D8 25. "VOUT1_VSYNC_WAKEUPEVENT,- NOWAKEUP" "VOUT1_VSYNC_WAKEUPEVENT_0,VOUT1_VSYNC_WAKEUPEVENT_1" newline bitfld.long 0x1D8 24. "VOUT1_VSYNC_WAKEUPENABLE,- DISABLE" "VOUT1_VSYNC_WAKEUPENABLE_0,VOUT1_VSYNC_WAKEUPENABLE_1" newline bitfld.long 0x1D8 19. "VOUT1_VSYNC_SLEWCONTROL,- SLOW_SLEW" "VOUT1_VSYNC_SLEWCONTROL_0,VOUT1_VSYNC_SLEWCONTROL_1" newline bitfld.long 0x1D8 18. "VOUT1_VSYNC_INPUTENABLE,- DISABLE" "VOUT1_VSYNC_INPUTENABLE_0,VOUT1_VSYNC_INPUTENABLE_1" newline bitfld.long 0x1D8 17. "VOUT1_VSYNC_PULLTYPESELECT,- PULL_DOWN" "VOUT1_VSYNC_PULLTYPESELECT_0,VOUT1_VSYNC_PULLTYPESELECT_1" newline bitfld.long 0x1D8 16. "VOUT1_VSYNC_PULLUDENABLE,- DISABLE" "VOUT1_VSYNC_PULLUDENABLE_0,VOUT1_VSYNC_PULLUDENABLE_1" newline bitfld.long 0x1D8 8. "VOUT1_VSYNC_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_VSYNC_MODESELECT_0,VOUT1_VSYNC_MODESELECT_1" newline bitfld.long 0x1D8 4.--7. "VOUT1_VSYNC_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1D8 0.--3. "VOUT1_VSYNC_MUXMODE,- PR2_PRU1_PRU_R3017_13" "VOUT1_VSYNC_MUXMODE_0,?,?,VOUT1_VSYNC_MUXMODE_3,VOUT1_VSYNC_MUXMODE_4,?,?,?,VOUT1_VSYNC_MUXMODE_8,?,?,?,VOUT1_VSYNC_MUXMODE_12,VOUT1_VSYNC_MUXMODE_13,VOUT1_VSYNC_MUXMODE_14,?" line.long 0x1DC "CTRL_CORE_PAD_VOUT1_D0," rbitfld.long 0x1DC 25. "VOUT1_D0_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D0_WAKEUPEVENT_0,VOUT1_D0_WAKEUPEVENT_1" newline bitfld.long 0x1DC 24. "VOUT1_D0_WAKEUPENABLE,- DISABLE" "VOUT1_D0_WAKEUPENABLE_0,VOUT1_D0_WAKEUPENABLE_1" newline bitfld.long 0x1DC 19. "VOUT1_D0_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D0_SLEWCONTROL_0,VOUT1_D0_SLEWCONTROL_1" newline bitfld.long 0x1DC 18. "VOUT1_D0_INPUTENABLE,- DISABLE" "VOUT1_D0_INPUTENABLE_0,VOUT1_D0_INPUTENABLE_1" newline bitfld.long 0x1DC 17. "VOUT1_D0_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D0_PULLTYPESELECT_0,VOUT1_D0_PULLTYPESELECT_1" newline bitfld.long 0x1DC 16. "VOUT1_D0_PULLUDENABLE,- DISABLE" "VOUT1_D0_PULLUDENABLE_0,VOUT1_D0_PULLUDENABLE_1" newline bitfld.long 0x1DC 8. "VOUT1_D0_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D0_MODESELECT_0,VOUT1_D0_MODESELECT_1" newline bitfld.long 0x1DC 4.--7. "VOUT1_D0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1DC 0.--3. "VOUT1_D0_MUXMODE,- PR2_PRU1_PRU_R3018_13" "VOUT1_D0_MUXMODE_0,?,VOUT1_D0_MUXMODE_2,VOUT1_D0_MUXMODE_3,VOUT1_D0_MUXMODE_4,?,?,?,VOUT1_D0_MUXMODE_8,?,VOUT1_D0_MUXMODE_10,?,VOUT1_D0_MUXMODE_12,VOUT1_D0_MUXMODE_13,VOUT1_D0_MUXMODE_14,?" line.long 0x1E0 "CTRL_CORE_PAD_VOUT1_D1," rbitfld.long 0x1E0 25. "VOUT1_D1_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D1_WAKEUPEVENT_0,VOUT1_D1_WAKEUPEVENT_1" newline bitfld.long 0x1E0 24. "VOUT1_D1_WAKEUPENABLE,- DISABLE" "VOUT1_D1_WAKEUPENABLE_0,VOUT1_D1_WAKEUPENABLE_1" newline bitfld.long 0x1E0 19. "VOUT1_D1_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D1_SLEWCONTROL_0,VOUT1_D1_SLEWCONTROL_1" newline bitfld.long 0x1E0 18. "VOUT1_D1_INPUTENABLE,- DISABLE" "VOUT1_D1_INPUTENABLE_0,VOUT1_D1_INPUTENABLE_1" newline bitfld.long 0x1E0 17. "VOUT1_D1_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D1_PULLTYPESELECT_0,VOUT1_D1_PULLTYPESELECT_1" newline bitfld.long 0x1E0 16. "VOUT1_D1_PULLUDENABLE,- DISABLE" "VOUT1_D1_PULLUDENABLE_0,VOUT1_D1_PULLUDENABLE_1" newline bitfld.long 0x1E0 8. "VOUT1_D1_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D1_MODESELECT_0,VOUT1_D1_MODESELECT_1" newline bitfld.long 0x1E0 4.--7. "VOUT1_D1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1E0 0.--3. "VOUT1_D1_MUXMODE,- PR2_PRU1_PRU_R3019_13" "VOUT1_D1_MUXMODE_0,?,VOUT1_D1_MUXMODE_2,VOUT1_D1_MUXMODE_3,VOUT1_D1_MUXMODE_4,?,?,?,?,?,VOUT1_D1_MUXMODE_10,?,VOUT1_D1_MUXMODE_12,VOUT1_D1_MUXMODE_13,VOUT1_D1_MUXMODE_14,?" line.long 0x1E4 "CTRL_CORE_PAD_VOUT1_D2," rbitfld.long 0x1E4 25. "VOUT1_D2_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D2_WAKEUPEVENT_0,VOUT1_D2_WAKEUPEVENT_1" newline bitfld.long 0x1E4 24. "VOUT1_D2_WAKEUPENABLE,- DISABLE" "VOUT1_D2_WAKEUPENABLE_0,VOUT1_D2_WAKEUPENABLE_1" newline bitfld.long 0x1E4 19. "VOUT1_D2_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D2_SLEWCONTROL_0,VOUT1_D2_SLEWCONTROL_1" newline bitfld.long 0x1E4 18. "VOUT1_D2_INPUTENABLE,- DISABLE" "VOUT1_D2_INPUTENABLE_0,VOUT1_D2_INPUTENABLE_1" newline bitfld.long 0x1E4 17. "VOUT1_D2_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D2_PULLTYPESELECT_0,VOUT1_D2_PULLTYPESELECT_1" newline bitfld.long 0x1E4 16. "VOUT1_D2_PULLUDENABLE,- DISABLE" "VOUT1_D2_PULLUDENABLE_0,VOUT1_D2_PULLUDENABLE_1" newline bitfld.long 0x1E4 8. "VOUT1_D2_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D2_MODESELECT_0,VOUT1_D2_MODESELECT_1" newline bitfld.long 0x1E4 4.--7. "VOUT1_D2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1E4 0.--3. "VOUT1_D2_MUXMODE,- PR2_PRU1_PRU_R3020_13" "VOUT1_D2_MUXMODE_0,?,VOUT1_D2_MUXMODE_2,VOUT1_D2_MUXMODE_3,VOUT1_D2_MUXMODE_4,VOUT1_D2_MUXMODE_5,VOUT1_D2_MUXMODE_6,VOUT1_D2_MUXMODE_7,?,?,VOUT1_D2_MUXMODE_10,?,VOUT1_D2_MUXMODE_12,VOUT1_D2_MUXMODE_13,VOUT1_D2_MUXMODE_14,?" line.long 0x1E8 "CTRL_CORE_PAD_VOUT1_D3," rbitfld.long 0x1E8 25. "VOUT1_D3_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D3_WAKEUPEVENT_0,VOUT1_D3_WAKEUPEVENT_1" newline bitfld.long 0x1E8 24. "VOUT1_D3_WAKEUPENABLE,- DISABLE" "VOUT1_D3_WAKEUPENABLE_0,VOUT1_D3_WAKEUPENABLE_1" newline bitfld.long 0x1E8 19. "VOUT1_D3_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D3_SLEWCONTROL_0,VOUT1_D3_SLEWCONTROL_1" newline bitfld.long 0x1E8 18. "VOUT1_D3_INPUTENABLE,- DISABLE" "VOUT1_D3_INPUTENABLE_0,VOUT1_D3_INPUTENABLE_1" newline bitfld.long 0x1E8 17. "VOUT1_D3_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D3_PULLTYPESELECT_0,VOUT1_D3_PULLTYPESELECT_1" newline bitfld.long 0x1E8 16. "VOUT1_D3_PULLUDENABLE,- DISABLE" "VOUT1_D3_PULLUDENABLE_0,VOUT1_D3_PULLUDENABLE_1" newline bitfld.long 0x1E8 8. "VOUT1_D3_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D3_MODESELECT_0,VOUT1_D3_MODESELECT_1" newline bitfld.long 0x1E8 4.--7. "VOUT1_D3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1E8 0.--3. "VOUT1_D3_MUXMODE,- PR2_PRU0_PRU_R300_13" "VOUT1_D3_MUXMODE_0,?,VOUT1_D3_MUXMODE_2,VOUT1_D3_MUXMODE_3,VOUT1_D3_MUXMODE_4,VOUT1_D3_MUXMODE_5,VOUT1_D3_MUXMODE_6,VOUT1_D3_MUXMODE_7,?,?,VOUT1_D3_MUXMODE_10,?,VOUT1_D3_MUXMODE_12,VOUT1_D3_MUXMODE_13,VOUT1_D3_MUXMODE_14,?" line.long 0x1EC "CTRL_CORE_PAD_VOUT1_D4," rbitfld.long 0x1EC 25. "VOUT1_D4_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D4_WAKEUPEVENT_0,VOUT1_D4_WAKEUPEVENT_1" newline bitfld.long 0x1EC 24. "VOUT1_D4_WAKEUPENABLE,- DISABLE" "VOUT1_D4_WAKEUPENABLE_0,VOUT1_D4_WAKEUPENABLE_1" newline bitfld.long 0x1EC 19. "VOUT1_D4_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D4_SLEWCONTROL_0,VOUT1_D4_SLEWCONTROL_1" newline bitfld.long 0x1EC 18. "VOUT1_D4_INPUTENABLE,- DISABLE" "VOUT1_D4_INPUTENABLE_0,VOUT1_D4_INPUTENABLE_1" newline bitfld.long 0x1EC 17. "VOUT1_D4_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D4_PULLTYPESELECT_0,VOUT1_D4_PULLTYPESELECT_1" newline bitfld.long 0x1EC 16. "VOUT1_D4_PULLUDENABLE,- DISABLE" "VOUT1_D4_PULLUDENABLE_0,VOUT1_D4_PULLUDENABLE_1" newline bitfld.long 0x1EC 8. "VOUT1_D4_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D4_MODESELECT_0,VOUT1_D4_MODESELECT_1" newline bitfld.long 0x1EC 4.--7. "VOUT1_D4_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1EC 0.--3. "VOUT1_D4_MUXMODE,- PR2_PRU0_PRU_R301_13" "VOUT1_D4_MUXMODE_0,?,VOUT1_D4_MUXMODE_2,VOUT1_D4_MUXMODE_3,VOUT1_D4_MUXMODE_4,VOUT1_D4_MUXMODE_5,VOUT1_D4_MUXMODE_6,?,?,?,VOUT1_D4_MUXMODE_10,?,VOUT1_D4_MUXMODE_12,VOUT1_D4_MUXMODE_13,VOUT1_D4_MUXMODE_14,?" line.long 0x1F0 "CTRL_CORE_PAD_VOUT1_D5," rbitfld.long 0x1F0 25. "VOUT1_D5_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D5_WAKEUPEVENT_0,VOUT1_D5_WAKEUPEVENT_1" newline bitfld.long 0x1F0 24. "VOUT1_D5_WAKEUPENABLE,- DISABLE" "VOUT1_D5_WAKEUPENABLE_0,VOUT1_D5_WAKEUPENABLE_1" newline bitfld.long 0x1F0 19. "VOUT1_D5_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D5_SLEWCONTROL_0,VOUT1_D5_SLEWCONTROL_1" newline bitfld.long 0x1F0 18. "VOUT1_D5_INPUTENABLE,- DISABLE" "VOUT1_D5_INPUTENABLE_0,VOUT1_D5_INPUTENABLE_1" newline bitfld.long 0x1F0 17. "VOUT1_D5_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D5_PULLTYPESELECT_0,VOUT1_D5_PULLTYPESELECT_1" newline bitfld.long 0x1F0 16. "VOUT1_D5_PULLUDENABLE,- DISABLE" "VOUT1_D5_PULLUDENABLE_0,VOUT1_D5_PULLUDENABLE_1" newline bitfld.long 0x1F0 8. "VOUT1_D5_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D5_MODESELECT_0,VOUT1_D5_MODESELECT_1" newline bitfld.long 0x1F0 4.--7. "VOUT1_D5_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1F0 0.--3. "VOUT1_D5_MUXMODE,- PR2_PRU0_PRU_R302_13" "VOUT1_D5_MUXMODE_0,?,VOUT1_D5_MUXMODE_2,VOUT1_D5_MUXMODE_3,VOUT1_D5_MUXMODE_4,VOUT1_D5_MUXMODE_5,VOUT1_D5_MUXMODE_6,?,?,?,VOUT1_D5_MUXMODE_10,?,VOUT1_D5_MUXMODE_12,VOUT1_D5_MUXMODE_13,VOUT1_D5_MUXMODE_14,?" line.long 0x1F4 "CTRL_CORE_PAD_VOUT1_D6," rbitfld.long 0x1F4 25. "VOUT1_D6_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D6_WAKEUPEVENT_0,VOUT1_D6_WAKEUPEVENT_1" newline bitfld.long 0x1F4 24. "VOUT1_D6_WAKEUPENABLE,- DISABLE" "VOUT1_D6_WAKEUPENABLE_0,VOUT1_D6_WAKEUPENABLE_1" newline bitfld.long 0x1F4 19. "VOUT1_D6_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D6_SLEWCONTROL_0,VOUT1_D6_SLEWCONTROL_1" newline bitfld.long 0x1F4 18. "VOUT1_D6_INPUTENABLE,- DISABLE" "VOUT1_D6_INPUTENABLE_0,VOUT1_D6_INPUTENABLE_1" newline bitfld.long 0x1F4 17. "VOUT1_D6_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D6_PULLTYPESELECT_0,VOUT1_D6_PULLTYPESELECT_1" newline bitfld.long 0x1F4 16. "VOUT1_D6_PULLUDENABLE,- DISABLE" "VOUT1_D6_PULLUDENABLE_0,VOUT1_D6_PULLUDENABLE_1" newline bitfld.long 0x1F4 8. "VOUT1_D6_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D6_MODESELECT_0,VOUT1_D6_MODESELECT_1" newline bitfld.long 0x1F4 4.--7. "VOUT1_D6_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1F4 0.--3. "VOUT1_D6_MUXMODE,- PR2_PRU0_PRU_R303_13" "VOUT1_D6_MUXMODE_0,?,VOUT1_D6_MUXMODE_2,VOUT1_D6_MUXMODE_3,VOUT1_D6_MUXMODE_4,VOUT1_D6_MUXMODE_5,VOUT1_D6_MUXMODE_6,?,?,?,VOUT1_D6_MUXMODE_10,?,VOUT1_D6_MUXMODE_12,VOUT1_D6_MUXMODE_13,VOUT1_D6_MUXMODE_14,?" line.long 0x1F8 "CTRL_CORE_PAD_VOUT1_D7," rbitfld.long 0x1F8 25. "VOUT1_D7_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D7_WAKEUPEVENT_0,VOUT1_D7_WAKEUPEVENT_1" newline bitfld.long 0x1F8 24. "VOUT1_D7_WAKEUPENABLE,- DISABLE" "VOUT1_D7_WAKEUPENABLE_0,VOUT1_D7_WAKEUPENABLE_1" newline bitfld.long 0x1F8 19. "VOUT1_D7_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D7_SLEWCONTROL_0,VOUT1_D7_SLEWCONTROL_1" newline bitfld.long 0x1F8 18. "VOUT1_D7_INPUTENABLE,- DISABLE" "VOUT1_D7_INPUTENABLE_0,VOUT1_D7_INPUTENABLE_1" newline bitfld.long 0x1F8 17. "VOUT1_D7_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D7_PULLTYPESELECT_0,VOUT1_D7_PULLTYPESELECT_1" newline bitfld.long 0x1F8 16. "VOUT1_D7_PULLUDENABLE,- DISABLE" "VOUT1_D7_PULLUDENABLE_0,VOUT1_D7_PULLUDENABLE_1" newline bitfld.long 0x1F8 8. "VOUT1_D7_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D7_MODESELECT_0,VOUT1_D7_MODESELECT_1" newline bitfld.long 0x1F8 4.--7. "VOUT1_D7_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1F8 0.--3. "VOUT1_D7_MUXMODE,- PR2_PRU0_PRU_R304_13" "VOUT1_D7_MUXMODE_0,?,VOUT1_D7_MUXMODE_2,VOUT1_D7_MUXMODE_3,VOUT1_D7_MUXMODE_4,?,?,?,?,?,VOUT1_D7_MUXMODE_10,?,VOUT1_D7_MUXMODE_12,VOUT1_D7_MUXMODE_13,VOUT1_D7_MUXMODE_14,?" line.long 0x1FC "CTRL_CORE_PAD_VOUT1_D8," rbitfld.long 0x1FC 25. "VOUT1_D8_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D8_WAKEUPEVENT_0,VOUT1_D8_WAKEUPEVENT_1" newline bitfld.long 0x1FC 24. "VOUT1_D8_WAKEUPENABLE,- DISABLE" "VOUT1_D8_WAKEUPENABLE_0,VOUT1_D8_WAKEUPENABLE_1" newline bitfld.long 0x1FC 19. "VOUT1_D8_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D8_SLEWCONTROL_0,VOUT1_D8_SLEWCONTROL_1" newline bitfld.long 0x1FC 18. "VOUT1_D8_INPUTENABLE,- DISABLE" "VOUT1_D8_INPUTENABLE_0,VOUT1_D8_INPUTENABLE_1" newline bitfld.long 0x1FC 17. "VOUT1_D8_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D8_PULLTYPESELECT_0,VOUT1_D8_PULLTYPESELECT_1" newline bitfld.long 0x1FC 16. "VOUT1_D8_PULLUDENABLE,- DISABLE" "VOUT1_D8_PULLUDENABLE_0,VOUT1_D8_PULLUDENABLE_1" newline bitfld.long 0x1FC 8. "VOUT1_D8_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D8_MODESELECT_0,VOUT1_D8_MODESELECT_1" newline bitfld.long 0x1FC 4.--7. "VOUT1_D8_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1FC 0.--3. "VOUT1_D8_MUXMODE,- PR2_PRU0_PRU_R305_13" "VOUT1_D8_MUXMODE_0,?,VOUT1_D8_MUXMODE_2,VOUT1_D8_MUXMODE_3,VOUT1_D8_MUXMODE_4,?,?,?,?,?,VOUT1_D8_MUXMODE_10,?,VOUT1_D8_MUXMODE_12,VOUT1_D8_MUXMODE_13,VOUT1_D8_MUXMODE_14,?" line.long 0x200 "CTRL_CORE_PAD_VOUT1_D9," rbitfld.long 0x200 25. "VOUT1_D9_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D9_WAKEUPEVENT_0,VOUT1_D9_WAKEUPEVENT_1" newline bitfld.long 0x200 24. "VOUT1_D9_WAKEUPENABLE,- DISABLE" "VOUT1_D9_WAKEUPENABLE_0,VOUT1_D9_WAKEUPENABLE_1" newline bitfld.long 0x200 19. "VOUT1_D9_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D9_SLEWCONTROL_0,VOUT1_D9_SLEWCONTROL_1" newline bitfld.long 0x200 18. "VOUT1_D9_INPUTENABLE,- DISABLE" "VOUT1_D9_INPUTENABLE_0,VOUT1_D9_INPUTENABLE_1" newline bitfld.long 0x200 17. "VOUT1_D9_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D9_PULLTYPESELECT_0,VOUT1_D9_PULLTYPESELECT_1" newline bitfld.long 0x200 16. "VOUT1_D9_PULLUDENABLE,- DISABLE" "VOUT1_D9_PULLUDENABLE_0,VOUT1_D9_PULLUDENABLE_1" newline bitfld.long 0x200 8. "VOUT1_D9_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D9_MODESELECT_0,VOUT1_D9_MODESELECT_1" newline bitfld.long 0x200 4.--7. "VOUT1_D9_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x200 0.--3. "VOUT1_D9_MUXMODE,- PR2_PRU0_PRU_R306_13" "VOUT1_D9_MUXMODE_0,?,VOUT1_D9_MUXMODE_2,VOUT1_D9_MUXMODE_3,VOUT1_D9_MUXMODE_4,?,?,?,?,?,VOUT1_D9_MUXMODE_10,?,VOUT1_D9_MUXMODE_12,VOUT1_D9_MUXMODE_13,VOUT1_D9_MUXMODE_14,?" line.long 0x204 "CTRL_CORE_PAD_VOUT1_D10," rbitfld.long 0x204 25. "VOUT1_D10_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D10_WAKEUPEVENT_0,VOUT1_D10_WAKEUPEVENT_1" newline bitfld.long 0x204 24. "VOUT1_D10_WAKEUPENABLE,- DISABLE" "VOUT1_D10_WAKEUPENABLE_0,VOUT1_D10_WAKEUPENABLE_1" newline bitfld.long 0x204 19. "VOUT1_D10_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D10_SLEWCONTROL_0,VOUT1_D10_SLEWCONTROL_1" newline bitfld.long 0x204 18. "VOUT1_D10_INPUTENABLE,- DISABLE" "VOUT1_D10_INPUTENABLE_0,VOUT1_D10_INPUTENABLE_1" newline bitfld.long 0x204 17. "VOUT1_D10_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D10_PULLTYPESELECT_0,VOUT1_D10_PULLTYPESELECT_1" newline bitfld.long 0x204 16. "VOUT1_D10_PULLUDENABLE,- DISABLE" "VOUT1_D10_PULLUDENABLE_0,VOUT1_D10_PULLUDENABLE_1" newline bitfld.long 0x204 8. "VOUT1_D10_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D10_MODESELECT_0,VOUT1_D10_MODESELECT_1" newline bitfld.long 0x204 4.--7. "VOUT1_D10_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x204 0.--3. "VOUT1_D10_MUXMODE,- PR2_PRU0_PRU_R307_13" "VOUT1_D10_MUXMODE_0,?,VOUT1_D10_MUXMODE_2,VOUT1_D10_MUXMODE_3,VOUT1_D10_MUXMODE_4,VOUT1_D10_MUXMODE_5,VOUT1_D10_MUXMODE_6,VOUT1_D10_MUXMODE_7,?,?,VOUT1_D10_MUXMODE_10,?,VOUT1_D10_MUXMODE_12,VOUT1_D10_MUXMODE_13,VOUT1_D10_MUXMODE_14,?" line.long 0x208 "CTRL_CORE_PAD_VOUT1_D11," rbitfld.long 0x208 25. "VOUT1_D11_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D11_WAKEUPEVENT_0,VOUT1_D11_WAKEUPEVENT_1" newline bitfld.long 0x208 24. "VOUT1_D11_WAKEUPENABLE,- DISABLE" "VOUT1_D11_WAKEUPENABLE_0,VOUT1_D11_WAKEUPENABLE_1" newline bitfld.long 0x208 19. "VOUT1_D11_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D11_SLEWCONTROL_0,VOUT1_D11_SLEWCONTROL_1" newline bitfld.long 0x208 18. "VOUT1_D11_INPUTENABLE,- DISABLE" "VOUT1_D11_INPUTENABLE_0,VOUT1_D11_INPUTENABLE_1" newline bitfld.long 0x208 17. "VOUT1_D11_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D11_PULLTYPESELECT_0,VOUT1_D11_PULLTYPESELECT_1" newline bitfld.long 0x208 16. "VOUT1_D11_PULLUDENABLE,- DISABLE" "VOUT1_D11_PULLUDENABLE_0,VOUT1_D11_PULLUDENABLE_1" newline bitfld.long 0x208 8. "VOUT1_D11_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D11_MODESELECT_0,VOUT1_D11_MODESELECT_1" newline bitfld.long 0x208 4.--7. "VOUT1_D11_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x208 0.--3. "VOUT1_D11_MUXMODE,- PR2_PRU0_PRU_R308_13" "VOUT1_D11_MUXMODE_0,?,VOUT1_D11_MUXMODE_2,VOUT1_D11_MUXMODE_3,VOUT1_D11_MUXMODE_4,VOUT1_D11_MUXMODE_5,VOUT1_D11_MUXMODE_6,VOUT1_D11_MUXMODE_7,?,?,VOUT1_D11_MUXMODE_10,?,VOUT1_D11_MUXMODE_12,VOUT1_D11_MUXMODE_13,VOUT1_D11_MUXMODE_14,?" line.long 0x20C "CTRL_CORE_PAD_VOUT1_D12," rbitfld.long 0x20C 25. "VOUT1_D12_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D12_WAKEUPEVENT_0,VOUT1_D12_WAKEUPEVENT_1" newline bitfld.long 0x20C 24. "VOUT1_D12_WAKEUPENABLE,- DISABLE" "VOUT1_D12_WAKEUPENABLE_0,VOUT1_D12_WAKEUPENABLE_1" newline bitfld.long 0x20C 19. "VOUT1_D12_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D12_SLEWCONTROL_0,VOUT1_D12_SLEWCONTROL_1" newline bitfld.long 0x20C 18. "VOUT1_D12_INPUTENABLE,- DISABLE" "VOUT1_D12_INPUTENABLE_0,VOUT1_D12_INPUTENABLE_1" newline bitfld.long 0x20C 17. "VOUT1_D12_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D12_PULLTYPESELECT_0,VOUT1_D12_PULLTYPESELECT_1" newline bitfld.long 0x20C 16. "VOUT1_D12_PULLUDENABLE,- DISABLE" "VOUT1_D12_PULLUDENABLE_0,VOUT1_D12_PULLUDENABLE_1" newline bitfld.long 0x20C 8. "VOUT1_D12_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D12_MODESELECT_0,VOUT1_D12_MODESELECT_1" newline bitfld.long 0x20C 4.--7. "VOUT1_D12_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20C 0.--3. "VOUT1_D12_MUXMODE,- PR2_PRU0_PRU_R309_13" "VOUT1_D12_MUXMODE_0,?,VOUT1_D12_MUXMODE_2,VOUT1_D12_MUXMODE_3,VOUT1_D12_MUXMODE_4,VOUT1_D12_MUXMODE_5,VOUT1_D12_MUXMODE_6,?,?,?,VOUT1_D12_MUXMODE_10,?,VOUT1_D12_MUXMODE_12,VOUT1_D12_MUXMODE_13,VOUT1_D12_MUXMODE_14,?" line.long 0x210 "CTRL_CORE_PAD_VOUT1_D13," rbitfld.long 0x210 25. "VOUT1_D13_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D13_WAKEUPEVENT_0,VOUT1_D13_WAKEUPEVENT_1" newline bitfld.long 0x210 24. "VOUT1_D13_WAKEUPENABLE,- DISABLE" "VOUT1_D13_WAKEUPENABLE_0,VOUT1_D13_WAKEUPENABLE_1" newline bitfld.long 0x210 19. "VOUT1_D13_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D13_SLEWCONTROL_0,VOUT1_D13_SLEWCONTROL_1" newline bitfld.long 0x210 18. "VOUT1_D13_INPUTENABLE,- DISABLE" "VOUT1_D13_INPUTENABLE_0,VOUT1_D13_INPUTENABLE_1" newline bitfld.long 0x210 17. "VOUT1_D13_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D13_PULLTYPESELECT_0,VOUT1_D13_PULLTYPESELECT_1" newline bitfld.long 0x210 16. "VOUT1_D13_PULLUDENABLE,- DISABLE" "VOUT1_D13_PULLUDENABLE_0,VOUT1_D13_PULLUDENABLE_1" newline bitfld.long 0x210 8. "VOUT1_D13_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D13_MODESELECT_0,VOUT1_D13_MODESELECT_1" newline bitfld.long 0x210 4.--7. "VOUT1_D13_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x210 0.--3. "VOUT1_D13_MUXMODE,- PR2_PRU0_PRU_R3010_13" "VOUT1_D13_MUXMODE_0,?,VOUT1_D13_MUXMODE_2,VOUT1_D13_MUXMODE_3,VOUT1_D13_MUXMODE_4,VOUT1_D13_MUXMODE_5,VOUT1_D13_MUXMODE_6,?,?,?,VOUT1_D13_MUXMODE_10,?,VOUT1_D13_MUXMODE_12,VOUT1_D13_MUXMODE_13,VOUT1_D13_MUXMODE_14,?" line.long 0x214 "CTRL_CORE_PAD_VOUT1_D14," rbitfld.long 0x214 25. "VOUT1_D14_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D14_WAKEUPEVENT_0,VOUT1_D14_WAKEUPEVENT_1" newline bitfld.long 0x214 24. "VOUT1_D14_WAKEUPENABLE,- DISABLE" "VOUT1_D14_WAKEUPENABLE_0,VOUT1_D14_WAKEUPENABLE_1" newline bitfld.long 0x214 19. "VOUT1_D14_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D14_SLEWCONTROL_0,VOUT1_D14_SLEWCONTROL_1" newline bitfld.long 0x214 18. "VOUT1_D14_INPUTENABLE,- DISABLE" "VOUT1_D14_INPUTENABLE_0,VOUT1_D14_INPUTENABLE_1" newline bitfld.long 0x214 17. "VOUT1_D14_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D14_PULLTYPESELECT_0,VOUT1_D14_PULLTYPESELECT_1" newline bitfld.long 0x214 16. "VOUT1_D14_PULLUDENABLE,- DISABLE" "VOUT1_D14_PULLUDENABLE_0,VOUT1_D14_PULLUDENABLE_1" newline bitfld.long 0x214 8. "VOUT1_D14_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D14_MODESELECT_0,VOUT1_D14_MODESELECT_1" newline bitfld.long 0x214 4.--7. "VOUT1_D14_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x214 0.--3. "VOUT1_D14_MUXMODE,- PR2_PRU0_PRU_R3011_13" "VOUT1_D14_MUXMODE_0,?,VOUT1_D14_MUXMODE_2,VOUT1_D14_MUXMODE_3,VOUT1_D14_MUXMODE_4,VOUT1_D14_MUXMODE_5,VOUT1_D14_MUXMODE_6,?,?,?,VOUT1_D14_MUXMODE_10,?,VOUT1_D14_MUXMODE_12,VOUT1_D14_MUXMODE_13,VOUT1_D14_MUXMODE_14,?" line.long 0x218 "CTRL_CORE_PAD_VOUT1_D15," rbitfld.long 0x218 25. "VOUT1_D15_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D15_WAKEUPEVENT_0,VOUT1_D15_WAKEUPEVENT_1" newline bitfld.long 0x218 24. "VOUT1_D15_WAKEUPENABLE,- DISABLE" "VOUT1_D15_WAKEUPENABLE_0,VOUT1_D15_WAKEUPENABLE_1" newline bitfld.long 0x218 19. "VOUT1_D15_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D15_SLEWCONTROL_0,VOUT1_D15_SLEWCONTROL_1" newline bitfld.long 0x218 18. "VOUT1_D15_INPUTENABLE,- DISABLE" "VOUT1_D15_INPUTENABLE_0,VOUT1_D15_INPUTENABLE_1" newline bitfld.long 0x218 17. "VOUT1_D15_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D15_PULLTYPESELECT_0,VOUT1_D15_PULLTYPESELECT_1" newline bitfld.long 0x218 16. "VOUT1_D15_PULLUDENABLE,- DISABLE" "VOUT1_D15_PULLUDENABLE_0,VOUT1_D15_PULLUDENABLE_1" newline bitfld.long 0x218 8. "VOUT1_D15_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D15_MODESELECT_0,VOUT1_D15_MODESELECT_1" newline bitfld.long 0x218 4.--7. "VOUT1_D15_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x218 0.--3. "VOUT1_D15_MUXMODE,- PR2_PRU0_PRU_R3012_13" "VOUT1_D15_MUXMODE_0,?,VOUT1_D15_MUXMODE_2,VOUT1_D15_MUXMODE_3,VOUT1_D15_MUXMODE_4,VOUT1_D15_MUXMODE_5,VOUT1_D15_MUXMODE_6,?,?,?,VOUT1_D15_MUXMODE_10,?,VOUT1_D15_MUXMODE_12,VOUT1_D15_MUXMODE_13,VOUT1_D15_MUXMODE_14,?" line.long 0x21C "CTRL_CORE_PAD_VOUT1_D16," rbitfld.long 0x21C 25. "VOUT1_D16_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D16_WAKEUPEVENT_0,VOUT1_D16_WAKEUPEVENT_1" newline bitfld.long 0x21C 24. "VOUT1_D16_WAKEUPENABLE,- DISABLE" "VOUT1_D16_WAKEUPENABLE_0,VOUT1_D16_WAKEUPENABLE_1" newline bitfld.long 0x21C 19. "VOUT1_D16_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D16_SLEWCONTROL_0,VOUT1_D16_SLEWCONTROL_1" newline bitfld.long 0x21C 18. "VOUT1_D16_INPUTENABLE,- DISABLE" "VOUT1_D16_INPUTENABLE_0,VOUT1_D16_INPUTENABLE_1" newline bitfld.long 0x21C 17. "VOUT1_D16_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D16_PULLTYPESELECT_0,VOUT1_D16_PULLTYPESELECT_1" newline bitfld.long 0x21C 16. "VOUT1_D16_PULLUDENABLE,- DISABLE" "VOUT1_D16_PULLUDENABLE_0,VOUT1_D16_PULLUDENABLE_1" newline bitfld.long 0x21C 8. "VOUT1_D16_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D16_MODESELECT_0,VOUT1_D16_MODESELECT_1" newline bitfld.long 0x21C 4.--7. "VOUT1_D16_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x21C 0.--3. "VOUT1_D16_MUXMODE,- PR2_PRU0_PRU_R3013_13" "VOUT1_D16_MUXMODE_0,?,VOUT1_D16_MUXMODE_2,VOUT1_D16_MUXMODE_3,VOUT1_D16_MUXMODE_4,?,?,?,?,?,VOUT1_D16_MUXMODE_10,VOUT1_D16_MUXMODE_11,VOUT1_D16_MUXMODE_12,VOUT1_D16_MUXMODE_13,VOUT1_D16_MUXMODE_14,?" line.long 0x220 "CTRL_CORE_PAD_VOUT1_D17," rbitfld.long 0x220 25. "VOUT1_D17_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D17_WAKEUPEVENT_0,VOUT1_D17_WAKEUPEVENT_1" newline bitfld.long 0x220 24. "VOUT1_D17_WAKEUPENABLE,- DISABLE" "VOUT1_D17_WAKEUPENABLE_0,VOUT1_D17_WAKEUPENABLE_1" newline bitfld.long 0x220 19. "VOUT1_D17_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D17_SLEWCONTROL_0,VOUT1_D17_SLEWCONTROL_1" newline bitfld.long 0x220 18. "VOUT1_D17_INPUTENABLE,- DISABLE" "VOUT1_D17_INPUTENABLE_0,VOUT1_D17_INPUTENABLE_1" newline bitfld.long 0x220 17. "VOUT1_D17_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D17_PULLTYPESELECT_0,VOUT1_D17_PULLTYPESELECT_1" newline bitfld.long 0x220 16. "VOUT1_D17_PULLUDENABLE,- DISABLE" "VOUT1_D17_PULLUDENABLE_0,VOUT1_D17_PULLUDENABLE_1" newline bitfld.long 0x220 8. "VOUT1_D17_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D17_MODESELECT_0,VOUT1_D17_MODESELECT_1" newline bitfld.long 0x220 4.--7. "VOUT1_D17_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x220 0.--3. "VOUT1_D17_MUXMODE,- PR2_PRU0_PRU_R3014_13" "VOUT1_D17_MUXMODE_0,?,VOUT1_D17_MUXMODE_2,VOUT1_D17_MUXMODE_3,VOUT1_D17_MUXMODE_4,?,?,?,?,?,VOUT1_D17_MUXMODE_10,VOUT1_D17_MUXMODE_11,VOUT1_D17_MUXMODE_12,VOUT1_D17_MUXMODE_13,VOUT1_D17_MUXMODE_14,?" line.long 0x224 "CTRL_CORE_PAD_VOUT1_D18," rbitfld.long 0x224 25. "VOUT1_D18_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D18_WAKEUPEVENT_0,VOUT1_D18_WAKEUPEVENT_1" newline bitfld.long 0x224 24. "VOUT1_D18_WAKEUPENABLE,- DISABLE" "VOUT1_D18_WAKEUPENABLE_0,VOUT1_D18_WAKEUPENABLE_1" newline bitfld.long 0x224 19. "VOUT1_D18_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D18_SLEWCONTROL_0,VOUT1_D18_SLEWCONTROL_1" newline bitfld.long 0x224 18. "VOUT1_D18_INPUTENABLE,- DISABLE" "VOUT1_D18_INPUTENABLE_0,VOUT1_D18_INPUTENABLE_1" newline bitfld.long 0x224 17. "VOUT1_D18_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D18_PULLTYPESELECT_0,VOUT1_D18_PULLTYPESELECT_1" newline bitfld.long 0x224 16. "VOUT1_D18_PULLUDENABLE,- DISABLE" "VOUT1_D18_PULLUDENABLE_0,VOUT1_D18_PULLUDENABLE_1" newline bitfld.long 0x224 8. "VOUT1_D18_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D18_MODESELECT_0,VOUT1_D18_MODESELECT_1" newline bitfld.long 0x224 4.--7. "VOUT1_D18_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x224 0.--3. "VOUT1_D18_MUXMODE,- PR2_PRU0_PRU_R3015_13" "VOUT1_D18_MUXMODE_0,?,VOUT1_D18_MUXMODE_2,VOUT1_D18_MUXMODE_3,VOUT1_D18_MUXMODE_4,VOUT1_D18_MUXMODE_5,VOUT1_D18_MUXMODE_6,?,?,?,VOUT1_D18_MUXMODE_10,VOUT1_D18_MUXMODE_11,VOUT1_D18_MUXMODE_12,VOUT1_D18_MUXMODE_13,VOUT1_D18_MUXMODE_14,?" line.long 0x228 "CTRL_CORE_PAD_VOUT1_D19," rbitfld.long 0x228 25. "VOUT1_D19_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D19_WAKEUPEVENT_0,VOUT1_D19_WAKEUPEVENT_1" newline bitfld.long 0x228 24. "VOUT1_D19_WAKEUPENABLE,- DISABLE" "VOUT1_D19_WAKEUPENABLE_0,VOUT1_D19_WAKEUPENABLE_1" newline bitfld.long 0x228 19. "VOUT1_D19_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D19_SLEWCONTROL_0,VOUT1_D19_SLEWCONTROL_1" newline bitfld.long 0x228 18. "VOUT1_D19_INPUTENABLE,- DISABLE" "VOUT1_D19_INPUTENABLE_0,VOUT1_D19_INPUTENABLE_1" newline bitfld.long 0x228 17. "VOUT1_D19_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D19_PULLTYPESELECT_0,VOUT1_D19_PULLTYPESELECT_1" newline bitfld.long 0x228 16. "VOUT1_D19_PULLUDENABLE,- DISABLE" "VOUT1_D19_PULLUDENABLE_0,VOUT1_D19_PULLUDENABLE_1" newline bitfld.long 0x228 8. "VOUT1_D19_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D19_MODESELECT_0,VOUT1_D19_MODESELECT_1" newline bitfld.long 0x228 4.--7. "VOUT1_D19_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x228 0.--3. "VOUT1_D19_MUXMODE,- PR2_PRU0_PRU_R3016_13" "VOUT1_D19_MUXMODE_0,?,VOUT1_D19_MUXMODE_2,VOUT1_D19_MUXMODE_3,VOUT1_D19_MUXMODE_4,VOUT1_D19_MUXMODE_5,VOUT1_D19_MUXMODE_6,?,?,?,VOUT1_D19_MUXMODE_10,VOUT1_D19_MUXMODE_11,VOUT1_D19_MUXMODE_12,VOUT1_D19_MUXMODE_13,VOUT1_D19_MUXMODE_14,?" line.long 0x22C "CTRL_CORE_PAD_VOUT1_D20," rbitfld.long 0x22C 25. "VOUT1_D20_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D20_WAKEUPEVENT_0,VOUT1_D20_WAKEUPEVENT_1" newline bitfld.long 0x22C 24. "VOUT1_D20_WAKEUPENABLE,- DISABLE" "VOUT1_D20_WAKEUPENABLE_0,VOUT1_D20_WAKEUPENABLE_1" newline bitfld.long 0x22C 19. "VOUT1_D20_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D20_SLEWCONTROL_0,VOUT1_D20_SLEWCONTROL_1" newline bitfld.long 0x22C 18. "VOUT1_D20_INPUTENABLE,- DISABLE" "VOUT1_D20_INPUTENABLE_0,VOUT1_D20_INPUTENABLE_1" newline bitfld.long 0x22C 17. "VOUT1_D20_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D20_PULLTYPESELECT_0,VOUT1_D20_PULLTYPESELECT_1" newline bitfld.long 0x22C 16. "VOUT1_D20_PULLUDENABLE,- DISABLE" "VOUT1_D20_PULLUDENABLE_0,VOUT1_D20_PULLUDENABLE_1" newline bitfld.long 0x22C 8. "VOUT1_D20_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D20_MODESELECT_0,VOUT1_D20_MODESELECT_1" newline bitfld.long 0x22C 4.--7. "VOUT1_D20_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x22C 0.--3. "VOUT1_D20_MUXMODE,- PR2_PRU0_PRU_R3017_13" "VOUT1_D20_MUXMODE_0,?,VOUT1_D20_MUXMODE_2,VOUT1_D20_MUXMODE_3,VOUT1_D20_MUXMODE_4,VOUT1_D20_MUXMODE_5,VOUT1_D20_MUXMODE_6,?,?,?,VOUT1_D20_MUXMODE_10,VOUT1_D20_MUXMODE_11,VOUT1_D20_MUXMODE_12,VOUT1_D20_MUXMODE_13,VOUT1_D20_MUXMODE_14,?" line.long 0x230 "CTRL_CORE_PAD_VOUT1_D21," rbitfld.long 0x230 25. "VOUT1_D21_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D21_WAKEUPEVENT_0,VOUT1_D21_WAKEUPEVENT_1" newline bitfld.long 0x230 24. "VOUT1_D21_WAKEUPENABLE,- DISABLE" "VOUT1_D21_WAKEUPENABLE_0,VOUT1_D21_WAKEUPENABLE_1" newline bitfld.long 0x230 19. "VOUT1_D21_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D21_SLEWCONTROL_0,VOUT1_D21_SLEWCONTROL_1" newline bitfld.long 0x230 18. "VOUT1_D21_INPUTENABLE,- DISABLE" "VOUT1_D21_INPUTENABLE_0,VOUT1_D21_INPUTENABLE_1" newline bitfld.long 0x230 17. "VOUT1_D21_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D21_PULLTYPESELECT_0,VOUT1_D21_PULLTYPESELECT_1" newline bitfld.long 0x230 16. "VOUT1_D21_PULLUDENABLE,- DISABLE" "VOUT1_D21_PULLUDENABLE_0,VOUT1_D21_PULLUDENABLE_1" newline bitfld.long 0x230 8. "VOUT1_D21_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D21_MODESELECT_0,VOUT1_D21_MODESELECT_1" newline bitfld.long 0x230 4.--7. "VOUT1_D21_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x230 0.--3. "VOUT1_D21_MUXMODE,- PR2_PRU0_PRU_R3018_13" "VOUT1_D21_MUXMODE_0,?,VOUT1_D21_MUXMODE_2,VOUT1_D21_MUXMODE_3,VOUT1_D21_MUXMODE_4,VOUT1_D21_MUXMODE_5,VOUT1_D21_MUXMODE_6,?,?,?,VOUT1_D21_MUXMODE_10,VOUT1_D21_MUXMODE_11,VOUT1_D21_MUXMODE_12,VOUT1_D21_MUXMODE_13,VOUT1_D21_MUXMODE_14,?" line.long 0x234 "CTRL_CORE_PAD_VOUT1_D22," rbitfld.long 0x234 25. "VOUT1_D22_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D22_WAKEUPEVENT_0,VOUT1_D22_WAKEUPEVENT_1" newline bitfld.long 0x234 24. "VOUT1_D22_WAKEUPENABLE,- DISABLE" "VOUT1_D22_WAKEUPENABLE_0,VOUT1_D22_WAKEUPENABLE_1" newline bitfld.long 0x234 19. "VOUT1_D22_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D22_SLEWCONTROL_0,VOUT1_D22_SLEWCONTROL_1" newline bitfld.long 0x234 18. "VOUT1_D22_INPUTENABLE,- DISABLE" "VOUT1_D22_INPUTENABLE_0,VOUT1_D22_INPUTENABLE_1" newline bitfld.long 0x234 17. "VOUT1_D22_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D22_PULLTYPESELECT_0,VOUT1_D22_PULLTYPESELECT_1" newline bitfld.long 0x234 16. "VOUT1_D22_PULLUDENABLE,- DISABLE" "VOUT1_D22_PULLUDENABLE_0,VOUT1_D22_PULLUDENABLE_1" newline bitfld.long 0x234 8. "VOUT1_D22_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D22_MODESELECT_0,VOUT1_D22_MODESELECT_1" newline bitfld.long 0x234 4.--7. "VOUT1_D22_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x234 0.--3. "VOUT1_D22_MUXMODE,- PR2_PRU0_PRU_R3019_13" "VOUT1_D22_MUXMODE_0,?,VOUT1_D22_MUXMODE_2,VOUT1_D22_MUXMODE_3,VOUT1_D22_MUXMODE_4,VOUT1_D22_MUXMODE_5,VOUT1_D22_MUXMODE_6,?,?,?,VOUT1_D22_MUXMODE_10,VOUT1_D22_MUXMODE_11,VOUT1_D22_MUXMODE_12,VOUT1_D22_MUXMODE_13,VOUT1_D22_MUXMODE_14,?" line.long 0x238 "CTRL_CORE_PAD_VOUT1_D23," rbitfld.long 0x238 25. "VOUT1_D23_WAKEUPEVENT,- NOWAKEUP" "VOUT1_D23_WAKEUPEVENT_0,VOUT1_D23_WAKEUPEVENT_1" newline bitfld.long 0x238 24. "VOUT1_D23_WAKEUPENABLE,- DISABLE" "VOUT1_D23_WAKEUPENABLE_0,VOUT1_D23_WAKEUPENABLE_1" newline bitfld.long 0x238 19. "VOUT1_D23_SLEWCONTROL,- SLOW_SLEW" "VOUT1_D23_SLEWCONTROL_0,VOUT1_D23_SLEWCONTROL_1" newline bitfld.long 0x238 18. "VOUT1_D23_INPUTENABLE,- DISABLE" "VOUT1_D23_INPUTENABLE_0,VOUT1_D23_INPUTENABLE_1" newline bitfld.long 0x238 17. "VOUT1_D23_PULLTYPESELECT,- PULL_DOWN" "VOUT1_D23_PULLTYPESELECT_0,VOUT1_D23_PULLTYPESELECT_1" newline bitfld.long 0x238 16. "VOUT1_D23_PULLUDENABLE,- DISABLE" "VOUT1_D23_PULLUDENABLE_0,VOUT1_D23_PULLUDENABLE_1" newline bitfld.long 0x238 8. "VOUT1_D23_MODESELECT,Selects between default and another IO delay different than the default one" "VOUT1_D23_MODESELECT_0,VOUT1_D23_MODESELECT_1" newline bitfld.long 0x238 4.--7. "VOUT1_D23_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x238 0.--3. "VOUT1_D23_MUXMODE,- PR2_PRU0_PRU_R3020_13" "VOUT1_D23_MUXMODE_0,?,VOUT1_D23_MUXMODE_2,VOUT1_D23_MUXMODE_3,VOUT1_D23_MUXMODE_4,?,?,?,VOUT1_D23_MUXMODE_8,?,VOUT1_D23_MUXMODE_10,VOUT1_D23_MUXMODE_11,VOUT1_D23_MUXMODE_12,VOUT1_D23_MUXMODE_13,VOUT1_D23_MUXMODE_14,?" line.long 0x23C "CTRL_CORE_PAD_MDIO_MCLK," rbitfld.long 0x23C 25. "MDIO_MCLK_WAKEUPEVENT,- NOWAKEUP" "MDIO_MCLK_WAKEUPEVENT_0,MDIO_MCLK_WAKEUPEVENT_1" newline bitfld.long 0x23C 24. "MDIO_MCLK_WAKEUPENABLE,- DISABLE" "MDIO_MCLK_WAKEUPENABLE_0,MDIO_MCLK_WAKEUPENABLE_1" newline bitfld.long 0x23C 19. "MDIO_MCLK_SLEWCONTROL,- SLOW_SLEW" "MDIO_MCLK_SLEWCONTROL_0,MDIO_MCLK_SLEWCONTROL_1" newline bitfld.long 0x23C 18. "MDIO_MCLK_INPUTENABLE,- DISABLE" "MDIO_MCLK_INPUTENABLE_0,MDIO_MCLK_INPUTENABLE_1" newline bitfld.long 0x23C 17. "MDIO_MCLK_PULLTYPESELECT,- PULL_DOWN" "MDIO_MCLK_PULLTYPESELECT_0,MDIO_MCLK_PULLTYPESELECT_1" newline bitfld.long 0x23C 16. "MDIO_MCLK_PULLUDENABLE,- DISABLE" "MDIO_MCLK_PULLUDENABLE_0,MDIO_MCLK_PULLUDENABLE_1" newline bitfld.long 0x23C 8. "MDIO_MCLK_MODESELECT,Selects between default and another IO delay different than the default one" "MDIO_MCLK_MODESELECT_0,MDIO_MCLK_MODESELECT_1" newline bitfld.long 0x23C 4.--7. "MDIO_MCLK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x23C 0.--3. "MDIO_MCLK_MUXMODE,- PR2_PRU1_PRU_R300_13" "MDIO_MCLK_MUXMODE_0,MDIO_MCLK_MUXMODE_1,?,MDIO_MCLK_MUXMODE_3,MDIO_MCLK_MUXMODE_4,MDIO_MCLK_MUXMODE_5,?,?,?,?,?,MDIO_MCLK_MUXMODE_11,MDIO_MCLK_MUXMODE_12,MDIO_MCLK_MUXMODE_13,MDIO_MCLK_MUXMODE_14,?" line.long 0x240 "CTRL_CORE_PAD_MDIO_D," rbitfld.long 0x240 25. "MDIO_D_WAKEUPEVENT,- NOWAKEUP" "MDIO_D_WAKEUPEVENT_0,MDIO_D_WAKEUPEVENT_1" newline bitfld.long 0x240 24. "MDIO_D_WAKEUPENABLE,- DISABLE" "MDIO_D_WAKEUPENABLE_0,MDIO_D_WAKEUPENABLE_1" newline bitfld.long 0x240 19. "MDIO_D_SLEWCONTROL,- SLOW_SLEW" "MDIO_D_SLEWCONTROL_0,MDIO_D_SLEWCONTROL_1" newline bitfld.long 0x240 18. "MDIO_D_INPUTENABLE,- DISABLE" "MDIO_D_INPUTENABLE_0,MDIO_D_INPUTENABLE_1" newline bitfld.long 0x240 17. "MDIO_D_PULLTYPESELECT,- PULL_DOWN" "MDIO_D_PULLTYPESELECT_0,MDIO_D_PULLTYPESELECT_1" newline bitfld.long 0x240 16. "MDIO_D_PULLUDENABLE,- DISABLE" "MDIO_D_PULLUDENABLE_0,MDIO_D_PULLUDENABLE_1" newline bitfld.long 0x240 8. "MDIO_D_MODESELECT,Selects between default and another IO delay different than the default one" "MDIO_D_MODESELECT_0,MDIO_D_MODESELECT_1" newline bitfld.long 0x240 4.--7. "MDIO_D_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x240 0.--3. "MDIO_D_MUXMODE,- PR2_PRU1_PRU_R301_13" "MDIO_D_MUXMODE_0,MDIO_D_MUXMODE_1,?,MDIO_D_MUXMODE_3,MDIO_D_MUXMODE_4,MDIO_D_MUXMODE_5,?,?,?,?,?,MDIO_D_MUXMODE_11,MDIO_D_MUXMODE_12,MDIO_D_MUXMODE_13,MDIO_D_MUXMODE_14,?" line.long 0x244 "CTRL_CORE_PAD_RMII_MHZ_50_CLK," rbitfld.long 0x244 25. "RMII_MHZ_50_CLK_WAKEUPEVENT,- NOWAKEUP" "RMII_MHZ_50_CLK_WAKEUPEVENT_0,RMII_MHZ_50_CLK_WAKEUPEVENT_1" newline bitfld.long 0x244 24. "RMII_MHZ_50_CLK_WAKEUPENABLE,- DISABLE" "RMII_MHZ_50_CLK_WAKEUPENABLE_0,RMII_MHZ_50_CLK_WAKEUPENABLE_1" newline bitfld.long 0x244 19. "RMII_MHZ_50_CLK_SLEWCONTROL,- SLOW_SLEW" "RMII_MHZ_50_CLK_SLEWCONTROL_0,RMII_MHZ_50_CLK_SLEWCONTROL_1" newline bitfld.long 0x244 18. "RMII_MHZ_50_CLK_INPUTENABLE,- DISABLE" "RMII_MHZ_50_CLK_INPUTENABLE_0,RMII_MHZ_50_CLK_INPUTENABLE_1" newline bitfld.long 0x244 17. "RMII_MHZ_50_CLK_PULLTYPESELECT,- PULL_DOWN" "RMII_MHZ_50_CLK_PULLTYPESELECT_0,RMII_MHZ_50_CLK_PULLTYPESELECT_1" newline bitfld.long 0x244 16. "RMII_MHZ_50_CLK_PULLUDENABLE,- DISABLE" "RMII_MHZ_50_CLK_PULLUDENABLE_0,RMII_MHZ_50_CLK_PULLUDENABLE_1" newline bitfld.long 0x244 8. "RMII_MHZ_50_CLK_MODESELECT,Selects between default and another IO delay different than the default one" "RMII_MHZ_50_CLK_MODESELECT_0,RMII_MHZ_50_CLK_MODESELECT_1" newline bitfld.long 0x244 4.--7. "RMII_MHZ_50_CLK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x244 0.--3. "RMII_MHZ_50_CLK_MUXMODE,- RMII_MHZ_50_CLK_0" "RMII_MHZ_50_CLK_MUXMODE_0,?,?,?,RMII_MHZ_50_CLK_MUXMODE_4,?,?,?,?,?,?,?,RMII_MHZ_50_CLK_MUXMODE_12,RMII_MHZ_50_CLK_MUXMODE_13,RMII_MHZ_50_CLK_MUXMODE_14,?" line.long 0x248 "CTRL_CORE_PAD_UART3_RXD," rbitfld.long 0x248 25. "UART3_RXD_WAKEUPEVENT,- NOWAKEUP" "UART3_RXD_WAKEUPEVENT_0,UART3_RXD_WAKEUPEVENT_1" newline bitfld.long 0x248 24. "UART3_RXD_WAKEUPENABLE,- DISABLE" "UART3_RXD_WAKEUPENABLE_0,UART3_RXD_WAKEUPENABLE_1" newline bitfld.long 0x248 19. "UART3_RXD_SLEWCONTROL,- SLOW_SLEW" "UART3_RXD_SLEWCONTROL_0,UART3_RXD_SLEWCONTROL_1" newline bitfld.long 0x248 18. "UART3_RXD_INPUTENABLE,- DISABLE" "UART3_RXD_INPUTENABLE_0,UART3_RXD_INPUTENABLE_1" newline bitfld.long 0x248 17. "UART3_RXD_PULLTYPESELECT,- PULL_DOWN" "UART3_RXD_PULLTYPESELECT_0,UART3_RXD_PULLTYPESELECT_1" newline bitfld.long 0x248 16. "UART3_RXD_PULLUDENABLE,- DISABLE" "UART3_RXD_PULLUDENABLE_0,UART3_RXD_PULLUDENABLE_1" newline bitfld.long 0x248 8. "UART3_RXD_MODESELECT,Selects between default and another IO delay different than the default one" "UART3_RXD_MODESELECT_0,UART3_RXD_MODESELECT_1" newline bitfld.long 0x248 4.--7. "UART3_RXD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x248 0.--3. "UART3_RXD_MUXMODE,- PR2_PRU1_PRU_R303_13" "UART3_RXD_MUXMODE_0,?,UART3_RXD_MUXMODE_2,UART3_RXD_MUXMODE_3,UART3_RXD_MUXMODE_4,UART3_RXD_MUXMODE_5,?,UART3_RXD_MUXMODE_7,?,?,?,UART3_RXD_MUXMODE_11,UART3_RXD_MUXMODE_12,UART3_RXD_MUXMODE_13,UART3_RXD_MUXMODE_14,?" line.long 0x24C "CTRL_CORE_PAD_UART3_TXD," rbitfld.long 0x24C 25. "UART3_TXD_WAKEUPEVENT,- NOWAKEUP" "UART3_TXD_WAKEUPEVENT_0,UART3_TXD_WAKEUPEVENT_1" newline bitfld.long 0x24C 24. "UART3_TXD_WAKEUPENABLE,- DISABLE" "UART3_TXD_WAKEUPENABLE_0,UART3_TXD_WAKEUPENABLE_1" newline bitfld.long 0x24C 19. "UART3_TXD_SLEWCONTROL,- SLOW_SLEW" "UART3_TXD_SLEWCONTROL_0,UART3_TXD_SLEWCONTROL_1" newline bitfld.long 0x24C 18. "UART3_TXD_INPUTENABLE,- DISABLE" "UART3_TXD_INPUTENABLE_0,UART3_TXD_INPUTENABLE_1" newline bitfld.long 0x24C 17. "UART3_TXD_PULLTYPESELECT,- PULL_DOWN" "UART3_TXD_PULLTYPESELECT_0,UART3_TXD_PULLTYPESELECT_1" newline bitfld.long 0x24C 16. "UART3_TXD_PULLUDENABLE,- DISABLE" "UART3_TXD_PULLUDENABLE_0,UART3_TXD_PULLUDENABLE_1" newline bitfld.long 0x24C 8. "UART3_TXD_MODESELECT,Selects between default and another IO delay different than the default one" "UART3_TXD_MODESELECT_0,UART3_TXD_MODESELECT_1" newline bitfld.long 0x24C 4.--7. "UART3_TXD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x24C 0.--3. "UART3_TXD_MUXMODE,- PR2_PRU1_PRU_R304_13" "UART3_TXD_MUXMODE_0,?,UART3_TXD_MUXMODE_2,UART3_TXD_MUXMODE_3,UART3_TXD_MUXMODE_4,UART3_TXD_MUXMODE_5,?,UART3_TXD_MUXMODE_7,UART3_TXD_MUXMODE_8,?,?,UART3_TXD_MUXMODE_11,UART3_TXD_MUXMODE_12,UART3_TXD_MUXMODE_13,UART3_TXD_MUXMODE_14,?" line.long 0x250 "CTRL_CORE_PAD_RGMII0_TXC," rbitfld.long 0x250 25. "RGMII0_TXC_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXC_WAKEUPEVENT_0,RGMII0_TXC_WAKEUPEVENT_1" newline bitfld.long 0x250 24. "RGMII0_TXC_WAKEUPENABLE,- DISABLE" "RGMII0_TXC_WAKEUPENABLE_0,RGMII0_TXC_WAKEUPENABLE_1" newline bitfld.long 0x250 19. "RGMII0_TXC_SLEWCONTROL,- SLOW_SLEW" "RGMII0_TXC_SLEWCONTROL_0,RGMII0_TXC_SLEWCONTROL_1" newline bitfld.long 0x250 18. "RGMII0_TXC_INPUTENABLE,- DISABLE" "RGMII0_TXC_INPUTENABLE_0,RGMII0_TXC_INPUTENABLE_1" newline bitfld.long 0x250 17. "RGMII0_TXC_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXC_PULLTYPESELECT_0,RGMII0_TXC_PULLTYPESELECT_1" newline bitfld.long 0x250 16. "RGMII0_TXC_PULLUDENABLE,- DISABLE" "RGMII0_TXC_PULLUDENABLE_0,RGMII0_TXC_PULLUDENABLE_1" newline bitfld.long 0x250 8. "RGMII0_TXC_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_TXC_MODESELECT_0,RGMII0_TXC_MODESELECT_1" newline bitfld.long 0x250 4.--7. "RGMII0_TXC_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x250 0.--3. "RGMII0_TXC_MUXMODE,- PR2_PRU1_PRU_R305_13" "RGMII0_TXC_MUXMODE_0,RGMII0_TXC_MUXMODE_1,RGMII0_TXC_MUXMODE_2,RGMII0_TXC_MUXMODE_3,RGMII0_TXC_MUXMODE_4,RGMII0_TXC_MUXMODE_5,RGMII0_TXC_MUXMODE_6,RGMII0_TXC_MUXMODE_7,RGMII0_TXC_MUXMODE_8,?,?,RGMII0_TXC_MUXMODE_11,RGMII0_TXC_MUXMODE_12,RGMII0_TXC_MUXMODE_13,RGMII0_TXC_MUXMODE_14,?" line.long 0x254 "CTRL_CORE_PAD_RGMII0_TXCTL," rbitfld.long 0x254 25. "RGMII0_TXCTL_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXCTL_WAKEUPEVENT_0,RGMII0_TXCTL_WAKEUPEVENT_1" newline bitfld.long 0x254 24. "RGMII0_TXCTL_WAKEUPENABLE,- DISABLE" "RGMII0_TXCTL_WAKEUPENABLE_0,RGMII0_TXCTL_WAKEUPENABLE_1" newline bitfld.long 0x254 19. "RGMII0_TXCTL_SLEWCONTROL,- SLOW_SLEW" "RGMII0_TXCTL_SLEWCONTROL_0,RGMII0_TXCTL_SLEWCONTROL_1" newline bitfld.long 0x254 18. "RGMII0_TXCTL_INPUTENABLE,- DISABLE" "RGMII0_TXCTL_INPUTENABLE_0,RGMII0_TXCTL_INPUTENABLE_1" newline bitfld.long 0x254 17. "RGMII0_TXCTL_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXCTL_PULLTYPESELECT_0,RGMII0_TXCTL_PULLTYPESELECT_1" newline bitfld.long 0x254 16. "RGMII0_TXCTL_PULLUDENABLE,- DISABLE" "RGMII0_TXCTL_PULLUDENABLE_0,RGMII0_TXCTL_PULLUDENABLE_1" newline bitfld.long 0x254 8. "RGMII0_TXCTL_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_TXCTL_MODESELECT_0,RGMII0_TXCTL_MODESELECT_1" newline bitfld.long 0x254 4.--7. "RGMII0_TXCTL_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x254 0.--3. "RGMII0_TXCTL_MUXMODE,- PR2_PRU1_PRU_R306_13" "RGMII0_TXCTL_MUXMODE_0,RGMII0_TXCTL_MUXMODE_1,RGMII0_TXCTL_MUXMODE_2,RGMII0_TXCTL_MUXMODE_3,RGMII0_TXCTL_MUXMODE_4,RGMII0_TXCTL_MUXMODE_5,RGMII0_TXCTL_MUXMODE_6,RGMII0_TXCTL_MUXMODE_7,RGMII0_TXCTL_MUXMODE_8,?,?,RGMII0_TXCTL_MUXMODE_11,RGMII0_TXCTL_MUXMODE_12,RGMII0_TXCTL_MUXMODE_13,RGMII0_TXCTL_MUXMODE_14,?" line.long 0x258 "CTRL_CORE_PAD_RGMII0_TXD3," rbitfld.long 0x258 25. "RGMII0_TXD3_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXD3_WAKEUPEVENT_0,RGMII0_TXD3_WAKEUPEVENT_1" newline bitfld.long 0x258 24. "RGMII0_TXD3_WAKEUPENABLE,- DISABLE" "RGMII0_TXD3_WAKEUPENABLE_0,RGMII0_TXD3_WAKEUPENABLE_1" newline bitfld.long 0x258 19. "RGMII0_TXD3_SLEWCONTROL,- SLOW_SLEW" "RGMII0_TXD3_SLEWCONTROL_0,RGMII0_TXD3_SLEWCONTROL_1" newline bitfld.long 0x258 18. "RGMII0_TXD3_INPUTENABLE,- DISABLE" "RGMII0_TXD3_INPUTENABLE_0,RGMII0_TXD3_INPUTENABLE_1" newline bitfld.long 0x258 17. "RGMII0_TXD3_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXD3_PULLTYPESELECT_0,RGMII0_TXD3_PULLTYPESELECT_1" newline bitfld.long 0x258 16. "RGMII0_TXD3_PULLUDENABLE,- DISABLE" "RGMII0_TXD3_PULLUDENABLE_0,RGMII0_TXD3_PULLUDENABLE_1" newline bitfld.long 0x258 8. "RGMII0_TXD3_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_TXD3_MODESELECT_0,RGMII0_TXD3_MODESELECT_1" newline bitfld.long 0x258 4.--7. "RGMII0_TXD3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x258 0.--3. "RGMII0_TXD3_MUXMODE,- PR2_PRU1_PRU_R307_13" "RGMII0_TXD3_MUXMODE_0,RGMII0_TXD3_MUXMODE_1,?,RGMII0_TXD3_MUXMODE_3,RGMII0_TXD3_MUXMODE_4,RGMII0_TXD3_MUXMODE_5,RGMII0_TXD3_MUXMODE_6,RGMII0_TXD3_MUXMODE_7,RGMII0_TXD3_MUXMODE_8,?,?,RGMII0_TXD3_MUXMODE_11,RGMII0_TXD3_MUXMODE_12,RGMII0_TXD3_MUXMODE_13,RGMII0_TXD3_MUXMODE_14,?" line.long 0x25C "CTRL_CORE_PAD_RGMII0_TXD2," rbitfld.long 0x25C 25. "RGMII0_TXD2_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXD2_WAKEUPEVENT_0,RGMII0_TXD2_WAKEUPEVENT_1" newline bitfld.long 0x25C 24. "RGMII0_TXD2_WAKEUPENABLE,- DISABLE" "RGMII0_TXD2_WAKEUPENABLE_0,RGMII0_TXD2_WAKEUPENABLE_1" newline bitfld.long 0x25C 19. "RGMII0_TXD2_SLEWCONTROL,- SLOW_SLEW" "RGMII0_TXD2_SLEWCONTROL_0,RGMII0_TXD2_SLEWCONTROL_1" newline bitfld.long 0x25C 18. "RGMII0_TXD2_INPUTENABLE,- DISABLE" "RGMII0_TXD2_INPUTENABLE_0,RGMII0_TXD2_INPUTENABLE_1" newline bitfld.long 0x25C 17. "RGMII0_TXD2_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXD2_PULLTYPESELECT_0,RGMII0_TXD2_PULLTYPESELECT_1" newline bitfld.long 0x25C 16. "RGMII0_TXD2_PULLUDENABLE,- DISABLE" "RGMII0_TXD2_PULLUDENABLE_0,RGMII0_TXD2_PULLUDENABLE_1" newline bitfld.long 0x25C 8. "RGMII0_TXD2_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_TXD2_MODESELECT_0,RGMII0_TXD2_MODESELECT_1" newline bitfld.long 0x25C 4.--7. "RGMII0_TXD2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x25C 0.--3. "RGMII0_TXD2_MUXMODE,- PR2_PRU1_PRU_R308_13" "RGMII0_TXD2_MUXMODE_0,RGMII0_TXD2_MUXMODE_1,?,RGMII0_TXD2_MUXMODE_3,RGMII0_TXD2_MUXMODE_4,RGMII0_TXD2_MUXMODE_5,RGMII0_TXD2_MUXMODE_6,RGMII0_TXD2_MUXMODE_7,RGMII0_TXD2_MUXMODE_8,?,?,RGMII0_TXD2_MUXMODE_11,RGMII0_TXD2_MUXMODE_12,RGMII0_TXD2_MUXMODE_13,RGMII0_TXD2_MUXMODE_14,?" line.long 0x260 "CTRL_CORE_PAD_RGMII0_TXD1," rbitfld.long 0x260 25. "RGMII0_TXD1_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXD1_WAKEUPEVENT_0,RGMII0_TXD1_WAKEUPEVENT_1" newline bitfld.long 0x260 24. "RGMII0_TXD1_WAKEUPENABLE,- DISABLE" "RGMII0_TXD1_WAKEUPENABLE_0,RGMII0_TXD1_WAKEUPENABLE_1" newline bitfld.long 0x260 19. "RGMII0_TXD1_SLEWCONTROL,- SLOW_SLEW" "RGMII0_TXD1_SLEWCONTROL_0,RGMII0_TXD1_SLEWCONTROL_1" newline bitfld.long 0x260 18. "RGMII0_TXD1_INPUTENABLE,- DISABLE" "RGMII0_TXD1_INPUTENABLE_0,RGMII0_TXD1_INPUTENABLE_1" newline bitfld.long 0x260 17. "RGMII0_TXD1_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXD1_PULLTYPESELECT_0,RGMII0_TXD1_PULLTYPESELECT_1" newline bitfld.long 0x260 16. "RGMII0_TXD1_PULLUDENABLE,- DISABLE" "RGMII0_TXD1_PULLUDENABLE_0,RGMII0_TXD1_PULLUDENABLE_1" newline bitfld.long 0x260 8. "RGMII0_TXD1_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_TXD1_MODESELECT_0,RGMII0_TXD1_MODESELECT_1" newline bitfld.long 0x260 4.--7. "RGMII0_TXD1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x260 0.--3. "RGMII0_TXD1_MUXMODE,- PR2_PRU1_PRU_R309_13" "RGMII0_TXD1_MUXMODE_0,RGMII0_TXD1_MUXMODE_1,?,RGMII0_TXD1_MUXMODE_3,RGMII0_TXD1_MUXMODE_4,RGMII0_TXD1_MUXMODE_5,RGMII0_TXD1_MUXMODE_6,RGMII0_TXD1_MUXMODE_7,RGMII0_TXD1_MUXMODE_8,?,?,RGMII0_TXD1_MUXMODE_11,RGMII0_TXD1_MUXMODE_12,RGMII0_TXD1_MUXMODE_13,RGMII0_TXD1_MUXMODE_14,?" line.long 0x264 "CTRL_CORE_PAD_RGMII0_TXD0," rbitfld.long 0x264 25. "RGMII0_TXD0_WAKEUPEVENT,- NOWAKEUP" "RGMII0_TXD0_WAKEUPEVENT_0,RGMII0_TXD0_WAKEUPEVENT_1" newline bitfld.long 0x264 24. "RGMII0_TXD0_WAKEUPENABLE,- DISABLE" "RGMII0_TXD0_WAKEUPENABLE_0,RGMII0_TXD0_WAKEUPENABLE_1" newline bitfld.long 0x264 19. "RGMII0_TXD0_SLEWCONTROL,- SLOW_SLEW" "RGMII0_TXD0_SLEWCONTROL_0,RGMII0_TXD0_SLEWCONTROL_1" newline bitfld.long 0x264 18. "RGMII0_TXD0_INPUTENABLE,- DISABLE" "RGMII0_TXD0_INPUTENABLE_0,RGMII0_TXD0_INPUTENABLE_1" newline bitfld.long 0x264 17. "RGMII0_TXD0_PULLTYPESELECT,- PULL_DOWN" "RGMII0_TXD0_PULLTYPESELECT_0,RGMII0_TXD0_PULLTYPESELECT_1" newline bitfld.long 0x264 16. "RGMII0_TXD0_PULLUDENABLE,- DISABLE" "RGMII0_TXD0_PULLUDENABLE_0,RGMII0_TXD0_PULLUDENABLE_1" newline bitfld.long 0x264 8. "RGMII0_TXD0_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_TXD0_MODESELECT_0,RGMII0_TXD0_MODESELECT_1" newline bitfld.long 0x264 4.--7. "RGMII0_TXD0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x264 0.--3. "RGMII0_TXD0_MUXMODE,- PR2_PRU1_PRU_R3010_13" "RGMII0_TXD0_MUXMODE_0,RGMII0_TXD0_MUXMODE_1,?,RGMII0_TXD0_MUXMODE_3,RGMII0_TXD0_MUXMODE_4,?,RGMII0_TXD0_MUXMODE_6,RGMII0_TXD0_MUXMODE_7,RGMII0_TXD0_MUXMODE_8,?,?,RGMII0_TXD0_MUXMODE_11,RGMII0_TXD0_MUXMODE_12,RGMII0_TXD0_MUXMODE_13,RGMII0_TXD0_MUXMODE_14,?" line.long 0x268 "CTRL_CORE_PAD_RGMII0_RXC," rbitfld.long 0x268 25. "RGMII0_RXC_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXC_WAKEUPEVENT_0,RGMII0_RXC_WAKEUPEVENT_1" newline bitfld.long 0x268 24. "RGMII0_RXC_WAKEUPENABLE,- DISABLE" "RGMII0_RXC_WAKEUPENABLE_0,RGMII0_RXC_WAKEUPENABLE_1" newline bitfld.long 0x268 19. "RGMII0_RXC_SLEWCONTROL,- SLOW_SLEW" "RGMII0_RXC_SLEWCONTROL_0,RGMII0_RXC_SLEWCONTROL_1" newline bitfld.long 0x268 18. "RGMII0_RXC_INPUTENABLE,- DISABLE" "RGMII0_RXC_INPUTENABLE_0,RGMII0_RXC_INPUTENABLE_1" newline bitfld.long 0x268 17. "RGMII0_RXC_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXC_PULLTYPESELECT_0,RGMII0_RXC_PULLTYPESELECT_1" newline bitfld.long 0x268 16. "RGMII0_RXC_PULLUDENABLE,- DISABLE" "RGMII0_RXC_PULLUDENABLE_0,RGMII0_RXC_PULLUDENABLE_1" newline bitfld.long 0x268 8. "RGMII0_RXC_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_RXC_MODESELECT_0,RGMII0_RXC_MODESELECT_1" newline bitfld.long 0x268 4.--7. "RGMII0_RXC_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x268 0.--3. "RGMII0_RXC_MUXMODE,- PR2_PRU1_PRU_R3011_13" "RGMII0_RXC_MUXMODE_0,?,RGMII0_RXC_MUXMODE_2,RGMII0_RXC_MUXMODE_3,RGMII0_RXC_MUXMODE_4,RGMII0_RXC_MUXMODE_5,RGMII0_RXC_MUXMODE_6,?,?,?,?,RGMII0_RXC_MUXMODE_11,RGMII0_RXC_MUXMODE_12,RGMII0_RXC_MUXMODE_13,RGMII0_RXC_MUXMODE_14,?" line.long 0x26C "CTRL_CORE_PAD_RGMII0_RXCTL," rbitfld.long 0x26C 25. "RGMII0_RXCTL_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXCTL_WAKEUPEVENT_0,RGMII0_RXCTL_WAKEUPEVENT_1" newline bitfld.long 0x26C 24. "RGMII0_RXCTL_WAKEUPENABLE,- DISABLE" "RGMII0_RXCTL_WAKEUPENABLE_0,RGMII0_RXCTL_WAKEUPENABLE_1" newline bitfld.long 0x26C 19. "RGMII0_RXCTL_SLEWCONTROL,- SLOW_SLEW" "RGMII0_RXCTL_SLEWCONTROL_0,RGMII0_RXCTL_SLEWCONTROL_1" newline bitfld.long 0x26C 18. "RGMII0_RXCTL_INPUTENABLE,- DISABLE" "RGMII0_RXCTL_INPUTENABLE_0,RGMII0_RXCTL_INPUTENABLE_1" newline bitfld.long 0x26C 17. "RGMII0_RXCTL_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXCTL_PULLTYPESELECT_0,RGMII0_RXCTL_PULLTYPESELECT_1" newline bitfld.long 0x26C 16. "RGMII0_RXCTL_PULLUDENABLE,- DISABLE" "RGMII0_RXCTL_PULLUDENABLE_0,RGMII0_RXCTL_PULLUDENABLE_1" newline bitfld.long 0x26C 8. "RGMII0_RXCTL_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_RXCTL_MODESELECT_0,RGMII0_RXCTL_MODESELECT_1" newline bitfld.long 0x26C 4.--7. "RGMII0_RXCTL_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x26C 0.--3. "RGMII0_RXCTL_MUXMODE,- PR2_PRU1_PRU_R3012_13" "RGMII0_RXCTL_MUXMODE_0,?,RGMII0_RXCTL_MUXMODE_2,RGMII0_RXCTL_MUXMODE_3,RGMII0_RXCTL_MUXMODE_4,RGMII0_RXCTL_MUXMODE_5,RGMII0_RXCTL_MUXMODE_6,?,?,?,?,RGMII0_RXCTL_MUXMODE_11,RGMII0_RXCTL_MUXMODE_12,RGMII0_RXCTL_MUXMODE_13,RGMII0_RXCTL_MUXMODE_14,?" line.long 0x270 "CTRL_CORE_PAD_RGMII0_RXD3," rbitfld.long 0x270 25. "RGMII0_RXD3_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXD3_WAKEUPEVENT_0,RGMII0_RXD3_WAKEUPEVENT_1" newline bitfld.long 0x270 24. "RGMII0_RXD3_WAKEUPENABLE,- DISABLE" "RGMII0_RXD3_WAKEUPENABLE_0,RGMII0_RXD3_WAKEUPENABLE_1" newline bitfld.long 0x270 19. "RGMII0_RXD3_SLEWCONTROL,- SLOW_SLEW" "RGMII0_RXD3_SLEWCONTROL_0,RGMII0_RXD3_SLEWCONTROL_1" newline bitfld.long 0x270 18. "RGMII0_RXD3_INPUTENABLE,- DISABLE" "RGMII0_RXD3_INPUTENABLE_0,RGMII0_RXD3_INPUTENABLE_1" newline bitfld.long 0x270 17. "RGMII0_RXD3_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXD3_PULLTYPESELECT_0,RGMII0_RXD3_PULLTYPESELECT_1" newline bitfld.long 0x270 16. "RGMII0_RXD3_PULLUDENABLE,- DISABLE" "RGMII0_RXD3_PULLUDENABLE_0,RGMII0_RXD3_PULLUDENABLE_1" newline bitfld.long 0x270 8. "RGMII0_RXD3_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_RXD3_MODESELECT_0,RGMII0_RXD3_MODESELECT_1" newline bitfld.long 0x270 4.--7. "RGMII0_RXD3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x270 0.--3. "RGMII0_RXD3_MUXMODE,- PR2_PRU1_PRU_R3013_13" "RGMII0_RXD3_MUXMODE_0,?,RGMII0_RXD3_MUXMODE_2,RGMII0_RXD3_MUXMODE_3,RGMII0_RXD3_MUXMODE_4,RGMII0_RXD3_MUXMODE_5,RGMII0_RXD3_MUXMODE_6,?,?,?,?,RGMII0_RXD3_MUXMODE_11,RGMII0_RXD3_MUXMODE_12,RGMII0_RXD3_MUXMODE_13,RGMII0_RXD3_MUXMODE_14,?" line.long 0x274 "CTRL_CORE_PAD_RGMII0_RXD2," rbitfld.long 0x274 25. "RGMII0_RXD2_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXD2_WAKEUPEVENT_0,RGMII0_RXD2_WAKEUPEVENT_1" newline bitfld.long 0x274 24. "RGMII0_RXD2_WAKEUPENABLE,- DISABLE" "RGMII0_RXD2_WAKEUPENABLE_0,RGMII0_RXD2_WAKEUPENABLE_1" newline bitfld.long 0x274 19. "RGMII0_RXD2_SLEWCONTROL,- SLOW_SLEW" "RGMII0_RXD2_SLEWCONTROL_0,RGMII0_RXD2_SLEWCONTROL_1" newline bitfld.long 0x274 18. "RGMII0_RXD2_INPUTENABLE,- DISABLE" "RGMII0_RXD2_INPUTENABLE_0,RGMII0_RXD2_INPUTENABLE_1" newline bitfld.long 0x274 17. "RGMII0_RXD2_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXD2_PULLTYPESELECT_0,RGMII0_RXD2_PULLTYPESELECT_1" newline bitfld.long 0x274 16. "RGMII0_RXD2_PULLUDENABLE,- DISABLE" "RGMII0_RXD2_PULLUDENABLE_0,RGMII0_RXD2_PULLUDENABLE_1" newline bitfld.long 0x274 8. "RGMII0_RXD2_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_RXD2_MODESELECT_0,RGMII0_RXD2_MODESELECT_1" newline bitfld.long 0x274 4.--7. "RGMII0_RXD2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x274 0.--3. "RGMII0_RXD2_MUXMODE,- PR2_PRU1_PRU_R3014_13" "RGMII0_RXD2_MUXMODE_0,RGMII0_RXD2_MUXMODE_1,?,RGMII0_RXD2_MUXMODE_3,RGMII0_RXD2_MUXMODE_4,?,RGMII0_RXD2_MUXMODE_6,?,?,?,?,RGMII0_RXD2_MUXMODE_11,RGMII0_RXD2_MUXMODE_12,RGMII0_RXD2_MUXMODE_13,RGMII0_RXD2_MUXMODE_14,?" line.long 0x278 "CTRL_CORE_PAD_RGMII0_RXD1," rbitfld.long 0x278 25. "RGMII0_RXD1_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXD1_WAKEUPEVENT_0,RGMII0_RXD1_WAKEUPEVENT_1" newline bitfld.long 0x278 24. "RGMII0_RXD1_WAKEUPENABLE,- DISABLE" "RGMII0_RXD1_WAKEUPENABLE_0,RGMII0_RXD1_WAKEUPENABLE_1" newline bitfld.long 0x278 19. "RGMII0_RXD1_SLEWCONTROL,- SLOW_SLEW" "RGMII0_RXD1_SLEWCONTROL_0,RGMII0_RXD1_SLEWCONTROL_1" newline bitfld.long 0x278 18. "RGMII0_RXD1_INPUTENABLE,- DISABLE" "RGMII0_RXD1_INPUTENABLE_0,RGMII0_RXD1_INPUTENABLE_1" newline bitfld.long 0x278 17. "RGMII0_RXD1_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXD1_PULLTYPESELECT_0,RGMII0_RXD1_PULLTYPESELECT_1" newline bitfld.long 0x278 16. "RGMII0_RXD1_PULLUDENABLE,- DISABLE" "RGMII0_RXD1_PULLUDENABLE_0,RGMII0_RXD1_PULLUDENABLE_1" newline bitfld.long 0x278 8. "RGMII0_RXD1_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_RXD1_MODESELECT_0,RGMII0_RXD1_MODESELECT_1" newline bitfld.long 0x278 4.--7. "RGMII0_RXD1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x278 0.--3. "RGMII0_RXD1_MUXMODE,- PR2_PRU1_PRU_R3015_13" "RGMII0_RXD1_MUXMODE_0,RGMII0_RXD1_MUXMODE_1,?,RGMII0_RXD1_MUXMODE_3,RGMII0_RXD1_MUXMODE_4,?,RGMII0_RXD1_MUXMODE_6,?,?,?,?,RGMII0_RXD1_MUXMODE_11,RGMII0_RXD1_MUXMODE_12,RGMII0_RXD1_MUXMODE_13,RGMII0_RXD1_MUXMODE_14,?" line.long 0x27C "CTRL_CORE_PAD_RGMII0_RXD0," rbitfld.long 0x27C 25. "RGMII0_RXD0_WAKEUPEVENT,- NOWAKEUP" "RGMII0_RXD0_WAKEUPEVENT_0,RGMII0_RXD0_WAKEUPEVENT_1" newline bitfld.long 0x27C 24. "RGMII0_RXD0_WAKEUPENABLE,- DISABLE" "RGMII0_RXD0_WAKEUPENABLE_0,RGMII0_RXD0_WAKEUPENABLE_1" newline bitfld.long 0x27C 19. "RGMII0_RXD0_SLEWCONTROL,- SLOW_SLEW" "RGMII0_RXD0_SLEWCONTROL_0,RGMII0_RXD0_SLEWCONTROL_1" newline bitfld.long 0x27C 18. "RGMII0_RXD0_INPUTENABLE,- DISABLE" "RGMII0_RXD0_INPUTENABLE_0,RGMII0_RXD0_INPUTENABLE_1" newline bitfld.long 0x27C 17. "RGMII0_RXD0_PULLTYPESELECT,- PULL_DOWN" "RGMII0_RXD0_PULLTYPESELECT_0,RGMII0_RXD0_PULLTYPESELECT_1" newline bitfld.long 0x27C 16. "RGMII0_RXD0_PULLUDENABLE,- DISABLE" "RGMII0_RXD0_PULLUDENABLE_0,RGMII0_RXD0_PULLUDENABLE_1" newline bitfld.long 0x27C 8. "RGMII0_RXD0_MODESELECT,Selects between default and another IO delay different than the default one" "RGMII0_RXD0_MODESELECT_0,RGMII0_RXD0_MODESELECT_1" newline bitfld.long 0x27C 4.--7. "RGMII0_RXD0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x27C 0.--3. "RGMII0_RXD0_MUXMODE,- PR2_PRU1_PRU_R3016_13" "RGMII0_RXD0_MUXMODE_0,RGMII0_RXD0_MUXMODE_1,?,RGMII0_RXD0_MUXMODE_3,RGMII0_RXD0_MUXMODE_4,RGMII0_RXD0_MUXMODE_5,RGMII0_RXD0_MUXMODE_6,?,?,?,?,RGMII0_RXD0_MUXMODE_11,RGMII0_RXD0_MUXMODE_12,RGMII0_RXD0_MUXMODE_13,RGMII0_RXD0_MUXMODE_14,?" line.long 0x280 "CTRL_CORE_PAD_USB1_DRVVBUS," rbitfld.long 0x280 25. "USB1_DRVVBUS_WAKEUPEVENT,- NOWAKEUP" "USB1_DRVVBUS_WAKEUPEVENT_0,USB1_DRVVBUS_WAKEUPEVENT_1" newline bitfld.long 0x280 24. "USB1_DRVVBUS_WAKEUPENABLE,- DISABLE" "USB1_DRVVBUS_WAKEUPENABLE_0,USB1_DRVVBUS_WAKEUPENABLE_1" newline bitfld.long 0x280 19. "USB1_DRVVBUS_SLEWCONTROL,- SLOW_SLEW" "USB1_DRVVBUS_SLEWCONTROL_0,USB1_DRVVBUS_SLEWCONTROL_1" newline bitfld.long 0x280 18. "USB1_DRVVBUS_INPUTENABLE,- DISABLE" "USB1_DRVVBUS_INPUTENABLE_0,USB1_DRVVBUS_INPUTENABLE_1" newline bitfld.long 0x280 17. "USB1_DRVVBUS_PULLTYPESELECT,- PULL_DOWN" "USB1_DRVVBUS_PULLTYPESELECT_0,USB1_DRVVBUS_PULLTYPESELECT_1" newline bitfld.long 0x280 16. "USB1_DRVVBUS_PULLUDENABLE,- DISABLE" "USB1_DRVVBUS_PULLUDENABLE_0,USB1_DRVVBUS_PULLUDENABLE_1" newline bitfld.long 0x280 8. "USB1_DRVVBUS_MODESELECT,Selects between default and another IO delay different than the default one" "USB1_DRVVBUS_MODESELECT_0,USB1_DRVVBUS_MODESELECT_1" newline bitfld.long 0x280 4.--7. "USB1_DRVVBUS_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x280 0.--3. "USB1_DRVVBUS_MUXMODE,- USB1_DRVVBUS_0" "USB1_DRVVBUS_MUXMODE_0,?,?,?,?,?,?,USB1_DRVVBUS_MUXMODE_7,?,?,?,?,?,?,USB1_DRVVBUS_MUXMODE_14,?" line.long 0x284 "CTRL_CORE_PAD_USB2_DRVVBUS," rbitfld.long 0x284 25. "USB2_DRVVBUS_WAKEUPEVENT,- NOWAKEUP" "USB2_DRVVBUS_WAKEUPEVENT_0,USB2_DRVVBUS_WAKEUPEVENT_1" newline bitfld.long 0x284 24. "USB2_DRVVBUS_WAKEUPENABLE,- DISABLE" "USB2_DRVVBUS_WAKEUPENABLE_0,USB2_DRVVBUS_WAKEUPENABLE_1" newline bitfld.long 0x284 19. "USB2_DRVVBUS_SLEWCONTROL,- SLOW_SLEW" "USB2_DRVVBUS_SLEWCONTROL_0,USB2_DRVVBUS_SLEWCONTROL_1" newline bitfld.long 0x284 18. "USB2_DRVVBUS_INPUTENABLE,- DISABLE" "USB2_DRVVBUS_INPUTENABLE_0,USB2_DRVVBUS_INPUTENABLE_1" newline bitfld.long 0x284 17. "USB2_DRVVBUS_PULLTYPESELECT,- PULL_DOWN" "USB2_DRVVBUS_PULLTYPESELECT_0,USB2_DRVVBUS_PULLTYPESELECT_1" newline bitfld.long 0x284 16. "USB2_DRVVBUS_PULLUDENABLE,- DISABLE" "USB2_DRVVBUS_PULLUDENABLE_0,USB2_DRVVBUS_PULLUDENABLE_1" newline bitfld.long 0x284 8. "USB2_DRVVBUS_MODESELECT,Selects between default and another IO delay different than the default one" "USB2_DRVVBUS_MODESELECT_0,USB2_DRVVBUS_MODESELECT_1" newline bitfld.long 0x284 4.--7. "USB2_DRVVBUS_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x284 0.--3. "USB2_DRVVBUS_MUXMODE,- USB2_DRVVBUS_0" "USB2_DRVVBUS_MUXMODE_0,?,?,?,?,?,?,USB2_DRVVBUS_MUXMODE_7,?,?,?,?,?,?,USB2_DRVVBUS_MUXMODE_14,?" line.long 0x288 "CTRL_CORE_PAD_GPIO6_14," rbitfld.long 0x288 25. "GPIO6_14_WAKEUPEVENT,- NOWAKEUP" "GPIO6_14_WAKEUPEVENT_0,GPIO6_14_WAKEUPEVENT_1" newline bitfld.long 0x288 24. "GPIO6_14_WAKEUPENABLE,- DISABLE" "GPIO6_14_WAKEUPENABLE_0,GPIO6_14_WAKEUPENABLE_1" newline bitfld.long 0x288 19. "GPIO6_14_SLEWCONTROL,- SLOW_SLEW" "GPIO6_14_SLEWCONTROL_0,GPIO6_14_SLEWCONTROL_1" newline bitfld.long 0x288 18. "GPIO6_14_INPUTENABLE,- DISABLE" "GPIO6_14_INPUTENABLE_0,GPIO6_14_INPUTENABLE_1" newline bitfld.long 0x288 17. "GPIO6_14_PULLTYPESELECT,- PULL_DOWN" "GPIO6_14_PULLTYPESELECT_0,GPIO6_14_PULLTYPESELECT_1" newline bitfld.long 0x288 16. "GPIO6_14_PULLUDENABLE,- DISABLE" "GPIO6_14_PULLUDENABLE_0,GPIO6_14_PULLUDENABLE_1" newline bitfld.long 0x288 8. "GPIO6_14_MODESELECT,Selects between default and another IO delay different than the default one" "GPIO6_14_MODESELECT_0,GPIO6_14_MODESELECT_1" newline bitfld.long 0x288 4.--7. "GPIO6_14_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x288 0.--3. "GPIO6_14_MUXMODE,- VOUT2_HSYNC_6" "GPIO6_14_MUXMODE_0,GPIO6_14_MUXMODE_1,GPIO6_14_MUXMODE_2,GPIO6_14_MUXMODE_3,?,?,GPIO6_14_MUXMODE_6,?,GPIO6_14_MUXMODE_8,GPIO6_14_MUXMODE_9,GPIO6_14_MUXMODE_10,?,?,?,GPIO6_14_MUXMODE_14,?" line.long 0x28C "CTRL_CORE_PAD_GPIO6_15," rbitfld.long 0x28C 25. "GPIO6_15_WAKEUPEVENT,- NOWAKEUP" "GPIO6_15_WAKEUPEVENT_0,GPIO6_15_WAKEUPEVENT_1" newline bitfld.long 0x28C 24. "GPIO6_15_WAKEUPENABLE,- DISABLE" "GPIO6_15_WAKEUPENABLE_0,GPIO6_15_WAKEUPENABLE_1" newline bitfld.long 0x28C 19. "GPIO6_15_SLEWCONTROL,- SLOW_SLEW" "GPIO6_15_SLEWCONTROL_0,GPIO6_15_SLEWCONTROL_1" newline bitfld.long 0x28C 18. "GPIO6_15_INPUTENABLE,- DISABLE" "GPIO6_15_INPUTENABLE_0,GPIO6_15_INPUTENABLE_1" newline bitfld.long 0x28C 17. "GPIO6_15_PULLTYPESELECT,- PULL_DOWN" "GPIO6_15_PULLTYPESELECT_0,GPIO6_15_PULLTYPESELECT_1" newline bitfld.long 0x28C 16. "GPIO6_15_PULLUDENABLE,- DISABLE" "GPIO6_15_PULLUDENABLE_0,GPIO6_15_PULLUDENABLE_1" newline bitfld.long 0x28C 8. "GPIO6_15_MODESELECT,Selects between default and another IO delay different than the default one" "GPIO6_15_MODESELECT_0,GPIO6_15_MODESELECT_1" newline bitfld.long 0x28C 4.--7. "GPIO6_15_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28C 0.--3. "GPIO6_15_MUXMODE,- VOUT2_VSYNC_6" "GPIO6_15_MUXMODE_0,GPIO6_15_MUXMODE_1,GPIO6_15_MUXMODE_2,GPIO6_15_MUXMODE_3,?,?,GPIO6_15_MUXMODE_6,?,GPIO6_15_MUXMODE_8,GPIO6_15_MUXMODE_9,GPIO6_15_MUXMODE_10,?,?,?,GPIO6_15_MUXMODE_14,?" line.long 0x290 "CTRL_CORE_PAD_GPIO6_16," rbitfld.long 0x290 25. "GPIO6_16_WAKEUPEVENT,- NOWAKEUP" "GPIO6_16_WAKEUPEVENT_0,GPIO6_16_WAKEUPEVENT_1" newline bitfld.long 0x290 24. "GPIO6_16_WAKEUPENABLE,- DISABLE" "GPIO6_16_WAKEUPENABLE_0,GPIO6_16_WAKEUPENABLE_1" newline bitfld.long 0x290 19. "GPIO6_16_SLEWCONTROL,- SLOW_SLEW" "GPIO6_16_SLEWCONTROL_0,GPIO6_16_SLEWCONTROL_1" newline bitfld.long 0x290 18. "GPIO6_16_INPUTENABLE,- DISABLE" "GPIO6_16_INPUTENABLE_0,GPIO6_16_INPUTENABLE_1" newline bitfld.long 0x290 17. "GPIO6_16_PULLTYPESELECT,- PULL_DOWN" "GPIO6_16_PULLTYPESELECT_0,GPIO6_16_PULLTYPESELECT_1" newline bitfld.long 0x290 16. "GPIO6_16_PULLUDENABLE,- DISABLE" "GPIO6_16_PULLUDENABLE_0,GPIO6_16_PULLUDENABLE_1" newline bitfld.long 0x290 8. "GPIO6_16_MODESELECT,Selects between default and another IO delay different than the default one" "GPIO6_16_MODESELECT_0,GPIO6_16_MODESELECT_1" newline bitfld.long 0x290 4.--7. "GPIO6_16_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x290 0.--3. "GPIO6_16_MUXMODE,- VOUT2_FLD_6" "GPIO6_16_MUXMODE_0,GPIO6_16_MUXMODE_1,?,?,?,?,GPIO6_16_MUXMODE_6,?,GPIO6_16_MUXMODE_8,GPIO6_16_MUXMODE_9,GPIO6_16_MUXMODE_10,?,?,?,GPIO6_16_MUXMODE_14,?" line.long 0x294 "CTRL_CORE_PAD_XREF_CLK0," rbitfld.long 0x294 25. "XREF_CLK0_WAKEUPEVENT,- NOWAKEUP" "XREF_CLK0_WAKEUPEVENT_0,XREF_CLK0_WAKEUPEVENT_1" newline bitfld.long 0x294 24. "XREF_CLK0_WAKEUPENABLE,- DISABLE" "XREF_CLK0_WAKEUPENABLE_0,XREF_CLK0_WAKEUPENABLE_1" newline bitfld.long 0x294 19. "XREF_CLK0_SLEWCONTROL,- SLOW_SLEW" "XREF_CLK0_SLEWCONTROL_0,XREF_CLK0_SLEWCONTROL_1" newline bitfld.long 0x294 18. "XREF_CLK0_INPUTENABLE,- DISABLE" "XREF_CLK0_INPUTENABLE_0,XREF_CLK0_INPUTENABLE_1" newline bitfld.long 0x294 17. "XREF_CLK0_PULLTYPESELECT,- PULL_DOWN" "XREF_CLK0_PULLTYPESELECT_0,XREF_CLK0_PULLTYPESELECT_1" newline bitfld.long 0x294 16. "XREF_CLK0_PULLUDENABLE,- DISABLE" "XREF_CLK0_PULLUDENABLE_0,XREF_CLK0_PULLUDENABLE_1" newline bitfld.long 0x294 8. "XREF_CLK0_MODESELECT,Selects between default and another IO delay different than the default one" "XREF_CLK0_MODESELECT_0,XREF_CLK0_MODESELECT_1" newline bitfld.long 0x294 4.--7. "XREF_CLK0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x294 0.--3. "XREF_CLK0_MUXMODE,- PR2_PRU1_PRU_R305_13" "XREF_CLK0_MUXMODE_0,XREF_CLK0_MUXMODE_1,XREF_CLK0_MUXMODE_2,XREF_CLK0_MUXMODE_3,XREF_CLK0_MUXMODE_4,XREF_CLK0_MUXMODE_5,?,XREF_CLK0_MUXMODE_7,XREF_CLK0_MUXMODE_8,XREF_CLK0_MUXMODE_9,XREF_CLK0_MUXMODE_10,XREF_CLK0_MUXMODE_11,XREF_CLK0_MUXMODE_12,XREF_CLK0_MUXMODE_13,XREF_CLK0_MUXMODE_14,?" line.long 0x298 "CTRL_CORE_PAD_XREF_CLK1," rbitfld.long 0x298 25. "XREF_CLK1_WAKEUPEVENT,- NOWAKEUP" "XREF_CLK1_WAKEUPEVENT_0,XREF_CLK1_WAKEUPEVENT_1" newline bitfld.long 0x298 24. "XREF_CLK1_WAKEUPENABLE,- DISABLE" "XREF_CLK1_WAKEUPENABLE_0,XREF_CLK1_WAKEUPENABLE_1" newline bitfld.long 0x298 19. "XREF_CLK1_SLEWCONTROL,- SLOW_SLEW" "XREF_CLK1_SLEWCONTROL_0,XREF_CLK1_SLEWCONTROL_1" newline bitfld.long 0x298 18. "XREF_CLK1_INPUTENABLE,- DISABLE" "XREF_CLK1_INPUTENABLE_0,XREF_CLK1_INPUTENABLE_1" newline bitfld.long 0x298 17. "XREF_CLK1_PULLTYPESELECT,- PULL_DOWN" "XREF_CLK1_PULLTYPESELECT_0,XREF_CLK1_PULLTYPESELECT_1" newline bitfld.long 0x298 16. "XREF_CLK1_PULLUDENABLE,- DISABLE" "XREF_CLK1_PULLUDENABLE_0,XREF_CLK1_PULLUDENABLE_1" newline bitfld.long 0x298 8. "XREF_CLK1_MODESELECT,Selects between default and another IO delay different than the default one" "XREF_CLK1_MODESELECT_0,XREF_CLK1_MODESELECT_1" newline bitfld.long 0x298 4.--7. "XREF_CLK1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x298 0.--3. "XREF_CLK1_MUXMODE,- PR2_PRU1_PRU_R306_13" "XREF_CLK1_MUXMODE_0,XREF_CLK1_MUXMODE_1,XREF_CLK1_MUXMODE_2,XREF_CLK1_MUXMODE_3,XREF_CLK1_MUXMODE_4,XREF_CLK1_MUXMODE_5,?,XREF_CLK1_MUXMODE_7,?,?,XREF_CLK1_MUXMODE_10,XREF_CLK1_MUXMODE_11,XREF_CLK1_MUXMODE_12,XREF_CLK1_MUXMODE_13,XREF_CLK1_MUXMODE_14,?" line.long 0x29C "CTRL_CORE_PAD_XREF_CLK2," rbitfld.long 0x29C 25. "XREF_CLK2_WAKEUPEVENT,- NOWAKEUP" "XREF_CLK2_WAKEUPEVENT_0,XREF_CLK2_WAKEUPEVENT_1" newline bitfld.long 0x29C 24. "XREF_CLK2_WAKEUPENABLE,- DISABLE" "XREF_CLK2_WAKEUPENABLE_0,XREF_CLK2_WAKEUPENABLE_1" newline bitfld.long 0x29C 19. "XREF_CLK2_SLEWCONTROL,- SLOW_SLEW" "XREF_CLK2_SLEWCONTROL_0,XREF_CLK2_SLEWCONTROL_1" newline bitfld.long 0x29C 18. "XREF_CLK2_INPUTENABLE,- DISABLE" "XREF_CLK2_INPUTENABLE_0,XREF_CLK2_INPUTENABLE_1" newline bitfld.long 0x29C 17. "XREF_CLK2_PULLTYPESELECT,- PULL_DOWN" "XREF_CLK2_PULLTYPESELECT_0,XREF_CLK2_PULLTYPESELECT_1" newline bitfld.long 0x29C 16. "XREF_CLK2_PULLUDENABLE,- DISABLE" "XREF_CLK2_PULLUDENABLE_0,XREF_CLK2_PULLUDENABLE_1" newline bitfld.long 0x29C 8. "XREF_CLK2_MODESELECT,Selects between default and another IO delay different than the default one" "XREF_CLK2_MODESELECT_0,XREF_CLK2_MODESELECT_1" newline bitfld.long 0x29C 4.--7. "XREF_CLK2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x29C 0.--3. "XREF_CLK2_MUXMODE,- VOUT2_CLK_6" "XREF_CLK2_MUXMODE_0,XREF_CLK2_MUXMODE_1,XREF_CLK2_MUXMODE_2,XREF_CLK2_MUXMODE_3,XREF_CLK2_MUXMODE_4,XREF_CLK2_MUXMODE_5,XREF_CLK2_MUXMODE_6,?,XREF_CLK2_MUXMODE_8,?,XREF_CLK2_MUXMODE_10,?,?,?,XREF_CLK2_MUXMODE_14,?" line.long 0x2A0 "CTRL_CORE_PAD_XREF_CLK3," rbitfld.long 0x2A0 25. "XREF_CLK3_WAKEUPEVENT,- NOWAKEUP" "XREF_CLK3_WAKEUPEVENT_0,XREF_CLK3_WAKEUPEVENT_1" newline bitfld.long 0x2A0 24. "XREF_CLK3_WAKEUPENABLE,- DISABLE" "XREF_CLK3_WAKEUPENABLE_0,XREF_CLK3_WAKEUPENABLE_1" newline bitfld.long 0x2A0 19. "XREF_CLK3_SLEWCONTROL,- SLOW_SLEW" "XREF_CLK3_SLEWCONTROL_0,XREF_CLK3_SLEWCONTROL_1" newline bitfld.long 0x2A0 18. "XREF_CLK3_INPUTENABLE,- DISABLE" "XREF_CLK3_INPUTENABLE_0,XREF_CLK3_INPUTENABLE_1" newline bitfld.long 0x2A0 17. "XREF_CLK3_PULLTYPESELECT,- PULL_DOWN" "XREF_CLK3_PULLTYPESELECT_0,XREF_CLK3_PULLTYPESELECT_1" newline bitfld.long 0x2A0 16. "XREF_CLK3_PULLUDENABLE,- DISABLE" "XREF_CLK3_PULLUDENABLE_0,XREF_CLK3_PULLUDENABLE_1" newline bitfld.long 0x2A0 8. "XREF_CLK3_MODESELECT,Selects between default and another IO delay different than the default one" "XREF_CLK3_MODESELECT_0,XREF_CLK3_MODESELECT_1" newline bitfld.long 0x2A0 4.--7. "XREF_CLK3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2A0 0.--3. "XREF_CLK3_MUXMODE,- VOUT2_DE_6" "XREF_CLK3_MUXMODE_0,XREF_CLK3_MUXMODE_1,XREF_CLK3_MUXMODE_2,XREF_CLK3_MUXMODE_3,XREF_CLK3_MUXMODE_4,XREF_CLK3_MUXMODE_5,XREF_CLK3_MUXMODE_6,XREF_CLK3_MUXMODE_7,XREF_CLK3_MUXMODE_8,XREF_CLK3_MUXMODE_9,XREF_CLK3_MUXMODE_10,?,?,?,XREF_CLK3_MUXMODE_14,?" line.long 0x2A4 "CTRL_CORE_PAD_MCASP1_ACLKX," rbitfld.long 0x2A4 25. "MCASP1_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP1_ACLKX_WAKEUPEVENT_0,MCASP1_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x2A4 24. "MCASP1_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP1_ACLKX_WAKEUPENABLE_0,MCASP1_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x2A4 19. "MCASP1_ACLKX_SLEWCONTROL,- SLOW_SLEW" "MCASP1_ACLKX_SLEWCONTROL_0,MCASP1_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x2A4 18. "MCASP1_ACLKX_INPUTENABLE,- DISABLE" "MCASP1_ACLKX_INPUTENABLE_0,MCASP1_ACLKX_INPUTENABLE_1" newline bitfld.long 0x2A4 17. "MCASP1_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP1_ACLKX_PULLTYPESELECT_0,MCASP1_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x2A4 16. "MCASP1_ACLKX_PULLUDENABLE,- DISABLE" "MCASP1_ACLKX_PULLUDENABLE_0,MCASP1_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x2A4 8. "MCASP1_ACLKX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_ACLKX_MODESELECT_0,MCASP1_ACLKX_MODESELECT_1" newline bitfld.long 0x2A4 4.--7. "MCASP1_ACLKX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2A4 0.--3. "MCASP1_ACLKX_MUXMODE,- PR2_PRU1_PRU_R307_13" "MCASP1_ACLKX_MUXMODE_0,?,?,?,?,?,?,MCASP1_ACLKX_MUXMODE_7,?,?,MCASP1_ACLKX_MUXMODE_10,MCASP1_ACLKX_MUXMODE_11,MCASP1_ACLKX_MUXMODE_12,MCASP1_ACLKX_MUXMODE_13,MCASP1_ACLKX_MUXMODE_14,?" line.long 0x2A8 "CTRL_CORE_PAD_MCASP1_FSX," rbitfld.long 0x2A8 25. "MCASP1_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP1_FSX_WAKEUPEVENT_0,MCASP1_FSX_WAKEUPEVENT_1" newline bitfld.long 0x2A8 24. "MCASP1_FSX_WAKEUPENABLE,- DISABLE" "MCASP1_FSX_WAKEUPENABLE_0,MCASP1_FSX_WAKEUPENABLE_1" newline bitfld.long 0x2A8 19. "MCASP1_FSX_SLEWCONTROL,- SLOW_SLEW" "MCASP1_FSX_SLEWCONTROL_0,MCASP1_FSX_SLEWCONTROL_1" newline bitfld.long 0x2A8 18. "MCASP1_FSX_INPUTENABLE,- DISABLE" "MCASP1_FSX_INPUTENABLE_0,MCASP1_FSX_INPUTENABLE_1" newline bitfld.long 0x2A8 17. "MCASP1_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP1_FSX_PULLTYPESELECT_0,MCASP1_FSX_PULLTYPESELECT_1" newline bitfld.long 0x2A8 16. "MCASP1_FSX_PULLUDENABLE,- DISABLE" "MCASP1_FSX_PULLUDENABLE_0,MCASP1_FSX_PULLUDENABLE_1" newline bitfld.long 0x2A8 8. "MCASP1_FSX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_FSX_MODESELECT_0,MCASP1_FSX_MODESELECT_1" newline bitfld.long 0x2A8 4.--7. "MCASP1_FSX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2A8 0.--3. "MCASP1_FSX_MUXMODE,- MCASP1_FSX_0" "MCASP1_FSX_MUXMODE_0,?,?,?,?,?,?,MCASP1_FSX_MUXMODE_7,?,?,MCASP1_FSX_MUXMODE_10,MCASP1_FSX_MUXMODE_11,?,?,MCASP1_FSX_MUXMODE_14,?" line.long 0x2AC "CTRL_CORE_PAD_MCASP1_ACLKR," rbitfld.long 0x2AC 25. "MCASP1_ACLKR_WAKEUPEVENT,- NOWAKEUP" "MCASP1_ACLKR_WAKEUPEVENT_0,MCASP1_ACLKR_WAKEUPEVENT_1" newline bitfld.long 0x2AC 24. "MCASP1_ACLKR_WAKEUPENABLE,- DISABLE" "MCASP1_ACLKR_WAKEUPENABLE_0,MCASP1_ACLKR_WAKEUPENABLE_1" newline bitfld.long 0x2AC 19. "MCASP1_ACLKR_SLEWCONTROL,- SLOW_SLEW" "MCASP1_ACLKR_SLEWCONTROL_0,MCASP1_ACLKR_SLEWCONTROL_1" newline bitfld.long 0x2AC 18. "MCASP1_ACLKR_INPUTENABLE,- DISABLE" "MCASP1_ACLKR_INPUTENABLE_0,MCASP1_ACLKR_INPUTENABLE_1" newline bitfld.long 0x2AC 17. "MCASP1_ACLKR_PULLTYPESELECT,- PULL_DOWN" "MCASP1_ACLKR_PULLTYPESELECT_0,MCASP1_ACLKR_PULLTYPESELECT_1" newline bitfld.long 0x2AC 16. "MCASP1_ACLKR_PULLUDENABLE,- DISABLE" "MCASP1_ACLKR_PULLUDENABLE_0,MCASP1_ACLKR_PULLUDENABLE_1" newline bitfld.long 0x2AC 8. "MCASP1_ACLKR_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_ACLKR_MODESELECT_0,MCASP1_ACLKR_MODESELECT_1" newline bitfld.long 0x2AC 4.--7. "MCASP1_ACLKR_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2AC 0.--3. "MCASP1_ACLKR_MUXMODE,- VOUT2_D0_6" "MCASP1_ACLKR_MUXMODE_0,MCASP1_ACLKR_MUXMODE_1,?,?,?,?,MCASP1_ACLKR_MUXMODE_6,?,MCASP1_ACLKR_MUXMODE_8,?,MCASP1_ACLKR_MUXMODE_10,?,?,?,MCASP1_ACLKR_MUXMODE_14,?" line.long 0x2B0 "CTRL_CORE_PAD_MCASP1_FSR," rbitfld.long 0x2B0 25. "MCASP1_FSR_WAKEUPEVENT,- NOWAKEUP" "MCASP1_FSR_WAKEUPEVENT_0,MCASP1_FSR_WAKEUPEVENT_1" newline bitfld.long 0x2B0 24. "MCASP1_FSR_WAKEUPENABLE,- DISABLE" "MCASP1_FSR_WAKEUPENABLE_0,MCASP1_FSR_WAKEUPENABLE_1" newline bitfld.long 0x2B0 19. "MCASP1_FSR_SLEWCONTROL,- SLOW_SLEW" "MCASP1_FSR_SLEWCONTROL_0,MCASP1_FSR_SLEWCONTROL_1" newline bitfld.long 0x2B0 18. "MCASP1_FSR_INPUTENABLE,- DISABLE" "MCASP1_FSR_INPUTENABLE_0,MCASP1_FSR_INPUTENABLE_1" newline bitfld.long 0x2B0 17. "MCASP1_FSR_PULLTYPESELECT,- PULL_DOWN" "MCASP1_FSR_PULLTYPESELECT_0,MCASP1_FSR_PULLTYPESELECT_1" newline bitfld.long 0x2B0 16. "MCASP1_FSR_PULLUDENABLE,- DISABLE" "MCASP1_FSR_PULLUDENABLE_0,MCASP1_FSR_PULLUDENABLE_1" newline bitfld.long 0x2B0 8. "MCASP1_FSR_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_FSR_MODESELECT_0,MCASP1_FSR_MODESELECT_1" newline bitfld.long 0x2B0 4.--7. "MCASP1_FSR_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2B0 0.--3. "MCASP1_FSR_MUXMODE,- VOUT2_D1_6" "MCASP1_FSR_MUXMODE_0,MCASP1_FSR_MUXMODE_1,?,?,?,?,MCASP1_FSR_MUXMODE_6,?,MCASP1_FSR_MUXMODE_8,?,MCASP1_FSR_MUXMODE_10,?,?,?,MCASP1_FSR_MUXMODE_14,?" line.long 0x2B4 "CTRL_CORE_PAD_MCASP1_AXR0," rbitfld.long 0x2B4 25. "MCASP1_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR0_WAKEUPEVENT_0,MCASP1_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x2B4 24. "MCASP1_AXR0_WAKEUPENABLE,- DISABLE" "MCASP1_AXR0_WAKEUPENABLE_0,MCASP1_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x2B4 19. "MCASP1_AXR0_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR0_SLEWCONTROL_0,MCASP1_AXR0_SLEWCONTROL_1" newline bitfld.long 0x2B4 18. "MCASP1_AXR0_INPUTENABLE,- DISABLE" "MCASP1_AXR0_INPUTENABLE_0,MCASP1_AXR0_INPUTENABLE_1" newline bitfld.long 0x2B4 17. "MCASP1_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR0_PULLTYPESELECT_0,MCASP1_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x2B4 16. "MCASP1_AXR0_PULLUDENABLE,- DISABLE" "MCASP1_AXR0_PULLUDENABLE_0,MCASP1_AXR0_PULLUDENABLE_1" newline bitfld.long 0x2B4 8. "MCASP1_AXR0_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR0_MODESELECT_0,MCASP1_AXR0_MODESELECT_1" newline bitfld.long 0x2B4 4.--7. "MCASP1_AXR0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2B4 0.--3. "MCASP1_AXR0_MUXMODE,- PR2_PRU1_PRU_R308_13" "MCASP1_AXR0_MUXMODE_0,?,?,MCASP1_AXR0_MUXMODE_3,?,?,?,MCASP1_AXR0_MUXMODE_7,?,?,MCASP1_AXR0_MUXMODE_10,MCASP1_AXR0_MUXMODE_11,MCASP1_AXR0_MUXMODE_12,MCASP1_AXR0_MUXMODE_13,MCASP1_AXR0_MUXMODE_14,?" line.long 0x2B8 "CTRL_CORE_PAD_MCASP1_AXR1," rbitfld.long 0x2B8 25. "MCASP1_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR1_WAKEUPEVENT_0,MCASP1_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x2B8 24. "MCASP1_AXR1_WAKEUPENABLE,- DISABLE" "MCASP1_AXR1_WAKEUPENABLE_0,MCASP1_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x2B8 19. "MCASP1_AXR1_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR1_SLEWCONTROL_0,MCASP1_AXR1_SLEWCONTROL_1" newline bitfld.long 0x2B8 18. "MCASP1_AXR1_INPUTENABLE,- DISABLE" "MCASP1_AXR1_INPUTENABLE_0,MCASP1_AXR1_INPUTENABLE_1" newline bitfld.long 0x2B8 17. "MCASP1_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR1_PULLTYPESELECT_0,MCASP1_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x2B8 16. "MCASP1_AXR1_PULLUDENABLE,- DISABLE" "MCASP1_AXR1_PULLUDENABLE_0,MCASP1_AXR1_PULLUDENABLE_1" newline bitfld.long 0x2B8 8. "MCASP1_AXR1_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR1_MODESELECT_0,MCASP1_AXR1_MODESELECT_1" newline bitfld.long 0x2B8 4.--7. "MCASP1_AXR1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2B8 0.--3. "MCASP1_AXR1_MUXMODE,- PR2_PRU1_PRU_R309_13" "MCASP1_AXR1_MUXMODE_0,?,?,MCASP1_AXR1_MUXMODE_3,?,?,?,MCASP1_AXR1_MUXMODE_7,?,?,MCASP1_AXR1_MUXMODE_10,MCASP1_AXR1_MUXMODE_11,MCASP1_AXR1_MUXMODE_12,MCASP1_AXR1_MUXMODE_13,MCASP1_AXR1_MUXMODE_14,?" line.long 0x2BC "CTRL_CORE_PAD_MCASP1_AXR2," rbitfld.long 0x2BC 25. "MCASP1_AXR2_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR2_WAKEUPEVENT_0,MCASP1_AXR2_WAKEUPEVENT_1" newline bitfld.long 0x2BC 24. "MCASP1_AXR2_WAKEUPENABLE,- DISABLE" "MCASP1_AXR2_WAKEUPENABLE_0,MCASP1_AXR2_WAKEUPENABLE_1" newline bitfld.long 0x2BC 19. "MCASP1_AXR2_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR2_SLEWCONTROL_0,MCASP1_AXR2_SLEWCONTROL_1" newline bitfld.long 0x2BC 18. "MCASP1_AXR2_INPUTENABLE,- DISABLE" "MCASP1_AXR2_INPUTENABLE_0,MCASP1_AXR2_INPUTENABLE_1" newline bitfld.long 0x2BC 17. "MCASP1_AXR2_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR2_PULLTYPESELECT_0,MCASP1_AXR2_PULLTYPESELECT_1" newline bitfld.long 0x2BC 16. "MCASP1_AXR2_PULLUDENABLE,- DISABLE" "MCASP1_AXR2_PULLUDENABLE_0,MCASP1_AXR2_PULLUDENABLE_1" newline bitfld.long 0x2BC 8. "MCASP1_AXR2_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR2_MODESELECT_0,MCASP1_AXR2_MODESELECT_1" newline bitfld.long 0x2BC 4.--7. "MCASP1_AXR2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2BC 0.--3. "MCASP1_AXR2_MUXMODE,- VOUT2_D2_6" "MCASP1_AXR2_MUXMODE_0,MCASP1_AXR2_MUXMODE_1,?,MCASP1_AXR2_MUXMODE_3,?,?,MCASP1_AXR2_MUXMODE_6,?,MCASP1_AXR2_MUXMODE_8,?,?,?,?,?,MCASP1_AXR2_MUXMODE_14,?" line.long 0x2C0 "CTRL_CORE_PAD_MCASP1_AXR3," rbitfld.long 0x2C0 25. "MCASP1_AXR3_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR3_WAKEUPEVENT_0,MCASP1_AXR3_WAKEUPEVENT_1" newline bitfld.long 0x2C0 24. "MCASP1_AXR3_WAKEUPENABLE,- DISABLE" "MCASP1_AXR3_WAKEUPENABLE_0,MCASP1_AXR3_WAKEUPENABLE_1" newline bitfld.long 0x2C0 19. "MCASP1_AXR3_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR3_SLEWCONTROL_0,MCASP1_AXR3_SLEWCONTROL_1" newline bitfld.long 0x2C0 18. "MCASP1_AXR3_INPUTENABLE,- DISABLE" "MCASP1_AXR3_INPUTENABLE_0,MCASP1_AXR3_INPUTENABLE_1" newline bitfld.long 0x2C0 17. "MCASP1_AXR3_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR3_PULLTYPESELECT_0,MCASP1_AXR3_PULLTYPESELECT_1" newline bitfld.long 0x2C0 16. "MCASP1_AXR3_PULLUDENABLE,- DISABLE" "MCASP1_AXR3_PULLUDENABLE_0,MCASP1_AXR3_PULLUDENABLE_1" newline bitfld.long 0x2C0 8. "MCASP1_AXR3_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR3_MODESELECT_0,MCASP1_AXR3_MODESELECT_1" newline bitfld.long 0x2C0 4.--7. "MCASP1_AXR3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C0 0.--3. "MCASP1_AXR3_MUXMODE,- VOUT2_D3_6" "MCASP1_AXR3_MUXMODE_0,MCASP1_AXR3_MUXMODE_1,?,MCASP1_AXR3_MUXMODE_3,?,?,MCASP1_AXR3_MUXMODE_6,?,MCASP1_AXR3_MUXMODE_8,?,?,?,?,?,MCASP1_AXR3_MUXMODE_14,?" line.long 0x2C4 "CTRL_CORE_PAD_MCASP1_AXR4," rbitfld.long 0x2C4 25. "MCASP1_AXR4_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR4_WAKEUPEVENT_0,MCASP1_AXR4_WAKEUPEVENT_1" newline bitfld.long 0x2C4 24. "MCASP1_AXR4_WAKEUPENABLE,- DISABLE" "MCASP1_AXR4_WAKEUPENABLE_0,MCASP1_AXR4_WAKEUPENABLE_1" newline bitfld.long 0x2C4 19. "MCASP1_AXR4_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR4_SLEWCONTROL_0,MCASP1_AXR4_SLEWCONTROL_1" newline bitfld.long 0x2C4 18. "MCASP1_AXR4_INPUTENABLE,- DISABLE" "MCASP1_AXR4_INPUTENABLE_0,MCASP1_AXR4_INPUTENABLE_1" newline bitfld.long 0x2C4 17. "MCASP1_AXR4_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR4_PULLTYPESELECT_0,MCASP1_AXR4_PULLTYPESELECT_1" newline bitfld.long 0x2C4 16. "MCASP1_AXR4_PULLUDENABLE,- DISABLE" "MCASP1_AXR4_PULLUDENABLE_0,MCASP1_AXR4_PULLUDENABLE_1" newline bitfld.long 0x2C4 8. "MCASP1_AXR4_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR4_MODESELECT_0,MCASP1_AXR4_MODESELECT_1" newline bitfld.long 0x2C4 4.--7. "MCASP1_AXR4_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C4 0.--3. "MCASP1_AXR4_MUXMODE,- VIN4A_D4_8" "MCASP1_AXR4_MUXMODE_0,MCASP1_AXR4_MUXMODE_1,?,?,?,?,MCASP1_AXR4_MUXMODE_6,?,MCASP1_AXR4_MUXMODE_8,?,?,?,?,?,MCASP1_AXR4_MUXMODE_14,?" line.long 0x2C8 "CTRL_CORE_PAD_MCASP1_AXR5," rbitfld.long 0x2C8 25. "MCASP1_AXR5_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR5_WAKEUPEVENT_0,MCASP1_AXR5_WAKEUPEVENT_1" newline bitfld.long 0x2C8 24. "MCASP1_AXR5_WAKEUPENABLE,- DISABLE" "MCASP1_AXR5_WAKEUPENABLE_0,MCASP1_AXR5_WAKEUPENABLE_1" newline bitfld.long 0x2C8 19. "MCASP1_AXR5_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR5_SLEWCONTROL_0,MCASP1_AXR5_SLEWCONTROL_1" newline bitfld.long 0x2C8 18. "MCASP1_AXR5_INPUTENABLE,- DISABLE" "MCASP1_AXR5_INPUTENABLE_0,MCASP1_AXR5_INPUTENABLE_1" newline bitfld.long 0x2C8 17. "MCASP1_AXR5_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR5_PULLTYPESELECT_0,MCASP1_AXR5_PULLTYPESELECT_1" newline bitfld.long 0x2C8 16. "MCASP1_AXR5_PULLUDENABLE,- DISABLE" "MCASP1_AXR5_PULLUDENABLE_0,MCASP1_AXR5_PULLUDENABLE_1" newline bitfld.long 0x2C8 8. "MCASP1_AXR5_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR5_MODESELECT_0,MCASP1_AXR5_MODESELECT_1" newline bitfld.long 0x2C8 4.--7. "MCASP1_AXR5_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C8 0.--3. "MCASP1_AXR5_MUXMODE,- VIN4A_D5_8" "MCASP1_AXR5_MUXMODE_0,MCASP1_AXR5_MUXMODE_1,?,?,?,?,MCASP1_AXR5_MUXMODE_6,?,MCASP1_AXR5_MUXMODE_8,?,?,?,?,?,MCASP1_AXR5_MUXMODE_14,?" line.long 0x2CC "CTRL_CORE_PAD_MCASP1_AXR6," rbitfld.long 0x2CC 25. "MCASP1_AXR6_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR6_WAKEUPEVENT_0,MCASP1_AXR6_WAKEUPEVENT_1" newline bitfld.long 0x2CC 24. "MCASP1_AXR6_WAKEUPENABLE,- DISABLE" "MCASP1_AXR6_WAKEUPENABLE_0,MCASP1_AXR6_WAKEUPENABLE_1" newline bitfld.long 0x2CC 19. "MCASP1_AXR6_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR6_SLEWCONTROL_0,MCASP1_AXR6_SLEWCONTROL_1" newline bitfld.long 0x2CC 18. "MCASP1_AXR6_INPUTENABLE,- DISABLE" "MCASP1_AXR6_INPUTENABLE_0,MCASP1_AXR6_INPUTENABLE_1" newline bitfld.long 0x2CC 17. "MCASP1_AXR6_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR6_PULLTYPESELECT_0,MCASP1_AXR6_PULLTYPESELECT_1" newline bitfld.long 0x2CC 16. "MCASP1_AXR6_PULLUDENABLE,- DISABLE" "MCASP1_AXR6_PULLUDENABLE_0,MCASP1_AXR6_PULLUDENABLE_1" newline bitfld.long 0x2CC 8. "MCASP1_AXR6_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR6_MODESELECT_0,MCASP1_AXR6_MODESELECT_1" newline bitfld.long 0x2CC 4.--7. "MCASP1_AXR6_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2CC 0.--3. "MCASP1_AXR6_MUXMODE,- VIN4A_D6_8" "MCASP1_AXR6_MUXMODE_0,MCASP1_AXR6_MUXMODE_1,?,?,?,?,MCASP1_AXR6_MUXMODE_6,?,MCASP1_AXR6_MUXMODE_8,?,?,?,?,?,MCASP1_AXR6_MUXMODE_14,?" line.long 0x2D0 "CTRL_CORE_PAD_MCASP1_AXR7," rbitfld.long 0x2D0 25. "MCASP1_AXR7_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR7_WAKEUPEVENT_0,MCASP1_AXR7_WAKEUPEVENT_1" newline bitfld.long 0x2D0 24. "MCASP1_AXR7_WAKEUPENABLE,- DISABLE" "MCASP1_AXR7_WAKEUPENABLE_0,MCASP1_AXR7_WAKEUPENABLE_1" newline bitfld.long 0x2D0 19. "MCASP1_AXR7_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR7_SLEWCONTROL_0,MCASP1_AXR7_SLEWCONTROL_1" newline bitfld.long 0x2D0 18. "MCASP1_AXR7_INPUTENABLE,- DISABLE" "MCASP1_AXR7_INPUTENABLE_0,MCASP1_AXR7_INPUTENABLE_1" newline bitfld.long 0x2D0 17. "MCASP1_AXR7_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR7_PULLTYPESELECT_0,MCASP1_AXR7_PULLTYPESELECT_1" newline bitfld.long 0x2D0 16. "MCASP1_AXR7_PULLUDENABLE,- DISABLE" "MCASP1_AXR7_PULLUDENABLE_0,MCASP1_AXR7_PULLUDENABLE_1" newline bitfld.long 0x2D0 8. "MCASP1_AXR7_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR7_MODESELECT_0,MCASP1_AXR7_MODESELECT_1" newline bitfld.long 0x2D0 4.--7. "MCASP1_AXR7_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2D0 0.--3. "MCASP1_AXR7_MUXMODE,- VOUT2_D7_6" "MCASP1_AXR7_MUXMODE_0,MCASP1_AXR7_MUXMODE_1,?,?,?,?,MCASP1_AXR7_MUXMODE_6,?,MCASP1_AXR7_MUXMODE_8,?,MCASP1_AXR7_MUXMODE_10,?,?,?,MCASP1_AXR7_MUXMODE_14,?" line.long 0x2D4 "CTRL_CORE_PAD_MCASP1_AXR8," rbitfld.long 0x2D4 25. "MCASP1_AXR8_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR8_WAKEUPEVENT_0,MCASP1_AXR8_WAKEUPEVENT_1" newline bitfld.long 0x2D4 24. "MCASP1_AXR8_WAKEUPENABLE,- DISABLE" "MCASP1_AXR8_WAKEUPENABLE_0,MCASP1_AXR8_WAKEUPENABLE_1" newline bitfld.long 0x2D4 19. "MCASP1_AXR8_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR8_SLEWCONTROL_0,MCASP1_AXR8_SLEWCONTROL_1" newline bitfld.long 0x2D4 18. "MCASP1_AXR8_INPUTENABLE,- DISABLE" "MCASP1_AXR8_INPUTENABLE_0,MCASP1_AXR8_INPUTENABLE_1" newline bitfld.long 0x2D4 17. "MCASP1_AXR8_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR8_PULLTYPESELECT_0,MCASP1_AXR8_PULLTYPESELECT_1" newline bitfld.long 0x2D4 16. "MCASP1_AXR8_PULLUDENABLE,- DISABLE" "MCASP1_AXR8_PULLUDENABLE_0,MCASP1_AXR8_PULLUDENABLE_1" newline bitfld.long 0x2D4 8. "MCASP1_AXR8_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR8_MODESELECT_0,MCASP1_AXR8_MODESELECT_1" newline bitfld.long 0x2D4 4.--7. "MCASP1_AXR8_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2D4 0.--3. "MCASP1_AXR8_MUXMODE,- PR2_PRU1_PRU_R3010_13" "MCASP1_AXR8_MUXMODE_0,MCASP1_AXR8_MUXMODE_1,?,MCASP1_AXR8_MUXMODE_3,?,?,?,MCASP1_AXR8_MUXMODE_7,?,?,MCASP1_AXR8_MUXMODE_10,MCASP1_AXR8_MUXMODE_11,MCASP1_AXR8_MUXMODE_12,MCASP1_AXR8_MUXMODE_13,MCASP1_AXR8_MUXMODE_14,?" line.long 0x2D8 "CTRL_CORE_PAD_MCASP1_AXR9," rbitfld.long 0x2D8 25. "MCASP1_AXR9_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR9_WAKEUPEVENT_0,MCASP1_AXR9_WAKEUPEVENT_1" newline bitfld.long 0x2D8 24. "MCASP1_AXR9_WAKEUPENABLE,- DISABLE" "MCASP1_AXR9_WAKEUPENABLE_0,MCASP1_AXR9_WAKEUPENABLE_1" newline bitfld.long 0x2D8 19. "MCASP1_AXR9_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR9_SLEWCONTROL_0,MCASP1_AXR9_SLEWCONTROL_1" newline bitfld.long 0x2D8 18. "MCASP1_AXR9_INPUTENABLE,- DISABLE" "MCASP1_AXR9_INPUTENABLE_0,MCASP1_AXR9_INPUTENABLE_1" newline bitfld.long 0x2D8 17. "MCASP1_AXR9_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR9_PULLTYPESELECT_0,MCASP1_AXR9_PULLTYPESELECT_1" newline bitfld.long 0x2D8 16. "MCASP1_AXR9_PULLUDENABLE,- DISABLE" "MCASP1_AXR9_PULLUDENABLE_0,MCASP1_AXR9_PULLUDENABLE_1" newline bitfld.long 0x2D8 8. "MCASP1_AXR9_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR9_MODESELECT_0,MCASP1_AXR9_MODESELECT_1" newline bitfld.long 0x2D8 4.--7. "MCASP1_AXR9_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2D8 0.--3. "MCASP1_AXR9_MUXMODE,- PR2_PRU1_PRU_R3011_13" "MCASP1_AXR9_MUXMODE_0,MCASP1_AXR9_MUXMODE_1,?,MCASP1_AXR9_MUXMODE_3,?,?,?,MCASP1_AXR9_MUXMODE_7,?,?,MCASP1_AXR9_MUXMODE_10,MCASP1_AXR9_MUXMODE_11,MCASP1_AXR9_MUXMODE_12,MCASP1_AXR9_MUXMODE_13,MCASP1_AXR9_MUXMODE_14,?" line.long 0x2DC "CTRL_CORE_PAD_MCASP1_AXR10," rbitfld.long 0x2DC 25. "MCASP1_AXR10_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR10_WAKEUPEVENT_0,MCASP1_AXR10_WAKEUPEVENT_1" newline bitfld.long 0x2DC 24. "MCASP1_AXR10_WAKEUPENABLE,- DISABLE" "MCASP1_AXR10_WAKEUPENABLE_0,MCASP1_AXR10_WAKEUPENABLE_1" newline bitfld.long 0x2DC 19. "MCASP1_AXR10_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR10_SLEWCONTROL_0,MCASP1_AXR10_SLEWCONTROL_1" newline bitfld.long 0x2DC 18. "MCASP1_AXR10_INPUTENABLE,- DISABLE" "MCASP1_AXR10_INPUTENABLE_0,MCASP1_AXR10_INPUTENABLE_1" newline bitfld.long 0x2DC 17. "MCASP1_AXR10_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR10_PULLTYPESELECT_0,MCASP1_AXR10_PULLTYPESELECT_1" newline bitfld.long 0x2DC 16. "MCASP1_AXR10_PULLUDENABLE,- DISABLE" "MCASP1_AXR10_PULLUDENABLE_0,MCASP1_AXR10_PULLUDENABLE_1" newline bitfld.long 0x2DC 8. "MCASP1_AXR10_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR10_MODESELECT_0,MCASP1_AXR10_MODESELECT_1" newline bitfld.long 0x2DC 4.--7. "MCASP1_AXR10_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2DC 0.--3. "MCASP1_AXR10_MUXMODE,- PR2_PRU1_PRU_R3012_13" "MCASP1_AXR10_MUXMODE_0,MCASP1_AXR10_MUXMODE_1,MCASP1_AXR10_MUXMODE_2,MCASP1_AXR10_MUXMODE_3,?,?,?,MCASP1_AXR10_MUXMODE_7,?,?,MCASP1_AXR10_MUXMODE_10,MCASP1_AXR10_MUXMODE_11,MCASP1_AXR10_MUXMODE_12,MCASP1_AXR10_MUXMODE_13,MCASP1_AXR10_MUXMODE_14,?" line.long 0x2E0 "CTRL_CORE_PAD_MCASP1_AXR11," rbitfld.long 0x2E0 25. "MCASP1_AXR11_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR11_WAKEUPEVENT_0,MCASP1_AXR11_WAKEUPEVENT_1" newline bitfld.long 0x2E0 24. "MCASP1_AXR11_WAKEUPENABLE,- DISABLE" "MCASP1_AXR11_WAKEUPENABLE_0,MCASP1_AXR11_WAKEUPENABLE_1" newline bitfld.long 0x2E0 19. "MCASP1_AXR11_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR11_SLEWCONTROL_0,MCASP1_AXR11_SLEWCONTROL_1" newline bitfld.long 0x2E0 18. "MCASP1_AXR11_INPUTENABLE,- DISABLE" "MCASP1_AXR11_INPUTENABLE_0,MCASP1_AXR11_INPUTENABLE_1" newline bitfld.long 0x2E0 17. "MCASP1_AXR11_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR11_PULLTYPESELECT_0,MCASP1_AXR11_PULLTYPESELECT_1" newline bitfld.long 0x2E0 16. "MCASP1_AXR11_PULLUDENABLE,- DISABLE" "MCASP1_AXR11_PULLUDENABLE_0,MCASP1_AXR11_PULLUDENABLE_1" newline bitfld.long 0x2E0 8. "MCASP1_AXR11_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR11_MODESELECT_0,MCASP1_AXR11_MODESELECT_1" newline bitfld.long 0x2E0 4.--7. "MCASP1_AXR11_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2E0 0.--3. "MCASP1_AXR11_MUXMODE,- PR2_PRU1_PRU_R3013_13" "MCASP1_AXR11_MUXMODE_0,MCASP1_AXR11_MUXMODE_1,MCASP1_AXR11_MUXMODE_2,MCASP1_AXR11_MUXMODE_3,?,?,?,MCASP1_AXR11_MUXMODE_7,?,?,MCASP1_AXR11_MUXMODE_10,MCASP1_AXR11_MUXMODE_11,MCASP1_AXR11_MUXMODE_12,MCASP1_AXR11_MUXMODE_13,MCASP1_AXR11_MUXMODE_14,?" line.long 0x2E4 "CTRL_CORE_PAD_MCASP1_AXR12," rbitfld.long 0x2E4 25. "MCASP1_AXR12_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR12_WAKEUPEVENT_0,MCASP1_AXR12_WAKEUPEVENT_1" newline bitfld.long 0x2E4 24. "MCASP1_AXR12_WAKEUPENABLE,- DISABLE" "MCASP1_AXR12_WAKEUPENABLE_0,MCASP1_AXR12_WAKEUPENABLE_1" newline bitfld.long 0x2E4 19. "MCASP1_AXR12_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR12_SLEWCONTROL_0,MCASP1_AXR12_SLEWCONTROL_1" newline bitfld.long 0x2E4 18. "MCASP1_AXR12_INPUTENABLE,- DISABLE" "MCASP1_AXR12_INPUTENABLE_0,MCASP1_AXR12_INPUTENABLE_1" newline bitfld.long 0x2E4 17. "MCASP1_AXR12_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR12_PULLTYPESELECT_0,MCASP1_AXR12_PULLTYPESELECT_1" newline bitfld.long 0x2E4 16. "MCASP1_AXR12_PULLUDENABLE,- DISABLE" "MCASP1_AXR12_PULLUDENABLE_0,MCASP1_AXR12_PULLUDENABLE_1" newline bitfld.long 0x2E4 8. "MCASP1_AXR12_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR12_MODESELECT_0,MCASP1_AXR12_MODESELECT_1" newline bitfld.long 0x2E4 4.--7. "MCASP1_AXR12_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2E4 0.--3. "MCASP1_AXR12_MUXMODE,- PR2_PRU1_PRU_R3014_13" "MCASP1_AXR12_MUXMODE_0,MCASP1_AXR12_MUXMODE_1,?,MCASP1_AXR12_MUXMODE_3,?,?,?,MCASP1_AXR12_MUXMODE_7,?,?,MCASP1_AXR12_MUXMODE_10,MCASP1_AXR12_MUXMODE_11,MCASP1_AXR12_MUXMODE_12,MCASP1_AXR12_MUXMODE_13,MCASP1_AXR12_MUXMODE_14,?" line.long 0x2E8 "CTRL_CORE_PAD_MCASP1_AXR13," rbitfld.long 0x2E8 25. "MCASP1_AXR13_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR13_WAKEUPEVENT_0,MCASP1_AXR13_WAKEUPEVENT_1" newline bitfld.long 0x2E8 24. "MCASP1_AXR13_WAKEUPENABLE,- DISABLE" "MCASP1_AXR13_WAKEUPENABLE_0,MCASP1_AXR13_WAKEUPENABLE_1" newline bitfld.long 0x2E8 19. "MCASP1_AXR13_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR13_SLEWCONTROL_0,MCASP1_AXR13_SLEWCONTROL_1" newline bitfld.long 0x2E8 18. "MCASP1_AXR13_INPUTENABLE,- DISABLE" "MCASP1_AXR13_INPUTENABLE_0,MCASP1_AXR13_INPUTENABLE_1" newline bitfld.long 0x2E8 17. "MCASP1_AXR13_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR13_PULLTYPESELECT_0,MCASP1_AXR13_PULLTYPESELECT_1" newline bitfld.long 0x2E8 16. "MCASP1_AXR13_PULLUDENABLE,- DISABLE" "MCASP1_AXR13_PULLUDENABLE_0,MCASP1_AXR13_PULLUDENABLE_1" newline bitfld.long 0x2E8 8. "MCASP1_AXR13_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR13_MODESELECT_0,MCASP1_AXR13_MODESELECT_1" newline bitfld.long 0x2E8 4.--7. "MCASP1_AXR13_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2E8 0.--3. "MCASP1_AXR13_MUXMODE,- PR2_PRU1_PRU_R3015_13" "MCASP1_AXR13_MUXMODE_0,MCASP1_AXR13_MUXMODE_1,?,?,?,?,?,MCASP1_AXR13_MUXMODE_7,?,?,MCASP1_AXR13_MUXMODE_10,MCASP1_AXR13_MUXMODE_11,MCASP1_AXR13_MUXMODE_12,MCASP1_AXR13_MUXMODE_13,MCASP1_AXR13_MUXMODE_14,?" line.long 0x2EC "CTRL_CORE_PAD_MCASP1_AXR14," rbitfld.long 0x2EC 25. "MCASP1_AXR14_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR14_WAKEUPEVENT_0,MCASP1_AXR14_WAKEUPEVENT_1" newline bitfld.long 0x2EC 24. "MCASP1_AXR14_WAKEUPENABLE,- DISABLE" "MCASP1_AXR14_WAKEUPENABLE_0,MCASP1_AXR14_WAKEUPENABLE_1" newline bitfld.long 0x2EC 19. "MCASP1_AXR14_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR14_SLEWCONTROL_0,MCASP1_AXR14_SLEWCONTROL_1" newline bitfld.long 0x2EC 18. "MCASP1_AXR14_INPUTENABLE,- DISABLE" "MCASP1_AXR14_INPUTENABLE_0,MCASP1_AXR14_INPUTENABLE_1" newline bitfld.long 0x2EC 17. "MCASP1_AXR14_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR14_PULLTYPESELECT_0,MCASP1_AXR14_PULLTYPESELECT_1" newline bitfld.long 0x2EC 16. "MCASP1_AXR14_PULLUDENABLE,- DISABLE" "MCASP1_AXR14_PULLUDENABLE_0,MCASP1_AXR14_PULLUDENABLE_1" newline bitfld.long 0x2EC 8. "MCASP1_AXR14_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR14_MODESELECT_0,MCASP1_AXR14_MODESELECT_1" newline bitfld.long 0x2EC 4.--7. "MCASP1_AXR14_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2EC 0.--3. "MCASP1_AXR14_MUXMODE,- PR2_PRU1_PRU_R3016_13" "MCASP1_AXR14_MUXMODE_0,MCASP1_AXR14_MUXMODE_1,MCASP1_AXR14_MUXMODE_2,?,?,?,?,MCASP1_AXR14_MUXMODE_7,?,?,MCASP1_AXR14_MUXMODE_10,MCASP1_AXR14_MUXMODE_11,MCASP1_AXR14_MUXMODE_12,MCASP1_AXR14_MUXMODE_13,MCASP1_AXR14_MUXMODE_14,?" line.long 0x2F0 "CTRL_CORE_PAD_MCASP1_AXR15," rbitfld.long 0x2F0 25. "MCASP1_AXR15_WAKEUPEVENT,- NOWAKEUP" "MCASP1_AXR15_WAKEUPEVENT_0,MCASP1_AXR15_WAKEUPEVENT_1" newline bitfld.long 0x2F0 24. "MCASP1_AXR15_WAKEUPENABLE,- DISABLE" "MCASP1_AXR15_WAKEUPENABLE_0,MCASP1_AXR15_WAKEUPENABLE_1" newline bitfld.long 0x2F0 19. "MCASP1_AXR15_SLEWCONTROL,- SLOW_SLEW" "MCASP1_AXR15_SLEWCONTROL_0,MCASP1_AXR15_SLEWCONTROL_1" newline bitfld.long 0x2F0 18. "MCASP1_AXR15_INPUTENABLE,- DISABLE" "MCASP1_AXR15_INPUTENABLE_0,MCASP1_AXR15_INPUTENABLE_1" newline bitfld.long 0x2F0 17. "MCASP1_AXR15_PULLTYPESELECT,- PULL_DOWN" "MCASP1_AXR15_PULLTYPESELECT_0,MCASP1_AXR15_PULLTYPESELECT_1" newline bitfld.long 0x2F0 16. "MCASP1_AXR15_PULLUDENABLE,- DISABLE" "MCASP1_AXR15_PULLUDENABLE_0,MCASP1_AXR15_PULLUDENABLE_1" newline bitfld.long 0x2F0 8. "MCASP1_AXR15_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP1_AXR15_MODESELECT_0,MCASP1_AXR15_MODESELECT_1" newline bitfld.long 0x2F0 4.--7. "MCASP1_AXR15_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2F0 0.--3. "MCASP1_AXR15_MUXMODE,- PR2_PRU0_PRU_R3020_13" "MCASP1_AXR15_MUXMODE_0,MCASP1_AXR15_MUXMODE_1,MCASP1_AXR15_MUXMODE_2,?,?,?,?,MCASP1_AXR15_MUXMODE_7,?,?,MCASP1_AXR15_MUXMODE_10,MCASP1_AXR15_MUXMODE_11,MCASP1_AXR15_MUXMODE_12,MCASP1_AXR15_MUXMODE_13,MCASP1_AXR15_MUXMODE_14,?" line.long 0x2F4 "CTRL_CORE_PAD_MCASP2_ACLKX," rbitfld.long 0x2F4 25. "MCASP2_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP2_ACLKX_WAKEUPEVENT_0,MCASP2_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x2F4 24. "MCASP2_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP2_ACLKX_WAKEUPENABLE_0,MCASP2_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x2F4 19. "MCASP2_ACLKX_SLEWCONTROL,- SLOW_SLEW" "MCASP2_ACLKX_SLEWCONTROL_0,MCASP2_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x2F4 18. "MCASP2_ACLKX_INPUTENABLE,- DISABLE" "MCASP2_ACLKX_INPUTENABLE_0,MCASP2_ACLKX_INPUTENABLE_1" newline bitfld.long 0x2F4 17. "MCASP2_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP2_ACLKX_PULLTYPESELECT_0,MCASP2_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x2F4 16. "MCASP2_ACLKX_PULLUDENABLE,- DISABLE" "MCASP2_ACLKX_PULLUDENABLE_0,MCASP2_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x2F4 8. "MCASP2_ACLKX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_ACLKX_MODESELECT_0,MCASP2_ACLKX_MODESELECT_1" newline bitfld.long 0x2F4 4.--7. "MCASP2_ACLKX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2F4 0.--3. "MCASP2_ACLKX_MUXMODE,- MCASP2_ACLKX_0" "MCASP2_ACLKX_MUXMODE_0,?,?,?,?,?,?,MCASP2_ACLKX_MUXMODE_7,?,?,?,MCASP2_ACLKX_MUXMODE_11,MCASP2_ACLKX_MUXMODE_12,MCASP2_ACLKX_MUXMODE_13,?,?" line.long 0x2F8 "CTRL_CORE_PAD_MCASP2_FSX," rbitfld.long 0x2F8 25. "MCASP2_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP2_FSX_WAKEUPEVENT_0,MCASP2_FSX_WAKEUPEVENT_1" newline bitfld.long 0x2F8 24. "MCASP2_FSX_WAKEUPENABLE,- DISABLE" "MCASP2_FSX_WAKEUPENABLE_0,MCASP2_FSX_WAKEUPENABLE_1" newline bitfld.long 0x2F8 19. "MCASP2_FSX_SLEWCONTROL,- SLOW_SLEW" "MCASP2_FSX_SLEWCONTROL_0,MCASP2_FSX_SLEWCONTROL_1" newline bitfld.long 0x2F8 18. "MCASP2_FSX_INPUTENABLE,- DISABLE" "MCASP2_FSX_INPUTENABLE_0,MCASP2_FSX_INPUTENABLE_1" newline bitfld.long 0x2F8 17. "MCASP2_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP2_FSX_PULLTYPESELECT_0,MCASP2_FSX_PULLTYPESELECT_1" newline bitfld.long 0x2F8 16. "MCASP2_FSX_PULLUDENABLE,- DISABLE" "MCASP2_FSX_PULLUDENABLE_0,MCASP2_FSX_PULLUDENABLE_1" newline bitfld.long 0x2F8 8. "MCASP2_FSX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_FSX_MODESELECT_0,MCASP2_FSX_MODESELECT_1" newline bitfld.long 0x2F8 4.--7. "MCASP2_FSX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2F8 0.--3. "MCASP2_FSX_MUXMODE,- MCASP2_FSX_0" "MCASP2_FSX_MUXMODE_0,?,?,?,?,?,?,MCASP2_FSX_MUXMODE_7,?,?,?,MCASP2_FSX_MUXMODE_11,MCASP2_FSX_MUXMODE_12,MCASP2_FSX_MUXMODE_13,?,?" line.long 0x2FC "CTRL_CORE_PAD_MCASP2_ACLKR," rbitfld.long 0x2FC 25. "MCASP2_ACLKR_WAKEUPEVENT,- NOWAKEUP" "MCASP2_ACLKR_WAKEUPEVENT_0,MCASP2_ACLKR_WAKEUPEVENT_1" newline bitfld.long 0x2FC 24. "MCASP2_ACLKR_WAKEUPENABLE,- DISABLE" "MCASP2_ACLKR_WAKEUPENABLE_0,MCASP2_ACLKR_WAKEUPENABLE_1" newline bitfld.long 0x2FC 19. "MCASP2_ACLKR_SLEWCONTROL,- SLOW_SLEW" "MCASP2_ACLKR_SLEWCONTROL_0,MCASP2_ACLKR_SLEWCONTROL_1" newline bitfld.long 0x2FC 18. "MCASP2_ACLKR_INPUTENABLE,- DISABLE" "MCASP2_ACLKR_INPUTENABLE_0,MCASP2_ACLKR_INPUTENABLE_1" newline bitfld.long 0x2FC 17. "MCASP2_ACLKR_PULLTYPESELECT,- PULL_DOWN" "MCASP2_ACLKR_PULLTYPESELECT_0,MCASP2_ACLKR_PULLTYPESELECT_1" newline bitfld.long 0x2FC 16. "MCASP2_ACLKR_PULLUDENABLE,- DISABLE" "MCASP2_ACLKR_PULLUDENABLE_0,MCASP2_ACLKR_PULLUDENABLE_1" newline bitfld.long 0x2FC 8. "MCASP2_ACLKR_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_ACLKR_MODESELECT_0,MCASP2_ACLKR_MODESELECT_1" newline bitfld.long 0x2FC 4.--7. "MCASP2_ACLKR_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2FC 0.--3. "MCASP2_ACLKR_MUXMODE,- MCASP2_ACLKR_0" "MCASP2_ACLKR_MUXMODE_0,MCASP2_ACLKR_MUXMODE_1,?,?,?,?,MCASP2_ACLKR_MUXMODE_6,?,MCASP2_ACLKR_MUXMODE_8,?,?,?,?,?,?,?" line.long 0x300 "CTRL_CORE_PAD_MCASP2_FSR," rbitfld.long 0x300 25. "MCASP2_FSR_WAKEUPEVENT,- NOWAKEUP" "MCASP2_FSR_WAKEUPEVENT_0,MCASP2_FSR_WAKEUPEVENT_1" newline bitfld.long 0x300 24. "MCASP2_FSR_WAKEUPENABLE,- DISABLE" "MCASP2_FSR_WAKEUPENABLE_0,MCASP2_FSR_WAKEUPENABLE_1" newline bitfld.long 0x300 19. "MCASP2_FSR_SLEWCONTROL,- SLOW_SLEW" "MCASP2_FSR_SLEWCONTROL_0,MCASP2_FSR_SLEWCONTROL_1" newline bitfld.long 0x300 18. "MCASP2_FSR_INPUTENABLE,- DISABLE" "MCASP2_FSR_INPUTENABLE_0,MCASP2_FSR_INPUTENABLE_1" newline bitfld.long 0x300 17. "MCASP2_FSR_PULLTYPESELECT,- PULL_DOWN" "MCASP2_FSR_PULLTYPESELECT_0,MCASP2_FSR_PULLTYPESELECT_1" newline bitfld.long 0x300 16. "MCASP2_FSR_PULLUDENABLE,- DISABLE" "MCASP2_FSR_PULLUDENABLE_0,MCASP2_FSR_PULLUDENABLE_1" newline bitfld.long 0x300 8. "MCASP2_FSR_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_FSR_MODESELECT_0,MCASP2_FSR_MODESELECT_1" newline bitfld.long 0x300 4.--7. "MCASP2_FSR_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x300 0.--3. "MCASP2_FSR_MUXMODE,- MCASP2_FSR_0" "MCASP2_FSR_MUXMODE_0,MCASP2_FSR_MUXMODE_1,?,?,?,?,MCASP2_FSR_MUXMODE_6,?,MCASP2_FSR_MUXMODE_8,?,?,?,?,?,?,?" line.long 0x304 "CTRL_CORE_PAD_MCASP2_AXR0," rbitfld.long 0x304 25. "MCASP2_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR0_WAKEUPEVENT_0,MCASP2_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x304 24. "MCASP2_AXR0_WAKEUPENABLE,- DISABLE" "MCASP2_AXR0_WAKEUPENABLE_0,MCASP2_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x304 19. "MCASP2_AXR0_SLEWCONTROL,- SLOW_SLEW" "MCASP2_AXR0_SLEWCONTROL_0,MCASP2_AXR0_SLEWCONTROL_1" newline bitfld.long 0x304 18. "MCASP2_AXR0_INPUTENABLE,- DISABLE" "MCASP2_AXR0_INPUTENABLE_0,MCASP2_AXR0_INPUTENABLE_1" newline bitfld.long 0x304 17. "MCASP2_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR0_PULLTYPESELECT_0,MCASP2_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x304 16. "MCASP2_AXR0_PULLUDENABLE,- DISABLE" "MCASP2_AXR0_PULLUDENABLE_0,MCASP2_AXR0_PULLUDENABLE_1" newline bitfld.long 0x304 8. "MCASP2_AXR0_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_AXR0_MODESELECT_0,MCASP2_AXR0_MODESELECT_1" newline bitfld.long 0x304 4.--7. "MCASP2_AXR0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x304 0.--3. "MCASP2_AXR0_MUXMODE,- MCASP2_AXR0_0" "MCASP2_AXR0_MUXMODE_0,?,?,?,?,?,MCASP2_AXR0_MUXMODE_6,?,MCASP2_AXR0_MUXMODE_8,?,?,?,?,?,?,?" line.long 0x308 "CTRL_CORE_PAD_MCASP2_AXR1," rbitfld.long 0x308 25. "MCASP2_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR1_WAKEUPEVENT_0,MCASP2_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x308 24. "MCASP2_AXR1_WAKEUPENABLE,- DISABLE" "MCASP2_AXR1_WAKEUPENABLE_0,MCASP2_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x308 19. "MCASP2_AXR1_SLEWCONTROL,- SLOW_SLEW" "MCASP2_AXR1_SLEWCONTROL_0,MCASP2_AXR1_SLEWCONTROL_1" newline bitfld.long 0x308 18. "MCASP2_AXR1_INPUTENABLE,- DISABLE" "MCASP2_AXR1_INPUTENABLE_0,MCASP2_AXR1_INPUTENABLE_1" newline bitfld.long 0x308 17. "MCASP2_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR1_PULLTYPESELECT_0,MCASP2_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x308 16. "MCASP2_AXR1_PULLUDENABLE,- DISABLE" "MCASP2_AXR1_PULLUDENABLE_0,MCASP2_AXR1_PULLUDENABLE_1" newline bitfld.long 0x308 8. "MCASP2_AXR1_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_AXR1_MODESELECT_0,MCASP2_AXR1_MODESELECT_1" newline bitfld.long 0x308 4.--7. "MCASP2_AXR1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x308 0.--3. "MCASP2_AXR1_MUXMODE,- MCASP2_AXR1_0" "MCASP2_AXR1_MUXMODE_0,?,?,?,?,?,MCASP2_AXR1_MUXMODE_6,?,MCASP2_AXR1_MUXMODE_8,?,?,?,?,?,?,?" line.long 0x30C "CTRL_CORE_PAD_MCASP2_AXR2," rbitfld.long 0x30C 25. "MCASP2_AXR2_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR2_WAKEUPEVENT_0,MCASP2_AXR2_WAKEUPEVENT_1" newline bitfld.long 0x30C 24. "MCASP2_AXR2_WAKEUPENABLE,- DISABLE" "MCASP2_AXR2_WAKEUPENABLE_0,MCASP2_AXR2_WAKEUPENABLE_1" newline bitfld.long 0x30C 19. "MCASP2_AXR2_SLEWCONTROL,- SLOW_SLEW" "MCASP2_AXR2_SLEWCONTROL_0,MCASP2_AXR2_SLEWCONTROL_1" newline bitfld.long 0x30C 18. "MCASP2_AXR2_INPUTENABLE,- DISABLE" "MCASP2_AXR2_INPUTENABLE_0,MCASP2_AXR2_INPUTENABLE_1" newline bitfld.long 0x30C 17. "MCASP2_AXR2_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR2_PULLTYPESELECT_0,MCASP2_AXR2_PULLTYPESELECT_1" newline bitfld.long 0x30C 16. "MCASP2_AXR2_PULLUDENABLE,- DISABLE" "MCASP2_AXR2_PULLUDENABLE_0,MCASP2_AXR2_PULLUDENABLE_1" newline bitfld.long 0x30C 8. "MCASP2_AXR2_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_AXR2_MODESELECT_0,MCASP2_AXR2_MODESELECT_1" newline bitfld.long 0x30C 4.--7. "MCASP2_AXR2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30C 0.--3. "MCASP2_AXR2_MUXMODE,- PR2_PRU0_PRU_R3016_13" "MCASP2_AXR2_MUXMODE_0,MCASP2_AXR2_MUXMODE_1,?,?,?,?,?,MCASP2_AXR2_MUXMODE_7,?,?,?,MCASP2_AXR2_MUXMODE_11,MCASP2_AXR2_MUXMODE_12,MCASP2_AXR2_MUXMODE_13,MCASP2_AXR2_MUXMODE_14,?" line.long 0x310 "CTRL_CORE_PAD_MCASP2_AXR3," rbitfld.long 0x310 25. "MCASP2_AXR3_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR3_WAKEUPEVENT_0,MCASP2_AXR3_WAKEUPEVENT_1" newline bitfld.long 0x310 24. "MCASP2_AXR3_WAKEUPENABLE,- DISABLE" "MCASP2_AXR3_WAKEUPENABLE_0,MCASP2_AXR3_WAKEUPENABLE_1" newline bitfld.long 0x310 19. "MCASP2_AXR3_SLEWCONTROL,- SLOW_SLEW" "MCASP2_AXR3_SLEWCONTROL_0,MCASP2_AXR3_SLEWCONTROL_1" newline bitfld.long 0x310 18. "MCASP2_AXR3_INPUTENABLE,- DISABLE" "MCASP2_AXR3_INPUTENABLE_0,MCASP2_AXR3_INPUTENABLE_1" newline bitfld.long 0x310 17. "MCASP2_AXR3_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR3_PULLTYPESELECT_0,MCASP2_AXR3_PULLTYPESELECT_1" newline bitfld.long 0x310 16. "MCASP2_AXR3_PULLUDENABLE,- DISABLE" "MCASP2_AXR3_PULLUDENABLE_0,MCASP2_AXR3_PULLUDENABLE_1" newline bitfld.long 0x310 8. "MCASP2_AXR3_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_AXR3_MODESELECT_0,MCASP2_AXR3_MODESELECT_1" newline bitfld.long 0x310 4.--7. "MCASP2_AXR3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x310 0.--3. "MCASP2_AXR3_MUXMODE,- PR2_PRU0_PRU_R3017_13" "MCASP2_AXR3_MUXMODE_0,MCASP2_AXR3_MUXMODE_1,?,?,?,?,?,MCASP2_AXR3_MUXMODE_7,?,?,?,MCASP2_AXR3_MUXMODE_11,MCASP2_AXR3_MUXMODE_12,MCASP2_AXR3_MUXMODE_13,MCASP2_AXR3_MUXMODE_14,?" line.long 0x314 "CTRL_CORE_PAD_MCASP2_AXR4," rbitfld.long 0x314 25. "MCASP2_AXR4_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR4_WAKEUPEVENT_0,MCASP2_AXR4_WAKEUPEVENT_1" newline bitfld.long 0x314 24. "MCASP2_AXR4_WAKEUPENABLE,- DISABLE" "MCASP2_AXR4_WAKEUPENABLE_0,MCASP2_AXR4_WAKEUPENABLE_1" newline bitfld.long 0x314 19. "MCASP2_AXR4_SLEWCONTROL,- SLOW_SLEW" "MCASP2_AXR4_SLEWCONTROL_0,MCASP2_AXR4_SLEWCONTROL_1" newline bitfld.long 0x314 18. "MCASP2_AXR4_INPUTENABLE,- DISABLE" "MCASP2_AXR4_INPUTENABLE_0,MCASP2_AXR4_INPUTENABLE_1" newline bitfld.long 0x314 17. "MCASP2_AXR4_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR4_PULLTYPESELECT_0,MCASP2_AXR4_PULLTYPESELECT_1" newline bitfld.long 0x314 16. "MCASP2_AXR4_PULLUDENABLE,- DISABLE" "MCASP2_AXR4_PULLUDENABLE_0,MCASP2_AXR4_PULLUDENABLE_1" newline bitfld.long 0x314 8. "MCASP2_AXR4_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_AXR4_MODESELECT_0,MCASP2_AXR4_MODESELECT_1" newline bitfld.long 0x314 4.--7. "MCASP2_AXR4_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x314 0.--3. "MCASP2_AXR4_MUXMODE,- VIN4A_D12_8" "MCASP2_AXR4_MUXMODE_0,MCASP2_AXR4_MUXMODE_1,?,?,?,?,MCASP2_AXR4_MUXMODE_6,?,MCASP2_AXR4_MUXMODE_8,?,?,?,?,?,MCASP2_AXR4_MUXMODE_14,?" line.long 0x318 "CTRL_CORE_PAD_MCASP2_AXR5," rbitfld.long 0x318 25. "MCASP2_AXR5_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR5_WAKEUPEVENT_0,MCASP2_AXR5_WAKEUPEVENT_1" newline bitfld.long 0x318 24. "MCASP2_AXR5_WAKEUPENABLE,- DISABLE" "MCASP2_AXR5_WAKEUPENABLE_0,MCASP2_AXR5_WAKEUPENABLE_1" newline bitfld.long 0x318 19. "MCASP2_AXR5_SLEWCONTROL,- SLOW_SLEW" "MCASP2_AXR5_SLEWCONTROL_0,MCASP2_AXR5_SLEWCONTROL_1" newline bitfld.long 0x318 18. "MCASP2_AXR5_INPUTENABLE,- DISABLE" "MCASP2_AXR5_INPUTENABLE_0,MCASP2_AXR5_INPUTENABLE_1" newline bitfld.long 0x318 17. "MCASP2_AXR5_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR5_PULLTYPESELECT_0,MCASP2_AXR5_PULLTYPESELECT_1" newline bitfld.long 0x318 16. "MCASP2_AXR5_PULLUDENABLE,- DISABLE" "MCASP2_AXR5_PULLUDENABLE_0,MCASP2_AXR5_PULLUDENABLE_1" newline bitfld.long 0x318 8. "MCASP2_AXR5_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_AXR5_MODESELECT_0,MCASP2_AXR5_MODESELECT_1" newline bitfld.long 0x318 4.--7. "MCASP2_AXR5_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x318 0.--3. "MCASP2_AXR5_MUXMODE,- VIN4A_D13_8" "MCASP2_AXR5_MUXMODE_0,MCASP2_AXR5_MUXMODE_1,?,?,?,?,MCASP2_AXR5_MUXMODE_6,?,MCASP2_AXR5_MUXMODE_8,?,?,?,?,?,MCASP2_AXR5_MUXMODE_14,?" line.long 0x31C "CTRL_CORE_PAD_MCASP2_AXR6," rbitfld.long 0x31C 25. "MCASP2_AXR6_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR6_WAKEUPEVENT_0,MCASP2_AXR6_WAKEUPEVENT_1" newline bitfld.long 0x31C 24. "MCASP2_AXR6_WAKEUPENABLE,- DISABLE" "MCASP2_AXR6_WAKEUPENABLE_0,MCASP2_AXR6_WAKEUPENABLE_1" newline bitfld.long 0x31C 19. "MCASP2_AXR6_SLEWCONTROL,- SLOW_SLEW" "MCASP2_AXR6_SLEWCONTROL_0,MCASP2_AXR6_SLEWCONTROL_1" newline bitfld.long 0x31C 18. "MCASP2_AXR6_INPUTENABLE,- DISABLE" "MCASP2_AXR6_INPUTENABLE_0,MCASP2_AXR6_INPUTENABLE_1" newline bitfld.long 0x31C 17. "MCASP2_AXR6_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR6_PULLTYPESELECT_0,MCASP2_AXR6_PULLTYPESELECT_1" newline bitfld.long 0x31C 16. "MCASP2_AXR6_PULLUDENABLE,- DISABLE" "MCASP2_AXR6_PULLUDENABLE_0,MCASP2_AXR6_PULLUDENABLE_1" newline bitfld.long 0x31C 8. "MCASP2_AXR6_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_AXR6_MODESELECT_0,MCASP2_AXR6_MODESELECT_1" newline bitfld.long 0x31C 4.--7. "MCASP2_AXR6_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x31C 0.--3. "MCASP2_AXR6_MUXMODE,- VOUT2_D14_6" "MCASP2_AXR6_MUXMODE_0,MCASP2_AXR6_MUXMODE_1,MCASP2_AXR6_MUXMODE_2,?,?,?,MCASP2_AXR6_MUXMODE_6,?,MCASP2_AXR6_MUXMODE_8,?,?,?,?,?,MCASP2_AXR6_MUXMODE_14,?" line.long 0x320 "CTRL_CORE_PAD_MCASP2_AXR7," rbitfld.long 0x320 25. "MCASP2_AXR7_WAKEUPEVENT,- NOWAKEUP" "MCASP2_AXR7_WAKEUPEVENT_0,MCASP2_AXR7_WAKEUPEVENT_1" newline bitfld.long 0x320 24. "MCASP2_AXR7_WAKEUPENABLE,- DISABLE" "MCASP2_AXR7_WAKEUPENABLE_0,MCASP2_AXR7_WAKEUPENABLE_1" newline bitfld.long 0x320 19. "MCASP2_AXR7_SLEWCONTROL,- SLOW_SLEW" "MCASP2_AXR7_SLEWCONTROL_0,MCASP2_AXR7_SLEWCONTROL_1" newline bitfld.long 0x320 18. "MCASP2_AXR7_INPUTENABLE,- DISABLE" "MCASP2_AXR7_INPUTENABLE_0,MCASP2_AXR7_INPUTENABLE_1" newline bitfld.long 0x320 17. "MCASP2_AXR7_PULLTYPESELECT,- PULL_DOWN" "MCASP2_AXR7_PULLTYPESELECT_0,MCASP2_AXR7_PULLTYPESELECT_1" newline bitfld.long 0x320 16. "MCASP2_AXR7_PULLUDENABLE,- DISABLE" "MCASP2_AXR7_PULLUDENABLE_0,MCASP2_AXR7_PULLUDENABLE_1" newline bitfld.long 0x320 8. "MCASP2_AXR7_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP2_AXR7_MODESELECT_0,MCASP2_AXR7_MODESELECT_1" newline bitfld.long 0x320 4.--7. "MCASP2_AXR7_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x320 0.--3. "MCASP2_AXR7_MUXMODE,- VOUT2_D15_6" "MCASP2_AXR7_MUXMODE_0,MCASP2_AXR7_MUXMODE_1,MCASP2_AXR7_MUXMODE_2,?,?,?,MCASP2_AXR7_MUXMODE_6,?,MCASP2_AXR7_MUXMODE_8,?,?,?,?,?,MCASP2_AXR7_MUXMODE_14,?" line.long 0x324 "CTRL_CORE_PAD_MCASP3_ACLKX," rbitfld.long 0x324 25. "MCASP3_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP3_ACLKX_WAKEUPEVENT_0,MCASP3_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x324 24. "MCASP3_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP3_ACLKX_WAKEUPENABLE_0,MCASP3_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x324 19. "MCASP3_ACLKX_SLEWCONTROL,- SLOW_SLEW" "MCASP3_ACLKX_SLEWCONTROL_0,MCASP3_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x324 18. "MCASP3_ACLKX_INPUTENABLE,- DISABLE" "MCASP3_ACLKX_INPUTENABLE_0,MCASP3_ACLKX_INPUTENABLE_1" newline bitfld.long 0x324 17. "MCASP3_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP3_ACLKX_PULLTYPESELECT_0,MCASP3_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x324 16. "MCASP3_ACLKX_PULLUDENABLE,- DISABLE" "MCASP3_ACLKX_PULLUDENABLE_0,MCASP3_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x324 8. "MCASP3_ACLKX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP3_ACLKX_MODESELECT_0,MCASP3_ACLKX_MODESELECT_1" newline bitfld.long 0x324 4.--7. "MCASP3_ACLKX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x324 0.--3. "MCASP3_ACLKX_MUXMODE,- PR2_PRU0_PRU_R3012_13" "MCASP3_ACLKX_MUXMODE_0,MCASP3_ACLKX_MUXMODE_1,MCASP3_ACLKX_MUXMODE_2,MCASP3_ACLKX_MUXMODE_3,?,?,?,MCASP3_ACLKX_MUXMODE_7,?,?,?,MCASP3_ACLKX_MUXMODE_11,MCASP3_ACLKX_MUXMODE_12,MCASP3_ACLKX_MUXMODE_13,MCASP3_ACLKX_MUXMODE_14,?" line.long 0x328 "CTRL_CORE_PAD_MCASP3_FSX," rbitfld.long 0x328 25. "MCASP3_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP3_FSX_WAKEUPEVENT_0,MCASP3_FSX_WAKEUPEVENT_1" newline bitfld.long 0x328 24. "MCASP3_FSX_WAKEUPENABLE,- DISABLE" "MCASP3_FSX_WAKEUPENABLE_0,MCASP3_FSX_WAKEUPENABLE_1" newline bitfld.long 0x328 19. "MCASP3_FSX_SLEWCONTROL,- SLOW_SLEW" "MCASP3_FSX_SLEWCONTROL_0,MCASP3_FSX_SLEWCONTROL_1" newline bitfld.long 0x328 18. "MCASP3_FSX_INPUTENABLE,- DISABLE" "MCASP3_FSX_INPUTENABLE_0,MCASP3_FSX_INPUTENABLE_1" newline bitfld.long 0x328 17. "MCASP3_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP3_FSX_PULLTYPESELECT_0,MCASP3_FSX_PULLTYPESELECT_1" newline bitfld.long 0x328 16. "MCASP3_FSX_PULLUDENABLE,- DISABLE" "MCASP3_FSX_PULLUDENABLE_0,MCASP3_FSX_PULLUDENABLE_1" newline bitfld.long 0x328 8. "MCASP3_FSX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP3_FSX_MODESELECT_0,MCASP3_FSX_MODESELECT_1" newline bitfld.long 0x328 4.--7. "MCASP3_FSX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x328 0.--3. "MCASP3_FSX_MUXMODE,- PR2_PRU0_PRU_R3013_13" "MCASP3_FSX_MUXMODE_0,MCASP3_FSX_MUXMODE_1,MCASP3_FSX_MUXMODE_2,MCASP3_FSX_MUXMODE_3,?,?,?,MCASP3_FSX_MUXMODE_7,?,?,?,MCASP3_FSX_MUXMODE_11,MCASP3_FSX_MUXMODE_12,MCASP3_FSX_MUXMODE_13,MCASP3_FSX_MUXMODE_14,?" line.long 0x32C "CTRL_CORE_PAD_MCASP3_AXR0," rbitfld.long 0x32C 25. "MCASP3_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP3_AXR0_WAKEUPEVENT_0,MCASP3_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x32C 24. "MCASP3_AXR0_WAKEUPENABLE,- DISABLE" "MCASP3_AXR0_WAKEUPENABLE_0,MCASP3_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x32C 19. "MCASP3_AXR0_SLEWCONTROL,- SLOW_SLEW" "MCASP3_AXR0_SLEWCONTROL_0,MCASP3_AXR0_SLEWCONTROL_1" newline bitfld.long 0x32C 18. "MCASP3_AXR0_INPUTENABLE,- DISABLE" "MCASP3_AXR0_INPUTENABLE_0,MCASP3_AXR0_INPUTENABLE_1" newline bitfld.long 0x32C 17. "MCASP3_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP3_AXR0_PULLTYPESELECT_0,MCASP3_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x32C 16. "MCASP3_AXR0_PULLUDENABLE,- DISABLE" "MCASP3_AXR0_PULLUDENABLE_0,MCASP3_AXR0_PULLUDENABLE_1" newline bitfld.long 0x32C 8. "MCASP3_AXR0_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP3_AXR0_MODESELECT_0,MCASP3_AXR0_MODESELECT_1" newline bitfld.long 0x32C 4.--7. "MCASP3_AXR0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x32C 0.--3. "MCASP3_AXR0_MUXMODE,- PR2_PRU0_PRU_R3014_13" "MCASP3_AXR0_MUXMODE_0,?,MCASP3_AXR0_MUXMODE_2,MCASP3_AXR0_MUXMODE_3,MCASP3_AXR0_MUXMODE_4,?,?,MCASP3_AXR0_MUXMODE_7,?,?,?,MCASP3_AXR0_MUXMODE_11,MCASP3_AXR0_MUXMODE_12,MCASP3_AXR0_MUXMODE_13,?,?" line.long 0x330 "CTRL_CORE_PAD_MCASP3_AXR1," rbitfld.long 0x330 25. "MCASP3_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP3_AXR1_WAKEUPEVENT_0,MCASP3_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x330 24. "MCASP3_AXR1_WAKEUPENABLE,- DISABLE" "MCASP3_AXR1_WAKEUPENABLE_0,MCASP3_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x330 19. "MCASP3_AXR1_SLEWCONTROL,- SLOW_SLEW" "MCASP3_AXR1_SLEWCONTROL_0,MCASP3_AXR1_SLEWCONTROL_1" newline bitfld.long 0x330 18. "MCASP3_AXR1_INPUTENABLE,- DISABLE" "MCASP3_AXR1_INPUTENABLE_0,MCASP3_AXR1_INPUTENABLE_1" newline bitfld.long 0x330 17. "MCASP3_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP3_AXR1_PULLTYPESELECT_0,MCASP3_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x330 16. "MCASP3_AXR1_PULLUDENABLE,- DISABLE" "MCASP3_AXR1_PULLUDENABLE_0,MCASP3_AXR1_PULLUDENABLE_1" newline bitfld.long 0x330 8. "MCASP3_AXR1_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP3_AXR1_MODESELECT_0,MCASP3_AXR1_MODESELECT_1" newline bitfld.long 0x330 4.--7. "MCASP3_AXR1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x330 0.--3. "MCASP3_AXR1_MUXMODE,- PR2_PRU0_PRU_R3015_13" "MCASP3_AXR1_MUXMODE_0,?,MCASP3_AXR1_MUXMODE_2,MCASP3_AXR1_MUXMODE_3,MCASP3_AXR1_MUXMODE_4,?,?,MCASP3_AXR1_MUXMODE_7,?,MCASP3_AXR1_MUXMODE_9,?,MCASP3_AXR1_MUXMODE_11,MCASP3_AXR1_MUXMODE_12,MCASP3_AXR1_MUXMODE_13,?,?" line.long 0x334 "CTRL_CORE_PAD_MCASP4_ACLKX," rbitfld.long 0x334 25. "MCASP4_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP4_ACLKX_WAKEUPEVENT_0,MCASP4_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x334 24. "MCASP4_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP4_ACLKX_WAKEUPENABLE_0,MCASP4_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x334 19. "MCASP4_ACLKX_SLEWCONTROL,- SLOW_SLEW" "MCASP4_ACLKX_SLEWCONTROL_0,MCASP4_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x334 18. "MCASP4_ACLKX_INPUTENABLE,- DISABLE" "MCASP4_ACLKX_INPUTENABLE_0,MCASP4_ACLKX_INPUTENABLE_1" newline bitfld.long 0x334 17. "MCASP4_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP4_ACLKX_PULLTYPESELECT_0,MCASP4_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x334 16. "MCASP4_ACLKX_PULLUDENABLE,- DISABLE" "MCASP4_ACLKX_PULLUDENABLE_0,MCASP4_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x334 8. "MCASP4_ACLKX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP4_ACLKX_MODESELECT_0,MCASP4_ACLKX_MODESELECT_1" newline bitfld.long 0x334 4.--7. "MCASP4_ACLKX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x334 0.--3. "MCASP4_ACLKX_MUXMODE,- VOUT2_D16_6" "MCASP4_ACLKX_MUXMODE_0,MCASP4_ACLKX_MUXMODE_1,MCASP4_ACLKX_MUXMODE_2,MCASP4_ACLKX_MUXMODE_3,MCASP4_ACLKX_MUXMODE_4,?,MCASP4_ACLKX_MUXMODE_6,?,MCASP4_ACLKX_MUXMODE_8,MCASP4_ACLKX_MUXMODE_9,?,?,?,?,?,?" line.long 0x338 "CTRL_CORE_PAD_MCASP4_FSX," rbitfld.long 0x338 25. "MCASP4_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP4_FSX_WAKEUPEVENT_0,MCASP4_FSX_WAKEUPEVENT_1" newline bitfld.long 0x338 24. "MCASP4_FSX_WAKEUPENABLE,- DISABLE" "MCASP4_FSX_WAKEUPENABLE_0,MCASP4_FSX_WAKEUPENABLE_1" newline bitfld.long 0x338 19. "MCASP4_FSX_SLEWCONTROL,- SLOW_SLEW" "MCASP4_FSX_SLEWCONTROL_0,MCASP4_FSX_SLEWCONTROL_1" newline bitfld.long 0x338 18. "MCASP4_FSX_INPUTENABLE,- DISABLE" "MCASP4_FSX_INPUTENABLE_0,MCASP4_FSX_INPUTENABLE_1" newline bitfld.long 0x338 17. "MCASP4_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP4_FSX_PULLTYPESELECT_0,MCASP4_FSX_PULLTYPESELECT_1" newline bitfld.long 0x338 16. "MCASP4_FSX_PULLUDENABLE,- DISABLE" "MCASP4_FSX_PULLUDENABLE_0,MCASP4_FSX_PULLUDENABLE_1" newline bitfld.long 0x338 8. "MCASP4_FSX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP4_FSX_MODESELECT_0,MCASP4_FSX_MODESELECT_1" newline bitfld.long 0x338 4.--7. "MCASP4_FSX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x338 0.--3. "MCASP4_FSX_MUXMODE,- VOUT2_D17_6" "MCASP4_FSX_MUXMODE_0,MCASP4_FSX_MUXMODE_1,MCASP4_FSX_MUXMODE_2,MCASP4_FSX_MUXMODE_3,MCASP4_FSX_MUXMODE_4,?,MCASP4_FSX_MUXMODE_6,?,MCASP4_FSX_MUXMODE_8,MCASP4_FSX_MUXMODE_9,?,?,?,?,?,?" line.long 0x33C "CTRL_CORE_PAD_MCASP4_AXR0," rbitfld.long 0x33C 25. "MCASP4_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP4_AXR0_WAKEUPEVENT_0,MCASP4_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x33C 24. "MCASP4_AXR0_WAKEUPENABLE,- DISABLE" "MCASP4_AXR0_WAKEUPENABLE_0,MCASP4_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x33C 19. "MCASP4_AXR0_SLEWCONTROL,- SLOW_SLEW" "MCASP4_AXR0_SLEWCONTROL_0,MCASP4_AXR0_SLEWCONTROL_1" newline bitfld.long 0x33C 18. "MCASP4_AXR0_INPUTENABLE,- DISABLE" "MCASP4_AXR0_INPUTENABLE_0,MCASP4_AXR0_INPUTENABLE_1" newline bitfld.long 0x33C 17. "MCASP4_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP4_AXR0_PULLTYPESELECT_0,MCASP4_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x33C 16. "MCASP4_AXR0_PULLUDENABLE,- DISABLE" "MCASP4_AXR0_PULLUDENABLE_0,MCASP4_AXR0_PULLUDENABLE_1" newline bitfld.long 0x33C 8. "MCASP4_AXR0_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP4_AXR0_MODESELECT_0,MCASP4_AXR0_MODESELECT_1" newline bitfld.long 0x33C 4.--7. "MCASP4_AXR0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x33C 0.--3. "MCASP4_AXR0_MUXMODE,- VOUT2_D18_6" "MCASP4_AXR0_MUXMODE_0,?,MCASP4_AXR0_MUXMODE_2,MCASP4_AXR0_MUXMODE_3,MCASP4_AXR0_MUXMODE_4,?,MCASP4_AXR0_MUXMODE_6,?,MCASP4_AXR0_MUXMODE_8,MCASP4_AXR0_MUXMODE_9,?,?,?,?,?,?" line.long 0x340 "CTRL_CORE_PAD_MCASP4_AXR1," rbitfld.long 0x340 25. "MCASP4_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP4_AXR1_WAKEUPEVENT_0,MCASP4_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x340 24. "MCASP4_AXR1_WAKEUPENABLE,- DISABLE" "MCASP4_AXR1_WAKEUPENABLE_0,MCASP4_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x340 19. "MCASP4_AXR1_SLEWCONTROL,- SLOW_SLEW" "MCASP4_AXR1_SLEWCONTROL_0,MCASP4_AXR1_SLEWCONTROL_1" newline bitfld.long 0x340 18. "MCASP4_AXR1_INPUTENABLE,- DISABLE" "MCASP4_AXR1_INPUTENABLE_0,MCASP4_AXR1_INPUTENABLE_1" newline bitfld.long 0x340 17. "MCASP4_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP4_AXR1_PULLTYPESELECT_0,MCASP4_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x340 16. "MCASP4_AXR1_PULLUDENABLE,- DISABLE" "MCASP4_AXR1_PULLUDENABLE_0,MCASP4_AXR1_PULLUDENABLE_1" newline bitfld.long 0x340 8. "MCASP4_AXR1_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP4_AXR1_MODESELECT_0,MCASP4_AXR1_MODESELECT_1" newline bitfld.long 0x340 4.--7. "MCASP4_AXR1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x340 0.--3. "MCASP4_AXR1_MUXMODE,- PR2_PRU1_PRU_R300_13" "MCASP4_AXR1_MUXMODE_0,?,MCASP4_AXR1_MUXMODE_2,MCASP4_AXR1_MUXMODE_3,MCASP4_AXR1_MUXMODE_4,?,MCASP4_AXR1_MUXMODE_6,?,MCASP4_AXR1_MUXMODE_8,MCASP4_AXR1_MUXMODE_9,?,?,MCASP4_AXR1_MUXMODE_12,MCASP4_AXR1_MUXMODE_13,?,?" line.long 0x344 "CTRL_CORE_PAD_MCASP5_ACLKX," rbitfld.long 0x344 25. "MCASP5_ACLKX_WAKEUPEVENT,- NOWAKEUP" "MCASP5_ACLKX_WAKEUPEVENT_0,MCASP5_ACLKX_WAKEUPEVENT_1" newline bitfld.long 0x344 24. "MCASP5_ACLKX_WAKEUPENABLE,- DISABLE" "MCASP5_ACLKX_WAKEUPENABLE_0,MCASP5_ACLKX_WAKEUPENABLE_1" newline bitfld.long 0x344 19. "MCASP5_ACLKX_SLEWCONTROL,- SLOW_SLEW" "MCASP5_ACLKX_SLEWCONTROL_0,MCASP5_ACLKX_SLEWCONTROL_1" newline bitfld.long 0x344 18. "MCASP5_ACLKX_INPUTENABLE,- DISABLE" "MCASP5_ACLKX_INPUTENABLE_0,MCASP5_ACLKX_INPUTENABLE_1" newline bitfld.long 0x344 17. "MCASP5_ACLKX_PULLTYPESELECT,- PULL_DOWN" "MCASP5_ACLKX_PULLTYPESELECT_0,MCASP5_ACLKX_PULLTYPESELECT_1" newline bitfld.long 0x344 16. "MCASP5_ACLKX_PULLUDENABLE,- DISABLE" "MCASP5_ACLKX_PULLUDENABLE_0,MCASP5_ACLKX_PULLUDENABLE_1" newline bitfld.long 0x344 8. "MCASP5_ACLKX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP5_ACLKX_MODESELECT_0,MCASP5_ACLKX_MODESELECT_1" newline bitfld.long 0x344 4.--7. "MCASP5_ACLKX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x344 0.--3. "MCASP5_ACLKX_MUXMODE,- PR2_PRU1_PRU_R301_13" "MCASP5_ACLKX_MUXMODE_0,MCASP5_ACLKX_MUXMODE_1,MCASP5_ACLKX_MUXMODE_2,MCASP5_ACLKX_MUXMODE_3,MCASP5_ACLKX_MUXMODE_4,MCASP5_ACLKX_MUXMODE_5,MCASP5_ACLKX_MUXMODE_6,?,MCASP5_ACLKX_MUXMODE_8,MCASP5_ACLKX_MUXMODE_9,?,?,MCASP5_ACLKX_MUXMODE_12,MCASP5_ACLKX_MUXMODE_13,?,?" line.long 0x348 "CTRL_CORE_PAD_MCASP5_FSX," rbitfld.long 0x348 25. "MCASP5_FSX_WAKEUPEVENT,- NOWAKEUP" "MCASP5_FSX_WAKEUPEVENT_0,MCASP5_FSX_WAKEUPEVENT_1" newline bitfld.long 0x348 24. "MCASP5_FSX_WAKEUPENABLE,- DISABLE" "MCASP5_FSX_WAKEUPENABLE_0,MCASP5_FSX_WAKEUPENABLE_1" newline bitfld.long 0x348 19. "MCASP5_FSX_SLEWCONTROL,- SLOW_SLEW" "MCASP5_FSX_SLEWCONTROL_0,MCASP5_FSX_SLEWCONTROL_1" newline bitfld.long 0x348 18. "MCASP5_FSX_INPUTENABLE,- DISABLE" "MCASP5_FSX_INPUTENABLE_0,MCASP5_FSX_INPUTENABLE_1" newline bitfld.long 0x348 17. "MCASP5_FSX_PULLTYPESELECT,- PULL_DOWN" "MCASP5_FSX_PULLTYPESELECT_0,MCASP5_FSX_PULLTYPESELECT_1" newline bitfld.long 0x348 16. "MCASP5_FSX_PULLUDENABLE,- DISABLE" "MCASP5_FSX_PULLUDENABLE_0,MCASP5_FSX_PULLUDENABLE_1" newline bitfld.long 0x348 8. "MCASP5_FSX_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP5_FSX_MODESELECT_0,MCASP5_FSX_MODESELECT_1" newline bitfld.long 0x348 4.--7. "MCASP5_FSX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x348 0.--3. "MCASP5_FSX_MUXMODE,- PR2_PRU1_PRU_R302_13" "MCASP5_FSX_MUXMODE_0,MCASP5_FSX_MUXMODE_1,MCASP5_FSX_MUXMODE_2,MCASP5_FSX_MUXMODE_3,MCASP5_FSX_MUXMODE_4,?,MCASP5_FSX_MUXMODE_6,?,MCASP5_FSX_MUXMODE_8,MCASP5_FSX_MUXMODE_9,?,?,MCASP5_FSX_MUXMODE_12,MCASP5_FSX_MUXMODE_13,?,?" line.long 0x34C "CTRL_CORE_PAD_MCASP5_AXR0," rbitfld.long 0x34C 25. "MCASP5_AXR0_WAKEUPEVENT,- NOWAKEUP" "MCASP5_AXR0_WAKEUPEVENT_0,MCASP5_AXR0_WAKEUPEVENT_1" newline bitfld.long 0x34C 24. "MCASP5_AXR0_WAKEUPENABLE,- DISABLE" "MCASP5_AXR0_WAKEUPENABLE_0,MCASP5_AXR0_WAKEUPENABLE_1" newline bitfld.long 0x34C 19. "MCASP5_AXR0_SLEWCONTROL,- SLOW_SLEW" "MCASP5_AXR0_SLEWCONTROL_0,MCASP5_AXR0_SLEWCONTROL_1" newline bitfld.long 0x34C 18. "MCASP5_AXR0_INPUTENABLE,- DISABLE" "MCASP5_AXR0_INPUTENABLE_0,MCASP5_AXR0_INPUTENABLE_1" newline bitfld.long 0x34C 17. "MCASP5_AXR0_PULLTYPESELECT,- PULL_DOWN" "MCASP5_AXR0_PULLTYPESELECT_0,MCASP5_AXR0_PULLTYPESELECT_1" newline bitfld.long 0x34C 16. "MCASP5_AXR0_PULLUDENABLE,- DISABLE" "MCASP5_AXR0_PULLUDENABLE_0,MCASP5_AXR0_PULLUDENABLE_1" newline bitfld.long 0x34C 8. "MCASP5_AXR0_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP5_AXR0_MODESELECT_0,MCASP5_AXR0_MODESELECT_1" newline bitfld.long 0x34C 4.--7. "MCASP5_AXR0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x34C 0.--3. "MCASP5_AXR0_MUXMODE,- PR2_PRU1_PRU_R303_13" "MCASP5_AXR0_MUXMODE_0,?,MCASP5_AXR0_MUXMODE_2,MCASP5_AXR0_MUXMODE_3,MCASP5_AXR0_MUXMODE_4,MCASP5_AXR0_MUXMODE_5,MCASP5_AXR0_MUXMODE_6,?,MCASP5_AXR0_MUXMODE_8,MCASP5_AXR0_MUXMODE_9,?,MCASP5_AXR0_MUXMODE_11,MCASP5_AXR0_MUXMODE_12,MCASP5_AXR0_MUXMODE_13,?,?" line.long 0x350 "CTRL_CORE_PAD_MCASP5_AXR1," rbitfld.long 0x350 25. "MCASP5_AXR1_WAKEUPEVENT,- NOWAKEUP" "MCASP5_AXR1_WAKEUPEVENT_0,MCASP5_AXR1_WAKEUPEVENT_1" newline bitfld.long 0x350 24. "MCASP5_AXR1_WAKEUPENABLE,- DISABLE" "MCASP5_AXR1_WAKEUPENABLE_0,MCASP5_AXR1_WAKEUPENABLE_1" newline bitfld.long 0x350 19. "MCASP5_AXR1_SLEWCONTROL,- SLOW_SLEW" "MCASP5_AXR1_SLEWCONTROL_0,MCASP5_AXR1_SLEWCONTROL_1" newline bitfld.long 0x350 18. "MCASP5_AXR1_INPUTENABLE,- DISABLE" "MCASP5_AXR1_INPUTENABLE_0,MCASP5_AXR1_INPUTENABLE_1" newline bitfld.long 0x350 17. "MCASP5_AXR1_PULLTYPESELECT,- PULL_DOWN" "MCASP5_AXR1_PULLTYPESELECT_0,MCASP5_AXR1_PULLTYPESELECT_1" newline bitfld.long 0x350 16. "MCASP5_AXR1_PULLUDENABLE,- DISABLE" "MCASP5_AXR1_PULLUDENABLE_0,MCASP5_AXR1_PULLUDENABLE_1" newline bitfld.long 0x350 8. "MCASP5_AXR1_MODESELECT,Selects between default and another IO delay different than the default one" "MCASP5_AXR1_MODESELECT_0,MCASP5_AXR1_MODESELECT_1" newline bitfld.long 0x350 4.--7. "MCASP5_AXR1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x350 0.--3. "MCASP5_AXR1_MUXMODE,- PR2_PRU1_PRU_R304_13" "MCASP5_AXR1_MUXMODE_0,?,MCASP5_AXR1_MUXMODE_2,MCASP5_AXR1_MUXMODE_3,MCASP5_AXR1_MUXMODE_4,MCASP5_AXR1_MUXMODE_5,MCASP5_AXR1_MUXMODE_6,?,MCASP5_AXR1_MUXMODE_8,MCASP5_AXR1_MUXMODE_9,?,MCASP5_AXR1_MUXMODE_11,MCASP5_AXR1_MUXMODE_12,MCASP5_AXR1_MUXMODE_13,?,?" line.long 0x354 "CTRL_CORE_PAD_MMC1_CLK," rbitfld.long 0x354 25. "MMC1_CLK_WAKEUPEVENT,- NOWAKEUP" "MMC1_CLK_WAKEUPEVENT_0,MMC1_CLK_WAKEUPEVENT_1" newline bitfld.long 0x354 24. "MMC1_CLK_WAKEUPENABLE,- DISABLE" "MMC1_CLK_WAKEUPENABLE_0,MMC1_CLK_WAKEUPENABLE_1" newline bitfld.long 0x354 18. "MMC1_CLK_ACTIVE," "0,1" newline bitfld.long 0x354 17. "MMC1_CLK_PULLTYPESELECT,- PULL_DOWN" "MMC1_CLK_PULLTYPESELECT_0,MMC1_CLK_PULLTYPESELECT_1" newline bitfld.long 0x354 16. "MMC1_CLK_PULLUDENABLE,- DISABLE" "MMC1_CLK_PULLUDENABLE_0,MMC1_CLK_PULLUDENABLE_1" newline bitfld.long 0x354 8. "MMC1_CLK_MODESELECT,Selects between default and another IO delay different than the default one" "MMC1_CLK_MODESELECT_0,MMC1_CLK_MODESELECT_1" newline bitfld.long 0x354 4.--7. "MMC1_CLK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x354 0.--3. "MMC1_CLK_MUXMODE,- MMC1_CLK_0" "MMC1_CLK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_CLK_MUXMODE_14,?" line.long 0x358 "CTRL_CORE_PAD_MMC1_CMD," rbitfld.long 0x358 25. "MMC1_CMD_WAKEUPEVENT,- NOWAKEUP" "MMC1_CMD_WAKEUPEVENT_0,MMC1_CMD_WAKEUPEVENT_1" newline bitfld.long 0x358 24. "MMC1_CMD_WAKEUPENABLE,- DISABLE" "MMC1_CMD_WAKEUPENABLE_0,MMC1_CMD_WAKEUPENABLE_1" newline bitfld.long 0x358 18. "MMC1_CMD_ACTIVE," "0,1" newline bitfld.long 0x358 17. "MMC1_CMD_PULLTYPESELECT,- PULL_DOWN" "MMC1_CMD_PULLTYPESELECT_0,MMC1_CMD_PULLTYPESELECT_1" newline bitfld.long 0x358 16. "MMC1_CMD_PULLUDENABLE,- DISABLE" "MMC1_CMD_PULLUDENABLE_0,MMC1_CMD_PULLUDENABLE_1" newline bitfld.long 0x358 8. "MMC1_CMD_MODESELECT,Selects between default and another IO delay different than the default one" "MMC1_CMD_MODESELECT_0,MMC1_CMD_MODESELECT_1" newline bitfld.long 0x358 4.--7. "MMC1_CMD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x358 0.--3. "MMC1_CMD_MUXMODE,- MMC1_CMD_0" "MMC1_CMD_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_CMD_MUXMODE_14,?" line.long 0x35C "CTRL_CORE_PAD_MMC1_DAT0," rbitfld.long 0x35C 25. "MMC1_DAT0_WAKEUPEVENT,- NOWAKEUP" "MMC1_DAT0_WAKEUPEVENT_0,MMC1_DAT0_WAKEUPEVENT_1" newline bitfld.long 0x35C 24. "MMC1_DAT0_WAKEUPENABLE,- DISABLE" "MMC1_DAT0_WAKEUPENABLE_0,MMC1_DAT0_WAKEUPENABLE_1" newline bitfld.long 0x35C 18. "MMC1_DAT0_ACTIVE," "0,1" newline bitfld.long 0x35C 17. "MMC1_DAT0_PULLTYPESELECT,- PULL_DOWN" "MMC1_DAT0_PULLTYPESELECT_0,MMC1_DAT0_PULLTYPESELECT_1" newline bitfld.long 0x35C 16. "MMC1_DAT0_PULLUDENABLE,- DISABLE" "MMC1_DAT0_PULLUDENABLE_0,MMC1_DAT0_PULLUDENABLE_1" newline bitfld.long 0x35C 8. "MMC1_DAT0_MODESELECT,Selects between default and another IO delay different than the default one" "MMC1_DAT0_MODESELECT_0,MMC1_DAT0_MODESELECT_1" newline bitfld.long 0x35C 4.--7. "MMC1_DAT0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x35C 0.--3. "MMC1_DAT0_MUXMODE,- MMC1_DAT0_0" "MMC1_DAT0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_DAT0_MUXMODE_14,?" line.long 0x360 "CTRL_CORE_PAD_MMC1_DAT1," rbitfld.long 0x360 25. "MMC1_DAT1_WAKEUPEVENT,- NOWAKEUP" "MMC1_DAT1_WAKEUPEVENT_0,MMC1_DAT1_WAKEUPEVENT_1" newline bitfld.long 0x360 24. "MMC1_DAT1_WAKEUPENABLE,- DISABLE" "MMC1_DAT1_WAKEUPENABLE_0,MMC1_DAT1_WAKEUPENABLE_1" newline bitfld.long 0x360 18. "MMC1_DAT1_ACTIVE," "0,1" newline bitfld.long 0x360 17. "MMC1_DAT1_PULLTYPESELECT,- PULL_DOWN" "MMC1_DAT1_PULLTYPESELECT_0,MMC1_DAT1_PULLTYPESELECT_1" newline bitfld.long 0x360 16. "MMC1_DAT1_PULLUDENABLE,- DISABLE" "MMC1_DAT1_PULLUDENABLE_0,MMC1_DAT1_PULLUDENABLE_1" newline bitfld.long 0x360 8. "MMC1_DAT1_MODESELECT,Selects between default and another IO delay different than the default one" "MMC1_DAT1_MODESELECT_0,MMC1_DAT1_MODESELECT_1" newline bitfld.long 0x360 4.--7. "MMC1_DAT1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x360 0.--3. "MMC1_DAT1_MUXMODE,- MMC1_DAT1_0" "MMC1_DAT1_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_DAT1_MUXMODE_14,?" line.long 0x364 "CTRL_CORE_PAD_MMC1_DAT2," rbitfld.long 0x364 25. "MMC1_DAT2_WAKEUPEVENT,- NOWAKEUP" "MMC1_DAT2_WAKEUPEVENT_0,MMC1_DAT2_WAKEUPEVENT_1" newline bitfld.long 0x364 24. "MMC1_DAT2_WAKEUPENABLE,- DISABLE" "MMC1_DAT2_WAKEUPENABLE_0,MMC1_DAT2_WAKEUPENABLE_1" newline bitfld.long 0x364 18. "MMC1_DAT2_ACTIVE," "0,1" newline bitfld.long 0x364 17. "MMC1_DAT2_PULLTYPESELECT,- PULL_DOWN" "MMC1_DAT2_PULLTYPESELECT_0,MMC1_DAT2_PULLTYPESELECT_1" newline bitfld.long 0x364 16. "MMC1_DAT2_PULLUDENABLE,- DISABLE" "MMC1_DAT2_PULLUDENABLE_0,MMC1_DAT2_PULLUDENABLE_1" newline bitfld.long 0x364 8. "MMC1_DAT2_MODESELECT,Selects between default and another IO delay different than the default one" "MMC1_DAT2_MODESELECT_0,MMC1_DAT2_MODESELECT_1" newline bitfld.long 0x364 4.--7. "MMC1_DAT2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x364 0.--3. "MMC1_DAT2_MUXMODE,- MMC1_DAT2_0" "MMC1_DAT2_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_DAT2_MUXMODE_14,?" line.long 0x368 "CTRL_CORE_PAD_MMC1_DAT3," rbitfld.long 0x368 25. "MMC1_DAT3_WAKEUPEVENT,- NOWAKEUP" "MMC1_DAT3_WAKEUPEVENT_0,MMC1_DAT3_WAKEUPEVENT_1" newline bitfld.long 0x368 24. "MMC1_DAT3_WAKEUPENABLE,- DISABLE" "MMC1_DAT3_WAKEUPENABLE_0,MMC1_DAT3_WAKEUPENABLE_1" newline bitfld.long 0x368 18. "MMC1_DAT3_ACTIVE," "0,1" newline bitfld.long 0x368 17. "MMC1_DAT3_PULLTYPESELECT,- PULL_DOWN" "MMC1_DAT3_PULLTYPESELECT_0,MMC1_DAT3_PULLTYPESELECT_1" newline bitfld.long 0x368 16. "MMC1_DAT3_PULLUDENABLE,- DISABLE" "MMC1_DAT3_PULLUDENABLE_0,MMC1_DAT3_PULLUDENABLE_1" newline bitfld.long 0x368 8. "MMC1_DAT3_MODESELECT,Selects between default and another IO delay different than the default one" "MMC1_DAT3_MODESELECT_0,MMC1_DAT3_MODESELECT_1" newline bitfld.long 0x368 4.--7. "MMC1_DAT3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x368 0.--3. "MMC1_DAT3_MUXMODE,- MMC1_DAT3_0" "MMC1_DAT3_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,MMC1_DAT3_MUXMODE_14,?" line.long 0x36C "CTRL_CORE_PAD_MMC1_SDCD," rbitfld.long 0x36C 25. "MMC1_SDCD_WAKEUPEVENT,- NOWAKEUP" "MMC1_SDCD_WAKEUPEVENT_0,MMC1_SDCD_WAKEUPEVENT_1" newline bitfld.long 0x36C 24. "MMC1_SDCD_WAKEUPENABLE,- DISABLE" "MMC1_SDCD_WAKEUPENABLE_0,MMC1_SDCD_WAKEUPENABLE_1" newline bitfld.long 0x36C 19. "MMC1_SDCD_SLEWCONTROL,- SLOW_SLEW" "MMC1_SDCD_SLEWCONTROL_0,MMC1_SDCD_SLEWCONTROL_1" newline bitfld.long 0x36C 18. "MMC1_SDCD_INPUTENABLE,- DISABLE" "MMC1_SDCD_INPUTENABLE_0,MMC1_SDCD_INPUTENABLE_1" newline bitfld.long 0x36C 17. "MMC1_SDCD_PULLTYPESELECT,- PULL_DOWN" "MMC1_SDCD_PULLTYPESELECT_0,MMC1_SDCD_PULLTYPESELECT_1" newline bitfld.long 0x36C 16. "MMC1_SDCD_PULLUDENABLE,- DISABLE" "MMC1_SDCD_PULLUDENABLE_0,MMC1_SDCD_PULLUDENABLE_1" newline bitfld.long 0x36C 8. "MMC1_SDCD_MODESELECT,Selects between default and another IO delay different than the default one" "MMC1_SDCD_MODESELECT_0,MMC1_SDCD_MODESELECT_1" newline bitfld.long 0x36C 4.--7. "MMC1_SDCD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x36C 0.--3. "MMC1_SDCD_MUXMODE,- MMC1_SDCD_0" "MMC1_SDCD_MUXMODE_0,?,?,MMC1_SDCD_MUXMODE_3,MMC1_SDCD_MUXMODE_4,?,?,?,?,?,?,?,?,?,MMC1_SDCD_MUXMODE_14,?" line.long 0x370 "CTRL_CORE_PAD_MMC1_SDWP," rbitfld.long 0x370 25. "MMC1_SDWP_WAKEUPEVENT,- NOWAKEUP" "MMC1_SDWP_WAKEUPEVENT_0,MMC1_SDWP_WAKEUPEVENT_1" newline bitfld.long 0x370 24. "MMC1_SDWP_WAKEUPENABLE,- DISABLE" "MMC1_SDWP_WAKEUPENABLE_0,MMC1_SDWP_WAKEUPENABLE_1" newline bitfld.long 0x370 19. "MMC1_SDWP_SLEWCONTROL,- SLOW_SLEW" "MMC1_SDWP_SLEWCONTROL_0,MMC1_SDWP_SLEWCONTROL_1" newline bitfld.long 0x370 18. "MMC1_SDWP_INPUTENABLE,- DISABLE" "MMC1_SDWP_INPUTENABLE_0,MMC1_SDWP_INPUTENABLE_1" newline bitfld.long 0x370 17. "MMC1_SDWP_PULLTYPESELECT,- PULL_DOWN" "MMC1_SDWP_PULLTYPESELECT_0,MMC1_SDWP_PULLTYPESELECT_1" newline bitfld.long 0x370 16. "MMC1_SDWP_PULLUDENABLE,- DISABLE" "MMC1_SDWP_PULLUDENABLE_0,MMC1_SDWP_PULLUDENABLE_1" newline bitfld.long 0x370 8. "MMC1_SDWP_MODESELECT,Selects between default and another IO delay different than the default one" "MMC1_SDWP_MODESELECT_0,MMC1_SDWP_MODESELECT_1" newline bitfld.long 0x370 4.--7. "MMC1_SDWP_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x370 0.--3. "MMC1_SDWP_MUXMODE,- MMC1_SDWP_0" "MMC1_SDWP_MUXMODE_0,?,?,MMC1_SDWP_MUXMODE_3,MMC1_SDWP_MUXMODE_4,?,?,?,?,?,?,?,?,?,MMC1_SDWP_MUXMODE_14,?" line.long 0x374 "CTRL_CORE_PAD_GPIO6_10," rbitfld.long 0x374 25. "GPIO6_10_WAKEUPEVENT,- NOWAKEUP" "GPIO6_10_WAKEUPEVENT_0,GPIO6_10_WAKEUPEVENT_1" newline bitfld.long 0x374 24. "GPIO6_10_WAKEUPENABLE,- DISABLE" "GPIO6_10_WAKEUPENABLE_0,GPIO6_10_WAKEUPENABLE_1" newline bitfld.long 0x374 19. "GPIO6_10_SLEWCONTROL,- SLOW_SLEW" "GPIO6_10_SLEWCONTROL_0,GPIO6_10_SLEWCONTROL_1" newline bitfld.long 0x374 18. "GPIO6_10_INPUTENABLE,- DISABLE" "GPIO6_10_INPUTENABLE_0,GPIO6_10_INPUTENABLE_1" newline bitfld.long 0x374 17. "GPIO6_10_PULLTYPESELECT,- PULL_DOWN" "GPIO6_10_PULLTYPESELECT_0,GPIO6_10_PULLTYPESELECT_1" newline bitfld.long 0x374 16. "GPIO6_10_PULLUDENABLE,- DISABLE" "GPIO6_10_PULLUDENABLE_0,GPIO6_10_PULLUDENABLE_1" newline bitfld.long 0x374 8. "GPIO6_10_MODESELECT,Selects between default and another IO delay different than the default one" "GPIO6_10_MODESELECT_0,GPIO6_10_MODESELECT_1" newline bitfld.long 0x374 4.--7. "GPIO6_10_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x374 0.--3. "GPIO6_10_MUXMODE,- PR2_PRU0_PRU_R300_13" "GPIO6_10_MUXMODE_0,GPIO6_10_MUXMODE_1,GPIO6_10_MUXMODE_2,GPIO6_10_MUXMODE_3,GPIO6_10_MUXMODE_4,?,?,?,?,GPIO6_10_MUXMODE_9,GPIO6_10_MUXMODE_10,GPIO6_10_MUXMODE_11,GPIO6_10_MUXMODE_12,GPIO6_10_MUXMODE_13,GPIO6_10_MUXMODE_14,?" line.long 0x378 "CTRL_CORE_PAD_GPIO6_11," rbitfld.long 0x378 25. "GPIO6_11_WAKEUPEVENT,- NOWAKEUP" "GPIO6_11_WAKEUPEVENT_0,GPIO6_11_WAKEUPEVENT_1" newline bitfld.long 0x378 24. "GPIO6_11_WAKEUPENABLE,- DISABLE" "GPIO6_11_WAKEUPENABLE_0,GPIO6_11_WAKEUPENABLE_1" newline bitfld.long 0x378 19. "GPIO6_11_SLEWCONTROL,- SLOW_SLEW" "GPIO6_11_SLEWCONTROL_0,GPIO6_11_SLEWCONTROL_1" newline bitfld.long 0x378 18. "GPIO6_11_INPUTENABLE,- DISABLE" "GPIO6_11_INPUTENABLE_0,GPIO6_11_INPUTENABLE_1" newline bitfld.long 0x378 17. "GPIO6_11_PULLTYPESELECT,- PULL_DOWN" "GPIO6_11_PULLTYPESELECT_0,GPIO6_11_PULLTYPESELECT_1" newline bitfld.long 0x378 16. "GPIO6_11_PULLUDENABLE,- DISABLE" "GPIO6_11_PULLUDENABLE_0,GPIO6_11_PULLUDENABLE_1" newline bitfld.long 0x378 8. "GPIO6_11_MODESELECT,Selects between default and another IO delay different than the default one" "GPIO6_11_MODESELECT_0,GPIO6_11_MODESELECT_1" newline bitfld.long 0x378 4.--7. "GPIO6_11_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x378 0.--3. "GPIO6_11_MUXMODE,- PR2_PRU0_PRU_R301_13" "GPIO6_11_MUXMODE_0,GPIO6_11_MUXMODE_1,GPIO6_11_MUXMODE_2,GPIO6_11_MUXMODE_3,GPIO6_11_MUXMODE_4,?,?,?,?,GPIO6_11_MUXMODE_9,GPIO6_11_MUXMODE_10,GPIO6_11_MUXMODE_11,GPIO6_11_MUXMODE_12,GPIO6_11_MUXMODE_13,GPIO6_11_MUXMODE_14,?" line.long 0x37C "CTRL_CORE_PAD_MMC3_CLK," rbitfld.long 0x37C 25. "MMC3_CLK_WAKEUPEVENT,- NOWAKEUP" "MMC3_CLK_WAKEUPEVENT_0,MMC3_CLK_WAKEUPEVENT_1" newline bitfld.long 0x37C 24. "MMC3_CLK_WAKEUPENABLE,- DISABLE" "MMC3_CLK_WAKEUPENABLE_0,MMC3_CLK_WAKEUPENABLE_1" newline bitfld.long 0x37C 19. "MMC3_CLK_SLEWCONTROL,- SLOW_SLEW" "MMC3_CLK_SLEWCONTROL_0,MMC3_CLK_SLEWCONTROL_1" newline bitfld.long 0x37C 18. "MMC3_CLK_INPUTENABLE,- DISABLE" "MMC3_CLK_INPUTENABLE_0,MMC3_CLK_INPUTENABLE_1" newline bitfld.long 0x37C 17. "MMC3_CLK_PULLTYPESELECT,- PULL_DOWN" "MMC3_CLK_PULLTYPESELECT_0,MMC3_CLK_PULLTYPESELECT_1" newline bitfld.long 0x37C 16. "MMC3_CLK_PULLUDENABLE,- DISABLE" "MMC3_CLK_PULLUDENABLE_0,MMC3_CLK_PULLUDENABLE_1" newline bitfld.long 0x37C 8. "MMC3_CLK_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_CLK_MODESELECT_0,MMC3_CLK_MODESELECT_1" newline bitfld.long 0x37C 4.--7. "MMC3_CLK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x37C 0.--3. "MMC3_CLK_MUXMODE,- PR2_PRU0_PRU_R302_13" "MMC3_CLK_MUXMODE_0,?,?,MMC3_CLK_MUXMODE_3,MMC3_CLK_MUXMODE_4,?,?,?,?,MMC3_CLK_MUXMODE_9,MMC3_CLK_MUXMODE_10,MMC3_CLK_MUXMODE_11,MMC3_CLK_MUXMODE_12,MMC3_CLK_MUXMODE_13,MMC3_CLK_MUXMODE_14,?" line.long 0x380 "CTRL_CORE_PAD_MMC3_CMD," rbitfld.long 0x380 25. "MMC3_CMD_WAKEUPEVENT,- NOWAKEUP" "MMC3_CMD_WAKEUPEVENT_0,MMC3_CMD_WAKEUPEVENT_1" newline bitfld.long 0x380 24. "MMC3_CMD_WAKEUPENABLE,- DISABLE" "MMC3_CMD_WAKEUPENABLE_0,MMC3_CMD_WAKEUPENABLE_1" newline bitfld.long 0x380 19. "MMC3_CMD_SLEWCONTROL,- SLOW_SLEW" "MMC3_CMD_SLEWCONTROL_0,MMC3_CMD_SLEWCONTROL_1" newline bitfld.long 0x380 18. "MMC3_CMD_INPUTENABLE,- DISABLE" "MMC3_CMD_INPUTENABLE_0,MMC3_CMD_INPUTENABLE_1" newline bitfld.long 0x380 17. "MMC3_CMD_PULLTYPESELECT,- PULL_DOWN" "MMC3_CMD_PULLTYPESELECT_0,MMC3_CMD_PULLTYPESELECT_1" newline bitfld.long 0x380 16. "MMC3_CMD_PULLUDENABLE,- DISABLE" "MMC3_CMD_PULLUDENABLE_0,MMC3_CMD_PULLUDENABLE_1" newline bitfld.long 0x380 8. "MMC3_CMD_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_CMD_MODESELECT_0,MMC3_CMD_MODESELECT_1" newline bitfld.long 0x380 4.--7. "MMC3_CMD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x380 0.--3. "MMC3_CMD_MUXMODE,- PR2_PRU0_PRU_R303_13" "MMC3_CMD_MUXMODE_0,MMC3_CMD_MUXMODE_1,?,MMC3_CMD_MUXMODE_3,MMC3_CMD_MUXMODE_4,?,?,?,?,MMC3_CMD_MUXMODE_9,MMC3_CMD_MUXMODE_10,MMC3_CMD_MUXMODE_11,MMC3_CMD_MUXMODE_12,MMC3_CMD_MUXMODE_13,MMC3_CMD_MUXMODE_14,?" line.long 0x384 "CTRL_CORE_PAD_MMC3_DAT0," rbitfld.long 0x384 25. "MMC3_DAT0_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT0_WAKEUPEVENT_0,MMC3_DAT0_WAKEUPEVENT_1" newline bitfld.long 0x384 24. "MMC3_DAT0_WAKEUPENABLE,- DISABLE" "MMC3_DAT0_WAKEUPENABLE_0,MMC3_DAT0_WAKEUPENABLE_1" newline bitfld.long 0x384 19. "MMC3_DAT0_SLEWCONTROL,- SLOW_SLEW" "MMC3_DAT0_SLEWCONTROL_0,MMC3_DAT0_SLEWCONTROL_1" newline bitfld.long 0x384 18. "MMC3_DAT0_INPUTENABLE,- DISABLE" "MMC3_DAT0_INPUTENABLE_0,MMC3_DAT0_INPUTENABLE_1" newline bitfld.long 0x384 17. "MMC3_DAT0_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT0_PULLTYPESELECT_0,MMC3_DAT0_PULLTYPESELECT_1" newline bitfld.long 0x384 16. "MMC3_DAT0_PULLUDENABLE,- DISABLE" "MMC3_DAT0_PULLUDENABLE_0,MMC3_DAT0_PULLUDENABLE_1" newline bitfld.long 0x384 8. "MMC3_DAT0_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_DAT0_MODESELECT_0,MMC3_DAT0_MODESELECT_1" newline bitfld.long 0x384 4.--7. "MMC3_DAT0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x384 0.--3. "MMC3_DAT0_MUXMODE,- PR2_PRU0_PRU_R304_13" "MMC3_DAT0_MUXMODE_0,MMC3_DAT0_MUXMODE_1,MMC3_DAT0_MUXMODE_2,MMC3_DAT0_MUXMODE_3,MMC3_DAT0_MUXMODE_4,?,?,?,?,MMC3_DAT0_MUXMODE_9,MMC3_DAT0_MUXMODE_10,MMC3_DAT0_MUXMODE_11,MMC3_DAT0_MUXMODE_12,MMC3_DAT0_MUXMODE_13,MMC3_DAT0_MUXMODE_14,?" line.long 0x388 "CTRL_CORE_PAD_MMC3_DAT1," rbitfld.long 0x388 25. "MMC3_DAT1_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT1_WAKEUPEVENT_0,MMC3_DAT1_WAKEUPEVENT_1" newline bitfld.long 0x388 24. "MMC3_DAT1_WAKEUPENABLE,- DISABLE" "MMC3_DAT1_WAKEUPENABLE_0,MMC3_DAT1_WAKEUPENABLE_1" newline bitfld.long 0x388 19. "MMC3_DAT1_SLEWCONTROL,- SLOW_SLEW" "MMC3_DAT1_SLEWCONTROL_0,MMC3_DAT1_SLEWCONTROL_1" newline bitfld.long 0x388 18. "MMC3_DAT1_INPUTENABLE,- DISABLE" "MMC3_DAT1_INPUTENABLE_0,MMC3_DAT1_INPUTENABLE_1" newline bitfld.long 0x388 17. "MMC3_DAT1_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT1_PULLTYPESELECT_0,MMC3_DAT1_PULLTYPESELECT_1" newline bitfld.long 0x388 16. "MMC3_DAT1_PULLUDENABLE,- DISABLE" "MMC3_DAT1_PULLUDENABLE_0,MMC3_DAT1_PULLUDENABLE_1" newline bitfld.long 0x388 8. "MMC3_DAT1_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_DAT1_MODESELECT_0,MMC3_DAT1_MODESELECT_1" newline bitfld.long 0x388 4.--7. "MMC3_DAT1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x388 0.--3. "MMC3_DAT1_MUXMODE,- PR2_PRU0_PRU_R305_13" "MMC3_DAT1_MUXMODE_0,MMC3_DAT1_MUXMODE_1,MMC3_DAT1_MUXMODE_2,MMC3_DAT1_MUXMODE_3,MMC3_DAT1_MUXMODE_4,?,?,?,?,MMC3_DAT1_MUXMODE_9,MMC3_DAT1_MUXMODE_10,MMC3_DAT1_MUXMODE_11,MMC3_DAT1_MUXMODE_12,MMC3_DAT1_MUXMODE_13,MMC3_DAT1_MUXMODE_14,?" line.long 0x38C "CTRL_CORE_PAD_MMC3_DAT2," rbitfld.long 0x38C 25. "MMC3_DAT2_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT2_WAKEUPEVENT_0,MMC3_DAT2_WAKEUPEVENT_1" newline bitfld.long 0x38C 24. "MMC3_DAT2_WAKEUPENABLE,- DISABLE" "MMC3_DAT2_WAKEUPENABLE_0,MMC3_DAT2_WAKEUPENABLE_1" newline bitfld.long 0x38C 19. "MMC3_DAT2_SLEWCONTROL,- SLOW_SLEW" "MMC3_DAT2_SLEWCONTROL_0,MMC3_DAT2_SLEWCONTROL_1" newline bitfld.long 0x38C 18. "MMC3_DAT2_INPUTENABLE,- DISABLE" "MMC3_DAT2_INPUTENABLE_0,MMC3_DAT2_INPUTENABLE_1" newline bitfld.long 0x38C 17. "MMC3_DAT2_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT2_PULLTYPESELECT_0,MMC3_DAT2_PULLTYPESELECT_1" newline bitfld.long 0x38C 16. "MMC3_DAT2_PULLUDENABLE,- DISABLE" "MMC3_DAT2_PULLUDENABLE_0,MMC3_DAT2_PULLUDENABLE_1" newline bitfld.long 0x38C 8. "MMC3_DAT2_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_DAT2_MODESELECT_0,MMC3_DAT2_MODESELECT_1" newline bitfld.long 0x38C 4.--7. "MMC3_DAT2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38C 0.--3. "MMC3_DAT2_MUXMODE,- PR2_PRU0_PRU_R306_13" "MMC3_DAT2_MUXMODE_0,MMC3_DAT2_MUXMODE_1,MMC3_DAT2_MUXMODE_2,MMC3_DAT2_MUXMODE_3,MMC3_DAT2_MUXMODE_4,?,?,?,?,MMC3_DAT2_MUXMODE_9,MMC3_DAT2_MUXMODE_10,MMC3_DAT2_MUXMODE_11,MMC3_DAT2_MUXMODE_12,MMC3_DAT2_MUXMODE_13,MMC3_DAT2_MUXMODE_14,?" line.long 0x390 "CTRL_CORE_PAD_MMC3_DAT3," rbitfld.long 0x390 25. "MMC3_DAT3_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT3_WAKEUPEVENT_0,MMC3_DAT3_WAKEUPEVENT_1" newline bitfld.long 0x390 24. "MMC3_DAT3_WAKEUPENABLE,- DISABLE" "MMC3_DAT3_WAKEUPENABLE_0,MMC3_DAT3_WAKEUPENABLE_1" newline bitfld.long 0x390 19. "MMC3_DAT3_SLEWCONTROL,- SLOW_SLEW" "MMC3_DAT3_SLEWCONTROL_0,MMC3_DAT3_SLEWCONTROL_1" newline bitfld.long 0x390 18. "MMC3_DAT3_INPUTENABLE,- DISABLE" "MMC3_DAT3_INPUTENABLE_0,MMC3_DAT3_INPUTENABLE_1" newline bitfld.long 0x390 17. "MMC3_DAT3_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT3_PULLTYPESELECT_0,MMC3_DAT3_PULLTYPESELECT_1" newline bitfld.long 0x390 16. "MMC3_DAT3_PULLUDENABLE,- DISABLE" "MMC3_DAT3_PULLUDENABLE_0,MMC3_DAT3_PULLUDENABLE_1" newline bitfld.long 0x390 8. "MMC3_DAT3_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_DAT3_MODESELECT_0,MMC3_DAT3_MODESELECT_1" newline bitfld.long 0x390 4.--7. "MMC3_DAT3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x390 0.--3. "MMC3_DAT3_MUXMODE,- PR2_PRU0_PRU_R307_13" "MMC3_DAT3_MUXMODE_0,MMC3_DAT3_MUXMODE_1,MMC3_DAT3_MUXMODE_2,MMC3_DAT3_MUXMODE_3,MMC3_DAT3_MUXMODE_4,?,?,?,?,MMC3_DAT3_MUXMODE_9,MMC3_DAT3_MUXMODE_10,MMC3_DAT3_MUXMODE_11,MMC3_DAT3_MUXMODE_12,MMC3_DAT3_MUXMODE_13,MMC3_DAT3_MUXMODE_14,?" line.long 0x394 "CTRL_CORE_PAD_MMC3_DAT4," rbitfld.long 0x394 25. "MMC3_DAT4_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT4_WAKEUPEVENT_0,MMC3_DAT4_WAKEUPEVENT_1" newline bitfld.long 0x394 24. "MMC3_DAT4_WAKEUPENABLE,- DISABLE" "MMC3_DAT4_WAKEUPENABLE_0,MMC3_DAT4_WAKEUPENABLE_1" newline bitfld.long 0x394 19. "MMC3_DAT4_SLEWCONTROL,- SLOW_SLEW" "MMC3_DAT4_SLEWCONTROL_0,MMC3_DAT4_SLEWCONTROL_1" newline bitfld.long 0x394 18. "MMC3_DAT4_INPUTENABLE,- DISABLE" "MMC3_DAT4_INPUTENABLE_0,MMC3_DAT4_INPUTENABLE_1" newline bitfld.long 0x394 17. "MMC3_DAT4_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT4_PULLTYPESELECT_0,MMC3_DAT4_PULLTYPESELECT_1" newline bitfld.long 0x394 16. "MMC3_DAT4_PULLUDENABLE,- DISABLE" "MMC3_DAT4_PULLUDENABLE_0,MMC3_DAT4_PULLUDENABLE_1" newline bitfld.long 0x394 8. "MMC3_DAT4_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_DAT4_MODESELECT_0,MMC3_DAT4_MODESELECT_1" newline bitfld.long 0x394 4.--7. "MMC3_DAT4_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x394 0.--3. "MMC3_DAT4_MUXMODE,- PR2_PRU0_PRU_R308_13" "MMC3_DAT4_MUXMODE_0,MMC3_DAT4_MUXMODE_1,MMC3_DAT4_MUXMODE_2,MMC3_DAT4_MUXMODE_3,MMC3_DAT4_MUXMODE_4,?,?,?,?,MMC3_DAT4_MUXMODE_9,MMC3_DAT4_MUXMODE_10,MMC3_DAT4_MUXMODE_11,MMC3_DAT4_MUXMODE_12,MMC3_DAT4_MUXMODE_13,MMC3_DAT4_MUXMODE_14,?" line.long 0x398 "CTRL_CORE_PAD_MMC3_DAT5," rbitfld.long 0x398 25. "MMC3_DAT5_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT5_WAKEUPEVENT_0,MMC3_DAT5_WAKEUPEVENT_1" newline bitfld.long 0x398 24. "MMC3_DAT5_WAKEUPENABLE,- DISABLE" "MMC3_DAT5_WAKEUPENABLE_0,MMC3_DAT5_WAKEUPENABLE_1" newline bitfld.long 0x398 19. "MMC3_DAT5_SLEWCONTROL,- SLOW_SLEW" "MMC3_DAT5_SLEWCONTROL_0,MMC3_DAT5_SLEWCONTROL_1" newline bitfld.long 0x398 18. "MMC3_DAT5_INPUTENABLE,- DISABLE" "MMC3_DAT5_INPUTENABLE_0,MMC3_DAT5_INPUTENABLE_1" newline bitfld.long 0x398 17. "MMC3_DAT5_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT5_PULLTYPESELECT_0,MMC3_DAT5_PULLTYPESELECT_1" newline bitfld.long 0x398 16. "MMC3_DAT5_PULLUDENABLE,- DISABLE" "MMC3_DAT5_PULLUDENABLE_0,MMC3_DAT5_PULLUDENABLE_1" newline bitfld.long 0x398 8. "MMC3_DAT5_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_DAT5_MODESELECT_0,MMC3_DAT5_MODESELECT_1" newline bitfld.long 0x398 4.--7. "MMC3_DAT5_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x398 0.--3. "MMC3_DAT5_MUXMODE,- PR2_PRU0_PRU_R309_13" "MMC3_DAT5_MUXMODE_0,MMC3_DAT5_MUXMODE_1,MMC3_DAT5_MUXMODE_2,MMC3_DAT5_MUXMODE_3,MMC3_DAT5_MUXMODE_4,?,?,?,?,MMC3_DAT5_MUXMODE_9,MMC3_DAT5_MUXMODE_10,MMC3_DAT5_MUXMODE_11,MMC3_DAT5_MUXMODE_12,MMC3_DAT5_MUXMODE_13,MMC3_DAT5_MUXMODE_14,?" line.long 0x39C "CTRL_CORE_PAD_MMC3_DAT6," rbitfld.long 0x39C 25. "MMC3_DAT6_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT6_WAKEUPEVENT_0,MMC3_DAT6_WAKEUPEVENT_1" newline bitfld.long 0x39C 24. "MMC3_DAT6_WAKEUPENABLE,- DISABLE" "MMC3_DAT6_WAKEUPENABLE_0,MMC3_DAT6_WAKEUPENABLE_1" newline bitfld.long 0x39C 19. "MMC3_DAT6_SLEWCONTROL,- SLOW_SLEW" "MMC3_DAT6_SLEWCONTROL_0,MMC3_DAT6_SLEWCONTROL_1" newline bitfld.long 0x39C 18. "MMC3_DAT6_INPUTENABLE,- DISABLE" "MMC3_DAT6_INPUTENABLE_0,MMC3_DAT6_INPUTENABLE_1" newline bitfld.long 0x39C 17. "MMC3_DAT6_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT6_PULLTYPESELECT_0,MMC3_DAT6_PULLTYPESELECT_1" newline bitfld.long 0x39C 16. "MMC3_DAT6_PULLUDENABLE,- DISABLE" "MMC3_DAT6_PULLUDENABLE_0,MMC3_DAT6_PULLUDENABLE_1" newline bitfld.long 0x39C 8. "MMC3_DAT6_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_DAT6_MODESELECT_0,MMC3_DAT6_MODESELECT_1" newline bitfld.long 0x39C 4.--7. "MMC3_DAT6_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x39C 0.--3. "MMC3_DAT6_MUXMODE,- PR2_PRU0_PRU_R3010_13" "MMC3_DAT6_MUXMODE_0,MMC3_DAT6_MUXMODE_1,MMC3_DAT6_MUXMODE_2,MMC3_DAT6_MUXMODE_3,MMC3_DAT6_MUXMODE_4,?,?,?,?,MMC3_DAT6_MUXMODE_9,MMC3_DAT6_MUXMODE_10,MMC3_DAT6_MUXMODE_11,MMC3_DAT6_MUXMODE_12,MMC3_DAT6_MUXMODE_13,MMC3_DAT6_MUXMODE_14,?" line.long 0x3A0 "CTRL_CORE_PAD_MMC3_DAT7," rbitfld.long 0x3A0 25. "MMC3_DAT7_WAKEUPEVENT,- NOWAKEUP" "MMC3_DAT7_WAKEUPEVENT_0,MMC3_DAT7_WAKEUPEVENT_1" newline bitfld.long 0x3A0 24. "MMC3_DAT7_WAKEUPENABLE,- DISABLE" "MMC3_DAT7_WAKEUPENABLE_0,MMC3_DAT7_WAKEUPENABLE_1" newline bitfld.long 0x3A0 19. "MMC3_DAT7_SLEWCONTROL,- SLOW_SLEW" "MMC3_DAT7_SLEWCONTROL_0,MMC3_DAT7_SLEWCONTROL_1" newline bitfld.long 0x3A0 18. "MMC3_DAT7_INPUTENABLE,- DISABLE" "MMC3_DAT7_INPUTENABLE_0,MMC3_DAT7_INPUTENABLE_1" newline bitfld.long 0x3A0 17. "MMC3_DAT7_PULLTYPESELECT,- PULL_DOWN" "MMC3_DAT7_PULLTYPESELECT_0,MMC3_DAT7_PULLTYPESELECT_1" newline bitfld.long 0x3A0 16. "MMC3_DAT7_PULLUDENABLE,- DISABLE" "MMC3_DAT7_PULLUDENABLE_0,MMC3_DAT7_PULLUDENABLE_1" newline bitfld.long 0x3A0 8. "MMC3_DAT7_MODESELECT,Selects between default and another IO delay different than the default one" "MMC3_DAT7_MODESELECT_0,MMC3_DAT7_MODESELECT_1" newline bitfld.long 0x3A0 4.--7. "MMC3_DAT7_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3A0 0.--3. "MMC3_DAT7_MUXMODE,- PR2_PRU0_PRU_R3011_13" "MMC3_DAT7_MUXMODE_0,MMC3_DAT7_MUXMODE_1,MMC3_DAT7_MUXMODE_2,MMC3_DAT7_MUXMODE_3,MMC3_DAT7_MUXMODE_4,?,?,?,?,MMC3_DAT7_MUXMODE_9,MMC3_DAT7_MUXMODE_10,MMC3_DAT7_MUXMODE_11,MMC3_DAT7_MUXMODE_12,MMC3_DAT7_MUXMODE_13,MMC3_DAT7_MUXMODE_14,?" line.long 0x3A4 "CTRL_CORE_PAD_SPI1_SCLK," rbitfld.long 0x3A4 25. "SPI1_SCLK_WAKEUPEVENT,- NOWAKEUP" "SPI1_SCLK_WAKEUPEVENT_0,SPI1_SCLK_WAKEUPEVENT_1" newline bitfld.long 0x3A4 24. "SPI1_SCLK_WAKEUPENABLE,- DISABLE" "SPI1_SCLK_WAKEUPENABLE_0,SPI1_SCLK_WAKEUPENABLE_1" newline bitfld.long 0x3A4 19. "SPI1_SCLK_SLEWCONTROL,- SLOW_SLEW" "SPI1_SCLK_SLEWCONTROL_0,SPI1_SCLK_SLEWCONTROL_1" newline bitfld.long 0x3A4 18. "SPI1_SCLK_INPUTENABLE,- DISABLE" "SPI1_SCLK_INPUTENABLE_0,SPI1_SCLK_INPUTENABLE_1" newline bitfld.long 0x3A4 17. "SPI1_SCLK_PULLTYPESELECT,- PULL_DOWN" "SPI1_SCLK_PULLTYPESELECT_0,SPI1_SCLK_PULLTYPESELECT_1" newline bitfld.long 0x3A4 16. "SPI1_SCLK_PULLUDENABLE,- DISABLE" "SPI1_SCLK_PULLUDENABLE_0,SPI1_SCLK_PULLUDENABLE_1" newline bitfld.long 0x3A4 8. "SPI1_SCLK_MODESELECT,Selects between default and another IO delay different than the default one" "SPI1_SCLK_MODESELECT_0,SPI1_SCLK_MODESELECT_1" newline bitfld.long 0x3A4 4.--7. "SPI1_SCLK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3A4 0.--3. "SPI1_SCLK_MUXMODE,- SPI1_SCLK_0" "SPI1_SCLK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_SCLK_MUXMODE_14,?" line.long 0x3A8 "CTRL_CORE_PAD_SPI1_D1," rbitfld.long 0x3A8 25. "SPI1_D1_WAKEUPEVENT,- NOWAKEUP" "SPI1_D1_WAKEUPEVENT_0,SPI1_D1_WAKEUPEVENT_1" newline bitfld.long 0x3A8 24. "SPI1_D1_WAKEUPENABLE,- DISABLE" "SPI1_D1_WAKEUPENABLE_0,SPI1_D1_WAKEUPENABLE_1" newline bitfld.long 0x3A8 19. "SPI1_D1_SLEWCONTROL,- SLOW_SLEW" "SPI1_D1_SLEWCONTROL_0,SPI1_D1_SLEWCONTROL_1" newline bitfld.long 0x3A8 18. "SPI1_D1_INPUTENABLE,- DISABLE" "SPI1_D1_INPUTENABLE_0,SPI1_D1_INPUTENABLE_1" newline bitfld.long 0x3A8 17. "SPI1_D1_PULLTYPESELECT,- PULL_DOWN" "SPI1_D1_PULLTYPESELECT_0,SPI1_D1_PULLTYPESELECT_1" newline bitfld.long 0x3A8 16. "SPI1_D1_PULLUDENABLE,- DISABLE" "SPI1_D1_PULLUDENABLE_0,SPI1_D1_PULLUDENABLE_1" newline bitfld.long 0x3A8 8. "SPI1_D1_MODESELECT,Selects between default and another IO delay different than the default one" "SPI1_D1_MODESELECT_0,SPI1_D1_MODESELECT_1" newline bitfld.long 0x3A8 4.--7. "SPI1_D1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3A8 0.--3. "SPI1_D1_MUXMODE,- SPI1_D1_0" "SPI1_D1_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_D1_MUXMODE_14,?" line.long 0x3AC "CTRL_CORE_PAD_SPI1_D0," rbitfld.long 0x3AC 25. "SPI1_D0_WAKEUPEVENT,- NOWAKEUP" "SPI1_D0_WAKEUPEVENT_0,SPI1_D0_WAKEUPEVENT_1" newline bitfld.long 0x3AC 24. "SPI1_D0_WAKEUPENABLE,- DISABLE" "SPI1_D0_WAKEUPENABLE_0,SPI1_D0_WAKEUPENABLE_1" newline bitfld.long 0x3AC 19. "SPI1_D0_SLEWCONTROL,- SLOW_SLEW" "SPI1_D0_SLEWCONTROL_0,SPI1_D0_SLEWCONTROL_1" newline bitfld.long 0x3AC 18. "SPI1_D0_INPUTENABLE,- DISABLE" "SPI1_D0_INPUTENABLE_0,SPI1_D0_INPUTENABLE_1" newline bitfld.long 0x3AC 17. "SPI1_D0_PULLTYPESELECT,- PULL_DOWN" "SPI1_D0_PULLTYPESELECT_0,SPI1_D0_PULLTYPESELECT_1" newline bitfld.long 0x3AC 16. "SPI1_D0_PULLUDENABLE,- DISABLE" "SPI1_D0_PULLUDENABLE_0,SPI1_D0_PULLUDENABLE_1" newline bitfld.long 0x3AC 8. "SPI1_D0_MODESELECT,Selects between default and another IO delay different than the default one" "SPI1_D0_MODESELECT_0,SPI1_D0_MODESELECT_1" newline bitfld.long 0x3AC 4.--7. "SPI1_D0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3AC 0.--3. "SPI1_D0_MUXMODE,- SPI1_D0_0" "SPI1_D0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_D0_MUXMODE_14,?" line.long 0x3B0 "CTRL_CORE_PAD_SPI1_CS0," rbitfld.long 0x3B0 25. "SPI1_CS0_WAKEUPEVENT,- NOWAKEUP" "SPI1_CS0_WAKEUPEVENT_0,SPI1_CS0_WAKEUPEVENT_1" newline bitfld.long 0x3B0 24. "SPI1_CS0_WAKEUPENABLE,- DISABLE" "SPI1_CS0_WAKEUPENABLE_0,SPI1_CS0_WAKEUPENABLE_1" newline bitfld.long 0x3B0 19. "SPI1_CS0_SLEWCONTROL,- SLOW_SLEW" "SPI1_CS0_SLEWCONTROL_0,SPI1_CS0_SLEWCONTROL_1" newline bitfld.long 0x3B0 18. "SPI1_CS0_INPUTENABLE,- DISABLE" "SPI1_CS0_INPUTENABLE_0,SPI1_CS0_INPUTENABLE_1" newline bitfld.long 0x3B0 17. "SPI1_CS0_PULLTYPESELECT,- PULL_DOWN" "SPI1_CS0_PULLTYPESELECT_0,SPI1_CS0_PULLTYPESELECT_1" newline bitfld.long 0x3B0 16. "SPI1_CS0_PULLUDENABLE,- DISABLE" "SPI1_CS0_PULLUDENABLE_0,SPI1_CS0_PULLUDENABLE_1" newline bitfld.long 0x3B0 8. "SPI1_CS0_MODESELECT,Selects between default and another IO delay different than the default one" "SPI1_CS0_MODESELECT_0,SPI1_CS0_MODESELECT_1" newline bitfld.long 0x3B0 4.--7. "SPI1_CS0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3B0 0.--3. "SPI1_CS0_MUXMODE,- SPI1_CS0_0" "SPI1_CS0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,SPI1_CS0_MUXMODE_14,?" line.long 0x3B4 "CTRL_CORE_PAD_SPI1_CS1," rbitfld.long 0x3B4 25. "SPI1_CS1_WAKEUPEVENT,- NOWAKEUP" "SPI1_CS1_WAKEUPEVENT_0,SPI1_CS1_WAKEUPEVENT_1" newline bitfld.long 0x3B4 24. "SPI1_CS1_WAKEUPENABLE,- DISABLE" "SPI1_CS1_WAKEUPENABLE_0,SPI1_CS1_WAKEUPENABLE_1" newline bitfld.long 0x3B4 19. "SPI1_CS1_SLEWCONTROL,- SLOW_SLEW" "SPI1_CS1_SLEWCONTROL_0,SPI1_CS1_SLEWCONTROL_1" newline bitfld.long 0x3B4 18. "SPI1_CS1_INPUTENABLE,- DISABLE" "SPI1_CS1_INPUTENABLE_0,SPI1_CS1_INPUTENABLE_1" newline bitfld.long 0x3B4 17. "SPI1_CS1_PULLTYPESELECT,- PULL_DOWN" "SPI1_CS1_PULLTYPESELECT_0,SPI1_CS1_PULLTYPESELECT_1" newline bitfld.long 0x3B4 16. "SPI1_CS1_PULLUDENABLE,- DISABLE" "SPI1_CS1_PULLUDENABLE_0,SPI1_CS1_PULLUDENABLE_1" newline bitfld.long 0x3B4 8. "SPI1_CS1_MODESELECT,Selects between default and another IO delay different than the default one" "SPI1_CS1_MODESELECT_0,SPI1_CS1_MODESELECT_1" newline bitfld.long 0x3B4 4.--7. "SPI1_CS1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3B4 0.--3. "SPI1_CS1_MUXMODE,- SPI1_CS1_0" "SPI1_CS1_MUXMODE_0,SPI1_CS1_MUXMODE_1,SPI1_CS1_MUXMODE_2,SPI1_CS1_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,SPI1_CS1_MUXMODE_14,?" line.long 0x3B8 "CTRL_CORE_PAD_SPI1_CS2," rbitfld.long 0x3B8 25. "SPI1_CS2_WAKEUPEVENT,- NOWAKEUP" "SPI1_CS2_WAKEUPEVENT_0,SPI1_CS2_WAKEUPEVENT_1" newline bitfld.long 0x3B8 24. "SPI1_CS2_WAKEUPENABLE,- DISABLE" "SPI1_CS2_WAKEUPENABLE_0,SPI1_CS2_WAKEUPENABLE_1" newline bitfld.long 0x3B8 19. "SPI1_CS2_SLEWCONTROL,- SLOW_SLEW" "SPI1_CS2_SLEWCONTROL_0,SPI1_CS2_SLEWCONTROL_1" newline bitfld.long 0x3B8 18. "SPI1_CS2_INPUTENABLE,- DISABLE" "SPI1_CS2_INPUTENABLE_0,SPI1_CS2_INPUTENABLE_1" newline bitfld.long 0x3B8 17. "SPI1_CS2_PULLTYPESELECT,- PULL_DOWN" "SPI1_CS2_PULLTYPESELECT_0,SPI1_CS2_PULLTYPESELECT_1" newline bitfld.long 0x3B8 16. "SPI1_CS2_PULLUDENABLE,- DISABLE" "SPI1_CS2_PULLUDENABLE_0,SPI1_CS2_PULLUDENABLE_1" newline bitfld.long 0x3B8 8. "SPI1_CS2_MODESELECT,Selects between default and another IO delay different than the default one" "SPI1_CS2_MODESELECT_0,SPI1_CS2_MODESELECT_1" newline bitfld.long 0x3B8 4.--7. "SPI1_CS2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3B8 0.--3. "SPI1_CS2_MUXMODE,- HDMI1_HPD_6" "SPI1_CS2_MUXMODE_0,SPI1_CS2_MUXMODE_1,SPI1_CS2_MUXMODE_2,SPI1_CS2_MUXMODE_3,SPI1_CS2_MUXMODE_4,SPI1_CS2_MUXMODE_5,SPI1_CS2_MUXMODE_6,SPI1_CS2_MUXMODE_7,?,?,?,?,?,?,SPI1_CS2_MUXMODE_14,?" line.long 0x3BC "CTRL_CORE_PAD_SPI1_CS3," rbitfld.long 0x3BC 25. "SPI1_CS3_WAKEUPEVENT,- NOWAKEUP" "SPI1_CS3_WAKEUPEVENT_0,SPI1_CS3_WAKEUPEVENT_1" newline bitfld.long 0x3BC 24. "SPI1_CS3_WAKEUPENABLE,- DISABLE" "SPI1_CS3_WAKEUPENABLE_0,SPI1_CS3_WAKEUPENABLE_1" newline bitfld.long 0x3BC 19. "SPI1_CS3_SLEWCONTROL,- SLOW_SLEW" "SPI1_CS3_SLEWCONTROL_0,SPI1_CS3_SLEWCONTROL_1" newline bitfld.long 0x3BC 18. "SPI1_CS3_INPUTENABLE,- DISABLE" "SPI1_CS3_INPUTENABLE_0,SPI1_CS3_INPUTENABLE_1" newline bitfld.long 0x3BC 17. "SPI1_CS3_PULLTYPESELECT,- PULL_DOWN" "SPI1_CS3_PULLTYPESELECT_0,SPI1_CS3_PULLTYPESELECT_1" newline bitfld.long 0x3BC 16. "SPI1_CS3_PULLUDENABLE,- DISABLE" "SPI1_CS3_PULLUDENABLE_0,SPI1_CS3_PULLUDENABLE_1" newline bitfld.long 0x3BC 8. "SPI1_CS3_MODESELECT,Selects between default and another IO delay different than the default one" "SPI1_CS3_MODESELECT_0,SPI1_CS3_MODESELECT_1" newline bitfld.long 0x3BC 4.--7. "SPI1_CS3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3BC 0.--3. "SPI1_CS3_MUXMODE,- HDMI1_CEC_6" "SPI1_CS3_MUXMODE_0,SPI1_CS3_MUXMODE_1,SPI1_CS3_MUXMODE_2,SPI1_CS3_MUXMODE_3,SPI1_CS3_MUXMODE_4,SPI1_CS3_MUXMODE_5,SPI1_CS3_MUXMODE_6,SPI1_CS3_MUXMODE_7,?,?,?,?,?,?,SPI1_CS3_MUXMODE_14,?" line.long 0x3C0 "CTRL_CORE_PAD_SPI2_SCLK," rbitfld.long 0x3C0 25. "SPI2_SCLK_WAKEUPEVENT,- NOWAKEUP" "SPI2_SCLK_WAKEUPEVENT_0,SPI2_SCLK_WAKEUPEVENT_1" newline bitfld.long 0x3C0 24. "SPI2_SCLK_WAKEUPENABLE,- DISABLE" "SPI2_SCLK_WAKEUPENABLE_0,SPI2_SCLK_WAKEUPENABLE_1" newline bitfld.long 0x3C0 19. "SPI2_SCLK_SLEWCONTROL,- SLOW_SLEW" "SPI2_SCLK_SLEWCONTROL_0,SPI2_SCLK_SLEWCONTROL_1" newline bitfld.long 0x3C0 18. "SPI2_SCLK_INPUTENABLE,- DISABLE" "SPI2_SCLK_INPUTENABLE_0,SPI2_SCLK_INPUTENABLE_1" newline bitfld.long 0x3C0 17. "SPI2_SCLK_PULLTYPESELECT,- PULL_DOWN" "SPI2_SCLK_PULLTYPESELECT_0,SPI2_SCLK_PULLTYPESELECT_1" newline bitfld.long 0x3C0 16. "SPI2_SCLK_PULLUDENABLE,- DISABLE" "SPI2_SCLK_PULLUDENABLE_0,SPI2_SCLK_PULLUDENABLE_1" newline bitfld.long 0x3C0 8. "SPI2_SCLK_MODESELECT,Selects between default and another IO delay different than the default one" "SPI2_SCLK_MODESELECT_0,SPI2_SCLK_MODESELECT_1" newline bitfld.long 0x3C0 4.--7. "SPI2_SCLK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C0 0.--3. "SPI2_SCLK_MUXMODE,- SPI2_SCLK_0" "SPI2_SCLK_MUXMODE_0,SPI2_SCLK_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI2_SCLK_MUXMODE_14,?" line.long 0x3C4 "CTRL_CORE_PAD_SPI2_D1," rbitfld.long 0x3C4 25. "SPI2_D1_WAKEUPEVENT,- NOWAKEUP" "SPI2_D1_WAKEUPEVENT_0,SPI2_D1_WAKEUPEVENT_1" newline bitfld.long 0x3C4 24. "SPI2_D1_WAKEUPENABLE,- DISABLE" "SPI2_D1_WAKEUPENABLE_0,SPI2_D1_WAKEUPENABLE_1" newline bitfld.long 0x3C4 19. "SPI2_D1_SLEWCONTROL,- SLOW_SLEW" "SPI2_D1_SLEWCONTROL_0,SPI2_D1_SLEWCONTROL_1" newline bitfld.long 0x3C4 18. "SPI2_D1_INPUTENABLE,- DISABLE" "SPI2_D1_INPUTENABLE_0,SPI2_D1_INPUTENABLE_1" newline bitfld.long 0x3C4 17. "SPI2_D1_PULLTYPESELECT,- PULL_DOWN" "SPI2_D1_PULLTYPESELECT_0,SPI2_D1_PULLTYPESELECT_1" newline bitfld.long 0x3C4 16. "SPI2_D1_PULLUDENABLE,- DISABLE" "SPI2_D1_PULLUDENABLE_0,SPI2_D1_PULLUDENABLE_1" newline bitfld.long 0x3C4 8. "SPI2_D1_MODESELECT,Selects between default and another IO delay different than the default one" "SPI2_D1_MODESELECT_0,SPI2_D1_MODESELECT_1" newline bitfld.long 0x3C4 4.--7. "SPI2_D1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C4 0.--3. "SPI2_D1_MUXMODE,- SPI2_D1_0" "SPI2_D1_MUXMODE_0,SPI2_D1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,SPI2_D1_MUXMODE_14,?" line.long 0x3C8 "CTRL_CORE_PAD_SPI2_D0," rbitfld.long 0x3C8 25. "SPI2_D0_WAKEUPEVENT,- NOWAKEUP" "SPI2_D0_WAKEUPEVENT_0,SPI2_D0_WAKEUPEVENT_1" newline bitfld.long 0x3C8 24. "SPI2_D0_WAKEUPENABLE,- DISABLE" "SPI2_D0_WAKEUPENABLE_0,SPI2_D0_WAKEUPENABLE_1" newline bitfld.long 0x3C8 19. "SPI2_D0_SLEWCONTROL,- SLOW_SLEW" "SPI2_D0_SLEWCONTROL_0,SPI2_D0_SLEWCONTROL_1" newline bitfld.long 0x3C8 18. "SPI2_D0_INPUTENABLE,- DISABLE" "SPI2_D0_INPUTENABLE_0,SPI2_D0_INPUTENABLE_1" newline bitfld.long 0x3C8 17. "SPI2_D0_PULLTYPESELECT,- PULL_DOWN" "SPI2_D0_PULLTYPESELECT_0,SPI2_D0_PULLTYPESELECT_1" newline bitfld.long 0x3C8 16. "SPI2_D0_PULLUDENABLE,- DISABLE" "SPI2_D0_PULLUDENABLE_0,SPI2_D0_PULLUDENABLE_1" newline bitfld.long 0x3C8 8. "SPI2_D0_MODESELECT,Selects between default and another IO delay different than the default one" "SPI2_D0_MODESELECT_0,SPI2_D0_MODESELECT_1" newline bitfld.long 0x3C8 4.--7. "SPI2_D0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3C8 0.--3. "SPI2_D0_MUXMODE,- SPI2_D0_0" "SPI2_D0_MUXMODE_0,SPI2_D0_MUXMODE_1,SPI2_D0_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,SPI2_D0_MUXMODE_14,?" line.long 0x3CC "CTRL_CORE_PAD_SPI2_CS0," rbitfld.long 0x3CC 25. "SPI2_CS0_WAKEUPEVENT,- NOWAKEUP" "SPI2_CS0_WAKEUPEVENT_0,SPI2_CS0_WAKEUPEVENT_1" newline bitfld.long 0x3CC 24. "SPI2_CS0_WAKEUPENABLE,- DISABLE" "SPI2_CS0_WAKEUPENABLE_0,SPI2_CS0_WAKEUPENABLE_1" newline bitfld.long 0x3CC 19. "SPI2_CS0_SLEWCONTROL,- SLOW_SLEW" "SPI2_CS0_SLEWCONTROL_0,SPI2_CS0_SLEWCONTROL_1" newline bitfld.long 0x3CC 18. "SPI2_CS0_INPUTENABLE,- DISABLE" "SPI2_CS0_INPUTENABLE_0,SPI2_CS0_INPUTENABLE_1" newline bitfld.long 0x3CC 17. "SPI2_CS0_PULLTYPESELECT,- PULL_DOWN" "SPI2_CS0_PULLTYPESELECT_0,SPI2_CS0_PULLTYPESELECT_1" newline bitfld.long 0x3CC 16. "SPI2_CS0_PULLUDENABLE,- DISABLE" "SPI2_CS0_PULLUDENABLE_0,SPI2_CS0_PULLUDENABLE_1" newline bitfld.long 0x3CC 8. "SPI2_CS0_MODESELECT,Selects between default and another IO delay different than the default one" "SPI2_CS0_MODESELECT_0,SPI2_CS0_MODESELECT_1" newline bitfld.long 0x3CC 4.--7. "SPI2_CS0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3CC 0.--3. "SPI2_CS0_MUXMODE,- SPI2_CS0_0" "SPI2_CS0_MUXMODE_0,SPI2_CS0_MUXMODE_1,SPI2_CS0_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,SPI2_CS0_MUXMODE_14,?" line.long 0x3D0 "CTRL_CORE_PAD_DCAN1_TX," rbitfld.long 0x3D0 25. "DCAN1_TX_WAKEUPEVENT,- NOWAKEUP" "DCAN1_TX_WAKEUPEVENT_0,DCAN1_TX_WAKEUPEVENT_1" newline bitfld.long 0x3D0 24. "DCAN1_TX_WAKEUPENABLE,- DISABLE" "DCAN1_TX_WAKEUPENABLE_0,DCAN1_TX_WAKEUPENABLE_1" newline bitfld.long 0x3D0 19. "DCAN1_TX_SLEWCONTROL,- SLOW_SLEW" "DCAN1_TX_SLEWCONTROL_0,DCAN1_TX_SLEWCONTROL_1" newline bitfld.long 0x3D0 18. "DCAN1_TX_INPUTENABLE,- DISABLE" "DCAN1_TX_INPUTENABLE_0,DCAN1_TX_INPUTENABLE_1" newline bitfld.long 0x3D0 17. "DCAN1_TX_PULLTYPESELECT,- PULL_DOWN" "DCAN1_TX_PULLTYPESELECT_0,DCAN1_TX_PULLTYPESELECT_1" newline bitfld.long 0x3D0 16. "DCAN1_TX_PULLUDENABLE,- DISABLE" "DCAN1_TX_PULLUDENABLE_0,DCAN1_TX_PULLUDENABLE_1" newline bitfld.long 0x3D0 8. "DCAN1_TX_MODESELECT,Selects between default and another IO delay different than the default one" "DCAN1_TX_MODESELECT_0,DCAN1_TX_MODESELECT_1" newline bitfld.long 0x3D0 4.--7. "DCAN1_TX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3D0 0.--3. "DCAN1_TX_MUXMODE,- HDMI1_HPD_6" "DCAN1_TX_MUXMODE_0,?,DCAN1_TX_MUXMODE_2,DCAN1_TX_MUXMODE_3,DCAN1_TX_MUXMODE_4,?,DCAN1_TX_MUXMODE_6,?,?,?,?,?,?,?,DCAN1_TX_MUXMODE_14,?" line.long 0x3D4 "CTRL_CORE_PAD_DCAN1_RX," rbitfld.long 0x3D4 25. "DCAN1_RX_WAKEUPEVENT,- NOWAKEUP" "DCAN1_RX_WAKEUPEVENT_0,DCAN1_RX_WAKEUPEVENT_1" newline bitfld.long 0x3D4 24. "DCAN1_RX_WAKEUPENABLE,- DISABLE" "DCAN1_RX_WAKEUPENABLE_0,DCAN1_RX_WAKEUPENABLE_1" newline bitfld.long 0x3D4 19. "DCAN1_RX_SLEWCONTROL,- SLOW_SLEW" "DCAN1_RX_SLEWCONTROL_0,DCAN1_RX_SLEWCONTROL_1" newline bitfld.long 0x3D4 18. "DCAN1_RX_INPUTENABLE,- DISABLE" "DCAN1_RX_INPUTENABLE_0,DCAN1_RX_INPUTENABLE_1" newline bitfld.long 0x3D4 17. "DCAN1_RX_PULLTYPESELECT,- PULL_DOWN" "DCAN1_RX_PULLTYPESELECT_0,DCAN1_RX_PULLTYPESELECT_1" newline bitfld.long 0x3D4 16. "DCAN1_RX_PULLUDENABLE,- DISABLE" "DCAN1_RX_PULLUDENABLE_0,DCAN1_RX_PULLUDENABLE_1" newline bitfld.long 0x3D4 8. "DCAN1_RX_MODESELECT,Selects between default and another IO delay different than the default one" "DCAN1_RX_MODESELECT_0,DCAN1_RX_MODESELECT_1" newline bitfld.long 0x3D4 4.--7. "DCAN1_RX_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x3D4 0.--3. "DCAN1_RX_MUXMODE,- HDMI1_CEC_6" "DCAN1_RX_MUXMODE_0,?,DCAN1_RX_MUXMODE_2,DCAN1_RX_MUXMODE_3,DCAN1_RX_MUXMODE_4,?,DCAN1_RX_MUXMODE_6,?,?,?,?,?,?,?,DCAN1_RX_MUXMODE_14,?" group.long 0x17E0++0x2F line.long 0x00 "CTRL_CORE_PAD_UART1_RXD," rbitfld.long 0x00 25. "UART1_RXD_WAKEUPEVENT,- NOWAKEUP" "UART1_RXD_WAKEUPEVENT_0,UART1_RXD_WAKEUPEVENT_1" newline bitfld.long 0x00 24. "UART1_RXD_WAKEUPENABLE,- DISABLE" "UART1_RXD_WAKEUPENABLE_0,UART1_RXD_WAKEUPENABLE_1" newline bitfld.long 0x00 19. "UART1_RXD_SLEWCONTROL,- SLOW_SLEW" "UART1_RXD_SLEWCONTROL_0,UART1_RXD_SLEWCONTROL_1" newline bitfld.long 0x00 18. "UART1_RXD_INPUTENABLE,- DISABLE" "UART1_RXD_INPUTENABLE_0,UART1_RXD_INPUTENABLE_1" newline bitfld.long 0x00 17. "UART1_RXD_PULLTYPESELECT,- PULL_DOWN" "UART1_RXD_PULLTYPESELECT_0,UART1_RXD_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "UART1_RXD_PULLUDENABLE,- DISABLE" "UART1_RXD_PULLUDENABLE_0,UART1_RXD_PULLUDENABLE_1" newline bitfld.long 0x00 8. "UART1_RXD_MODESELECT,Selects between default and another IO delay different than the default one" "UART1_RXD_MODESELECT_0,UART1_RXD_MODESELECT_1" newline bitfld.long 0x00 4.--7. "UART1_RXD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "UART1_RXD_MUXMODE,- UART1_RXD_0" "UART1_RXD_MUXMODE_0,?,?,UART1_RXD_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,UART1_RXD_MUXMODE_14,?" line.long 0x04 "CTRL_CORE_PAD_UART1_TXD," rbitfld.long 0x04 25. "UART1_TXD_WAKEUPEVENT,- NOWAKEUP" "UART1_TXD_WAKEUPEVENT_0,UART1_TXD_WAKEUPEVENT_1" newline bitfld.long 0x04 24. "UART1_TXD_WAKEUPENABLE,- DISABLE" "UART1_TXD_WAKEUPENABLE_0,UART1_TXD_WAKEUPENABLE_1" newline bitfld.long 0x04 19. "UART1_TXD_SLEWCONTROL,- SLOW_SLEW" "UART1_TXD_SLEWCONTROL_0,UART1_TXD_SLEWCONTROL_1" newline bitfld.long 0x04 18. "UART1_TXD_INPUTENABLE,- DISABLE" "UART1_TXD_INPUTENABLE_0,UART1_TXD_INPUTENABLE_1" newline bitfld.long 0x04 17. "UART1_TXD_PULLTYPESELECT,- PULL_DOWN" "UART1_TXD_PULLTYPESELECT_0,UART1_TXD_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "UART1_TXD_PULLUDENABLE,- DISABLE" "UART1_TXD_PULLUDENABLE_0,UART1_TXD_PULLUDENABLE_1" newline bitfld.long 0x04 8. "UART1_TXD_MODESELECT,Selects between default and another IO delay different than the default one" "UART1_TXD_MODESELECT_0,UART1_TXD_MODESELECT_1" newline bitfld.long 0x04 4.--7. "UART1_TXD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "UART1_TXD_MUXMODE,- UART1_TXD_0" "UART1_TXD_MUXMODE_0,?,?,UART1_TXD_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,UART1_TXD_MUXMODE_14,?" line.long 0x08 "CTRL_CORE_PAD_UART1_CTSN," rbitfld.long 0x08 25. "UART1_CTSN_WAKEUPEVENT,- NOWAKEUP" "UART1_CTSN_WAKEUPEVENT_0,UART1_CTSN_WAKEUPEVENT_1" newline bitfld.long 0x08 24. "UART1_CTSN_WAKEUPENABLE,- DISABLE" "UART1_CTSN_WAKEUPENABLE_0,UART1_CTSN_WAKEUPENABLE_1" newline bitfld.long 0x08 19. "UART1_CTSN_SLEWCONTROL,- SLOW_SLEW" "UART1_CTSN_SLEWCONTROL_0,UART1_CTSN_SLEWCONTROL_1" newline bitfld.long 0x08 18. "UART1_CTSN_INPUTENABLE,- DISABLE" "UART1_CTSN_INPUTENABLE_0,UART1_CTSN_INPUTENABLE_1" newline bitfld.long 0x08 17. "UART1_CTSN_PULLTYPESELECT,- PULL_DOWN" "UART1_CTSN_PULLTYPESELECT_0,UART1_CTSN_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "UART1_CTSN_PULLUDENABLE,- DISABLE" "UART1_CTSN_PULLUDENABLE_0,UART1_CTSN_PULLUDENABLE_1" newline bitfld.long 0x08 8. "UART1_CTSN_MODESELECT,Selects between default and another IO delay different than the default one" "UART1_CTSN_MODESELECT_0,UART1_CTSN_MODESELECT_1" newline bitfld.long 0x08 4.--7. "UART1_CTSN_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "UART1_CTSN_MUXMODE,- UART1_CTSN_0" "UART1_CTSN_MUXMODE_0,?,UART1_CTSN_MUXMODE_2,UART1_CTSN_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,UART1_CTSN_MUXMODE_14,?" line.long 0x0C "CTRL_CORE_PAD_UART1_RTSN," rbitfld.long 0x0C 25. "UART1_RTSN_WAKEUPEVENT,- NOWAKEUP" "UART1_RTSN_WAKEUPEVENT_0,UART1_RTSN_WAKEUPEVENT_1" newline bitfld.long 0x0C 24. "UART1_RTSN_WAKEUPENABLE,- DISABLE" "UART1_RTSN_WAKEUPENABLE_0,UART1_RTSN_WAKEUPENABLE_1" newline bitfld.long 0x0C 19. "UART1_RTSN_SLEWCONTROL,- SLOW_SLEW" "UART1_RTSN_SLEWCONTROL_0,UART1_RTSN_SLEWCONTROL_1" newline bitfld.long 0x0C 18. "UART1_RTSN_INPUTENABLE,- DISABLE" "UART1_RTSN_INPUTENABLE_0,UART1_RTSN_INPUTENABLE_1" newline bitfld.long 0x0C 17. "UART1_RTSN_PULLTYPESELECT,- PULL_DOWN" "UART1_RTSN_PULLTYPESELECT_0,UART1_RTSN_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "UART1_RTSN_PULLUDENABLE,- DISABLE" "UART1_RTSN_PULLUDENABLE_0,UART1_RTSN_PULLUDENABLE_1" newline bitfld.long 0x0C 8. "UART1_RTSN_MODESELECT,Selects between default and another IO delay different than the default one" "UART1_RTSN_MODESELECT_0,UART1_RTSN_MODESELECT_1" newline bitfld.long 0x0C 4.--7. "UART1_RTSN_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "UART1_RTSN_MUXMODE,- UART1_RTSN_0" "UART1_RTSN_MUXMODE_0,?,UART1_RTSN_MUXMODE_2,UART1_RTSN_MUXMODE_3,?,?,?,?,?,?,?,?,?,?,UART1_RTSN_MUXMODE_14,?" line.long 0x10 "CTRL_CORE_PAD_UART2_RXD," rbitfld.long 0x10 25. "UART2_RXD_WAKEUPEVENT,- NOWAKEUP" "UART2_RXD_WAKEUPEVENT_0,UART2_RXD_WAKEUPEVENT_1" newline bitfld.long 0x10 24. "UART2_RXD_WAKEUPENABLE,- DISABLE" "UART2_RXD_WAKEUPENABLE_0,UART2_RXD_WAKEUPENABLE_1" newline bitfld.long 0x10 19. "UART2_RXD_SLEWCONTROL,- SLOW_SLEW" "UART2_RXD_SLEWCONTROL_0,UART2_RXD_SLEWCONTROL_1" newline bitfld.long 0x10 18. "UART2_RXD_INPUTENABLE,- DISABLE" "UART2_RXD_INPUTENABLE_0,UART2_RXD_INPUTENABLE_1" newline bitfld.long 0x10 17. "UART2_RXD_PULLTYPESELECT,- PULL_DOWN" "UART2_RXD_PULLTYPESELECT_0,UART2_RXD_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "UART2_RXD_PULLUDENABLE,- DISABLE" "UART2_RXD_PULLUDENABLE_0,UART2_RXD_PULLUDENABLE_1" newline bitfld.long 0x10 8. "UART2_RXD_MODESELECT,Selects between default and another IO delay different than the default one" "UART2_RXD_MODESELECT_0,UART2_RXD_MODESELECT_1" newline bitfld.long 0x10 4.--7. "UART2_RXD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--3. "UART2_RXD_MUXMODE,- UART3_CTSN_1" "UART2_RXD_MUXMODE_0,UART2_RXD_MUXMODE_1,UART2_RXD_MUXMODE_2,UART2_RXD_MUXMODE_3,UART2_RXD_MUXMODE_4,UART2_RXD_MUXMODE_5,?,?,?,?,?,?,?,?,UART2_RXD_MUXMODE_14,?" line.long 0x14 "CTRL_CORE_PAD_UART2_TXD," rbitfld.long 0x14 25. "UART2_TXD_WAKEUPEVENT,- NOWAKEUP" "UART2_TXD_WAKEUPEVENT_0,UART2_TXD_WAKEUPEVENT_1" newline bitfld.long 0x14 24. "UART2_TXD_WAKEUPENABLE,- DISABLE" "UART2_TXD_WAKEUPENABLE_0,UART2_TXD_WAKEUPENABLE_1" newline bitfld.long 0x14 19. "UART2_TXD_SLEWCONTROL,- SLOW_SLEW" "UART2_TXD_SLEWCONTROL_0,UART2_TXD_SLEWCONTROL_1" newline bitfld.long 0x14 18. "UART2_TXD_INPUTENABLE,- DISABLE" "UART2_TXD_INPUTENABLE_0,UART2_TXD_INPUTENABLE_1" newline bitfld.long 0x14 17. "UART2_TXD_PULLTYPESELECT,- PULL_DOWN" "UART2_TXD_PULLTYPESELECT_0,UART2_TXD_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "UART2_TXD_PULLUDENABLE,- DISABLE" "UART2_TXD_PULLUDENABLE_0,UART2_TXD_PULLUDENABLE_1" newline bitfld.long 0x14 8. "UART2_TXD_MODESELECT,Selects between default and another IO delay different than the default one" "UART2_TXD_MODESELECT_0,UART2_TXD_MODESELECT_1" newline bitfld.long 0x14 4.--7. "UART2_TXD_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0.--3. "UART2_TXD_MUXMODE,- UART3_RTSN_1" "UART2_TXD_MUXMODE_0,UART2_TXD_MUXMODE_1,UART2_TXD_MUXMODE_2,UART2_TXD_MUXMODE_3,UART2_TXD_MUXMODE_4,UART2_TXD_MUXMODE_5,?,?,?,?,?,?,?,?,UART2_TXD_MUXMODE_14,?" line.long 0x18 "CTRL_CORE_PAD_UART2_CTSN," rbitfld.long 0x18 25. "UART2_CTSN_WAKEUPEVENT,- NOWAKEUP" "UART2_CTSN_WAKEUPEVENT_0,UART2_CTSN_WAKEUPEVENT_1" newline bitfld.long 0x18 24. "UART2_CTSN_WAKEUPENABLE,- DISABLE" "UART2_CTSN_WAKEUPENABLE_0,UART2_CTSN_WAKEUPENABLE_1" newline bitfld.long 0x18 19. "UART2_CTSN_SLEWCONTROL,- SLOW_SLEW" "UART2_CTSN_SLEWCONTROL_0,UART2_CTSN_SLEWCONTROL_1" newline bitfld.long 0x18 18. "UART2_CTSN_INPUTENABLE,- DISABLE" "UART2_CTSN_INPUTENABLE_0,UART2_CTSN_INPUTENABLE_1" newline bitfld.long 0x18 17. "UART2_CTSN_PULLTYPESELECT,- PULL_DOWN" "UART2_CTSN_PULLTYPESELECT_0,UART2_CTSN_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "UART2_CTSN_PULLUDENABLE,- DISABLE" "UART2_CTSN_PULLUDENABLE_0,UART2_CTSN_PULLUDENABLE_1" newline bitfld.long 0x18 8. "UART2_CTSN_MODESELECT,Selects between default and another IO delay different than the default one" "UART2_CTSN_MODESELECT_0,UART2_CTSN_MODESELECT_1" newline bitfld.long 0x18 4.--7. "UART2_CTSN_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--3. "UART2_CTSN_MUXMODE,- UART3_RXD_1" "UART2_CTSN_MUXMODE_0,UART2_CTSN_MUXMODE_1,UART2_CTSN_MUXMODE_2,UART2_CTSN_MUXMODE_3,UART2_CTSN_MUXMODE_4,UART2_CTSN_MUXMODE_5,?,?,?,?,?,?,?,?,UART2_CTSN_MUXMODE_14,?" line.long 0x1C "CTRL_CORE_PAD_UART2_RTSN," rbitfld.long 0x1C 25. "UART2_RTSN_WAKEUPEVENT,- NOWAKEUP" "UART2_RTSN_WAKEUPEVENT_0,UART2_RTSN_WAKEUPEVENT_1" newline bitfld.long 0x1C 24. "UART2_RTSN_WAKEUPENABLE,- DISABLE" "UART2_RTSN_WAKEUPENABLE_0,UART2_RTSN_WAKEUPENABLE_1" newline bitfld.long 0x1C 19. "UART2_RTSN_SLEWCONTROL,- SLOW_SLEW" "UART2_RTSN_SLEWCONTROL_0,UART2_RTSN_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "UART2_RTSN_INPUTENABLE,- DISABLE" "UART2_RTSN_INPUTENABLE_0,UART2_RTSN_INPUTENABLE_1" newline bitfld.long 0x1C 17. "UART2_RTSN_PULLTYPESELECT,- PULL_DOWN" "UART2_RTSN_PULLTYPESELECT_0,UART2_RTSN_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "UART2_RTSN_PULLUDENABLE,- DISABLE" "UART2_RTSN_PULLUDENABLE_0,UART2_RTSN_PULLUDENABLE_1" newline bitfld.long 0x1C 8. "UART2_RTSN_MODESELECT,Selects between default and another IO delay different than the default one" "UART2_RTSN_MODESELECT_0,UART2_RTSN_MODESELECT_1" newline bitfld.long 0x1C 4.--7. "UART2_RTSN_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 0.--3. "UART2_RTSN_MUXMODE,- UART3_TXD_1" "UART2_RTSN_MUXMODE_0,UART2_RTSN_MUXMODE_1,UART2_RTSN_MUXMODE_2,UART2_RTSN_MUXMODE_3,UART2_RTSN_MUXMODE_4,UART2_RTSN_MUXMODE_5,?,?,?,?,?,?,?,?,UART2_RTSN_MUXMODE_14,?" line.long 0x20 "CTRL_CORE_PAD_I2C1_SDA," rbitfld.long 0x20 25. "I2C1_SDA_WAKEUPEVENT,- NOWAKEUP" "I2C1_SDA_WAKEUPEVENT_0,I2C1_SDA_WAKEUPEVENT_1" newline bitfld.long 0x20 24. "I2C1_SDA_WAKEUPENABLE,- DISABLE" "I2C1_SDA_WAKEUPENABLE_0,I2C1_SDA_WAKEUPENABLE_1" newline bitfld.long 0x20 18. "I2C1_SDA_INPUTENABLE,- DISABLE" "I2C1_SDA_INPUTENABLE_0,I2C1_SDA_INPUTENABLE_1" newline bitfld.long 0x20 17. "I2C1_SDA_PULLTYPESELECT,- PULL_DOWN" "I2C1_SDA_PULLTYPESELECT_0,I2C1_SDA_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "I2C1_SDA_PULLUDENABLE,- DISABLE" "I2C1_SDA_PULLUDENABLE_0,I2C1_SDA_PULLUDENABLE_1" line.long 0x24 "CTRL_CORE_PAD_I2C1_SCL," rbitfld.long 0x24 25. "I2C1_SCL_WAKEUPEVENT,- NOWAKEUP" "I2C1_SCL_WAKEUPEVENT_0,I2C1_SCL_WAKEUPEVENT_1" newline bitfld.long 0x24 24. "I2C1_SCL_WAKEUPENABLE,- DISABLE" "I2C1_SCL_WAKEUPENABLE_0,I2C1_SCL_WAKEUPENABLE_1" newline bitfld.long 0x24 18. "I2C1_SCL_INPUTENABLE,- DISABLE" "I2C1_SCL_INPUTENABLE_0,I2C1_SCL_INPUTENABLE_1" newline bitfld.long 0x24 17. "I2C1_SCL_PULLTYPESELECT,- PULL_DOWN" "I2C1_SCL_PULLTYPESELECT_0,I2C1_SCL_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "I2C1_SCL_PULLUDENABLE,- DISABLE" "I2C1_SCL_PULLUDENABLE_0,I2C1_SCL_PULLUDENABLE_1" line.long 0x28 "CTRL_CORE_PAD_I2C2_SDA," rbitfld.long 0x28 25. "I2C2_SDA_WAKEUPEVENT,- NOWAKEUP" "I2C2_SDA_WAKEUPEVENT_0,I2C2_SDA_WAKEUPEVENT_1" newline bitfld.long 0x28 24. "I2C2_SDA_WAKEUPENABLE,- DISABLE" "I2C2_SDA_WAKEUPENABLE_0,I2C2_SDA_WAKEUPENABLE_1" newline bitfld.long 0x28 18. "I2C2_SDA_INPUTENABLE,- DISABLE" "I2C2_SDA_INPUTENABLE_0,I2C2_SDA_INPUTENABLE_1" newline bitfld.long 0x28 17. "I2C2_SDA_PULLTYPESELECT,- PULL_DOWN" "I2C2_SDA_PULLTYPESELECT_0,I2C2_SDA_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "I2C2_SDA_PULLUDENABLE,- DISABLE" "I2C2_SDA_PULLUDENABLE_0,I2C2_SDA_PULLUDENABLE_1" newline bitfld.long 0x28 0.--3. "I2C2_SDA_MUXMODE,- I2C2_SDA_0" "I2C2_SDA_MUXMODE_0,I2C2_SDA_MUXMODE_1,I2C2_SDA_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x2C "CTRL_CORE_PAD_I2C2_SCL," rbitfld.long 0x2C 25. "I2C2_SCL_WAKEUPEVENT,- NOWAKEUP" "I2C2_SCL_WAKEUPEVENT_0,I2C2_SCL_WAKEUPEVENT_1" newline bitfld.long 0x2C 24. "I2C2_SCL_WAKEUPENABLE,- DISABLE" "I2C2_SCL_WAKEUPENABLE_0,I2C2_SCL_WAKEUPENABLE_1" newline bitfld.long 0x2C 18. "I2C2_SCL_INPUTENABLE,- DISABLE" "I2C2_SCL_INPUTENABLE_0,I2C2_SCL_INPUTENABLE_1" newline bitfld.long 0x2C 17. "I2C2_SCL_PULLTYPESELECT,- PULL_DOWN" "I2C2_SCL_PULLTYPESELECT_0,I2C2_SCL_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "I2C2_SCL_PULLUDENABLE,- DISABLE" "I2C2_SCL_PULLUDENABLE_0,I2C2_SCL_PULLUDENABLE_1" newline bitfld.long 0x2C 0.--3. "I2C2_SCL_MUXMODE,- I2C2_SCL_0" "I2C2_SCL_MUXMODE_0,I2C2_SCL_MUXMODE_1,I2C2_SCL_MUXMODE_2,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x1818++0x37 line.long 0x00 "CTRL_CORE_PAD_WAKEUP0," rbitfld.long 0x00 25. "WAKEUP0_WAKEUPEVENT,- NOWAKEUP" "WAKEUP0_WAKEUPEVENT_0,WAKEUP0_WAKEUPEVENT_1" newline bitfld.long 0x00 24. "WAKEUP0_WAKEUPENABLE,- DISABLE" "WAKEUP0_WAKEUPENABLE_0,WAKEUP0_WAKEUPENABLE_1" newline bitfld.long 0x00 17. "WAKEUP0_PULLTYPESELECT,- PULL_DOWN" "WAKEUP0_PULLTYPESELECT_0,WAKEUP0_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "WAKEUP0_PULLUDENABLE,- DISABLE" "WAKEUP0_PULLUDENABLE_0,WAKEUP0_PULLUDENABLE_1" newline bitfld.long 0x00 8. "WAKEUP0_MODESELECT,Selects between default and another IO delay different than the default one" "WAKEUP0_MODESELECT_0,WAKEUP0_MODESELECT_1" newline bitfld.long 0x00 4.--7. "WAKEUP0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "WAKEUP0_MUXMODE,- WAKEUP0_0" "WAKEUP0_MUXMODE_0,WAKEUP0_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,WAKEUP0_MUXMODE_14,?" line.long 0x04 "CTRL_CORE_PAD_WAKEUP1," rbitfld.long 0x04 25. "WAKEUP1_WAKEUPEVENT,- NOWAKEUP" "WAKEUP1_WAKEUPEVENT_0,WAKEUP1_WAKEUPEVENT_1" newline bitfld.long 0x04 24. "WAKEUP1_WAKEUPENABLE,- DISABLE" "WAKEUP1_WAKEUPENABLE_0,WAKEUP1_WAKEUPENABLE_1" newline bitfld.long 0x04 17. "WAKEUP1_PULLTYPESELECT,- PULL_DOWN" "WAKEUP1_PULLTYPESELECT_0,WAKEUP1_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "WAKEUP1_PULLUDENABLE,- DISABLE" "WAKEUP1_PULLUDENABLE_0,WAKEUP1_PULLUDENABLE_1" newline bitfld.long 0x04 8. "WAKEUP1_MODESELECT,Selects between default and another IO delay different than the default one" "WAKEUP1_MODESELECT_0,WAKEUP1_MODESELECT_1" newline bitfld.long 0x04 4.--7. "WAKEUP1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "WAKEUP1_MUXMODE,- WAKEUP1_0" "WAKEUP1_MUXMODE_0,WAKEUP1_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,WAKEUP1_MUXMODE_14,?" line.long 0x08 "CTRL_CORE_PAD_WAKEUP2," rbitfld.long 0x08 25. "WAKEUP2_WAKEUPEVENT,- NOWAKEUP" "WAKEUP2_WAKEUPEVENT_0,WAKEUP2_WAKEUPEVENT_1" newline bitfld.long 0x08 24. "WAKEUP2_WAKEUPENABLE,- DISABLE" "WAKEUP2_WAKEUPENABLE_0,WAKEUP2_WAKEUPENABLE_1" newline bitfld.long 0x08 17. "WAKEUP2_PULLTYPESELECT,- PULL_DOWN" "WAKEUP2_PULLTYPESELECT_0,WAKEUP2_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "WAKEUP2_PULLUDENABLE,- DISABLE" "WAKEUP2_PULLUDENABLE_0,WAKEUP2_PULLUDENABLE_1" newline bitfld.long 0x08 8. "WAKEUP2_MODESELECT,Selects between default and another IO delay different than the default one" "WAKEUP2_MODESELECT_0,WAKEUP2_MODESELECT_1" newline bitfld.long 0x08 4.--7. "WAKEUP2_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 0.--3. "WAKEUP2_MUXMODE,- WAKEUP2_0" "WAKEUP2_MUXMODE_0,WAKEUP2_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,WAKEUP2_MUXMODE_14,?" line.long 0x0C "CTRL_CORE_PAD_WAKEUP3," rbitfld.long 0x0C 25. "WAKEUP3_WAKEUPEVENT,- NOWAKEUP" "WAKEUP3_WAKEUPEVENT_0,WAKEUP3_WAKEUPEVENT_1" newline bitfld.long 0x0C 24. "WAKEUP3_WAKEUPENABLE,- DISABLE" "WAKEUP3_WAKEUPENABLE_0,WAKEUP3_WAKEUPENABLE_1" newline bitfld.long 0x0C 17. "WAKEUP3_PULLTYPESELECT,- PULL_DOWN" "WAKEUP3_PULLTYPESELECT_0,WAKEUP3_PULLTYPESELECT_1" newline bitfld.long 0x0C 16. "WAKEUP3_PULLUDENABLE,- DISABLE" "WAKEUP3_PULLUDENABLE_0,WAKEUP3_PULLUDENABLE_1" newline bitfld.long 0x0C 8. "WAKEUP3_MODESELECT,Selects between default and another IO delay different than the default one" "WAKEUP3_MODESELECT_0,WAKEUP3_MODESELECT_1" newline bitfld.long 0x0C 4.--7. "WAKEUP3_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 0.--3. "WAKEUP3_MUXMODE,- WAKEUP3_0" "WAKEUP3_MUXMODE_0,WAKEUP3_MUXMODE_1,?,?,?,?,?,?,?,?,?,?,?,?,WAKEUP3_MUXMODE_14,?" line.long 0x10 "CTRL_CORE_PAD_ON_OFF," bitfld.long 0x10 17. "ON_OFF_PULLTYPESELECT,- PULL_DOWN" "ON_OFF_PULLTYPESELECT_0,ON_OFF_PULLTYPESELECT_1" newline bitfld.long 0x10 16. "ON_OFF_PULLUDENABLE,- DISABLE" "ON_OFF_PULLUDENABLE_0,ON_OFF_PULLUDENABLE_1" line.long 0x14 "CTRL_CORE_PAD_RTC_PORZ," bitfld.long 0x14 17. "RTC_PORZ_PULLTYPESELECT,- PULL_DOWN" "RTC_PORZ_PULLTYPESELECT_0,RTC_PORZ_PULLTYPESELECT_1" newline bitfld.long 0x14 16. "RTC_PORZ_PULLUDENABLE,- DISABLE" "RTC_PORZ_PULLUDENABLE_0,RTC_PORZ_PULLUDENABLE_1" line.long 0x18 "CTRL_CORE_PAD_TMS," bitfld.long 0x18 19. "TMS_SLEWCONTROL,- SLOW_SLEW" "TMS_SLEWCONTROL_0,TMS_SLEWCONTROL_1" newline bitfld.long 0x18 18. "TMS_INPUTENABLE,- DISABLE" "TMS_INPUTENABLE_0,TMS_INPUTENABLE_1" newline bitfld.long 0x18 17. "TMS_PULLTYPESELECT,- PULL_DOWN" "TMS_PULLTYPESELECT_0,TMS_PULLTYPESELECT_1" newline bitfld.long 0x18 16. "TMS_PULLUDENABLE,- DISABLE" "TMS_PULLUDENABLE_0,TMS_PULLUDENABLE_1" line.long 0x1C "CTRL_CORE_PAD_TDI," rbitfld.long 0x1C 25. "TDI_WAKEUPEVENT,- NOWAKEUP" "TDI_WAKEUPEVENT_0,TDI_WAKEUPEVENT_1" newline bitfld.long 0x1C 24. "TDI_WAKEUPENABLE,- DISABLE" "TDI_WAKEUPENABLE_0,TDI_WAKEUPENABLE_1" newline bitfld.long 0x1C 19. "TDI_SLEWCONTROL,- SLOW_SLEW" "TDI_SLEWCONTROL_0,TDI_SLEWCONTROL_1" newline bitfld.long 0x1C 18. "TDI_INPUTENABLE,- DISABLE" "TDI_INPUTENABLE_0,TDI_INPUTENABLE_1" newline bitfld.long 0x1C 17. "TDI_PULLTYPESELECT,- PULL_DOWN" "TDI_PULLTYPESELECT_0,TDI_PULLTYPESELECT_1" newline bitfld.long 0x1C 16. "TDI_PULLUDENABLE,- DISABLE" "TDI_PULLUDENABLE_0,TDI_PULLUDENABLE_1" newline bitfld.long 0x1C 8. "TDI_MODESELECT,Selects between default and another IO delay different than the default one" "TDI_MODESELECT_0,TDI_MODESELECT_1" newline bitfld.long 0x1C 4.--7. "TDI_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 0.--3. "TDI_MUXMODE,- TDI_0" "TDI_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,TDI_MUXMODE_14,?" line.long 0x20 "CTRL_CORE_PAD_TDO," rbitfld.long 0x20 25. "TDO_WAKEUPEVENT,- NOWAKEUP" "TDO_WAKEUPEVENT_0,TDO_WAKEUPEVENT_1" newline bitfld.long 0x20 24. "TDO_WAKEUPENABLE,- DISABLE" "TDO_WAKEUPENABLE_0,TDO_WAKEUPENABLE_1" newline bitfld.long 0x20 19. "TDO_SLEWCONTROL,- SLOW_SLEW" "TDO_SLEWCONTROL_0,TDO_SLEWCONTROL_1" newline bitfld.long 0x20 18. "TDO_INPUTENABLE,- DISABLE" "TDO_INPUTENABLE_0,TDO_INPUTENABLE_1" newline bitfld.long 0x20 17. "TDO_PULLTYPESELECT,- PULL_DOWN" "TDO_PULLTYPESELECT_0,TDO_PULLTYPESELECT_1" newline bitfld.long 0x20 16. "TDO_PULLUDENABLE,- DISABLE" "TDO_PULLUDENABLE_0,TDO_PULLUDENABLE_1" newline bitfld.long 0x20 8. "TDO_MODESELECT,Selects between default and another IO delay different than the default one" "TDO_MODESELECT_0,TDO_MODESELECT_1" newline bitfld.long 0x20 4.--7. "TDO_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20 0.--3. "TDO_MUXMODE,- TDO_0" "TDO_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,TDO_MUXMODE_14,?" line.long 0x24 "CTRL_CORE_PAD_TCLK," bitfld.long 0x24 18. "TCLK_INPUTENABLE,- DISABLE" "TCLK_INPUTENABLE_0,TCLK_INPUTENABLE_1" newline bitfld.long 0x24 17. "TCLK_PULLTYPESELECT,- PULL_DOWN" "TCLK_PULLTYPESELECT_0,TCLK_PULLTYPESELECT_1" newline bitfld.long 0x24 16. "TCLK_PULLUDENABLE,- DISABLE" "TCLK_PULLUDENABLE_0,TCLK_PULLUDENABLE_1" line.long 0x28 "CTRL_CORE_PAD_TRSTN," bitfld.long 0x28 19. "TRSTN_SLEWCONTROL,- SLOW_SLEW" "TRSTN_SLEWCONTROL_0,TRSTN_SLEWCONTROL_1" newline bitfld.long 0x28 18. "TRSTN_INPUTENABLE,- DISABLE" "TRSTN_INPUTENABLE_0,TRSTN_INPUTENABLE_1" newline bitfld.long 0x28 17. "TRSTN_PULLTYPESELECT,- PULL_DOWN" "TRSTN_PULLTYPESELECT_0,TRSTN_PULLTYPESELECT_1" newline bitfld.long 0x28 16. "TRSTN_PULLUDENABLE,- DISABLE" "TRSTN_PULLUDENABLE_0,TRSTN_PULLUDENABLE_1" line.long 0x2C "CTRL_CORE_PAD_RTCK," rbitfld.long 0x2C 25. "RTCK_WAKEUPEVENT,- NOWAKEUP" "RTCK_WAKEUPEVENT_0,RTCK_WAKEUPEVENT_1" newline bitfld.long 0x2C 24. "RTCK_WAKEUPENABLE,- DISABLE" "RTCK_WAKEUPENABLE_0,RTCK_WAKEUPENABLE_1" newline bitfld.long 0x2C 19. "RTCK_SLEWCONTROL,- SLOW_SLEW" "RTCK_SLEWCONTROL_0,RTCK_SLEWCONTROL_1" newline bitfld.long 0x2C 18. "RTCK_INPUTENABLE,- DISABLE" "RTCK_INPUTENABLE_0,RTCK_INPUTENABLE_1" newline bitfld.long 0x2C 17. "RTCK_PULLTYPESELECT,- PULL_DOWN" "RTCK_PULLTYPESELECT_0,RTCK_PULLTYPESELECT_1" newline bitfld.long 0x2C 16. "RTCK_PULLUDENABLE,- DISABLE" "RTCK_PULLUDENABLE_0,RTCK_PULLUDENABLE_1" newline bitfld.long 0x2C 8. "RTCK_MODESELECT,Selects between default and another IO delay different than the default one" "RTCK_MODESELECT_0,RTCK_MODESELECT_1" newline bitfld.long 0x2C 4.--7. "RTCK_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 0.--3. "RTCK_MUXMODE,- RTCK_0" "RTCK_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,RTCK_MUXMODE_14,?" line.long 0x30 "CTRL_CORE_PAD_EMU0," rbitfld.long 0x30 25. "EMU0_WAKEUPEVENT,- NOWAKEUP" "EMU0_WAKEUPEVENT_0,EMU0_WAKEUPEVENT_1" newline bitfld.long 0x30 24. "EMU0_WAKEUPENABLE,- DISABLE" "EMU0_WAKEUPENABLE_0,EMU0_WAKEUPENABLE_1" newline bitfld.long 0x30 19. "EMU0_SLEWCONTROL,- SLOW_SLEW" "EMU0_SLEWCONTROL_0,EMU0_SLEWCONTROL_1" newline bitfld.long 0x30 18. "EMU0_INPUTENABLE,- DISABLE" "EMU0_INPUTENABLE_0,EMU0_INPUTENABLE_1" newline bitfld.long 0x30 17. "EMU0_PULLTYPESELECT,- PULL_DOWN" "EMU0_PULLTYPESELECT_0,EMU0_PULLTYPESELECT_1" newline bitfld.long 0x30 16. "EMU0_PULLUDENABLE,- DISABLE" "EMU0_PULLUDENABLE_0,EMU0_PULLUDENABLE_1" newline bitfld.long 0x30 8. "EMU0_MODESELECT,Selects between default and another IO delay different than the default one" "EMU0_MODESELECT_0,EMU0_MODESELECT_1" newline bitfld.long 0x30 4.--7. "EMU0_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x30 0.--3. "EMU0_MUXMODE,- EMU0_0" "EMU0_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,EMU0_MUXMODE_14,?" line.long 0x34 "CTRL_CORE_PAD_EMU1," rbitfld.long 0x34 25. "EMU1_WAKEUPEVENT,- NOWAKEUP" "EMU1_WAKEUPEVENT_0,EMU1_WAKEUPEVENT_1" newline bitfld.long 0x34 24. "EMU1_WAKEUPENABLE,- DISABLE" "EMU1_WAKEUPENABLE_0,EMU1_WAKEUPENABLE_1" newline bitfld.long 0x34 19. "EMU1_SLEWCONTROL,- SLOW_SLEW" "EMU1_SLEWCONTROL_0,EMU1_SLEWCONTROL_1" newline bitfld.long 0x34 18. "EMU1_INPUTENABLE,- DISABLE" "EMU1_INPUTENABLE_0,EMU1_INPUTENABLE_1" newline bitfld.long 0x34 17. "EMU1_PULLTYPESELECT,- PULL_DOWN" "EMU1_PULLTYPESELECT_0,EMU1_PULLTYPESELECT_1" newline bitfld.long 0x34 16. "EMU1_PULLUDENABLE,- DISABLE" "EMU1_PULLUDENABLE_0,EMU1_PULLUDENABLE_1" newline bitfld.long 0x34 8. "EMU1_MODESELECT,Selects between default and another IO delay different than the default one" "EMU1_MODESELECT_0,EMU1_MODESELECT_1" newline bitfld.long 0x34 4.--7. "EMU1_DELAYMODE,Defines an IO delay different than the default one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x34 0.--3. "EMU1_MUXMODE,- EMU1_0" "EMU1_MUXMODE_0,?,?,?,?,?,?,?,?,?,?,?,?,?,EMU1_MUXMODE_14,?" group.long 0x185C++0x2F line.long 0x00 "CTRL_CORE_PAD_RESETN," bitfld.long 0x00 17. "RESETN_PULLTYPESELECT,- PULL_DOWN" "RESETN_PULLTYPESELECT_0,RESETN_PULLTYPESELECT_1" newline bitfld.long 0x00 16. "RESETN_PULLUDENABLE,- DISABLE" "RESETN_PULLUDENABLE_0,RESETN_PULLUDENABLE_1" line.long 0x04 "CTRL_CORE_PAD_NMIN," rbitfld.long 0x04 25. "NMIN_WAKEUPEVENT,- NOWAKEUP" "NMIN_WAKEUPEVENT_0,NMIN_WAKEUPEVENT_1" newline bitfld.long 0x04 24. "NMIN_WAKEUPENABLE,- DISABLE" "NMIN_WAKEUPENABLE_0,NMIN_WAKEUPENABLE_1" newline bitfld.long 0x04 17. "NMIN_PULLTYPESELECT,- PULL_DOWN" "NMIN_PULLTYPESELECT_0,NMIN_PULLTYPESELECT_1" newline bitfld.long 0x04 16. "NMIN_PULLUDENABLE,- DISABLE" "NMIN_PULLUDENABLE_0,NMIN_PULLUDENABLE_1" line.long 0x08 "CTRL_CORE_PAD_RSTOUTN," bitfld.long 0x08 17. "RSTOUTN_PULLTYPESELECT,- PULL_DOWN" "RSTOUTN_PULLTYPESELECT_0,RSTOUTN_PULLTYPESELECT_1" newline bitfld.long 0x08 16. "RSTOUTN_PULLUDENABLE,- DISABLE" "RSTOUTN_PULLUDENABLE_0,RSTOUTN_PULLUDENABLE_1" line.long 0x0C "CTRL_CORE_PADCONF_WAKEUPEVENT_0," bitfld.long 0x0C 31. "GPMC_A15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 30. "GPMC_A14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 29. "GPMC_A13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 28. "GPMC_A12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 27. "GPMC_A11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 26. "GPMC_A10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 25. "GPMC_A9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 24. "GPMC_A8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 23. "GPMC_A7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 22. "GPMC_A6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 21. "GPMC_A5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 20. "GPMC_A4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 19. "GPMC_A3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 18. "GPMC_A2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 17. "GPMC_A1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 16. "GPMC_A0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 15. "GPMC_AD15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 14. "GPMC_AD14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 13. "GPMC_AD13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 12. "GPMC_AD12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 11. "GPMC_AD11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 10. "GPMC_AD10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 9. "GPMC_AD9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 8. "GPMC_AD8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 7. "GPMC_AD7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 6. "GPMC_AD6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 5. "GPMC_AD5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 4. "GPMC_AD4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 3. "GPMC_AD3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 2. "GPMC_AD2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 1. "GPMC_AD1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x0C 0. "GPMC_AD0_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x10 "CTRL_CORE_PADCONF_WAKEUPEVENT_1," bitfld.long 0x10 31. "VIN1A_D2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 30. "VIN1A_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 29. "VIN1A_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 28. "VIN1A_VSYNC0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 27. "VIN1A_HSYNC0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 26. "VIN1A_FLD0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 25. "VIN1A_DE0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 24. "VIN1B_CLK1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 23. "VIN1A_CLK0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 22. "GPMC_WAIT0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 21. "GPMC_BEN1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 20. "GPMC_BEN0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 19. "GPMC_WEN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 18. "GPMC_OEN_REN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 17. "GPMC_ADVN_ALE_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 16. "GPMC_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 15. "GPMC_CS3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 14. "GPMC_CS2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 13. "GPMC_CS0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 12. "GPMC_CS1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 11. "GPMC_A27_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 10. "GPMC_A26_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 9. "GPMC_A25_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 8. "GPMC_A24_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 7. "GPMC_A23_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 6. "GPMC_A22_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 5. "GPMC_A21_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 4. "GPMC_A20_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 3. "GPMC_A19_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 2. "GPMC_A18_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 1. "GPMC_A17_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x10 0. "GPMC_A16_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x14 "CTRL_CORE_PADCONF_WAKEUPEVENT_2," bitfld.long 0x14 31. "VIN2A_D5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 30. "VIN2A_D4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 29. "VIN2A_D3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 28. "VIN2A_D2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 27. "VIN2A_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 26. "VIN2A_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 25. "VIN2A_VSYNC0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 24. "VIN2A_HSYNC0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 23. "VIN2A_FLD0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 22. "VIN2A_DE0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 21. "VIN2A_CLK0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 20. "VIN1A_D23_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 19. "VIN1A_D22_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 18. "VIN1A_D21_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 17. "VIN1A_D20_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 16. "VIN1A_D19_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 15. "VIN1A_D18_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 14. "VIN1A_D17_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 13. "VIN1A_D16_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 12. "VIN1A_D15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 11. "VIN1A_D14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 10. "VIN1A_D13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 9. "VIN1A_D12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 8. "VIN1A_D11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 7. "VIN1A_D10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 6. "VIN1A_D9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 5. "VIN1A_D8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 4. "VIN1A_D7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 3. "VIN1A_D6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 2. "VIN1A_D5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 1. "VIN1A_D4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x14 0. "VIN1A_D3_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x18 "CTRL_CORE_PADCONF_WAKEUPEVENT_3," bitfld.long 0x18 31. "VOUT1_D8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 30. "VOUT1_D7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 29. "VOUT1_D6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 28. "VOUT1_D5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 27. "VOUT1_D4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 26. "VOUT1_D3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 25. "VOUT1_D2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 24. "VOUT1_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 23. "VOUT1_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 22. "VOUT1_VSYNC_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 21. "VOUT1_HSYNC_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 20. "VOUT1_FLD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 19. "VOUT1_DE_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 18. "VOUT1_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 17. "VIN2A_D23_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 16. "VIN2A_D22_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 15. "VIN2A_D21_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 14. "VIN2A_D20_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 13. "VIN2A_D19_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 12. "VIN2A_D18_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 11. "VIN2A_D17_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 10. "VIN2A_D16_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 9. "VIN2A_D15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 8. "VIN2A_D14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 7. "VIN2A_D13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 6. "VIN2A_D12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 5. "VIN2A_D11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 4. "VIN2A_D10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 3. "VIN2A_D9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 2. "VIN2A_D8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 1. "VIN2A_D7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x18 0. "VIN2A_D6_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x1C "CTRL_CORE_PADCONF_WAKEUPEVENT_4," bitfld.long 0x1C 31. "RGMII0_RXD0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 30. "RGMII0_RXD1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 29. "RGMII0_RXD2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 28. "RGMII0_RXD3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 27. "RGMII0_RXCTL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 26. "RGMII0_RXC_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 25. "RGMII0_TXD0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 24. "RGMII0_TXD1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 23. "RGMII0_TXD2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 22. "RGMII0_TXD3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 21. "RGMII0_TXCTL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 20. "RGMII0_TXC_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 19. "UART3_TXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 18. "UART3_RXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 17. "RMII_MHZ_50_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 16. "MDIO_D_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 15. "MDIO_MCLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 14. "VOUT1_D23_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 13. "VOUT1_D22_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 12. "VOUT1_D21_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 11. "VOUT1_D20_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 10. "VOUT1_D19_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 9. "VOUT1_D18_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 8. "VOUT1_D17_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 7. "VOUT1_D16_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 6. "VOUT1_D15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 5. "VOUT1_D14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 4. "VOUT1_D13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 3. "VOUT1_D12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 2. "VOUT1_D11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 1. "VOUT1_D10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x1C 0. "VOUT1_D9_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x20 "CTRL_CORE_PADCONF_WAKEUPEVENT_5," bitfld.long 0x20 31. "MCASP2_ACLKR_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 30. "MCASP2_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 29. "MCASP2_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 28. "MCASP1_AXR15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 27. "MCASP1_AXR14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 26. "MCASP1_AXR13_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 25. "MCASP1_AXR12_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 24. "MCASP1_AXR11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 23. "MCASP1_AXR10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 22. "MCASP1_AXR9_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 21. "MCASP1_AXR8_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 20. "MCASP1_AXR7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 19. "MCASP1_AXR6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 18. "MCASP1_AXR5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 17. "MCASP1_AXR4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 16. "MCASP1_AXR3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 15. "MCASP1_AXR2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 14. "MCASP1_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 13. "MCASP1_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 12. "MCASP1_FSR_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 11. "MCASP1_ACLKR_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 10. "MCASP1_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 9. "MCASP1_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 8. "XREF_CLK3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 7. "XREF_CLK2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 6. "XREF_CLK1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 5. "XREF_CLK0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 4. "GPIO6_16_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 3. "GPIO6_15_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 2. "GPIO6_14_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 1. "USB2_DRVVBUS_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x20 0. "USB1_DRVVBUS_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x24 "CTRL_CORE_PADCONF_WAKEUPEVENT_6," bitfld.long 0x24 31. "MMC3_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 30. "GPIO6_11_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 29. "GPIO6_10_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 28. "MMC1_SDWP_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 27. "MMC1_SDCD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 26. "MMC1_DAT3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 25. "MMC1_DAT2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 24. "MMC1_DAT1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 23. "MMC1_DAT0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 22. "MMC1_CMD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 21. "MMC1_CLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 20. "MCASP5_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 19. "MCASP5_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 18. "MCASP5_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 17. "MCASP5_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 16. "MCASP4_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 15. "MCASP4_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 14. "MCASP4_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 13. "MCASP4_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 12. "MCASP3_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 11. "MCASP3_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 10. "MCASP3_FSX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 9. "MCASP3_ACLKX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 8. "MCASP2_AXR7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 7. "MCASP2_AXR6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 6. "MCASP2_AXR5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 5. "MCASP2_AXR4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 4. "MCASP2_AXR3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 3. "MCASP2_AXR2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 2. "MCASP2_AXR1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 1. "MCASP2_AXR0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x24 0. "MCASP2_FSR_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x28 "CTRL_CORE_PADCONF_WAKEUPEVENT_7," bitfld.long 0x28 31. "UART2_RTSN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 30. "UART2_CTSN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 29. "UART2_TXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 28. "UART2_RXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 27. "UART1_RTSN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 26. "UART1_CTSN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 25. "UART1_TXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 24. "UART1_RXD_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 23. "DCAN2_RX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 22. "DCAN2_TX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 21. "DCAN1_RX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 20. "DCAN1_TX_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 19. "SPI2_CS0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 18. "SPI2_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 17. "SPI2_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 16. "SPI2_SCLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 15. "SPI1_CS3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 14. "SPI1_CS2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 13. "SPI1_CS1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 12. "SPI1_CS0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 11. "SPI1_D0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 10. "SPI1_D1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 9. "SPI1_SCLK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 8. "MMC3_DAT7_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 7. "MMC3_DAT6_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 6. "MMC3_DAT5_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 5. "MMC3_DAT4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 4. "MMC3_DAT3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 3. "MMC3_DAT2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 2. "MMC3_DAT1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 1. "MMC3_DAT0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x28 0. "MMC3_CMD_DUPLICATEWAKEUPEVENT," "0,1" line.long 0x2C "CTRL_CORE_PADCONF_WAKEUPEVENT_8," bitfld.long 0x2C 18. "NMIN_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 17. "EMU4_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 16. "EMU3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 15. "EMU2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 14. "EMU1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 13. "EMU0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 12. "RTCK_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 11. "TDO_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 10. "TDI_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 9. "WAKEUP3_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 8. "WAKEUP2_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 7. "WAKEUP1_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 6. "WAKEUP0_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 5. "I2C3_SCL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 4. "I2C3_SDA_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 3. "I2C2_SCL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 2. "I2C2_SDA_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 1. "I2C1_SCL_DUPLICATEWAKEUPEVENT," "0,1" newline bitfld.long 0x2C 0. "I2C1_SDA_DUPLICATEWAKEUPEVENT," "0,1" rgroup.long 0x1B00++0x0F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_0,Standard Fuse OPP Vmin_GPU [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_1,Standard Fuse OPP Vmin_GPU [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_2,Standard Fuse OPP Vmin_GPU [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_3,Standard Fuse OPP Vmin_GPU [127:96]" rgroup.long 0x1B18++0x0F line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_0,Standard Fuse OPP Vmin_MPU [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_1,Standard Fuse OPP Vmin_MPU [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_2,Standard Fuse OPP Vmin_MPU [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_3,Standard Fuse OPP Vmin_MPU [127:96]" rgroup.long 0x1B38++0x47 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_0,Standard Fuse OPP VDD_GPU [31:0]" line.long 0x04 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_1,Standard Fuse OPP VDD_GPU [63:32]" line.long 0x08 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_2,Standard Fuse OPP VDD_GPU [95:64]" line.long 0x0C "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_3,Standard Fuse OPP VDD_GPU [127:96]" line.long 0x10 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_4,Standard Fuse OPP VDD_GPU [159:128]" line.long 0x14 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_0,Standard Fuse OPP VDD_IVA [31:0]" line.long 0x18 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_1,Standard Fuse OPP VDD_IVA [63:32]" line.long 0x1C "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_2,Standard Fuse OPP VDD_IVA [95:64]" line.long 0x20 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_3,Standard Fuse OPP VDD_IVA [127:96]" line.long 0x24 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_4,Standard Fuse OPP VDD_IVA [159:128]" line.long 0x28 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_0,Standard Fuse OPP VDD_CORE [31:0]" line.long 0x2C "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_1,Standard Fuse OPP VDD_CORE [63:32]" line.long 0x30 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_2,Standard Fuse OPP VDD_CORE [95:64]" line.long 0x34 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_3,Standard Fuse OPP VDD_CORE [127:96]" line.long 0x38 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_4,Standard Fuse OPP VDD_CORE [159:128]" line.long 0x3C "CTRL_CORE_LDOSRAM_CORE_4_VOLTAGE_CTRL,CORE 4th SRAM LDO Control register" bitfld.long 0x3C 26. "LDOSRAMCORE_4_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_4_RETMODE_MUX_CTRL_0,LDOSRAMCORE_4_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x3C 21.--25. "LDOSRAMCORE_4_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x3C 16.--20. "LDOSRAMCORE_4_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x3C 10. "LDOSRAMCORE_4_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_4_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_4_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x3C 5.--9. "LDOSRAMCORE_4_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x3C 0.--4. "LDOSRAMCORE_4_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x40 "CTRL_CORE_LDOSRAM_CORE_5_VOLTAGE_CTRL,CORE 5th SRAM LDO Control register" bitfld.long 0x40 26. "LDOSRAMCORE_5_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_5_RETMODE_MUX_CTRL_0,LDOSRAMCORE_5_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x40 21.--25. "LDOSRAMCORE_5_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x40 16.--20. "LDOSRAMCORE_5_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x40 10. "LDOSRAMCORE_5_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_5_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_5_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x40 5.--9. "LDOSRAMCORE_5_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x40 0.--4. "LDOSRAMCORE_5_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x44 "CTRL_CORE_LDOSRAM_DSPEVE_2_VOLTAGE_CTRL,DSPEVE 2nd SRAM LDO Control register" bitfld.long 0x44 26. "LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL_0,LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x44 21.--25. "LDOSRAMDSPEVE_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x44 16.--20. "LDOSRAMDSPEVE_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x44 10. "LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL_0,LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x44 5.--9. "LDOSRAMDSPEVE_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x44 0.--4. "LDOSRAMDSPEVE_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C14++0x07 line.long 0x00 "CTRL_CORE_SMA_SW_6,OCP Spare Register" bitfld.long 0x00 24.--28. "PLLEN_CONTROL,PLLEN control setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--17. "PCIE_TX_RX_CONTROL,PCIe RX and TX control of ACSPCIe" "0,1,2,3" newline bitfld.long 0x00 8. "RMII_CLK_SETTING,RMII CLK setting" "0,1" newline bitfld.long 0x00 0. "MUXSEL_32K_CLKIN,Setting for mux to select 32KHz clock input to PRCM" "0,1" line.long 0x04 "CTRL_CORE_SMA_SW_7,OCP Spare Register" bitfld.long 0x04 17. "MMU1_ABORT_ENABLE,MU1 abort enable" "0,1" newline bitfld.long 0x04 16. "MMU2_ABORT_ENABLE,MU2 abort enable" "0,1" newline bitfld.long 0x04 13. "EDMA_TC1_WR_MMU_ROUTE_ENABLE,EDMA TC1 WR traffic MMU route enable" "0,1" newline bitfld.long 0x04 12. "EDMA_TC1_RD_MMU_ROUTE_ENABLE,EDMA TC1 RD traffic MMU route enable" "0,1" newline bitfld.long 0x04 11. "EDMA_TC0_WR_MMU_ROUTE_ENABLE,EDMA TC0 WR traffic MMU route enable" "0,1" newline bitfld.long 0x04 10. "EDMA_TC0_RD_MMU_ROUTE_ENABLE,EDMA TC0 RD traffic MMU route enable" "0,1" newline bitfld.long 0x04 9. "PCIE_SS2_MMU_ROUTE_ENABLE,PCIe_SS2 MMU route enable" "0,1" newline bitfld.long 0x04 8. "PCIE_SS1_MMU_ROUTE_ENABLE,PCIe_SS1 MMU route enable" "0,1" newline bitfld.long 0x04 1. "PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE,PCIe_SS1 AXI2OCP legacy mode enable" "0,1" newline bitfld.long 0x04 0. "PCIE_SS2_AXI2OCP_LEGACY_MODE_ENABLE,PCIe_SS2 AXI2OCP legacy mode enable" "0,1" group.long 0x1C24++0x23 line.long 0x00 "CTRL_CORE_PCIESS1_PCS1," hexmask.long.word 0x00 22.--31. 1. "PCIESS1_PCS_TEST_TXDATA," newline hexmask.long.word 0x00 12.--21. 1. "PCIESS1_PCS_ERR_BIT_EN," newline hexmask.long.byte 0x00 4.--11. 1. "PCIESS1_PCS_CFG_HOLDOFF," newline bitfld.long 0x00 0.--3. "PCIESS1_PCS_DET_DELAY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CTRL_CORE_PCIESS1_PCS2," bitfld.long 0x04 27.--31. "PCIESS1_PCS_CFG_SYNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 23.--26. "PCIESS1_PCS_CFG_EQ_FUNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 19.--22. "PCIESS1_PCS_CFG_EQ_HOLD," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 15.--18. "PCIESS1_PCS_CFG_EQ_INIT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 12.--14. "PCIESS1_PCS_TEST_OSEL," "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 9. "PCIESS1_PCS_TEST_LSEL," "0,1" newline bitfld.long 0x04 6.--7. "PCIESS1_PCS_ERR_MODE," "0,1,2,3" newline bitfld.long 0x04 5. "PCIESS1_PCS_L1_SLEEP," "0,1" newline bitfld.long 0x04 4. "PCIESS1_PCS_TEST_MODE," "0,1" newline bitfld.long 0x04 2.--3. "PCIESS1_PCS_ERR_LN_EN," "0,1,2,3" newline bitfld.long 0x04 0. "PCIESS1_PCS_SHORT_TIMES," "0,1" line.long 0x08 "CTRL_CORE_PCIESS2_PCS1," hexmask.long.word 0x08 22.--31. 1. "PCIESS2_PCS_TEST_TXDATA," newline hexmask.long.word 0x08 12.--21. 1. "PCIESS2_PCS_ERR_BIT_EN," newline hexmask.long.byte 0x08 4.--11. 1. "PCIESS2_PCS_CFG_HOLDOFF," newline bitfld.long 0x08 0.--3. "PCIESS2_PCS_DET_DELAY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "CTRL_CORE_PCIESS2_PCS2," bitfld.long 0x0C 27.--31. "PCIESS2_PCS_CFG_SYNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 23.--26. "PCIESS2_PCS_CFG_EQ_FUNC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 19.--22. "PCIESS2_PCS_CFG_EQ_HOLD," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 15.--18. "PCIESS2_PCS_CFG_EQ_INIT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 12.--14. "PCIESS2_PCS_TEST_OSEL," "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 9. "PCIESS2_PCS_TEST_LSEL," "0,1" newline bitfld.long 0x0C 6.--7. "PCIESS2_PCS_ERR_MODE," "0,1,2,3" newline bitfld.long 0x0C 5. "PCIESS2_PCS_L1_SLEEP," "0,1" newline bitfld.long 0x0C 4. "PCIESS2_PCS_TEST_MODE," "0,1" newline bitfld.long 0x0C 2.--3. "PCIESS2_PCS_ERR_LN_EN," "0,1,2,3" newline bitfld.long 0x0C 0. "PCIESS2_PCS_SHORT_TIMES," "0,1" line.long 0x10 "CTRL_CORE_PCIE_PCS," hexmask.long.byte 0x10 16.--23. 1. "PCIESS2_PCS_RC_DELAY_COUNT," newline hexmask.long.byte 0x10 8.--15. 1. "PCIESS1_PCS_RC_DELAY_COUNT," line.long 0x14 "CTRL_CORE_PCIE_PCS_REVISION,pcs_revision" bitfld.long 0x14 23.--25. "PCIESS2_PCS_REVISION," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--22. "PCIESS1_PCS_REVISION," "0,1,2,3,4,5,6,7" line.long 0x18 "CTRL_CORE_PCIE_CONTROL,serdes control selection PCIE C0 (0 default) vs PCIE B1 (1)" bitfld.long 0x18 2. "PCIE_B1C0_MODE_SEL," "0,1" newline bitfld.long 0x18 0. "PCIE_B0_B1_TSYNCEN," "0,1" line.long 0x1C "CTRL_CORE_PHY_POWER_PCIESS1," hexmask.long.word 0x1C 22.--31. 1. "PCIESS1_PWRCTL_CLKFREQ," newline hexmask.long.byte 0x1C 14.--21. 1. "PCIESS1_PWRCTL_CMD," line.long 0x20 "CTRL_CORE_PHY_POWER_PCIESS2," hexmask.long.word 0x20 22.--31. 1. "PCIESS2_PWRCTL_CLKFREQ," newline hexmask.long.byte 0x20 14.--21. 1. "PCIESS2_PWRCTL_CMD," repeat 2. (list 8. 9. )(list 0x00 0x04 ) group.long ($2+0x1C1C)++0x03 line.long 0x00 "CTRL_CORE_SMA_SW_$1,Test control inputs used by the module" repeat.end repeat 2. (list 2. 3. )(list 0x00 0x04 ) group.long ($2+0x1C04)++0x03 line.long 0x00 "CTRL_CORE_SMA_SW_$1,OCP Spare Register" repeat.end repeat 4. (list 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0x1B28)++0x03 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_$1,Standard Fuse OPP Vmin_MPU [159:128]" repeat.end repeat 2. (list 4. 5. )(list 0x00 0x04 ) rgroup.long ($2+0x1B10)++0x03 line.long 0x00 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_$1,Standard Fuse OPP Vmin_GPU [159:128]" repeat.end repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) rgroup.long ($2+0x5B4)++0x03 line.long 0x00 "CTRL_CORE_DTEMP_IVA_$1,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_IVA_1,tag" hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_IVA_1,temperature" repeat.end repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) rgroup.long ($2+0x5A0)++0x03 line.long 0x00 "CTRL_CORE_DTEMP_DSPEVE_$1,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_DSPEVE_1,tag" hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_DSPEVE_1,temperature" repeat.end repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0x514)++0x03 line.long 0x00 "CTRL_CORE_MAC_ID_SW_$1,Standard Fuse keys. MAC ID_1 [63:32]" hexmask.long 0x00 0.--24. 1. "STD_FUSE_MAC_ID_SW_0," repeat.end repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) rgroup.long ($2+0x3EC)++0x03 line.long 0x00 "CTRL_CORE_DTEMP_CORE_$1,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_CORE_1,tag" hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_CORE_1,temperature" repeat.end repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) rgroup.long ($2+0x3D8)++0x03 line.long 0x00 "CTRL_CORE_DTEMP_GPU_$1,TAGGED TEMPERATURE GPU DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_GPU_1,tag" hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_GPU_1,temperature" repeat.end repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) rgroup.long ($2+0x3C4)++0x03 line.long 0x00 "CTRL_CORE_DTEMP_MPU_$1,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.tbyte 0x00 10.--31. 1. "DTEMP_TAG_MPU_1,tag" hexmask.long.word 0x00 0.--9. 1. "DTEMP_TEMPERATURE_MPU_1,temperature" repeat.end tree.end tree "CTRL_MODULE_WKUP" base ad:0x4AE0C000 group.long 0x100++0x03 line.long 0x00 "CTRL_WKUP_SEC_CTRL,Control Register" bitfld.long 0x00 31. "SECCTRLWRDISABLE,Control Register write disable control" "0,1" newline bitfld.long 0x00 4. "SECURE_EMIF_CONFIG_RO_EN,Access mode for registers: CTRL_WKUP_EMIF1_SDRAM_CONFIG CTRL_WKUP_EMIF2_SDRAM_CONFIG" "0,1" group.long 0x108++0x3 line.long 0x00 "CTRL_WKUP_SEC_TAP,TAP controllers register" bitfld.long 0x00 31. "SECTAPWR_DISABLE,TAP controllers register write disable control" "Disabled,Enabled" newline bitfld.long 0x00 13. "IPU2_TAPENABLE,IPU2 TAP control" "Disabled,Enabled" newline bitfld.long 0x00 11. "JTAGEXT_TAPENABLE,External JTAG expansion TAP control" "Disabled,Enabled" newline bitfld.long 0x00 10. "IVA_TAPENABLE,IVA TAP control" "Disabled,Enabled" newline bitfld.long 0x00 9. "MPUGLOBALDEBUG_ENABLE,MPU TAP control" "Disabled,Enabled" newline eventfld.long 0x00 4. "IEEE1500_ENABLE,IEEE1500 and P1500 access enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P1500_ENABLE,P1500 access enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "IPU1_TAPENABLE,IPU1 TAP control" "Disabled,Enabled" newline bitfld.long 0x00 1. "DSP1_TAPENABLE,DSP1 TAP control" "Disabled,Enabled" newline bitfld.long 0x00 0. "DAP_TAPENABLE,DAP TAP control" "Disabled,Enabled" group.long 0x10C++0x07 line.long 0x00 "CTRL_WKUP_OCPREG_SPARE,OCP Spare Register" bitfld.long 0x00 31. "OCPREG_SPARE31,OCP spare register 31" "0,1" newline bitfld.long 0x00 30. "OCPREG_SPARE30,OCP spare register 30" "0,1" newline bitfld.long 0x00 29. "OCPREG_SPARE29,OCP spare register 29" "0,1" newline bitfld.long 0x00 28. "OCPREG_SPARE28,OCP spare register 28" "0,1" newline bitfld.long 0x00 27. "OCPREG_SPARE27,OCP spare register 27" "0,1" newline bitfld.long 0x00 26. "OCPREG_SPARE26,OCP spare register 26" "0,1" newline bitfld.long 0x00 25. "OCPREG_SPARE25,OCP spare register 25" "0,1" newline bitfld.long 0x00 24. "OCPREG_SPARE24,OCP spare register 24" "0,1" newline bitfld.long 0x00 23. "OCPREG_SPARE23,OCP spare register 23" "0,1" newline bitfld.long 0x00 22. "OCPREG_SPARE22,OCP spare register 22" "0,1" newline bitfld.long 0x00 21. "OCPREG_SPARE21,OCP spare register 21" "0,1" newline bitfld.long 0x00 20. "OCPREG_SPARE20,OCP spare register 20" "0,1" newline bitfld.long 0x00 19. "OCPREG_SPARE19,OCP spare register 19" "0,1" newline bitfld.long 0x00 18. "OCPREG_SPARE18,OCP spare register 18" "0,1" newline bitfld.long 0x00 17. "OCPREG_SPARE17,OCP spare register 17" "0,1" newline bitfld.long 0x00 16. "OCPREG_SPARE16,OCP spare register 16" "0,1" newline bitfld.long 0x00 15. "OCPREG_SPARE15,OCP spare register 15" "0,1" newline bitfld.long 0x00 14. "OCPREG_SPARE14,OCP spare register 14" "0,1" newline bitfld.long 0x00 13. "OCPREG_SPARE13,OCP spare register 13" "0,1" newline bitfld.long 0x00 12. "OCPREG_SPARE12,OCP spare register 12" "0,1" newline bitfld.long 0x00 11. "OCPREG_SPARE11,OCP spare register 11" "0,1" newline bitfld.long 0x00 10. "OCPREG_SPARE10,OCP spare register 10" "0,1" newline bitfld.long 0x00 9. "OCPREG_SPARE9,OCP spare register 9" "0,1" newline bitfld.long 0x00 8. "OCPREG_SPARE8,OCP spare register 8" "0,1" newline bitfld.long 0x00 7. "OCPREG_SPARE7,OCP spare register 7" "0,1" newline bitfld.long 0x00 6. "OCPREG_SPARE6,OCP spare register 6" "0,1" newline bitfld.long 0x00 5. "OCPREG_SPARE5,OCP spare register 5" "0,1" newline bitfld.long 0x00 4. "OCPREG_SPARE4,OCP spare register 4" "0,1" newline bitfld.long 0x00 3. "OCPREG_SPARE3,OCP spare register 3" "0,1" newline bitfld.long 0x00 2. "OCPREG_SPARE2,OCP spare register 2" "0,1" newline bitfld.long 0x00 1. "OCPREG_SPARE1,OCP spare register 1" "0,1" line.long 0x04 "CTRL_WKUP_SECURE_EMIF1_SDRAM_CONFIG,EMIF1 SDRAM configuration register" bitfld.long 0x04 27.--28. "EMIF1_SDRAM_IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x04 24.--26. "EMIF1_SDRAM_DDR_TERM,DDR2 and DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 23. "EMIF1_SDRAM_DDR2_DDQS,DDR2 differential DQS enable" "0,1" newline bitfld.long 0x04 21.--22. "EMIF1_SDRAM_DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x04 20. "EMIF1_SDRAM_DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x04 18.--19. "EMIF1_SDRAM_DRIVE,SDRAM drive strength" "0,1,2,3" newline bitfld.long 0x04 16.--17. "EMIF1_SDRAM_CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x04 10.--13. "EMIF1_SDRAM_CL,CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 7.--9. "EMIF1_SDRAM_ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 4.--6. "EMIF1_SDRAM_IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. "EMIF1_SDRAM_PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" group.long 0x118++0x03 line.long 0x00 "CTRL_WKUP_SECURE_EMIF2_SDRAM_CONFIG,EMIF2 SDRAM register" bitfld.long 0x00 27.--28. "EMIF2_SDRAM_IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x00 24.--26. "EMIF2_SDRAM_DDR_TERM,DDR2 and DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "EMIF2_SDRAM_DDR2_DDQS,DDR2 differential DQS enable" "0,1" newline bitfld.long 0x00 21.--22. "EMIF2_SDRAM_DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x00 20. "EMIF2_SDRAM_DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x00 18.--19. "EMIF2_SDRAM_DRIVE,SDRAM drive strength" "0,1,2,3" newline bitfld.long 0x00 16.--17. "EMIF2_SDRAM_CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x00 10.--13. "EMIF2_SDRAM_CL,CAS Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7.--9. "EMIF2_SDRAM_ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "EMIF2_SDRAM_IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. "EMIF2_SDRAM_PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" rgroup.long 0x138++0x07 line.long 0x00 "CTRL_WKUP_STD_FUSE_USB_CONF,Standard Fuse conf [31:0]" hexmask.long.word 0x00 16.--31. 1. "USB_PROD_ID,USB Product Identification" newline hexmask.long.word 0x00 0.--15. 1. "USB_VENDOR_ID,USB Vendor Identification" line.long 0x04 "CTRL_WKUP_STD_FUSE_CONF,Standard Fuse conf [63:32]" bitfld.long 0x04 21. "STD_FUSE_EMIF2_INITREF_DEF_DIS,Disable EMIF2 DDR refresh and initialization sequence" "0,1" newline bitfld.long 0x04 20. "STD_FUSE_EMIF2_DDR3_LPDDR2N,EMIF2 DDR3" "0,1" newline bitfld.long 0x04 19. "STD_FUSE_EMIF1_INITREF_DEF_DIS,Disable EMIF1 DDR refresh and initialization sequence" "0,1" newline bitfld.long 0x04 18. "STD_FUSE_EMIF1_DDR3_LPDDR2N,EMIF1 DDR3" "0,1" newline bitfld.long 0x04 16. "STD_FUSE_HDCP_ENABLE,Enable hdcp" "0,1" newline bitfld.long 0x04 12. "STD_FUSE_CH_SPEEDUP_DISABLE,ROM code settings for configuration header block and speedup block" "0,1" newline bitfld.long 0x04 4. "STD_FUSE_SGX540_3D_CLOCK_SOURCE,Functional clock selection for the 3D accelerator engine" "0,1" newline bitfld.long 0x04 3. "STD_FUSE_SGX540_3D_DISABLE,Disable the 3D accelerator engine" "0,1" group.long 0x144++0x27 line.long 0x00 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT,SLICE register for emif1 and emif2" bitfld.long 0x00 17. "EMIF1_NARROW_ONLY,EMIF1 operates in narrow mode to allow for data macros to be powered down to save power" "0,1" newline bitfld.long 0x00 16. "EMIF1_EN_ECC,EMIF1 ECC enable" "0,1" newline bitfld.long 0x00 14.--15. "EMIF1_REG_PHY_NUM_OF_SAMPLES,Controls the number of DQ samples required for read leveling" "0,1,2,3" newline bitfld.long 0x00 13. "EMIF1_REG_PHY_SEL_LOGIC,Selects an algorithm for read leveling" "0,1" newline bitfld.long 0x00 12. "EMIF1_REG_PHY_ALL_DQ_MPR_RD_RESP,Analysis method of DQ bits during read leveling" "0,1" newline bitfld.long 0x00 9.--11. "EMIF1_REG_PHY_OUTPUT_STATUS_SELECT,Selects the status to be observed on the outputs of the DDR PHYs through" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "EMIF1_SDRAM_DISABLE_RESET,DDR3 SDRAM reset disable" "0,1" newline bitfld.long 0x00 5.--6. "EMIF1_PHY_RD_LOCAL_ODT,Control of ODT (on - die termination) settings for the device DDR I/Os" "0,1,2,3" newline bitfld.long 0x00 3. "EMIF1_DFI_CLOCK_PHASE_CTRL,EMIF_FICLK clock phase control (shifting by 180Degree)" "0,1" newline bitfld.long 0x00 2. "EMIF1_EN_SLICE_2,Enable command PHY 2" "0,1" newline bitfld.long 0x00 1. "EMIF1_EN_SLICE_1,Enable command PHY 1" "0,1" newline bitfld.long 0x00 0. "EMIF1_EN_SLICE_0,Enable command PHY 0" "0,1" line.long 0x04 "CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT,SLICE register for emif1 and emif2" bitfld.long 0x04 17. "EMIF2_NARROW_ONLY,EMIF2 operates in narrow mode to allow for data macros to be powered down to save power" "0,1" newline bitfld.long 0x04 14.--15. "EMIF2_REG_PHY_NUM_OF_SAMPLES,Controls the number of DQ samples required for read leveling" "0,1,2,3" newline bitfld.long 0x04 13. "EMIF2_REG_PHY_SEL_LOGIC,Selects an algorithm for read leveling" "0,1" newline bitfld.long 0x04 12. "EMIF2_REG_PHY_ALL_DQ_MPR_RD_RESP,Analysis method of DQ bits during read leveling" "0,1" newline bitfld.long 0x04 9.--11. "EMIF2_REG_PHY_OUTPUT_STATUS_SELECT,Selects the status to be observed on the outputs of the DDR PHYs through" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 7. "EMIF2_SDRAM_DISABLE_RESET,DDR3 SDRAM reset disable" "0,1" newline bitfld.long 0x04 5.--6. "EMIF2_PHY_RD_LOCAL_ODT,Control of ODT (on - die termination) settings for the device DDR I/Os" "0,1,2,3" newline bitfld.long 0x04 3. "EMIF2_DFI_CLOCK_PHASE_CTRL,EMIF_FICLK clock phase control (shifting by 180Degree)" "0,1" newline bitfld.long 0x04 2. "EMIF2_EN_SLICE_2,Enable command PHY 2" "0,1" newline bitfld.long 0x04 1. "EMIF2_EN_SLICE_1,Enable command PHY 1" "0,1" newline bitfld.long 0x04 0. "EMIF2_EN_SLICE_0,Enable command PHY 0" "0,1" line.long 0x08 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1," line.long 0x0C "CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT_2," line.long 0x10 "CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL,GPU Voltage Body Bias LDO Control register" bitfld.long 0x10 10. "LDOVBBGPU_FBB_MUX_CTRL,Override control of EFUSE Forward Body Bias voltage value" "0,1" newline rbitfld.long 0x10 5.--9. "LDOVBBGPU_FBB_VSET_IN,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 0.--4. "LDOVBBGPU_FBB_VSET_OUT,Override value for Forward Body Bias voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL,MPU Voltage Body Bias LDO Control register" bitfld.long 0x14 10. "LDOVBBMPU_FBB_MUX_CTRL,Override control of EFUSE Forward Body Bias voltage value" "0,1" newline rbitfld.long 0x14 5.--9. "LDOVBBMPU_FBB_VSET_IN,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "LDOVBBMPU_FBB_VSET_OUT,Override value for Forward Body Bias voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "CTRL_WKUP_LDOSRAM_GPU_VOLTAGE_CTRL,GPU SRAM LDO Control register" bitfld.long 0x18 26. "LDOSRAMGPU_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMGPU_RETMODE_MUX_CTRL_0,LDOSRAMGPU_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x18 21.--25. "LDOSRAMGPU_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 16.--20. "LDOSRAMGPU_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 10. "LDOSRAMGPU_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMGPU_ACTMODE_MUX_CTRL_0,LDOSRAMGPU_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x18 5.--9. "LDOSRAMGPU_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 0.--4. "LDOSRAMGPU_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "CTRL_WKUP_LDOSRAM_MPU_VOLTAGE_CTRL,MPU SRAM LDO Control register" bitfld.long 0x1C 26. "LDOSRAMMPU_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMMPU_RETMODE_MUX_CTRL_0,LDOSRAMMPU_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x1C 21.--25. "LDOSRAMMPU_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 16.--20. "LDOSRAMMPU_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 10. "LDOSRAMMPU_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMMPU_ACTMODE_MUX_CTRL_0,LDOSRAMMPU_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x1C 5.--9. "LDOSRAMMPU_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 0.--4. "LDOSRAMMPU_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "CTRL_WKUP_LDOSRAM_CORE_VOLTAGE_CTRL,Core SRAM LDO Control register" bitfld.long 0x20 26. "LDOSRAMCORE_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMCORE_RETMODE_MUX_CTRL_0,LDOSRAMCORE_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x20 21.--25. "LDOSRAMCORE_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 16.--20. "LDOSRAMCORE_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 10. "LDOSRAMCORE_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMCORE_ACTMODE_MUX_CTRL_0,LDOSRAMCORE_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x20 5.--9. "LDOSRAMCORE_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 0.--4. "LDOSRAMCORE_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "CTRL_WKUP_LDOSRAM_MPU_2_VOLTAGE_CTRL,MPU 2nd SRAM LDO Control register" bitfld.long 0x24 26. "LDOSRAMMPU_2_RETMODE_MUX_CTRL,Override control of EFUSE Retention Mode Voltage value - EFUSE" "LDOSRAMMPU_2_RETMODE_MUX_CTRL_0,LDOSRAMMPU_2_RETMODE_MUX_CTRL_1" newline rbitfld.long 0x24 21.--25. "LDOSRAMMPU_2_RETMODE_VSET_IN,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 16.--20. "LDOSRAMMPU_2_RETMODE_VSET_OUT,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 10. "LDOSRAMMPU_2_ACTMODE_MUX_CTRL,Override control of EFUSE Active Mode Voltage value - EFUSE" "LDOSRAMMPU_2_ACTMODE_MUX_CTRL_0,LDOSRAMMPU_2_ACTMODE_MUX_CTRL_1" newline rbitfld.long 0x24 5.--9. "LDOSRAMMPU_2_ACTMODE_VSET_IN,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x24 0.--4. "LDOSRAMMPU_2_ACTMODE_VSET_OUT,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x200++0x17 line.long 0x00 "CTRL_WKUP_STD_FUSE_DIE_ID_0,Die ID Register : Part 0" line.long 0x04 "CTRL_WKUP_ID_CODE,ID_CODE Key Register" line.long 0x08 "CTRL_WKUP_STD_FUSE_DIE_ID_1,Die ID Register : Part 1" line.long 0x0C "CTRL_WKUP_STD_FUSE_DIE_ID_2,Die ID Register : Part 2" line.long 0x10 "CTRL_WKUP_STD_FUSE_DIE_ID_3,Die ID Register : Part 3" line.long 0x14 "CTRL_WKUP_STD_FUSE_PROD_ID_0,Prod ID Register : Part 0" group.long 0x5AC++0x03 line.long 0x00 "CTRL_WKUP_CONTROL_XTAL_OSCILLATOR,XTAL OSCILLATOR control" bitfld.long 0x00 31. "OSCILLATOR0_BOOST,Fast startup control of OSC0" "0,1" newline rbitfld.long 0x00 30. "OSCILLATOR0_OS_OUT,Oscillator output of OSC0" "0,1" newline bitfld.long 0x00 29. "OSCILLATOR1_BOOST,Fast startup control of OSC1" "0,1" newline rbitfld.long 0x00 28. "OSCILLATOR1_OS_OUT,Oscillator output of OSC1" "0,1" group.long 0x5C8++0x0F line.long 0x00 "CTRL_WKUP_EFUSE_1,EFUSE compensation 1" bitfld.long 0x00 31. "DDRDIFF_PTV_NORTH_SIDE_N5," "0,1" newline bitfld.long 0x00 30. "DDRDIFF_PTV_NORTH_SIDE_N4," "0,1" newline bitfld.long 0x00 29. "DDRDIFF_PTV_NORTH_SIDE_N3," "0,1" newline bitfld.long 0x00 28. "DDRDIFF_PTV_NORTH_SIDE_N2," "0,1" newline bitfld.long 0x00 27. "DDRDIFF_PTV_NORTH_SIDE_N1," "0,1" newline bitfld.long 0x00 26. "DDRDIFF_PTV_NORTH_SIDE_N0," "0,1" newline bitfld.long 0x00 25. "DDRDIFF_PTV_NORTH_SIDE_P5," "0,1" newline bitfld.long 0x00 24. "DDRDIFF_PTV_NORTH_SIDE_P4," "0,1" newline bitfld.long 0x00 23. "DDRDIFF_PTV_NORTH_SIDE_P3," "0,1" newline bitfld.long 0x00 22. "DDRDIFF_PTV_NORTH_SIDE_P2," "0,1" newline bitfld.long 0x00 21. "DDRDIFF_PTV_NORTH_SIDE_P1," "0,1" newline bitfld.long 0x00 20. "DDRDIFF_PTV_NORTH_SIDE_P0," "0,1" newline bitfld.long 0x00 19. "DDRDIFF_PTV_EAST_SIDE_N5," "0,1" newline bitfld.long 0x00 18. "DDRDIFF_PTV_EAST_SIDE_N4," "0,1" newline bitfld.long 0x00 17. "DDRDIFF_PTV_EAST_SIDE_N3," "0,1" newline bitfld.long 0x00 16. "DDRDIFF_PTV_EAST_SIDE_N2," "0,1" newline bitfld.long 0x00 15. "DDRDIFF_PTV_EAST_SIDE_N1," "0,1" newline bitfld.long 0x00 14. "DDRDIFF_PTV_EAST_SIDE_N0," "0,1" newline bitfld.long 0x00 13. "DDRDIFF_PTV_EAST_SIDE_P5," "0,1" newline bitfld.long 0x00 12. "DDRDIFF_PTV_EAST_SIDE_P4," "0,1" newline bitfld.long 0x00 11. "DDRDIFF_PTV_EAST_SIDE_P3," "0,1" newline bitfld.long 0x00 10. "DDRDIFF_PTV_EAST_SIDE_P2," "0,1" newline bitfld.long 0x00 9. "DDRDIFF_PTV_EAST_SIDE_P1," "0,1" newline bitfld.long 0x00 8. "DDRDIFF_PTV_EAST_SIDE_P0," "0,1" line.long 0x04 "CTRL_WKUP_EFUSE_2,EFUSE compensation 2" bitfld.long 0x04 31. "DDRDIFF_PTV_SOUTH_SIDE_N5," "0,1" newline bitfld.long 0x04 30. "DDRDIFF_PTV_SOUTH_SIDE_N4," "0,1" newline bitfld.long 0x04 29. "DDRDIFF_PTV_SOUTH_SIDE_N3," "0,1" newline bitfld.long 0x04 28. "DDRDIFF_PTV_SOUTH_SIDE_N2," "0,1" newline bitfld.long 0x04 27. "DDRDIFF_PTV_SOUTH_SIDE_N1," "0,1" newline bitfld.long 0x04 26. "DDRDIFF_PTV_SOUTH_SIDE_N0," "0,1" newline bitfld.long 0x04 25. "DDRDIFF_PTV_SOUTH_SIDE_P5," "0,1" newline bitfld.long 0x04 24. "DDRDIFF_PTV_SOUTH_SIDE_P4," "0,1" newline bitfld.long 0x04 23. "DDRDIFF_PTV_SOUTH_SIDE_P3," "0,1" newline bitfld.long 0x04 22. "DDRDIFF_PTV_SOUTH_SIDE_P2," "0,1" newline bitfld.long 0x04 21. "DDRDIFF_PTV_SOUTH_SIDE_P1," "0,1" newline bitfld.long 0x04 20. "DDRDIFF_PTV_SOUTH_SIDE_P0," "0,1" newline bitfld.long 0x04 19. "DDRDIFF_PTV_WEST_SIDE_N5," "0,1" newline bitfld.long 0x04 18. "DDRDIFF_PTV_WEST_SIDE_N4," "0,1" newline bitfld.long 0x04 17. "DDRDIFF_PTV_WEST_SIDE_N3," "0,1" newline bitfld.long 0x04 16. "DDRDIFF_PTV_WEST_SIDE_N2," "0,1" newline bitfld.long 0x04 15. "DDRDIFF_PTV_WEST_SIDE_N1," "0,1" newline bitfld.long 0x04 14. "DDRDIFF_PTV_WEST_SIDE_N0," "0,1" newline bitfld.long 0x04 13. "DDRDIFF_PTV_WEST_SIDE_P5," "0,1" newline bitfld.long 0x04 12. "DDRDIFF_PTV_WEST_SIDE_P4," "0,1" newline bitfld.long 0x04 11. "DDRDIFF_PTV_WEST_SIDE_P3," "0,1" newline bitfld.long 0x04 10. "DDRDIFF_PTV_WEST_SIDE_P2," "0,1" newline bitfld.long 0x04 9. "DDRDIFF_PTV_WEST_SIDE_P1," "0,1" newline bitfld.long 0x04 8. "DDRDIFF_PTV_WEST_SIDE_P0," "0,1" line.long 0x08 "CTRL_WKUP_EFUSE_3,EFUSE compensation 3" bitfld.long 0x08 31. "DDRSE_PTV_NORTH_SIDE_N5," "0,1" newline bitfld.long 0x08 30. "DDRSE_PTV_NORTH_SIDE_N4," "0,1" newline bitfld.long 0x08 29. "DDRSE_PTV_NORTH_SIDE_N3," "0,1" newline bitfld.long 0x08 28. "DDRSE_PTV_NORTH_SIDE_N2," "0,1" newline bitfld.long 0x08 27. "DDRSE_PTV_NORTH_SIDE_N1," "0,1" newline bitfld.long 0x08 26. "DDRSE_PTV_NORTH_SIDE_N0," "0,1" newline bitfld.long 0x08 25. "DDRSE_PTV_NORTH_SIDE_P5," "0,1" newline bitfld.long 0x08 24. "DDRSE_PTV_NORTH_SIDE_P4," "0,1" newline bitfld.long 0x08 23. "DDRSE_PTV_NORTH_SIDE_P3," "0,1" newline bitfld.long 0x08 22. "DDRSE_PTV_NORTH_SIDE_P2," "0,1" newline bitfld.long 0x08 21. "DDRSE_PTV_NORTH_SIDE_P1," "0,1" newline bitfld.long 0x08 20. "DDRSE_PTV_NORTH_SIDE_P0," "0,1" newline bitfld.long 0x08 19. "DDRSE_PTV_EAST_SIDE_N5," "0,1" newline bitfld.long 0x08 18. "DDRSE_PTV_EAST_SIDE_N4," "0,1" newline bitfld.long 0x08 17. "DDRSE_PTV_EAST_SIDE_N3," "0,1" newline bitfld.long 0x08 16. "DDRSE_PTV_EAST_SIDE_N2," "0,1" newline bitfld.long 0x08 15. "DDRSE_PTV_EAST_SIDE_N1," "0,1" newline bitfld.long 0x08 14. "DDRSE_PTV_EAST_SIDE_N0," "0,1" newline bitfld.long 0x08 13. "DDRSE_PTV_EAST_SIDE_P5," "0,1" newline bitfld.long 0x08 12. "DDRSE_PTV_EAST_SIDE_P4," "0,1" newline bitfld.long 0x08 11. "DDRSE_PTV_EAST_SIDE_P3," "0,1" newline bitfld.long 0x08 10. "DDRSE_PTV_EAST_SIDE_P2," "0,1" newline bitfld.long 0x08 9. "DDRSE_PTV_EAST_SIDE_P1," "0,1" newline bitfld.long 0x08 8. "DDRSE_PTV_EAST_SIDE_P0," "0,1" line.long 0x0C "CTRL_WKUP_EFUSE_4,EFUSE compensation 4" bitfld.long 0x0C 31. "DDRSE_PTV_SOUTH_SIDE_N5," "0,1" newline bitfld.long 0x0C 30. "DDRSE_PTV_SOUTH_SIDE_N4," "0,1" newline bitfld.long 0x0C 29. "DDRSE_PTV_SOUTH_SIDE_N3," "0,1" newline bitfld.long 0x0C 28. "DDRSE_PTV_SOUTH_SIDE_N2," "0,1" newline bitfld.long 0x0C 27. "DDRSE_PTV_SOUTH_SIDE_N1," "0,1" newline bitfld.long 0x0C 26. "DDRSE_PTV_SOUTH_SIDE_N0," "0,1" newline bitfld.long 0x0C 25. "DDRSE_PTV_SOUTH_SIDE_P5," "0,1" newline bitfld.long 0x0C 24. "DDRSE_PTV_SOUTH_SIDE_P4," "0,1" newline bitfld.long 0x0C 23. "DDRSE_PTV_SOUTH_SIDE_P3," "0,1" newline bitfld.long 0x0C 22. "DDRSE_PTV_SOUTH_SIDE_P2," "0,1" newline bitfld.long 0x0C 21. "DDRSE_PTV_SOUTH_SIDE_P1," "0,1" newline bitfld.long 0x0C 20. "DDRSE_PTV_SOUTH_SIDE_P0," "0,1" newline bitfld.long 0x0C 19. "DDRSE_PTV_WEST_SIDE_N5," "0,1" newline bitfld.long 0x0C 18. "DDRSE_PTV_WEST_SIDE_N4," "0,1" newline bitfld.long 0x0C 17. "DDRSE_PTV_WEST_SIDE_N3," "0,1" newline bitfld.long 0x0C 16. "DDRSE_PTV_WEST_SIDE_N2," "0,1" newline bitfld.long 0x0C 15. "DDRSE_PTV_WEST_SIDE_N1," "0,1" newline bitfld.long 0x0C 14. "DDRSE_PTV_WEST_SIDE_N0," "0,1" newline bitfld.long 0x0C 13. "DDRSE_PTV_WEST_SIDE_P5," "0,1" newline bitfld.long 0x0C 12. "DDRSE_PTV_WEST_SIDE_P4," "0,1" newline bitfld.long 0x0C 11. "DDRSE_PTV_WEST_SIDE_P3," "0,1" newline bitfld.long 0x0C 10. "DDRSE_PTV_WEST_SIDE_P2," "0,1" newline bitfld.long 0x0C 9. "DDRSE_PTV_WEST_SIDE_P1," "0,1" newline bitfld.long 0x0C 8. "DDRSE_PTV_WEST_SIDE_P0," "0,1" group.long 0x5F8++0x03 line.long 0x00 "CTRL_WKUP_EFUSE_13," bitfld.long 0x00 31. "SDIO1833_PTV_N5," "0,1" newline bitfld.long 0x00 30. "SDIO1833_PTV_N4," "0,1" newline bitfld.long 0x00 29. "SDIO1833_PTV_N3," "0,1" newline bitfld.long 0x00 28. "SDIO1833_PTV_N2," "0,1" newline bitfld.long 0x00 27. "SDIO1833_PTV_N1," "0,1" newline bitfld.long 0x00 26. "SDIO1833_PTV_N0," "0,1" newline bitfld.long 0x00 25. "SDIO1833_PTV_P5," "0,1" newline bitfld.long 0x00 24. "SDIO1833_PTV_P4," "0,1" newline bitfld.long 0x00 23. "SDIO1833_PTV_P3," "0,1" newline bitfld.long 0x00 22. "SDIO1833_PTV_P2," "0,1" newline bitfld.long 0x00 21. "SDIO1833_PTV_P1," "0,1" newline bitfld.long 0x00 20. "SDIO1833_PTV_P0," "0,1" tree.end tree.end tree.open "DCAN" repeat 2. (list 2. 1. )(list ad:0x48480000 ad:0x4AE3C000 ) tree "DCAN$1" base $2 group.long 0x00++0x17 line.long 0x00 "DCAN_CTL,DCAN control register NOTE: The Bus-Off recovery sequence (refer to CAN specification) cannot be shortened by setting or resetting INIT bit" bitfld.long 0x00 25. "WUBA,Automatic wake up on bus activity when in local power-down mode" "WUBA_0,WUBA_1" bitfld.long 0x00 24. "PDR,Request for local low power-down mode" "PDR_0,PDR_1" bitfld.long 0x00 20. "DE3,Enable DMA request line for IF3" "DE3_0,DE3_1" bitfld.long 0x00 19. "DE2,Enable DMA request line for IF2" "DE2_0,DE2_1" newline bitfld.long 0x00 18. "DE1,Enable DMA request line for IF1" "DE1_0,DE1_1" bitfld.long 0x00 17. "IE1,Interrupt line 1 enable" "IE1_0,IE1_1" bitfld.long 0x00 16. "INITDBG,Internal init state while debug access" "INITDBG_0,INITDBG_1" bitfld.long 0x00 15. "SWR,Software reset enable" "SWR_0,SWR_1" newline bitfld.long 0x00 10.--13. "PMD,Parity on/off" "?,?,?,?,?,PMD_5,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 9. "ABO,Auto-Bus-On enable" "ABO_0,ABO_1" bitfld.long 0x00 8. "IDS,Interruption debug support enable" "IDS_0,IDS_1" bitfld.long 0x00 7. "TEST,Test mode enable" "TEST_0,TEST_1" newline bitfld.long 0x00 6. "CCE,Configuration change enable" "CCE_0,CCE_1" bitfld.long 0x00 5. "DAR,Disable automatic retransmission" "DAR_0,DAR_1" bitfld.long 0x00 3. "EIE,Error interrupt enable" "EIE_0,EIE_1" bitfld.long 0x00 2. "SIE,Status change interrupt enable" "SIE_0,SIE_1" newline bitfld.long 0x00 1. "IE0,Interrupt line 0 enable" "IE0_0,IE0_1" bitfld.long 0x00 0. "INIT,Initialization" "INIT_0,INIT_1" line.long 0x04 "DCAN_ES,Error and Status Register Interrupts are generated by bits PER. BOFF and EWARN (if EIE bit in is 1) and by bits WAKEUPPND. RXOK. TXOK. and LEC (if SIE bit in is 1)" rbitfld.long 0x04 10. "PDA,Local power-down mode acknowledge" "PDA_0,PDA_1" rbitfld.long 0x04 9. "WAKEUPPND,Wake up pending" "WAKEUPPND_0,WAKEUPPND_1" bitfld.long 0x04 8. "PER,Parity error detected" "PER_0_w,PER_1_w" rbitfld.long 0x04 7. "BOFF,Bus-Off state" "BOFF_0,BOFF_1" newline rbitfld.long 0x04 6. "EWARN,Warning state" "EWARN_0,EWARN_1" rbitfld.long 0x04 5. "EPASS,Error passive state" "EPASS_0,EPASS_1" rbitfld.long 0x04 4. "RXOK,Received a message successfully" "RXOK_0,RXOK_1" rbitfld.long 0x04 3. "TXOK,Transmitted a message successfully" "TXOK_0,TXOK_1" newline rbitfld.long 0x04 0.--2. "LEC,Last error code" "LEC_0,LEC_1,LEC_2,LEC_3,LEC_4,LEC_5,LEC_6,LEC_7" line.long 0x08 "DCAN_ERRC,Error Counter Register" bitfld.long 0x08 15. "RP,Receive error passive" "RP_0,RP_1" hexmask.long.byte 0x08 8.--14. 1. "REC,Receive error counter" hexmask.long.byte 0x08 0.--7. 1. "TEC,Transmit error counter" line.long 0x0C "DCAN_BTR,Bit timing register This register is only writable if CCE and INIT bits in the are set" bitfld.long 0x0C 16.--19. "BRPE,Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 12.--14. "TSEG2,Time segment after the sample point - Valid programmed values are 0 to 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--11. "TSEG1,Time segment before the sample point - Valid programmed values are 1 to15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 6.--7. "SJW,Synchronization Jump Width - Valid programmed values are 0 to 3" "0,1,2,3" newline bitfld.long 0x0C 0.--5. "BRP,Baud rate prescaler - Value by which the CAN_CLK frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "DCAN_INT,Interrupt register" hexmask.long.byte 0x10 16.--23. 1. "INT1ID,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)" hexmask.long.word 0x10 0.--15. 1. "INT0ID,Interrupt Identifier (the number here indicates the source of the interrupt)" line.long 0x14 "DCAN_TEST,Test Register For all test modes. the TEST bit in control register needs to be set to 1" bitfld.long 0x14 9. "RDA,RAM direct access enable" "RDA_0,RDA_1" bitfld.long 0x14 8. "EXL,External loopback mode" "EXL_0,EXL_1" rbitfld.long 0x14 7. "RX,Receive pin" "RX_0,RX_1" bitfld.long 0x14 5.--6. "TX,Control of CAN_TX pin" "TX_0,TX_1,TX_2,TX_3" newline bitfld.long 0x14 4. "LBACK,Loopback mode" "LBACK_0,LBACK_1" bitfld.long 0x14 3. "SILENT,Silent mode" "SILENT_0,SILENT_1" rgroup.long 0x1C++0x03 line.long 0x00 "DCAN_PERR,Parity Error Code Register If a parity error is detected. the PER flag will be set in" bitfld.long 0x00 8.--10. "WORD_NUMBER,Word number where parity error has been detected - RDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Message object number where parity error has been detected (0x01-0x80)" group.long 0x80++0x53 line.long 0x00 "DCAN_ABOTR,Auto-Bus-On Time Register On write access to the while Auto-Bus-On timer is running. the Auto-Bus-On procedure will be aborted" line.long 0x04 "DCAN_TXRQ_X,Transmission Request X Register The software can detect if one or more bits in the different transmission request registers are set" bitfld.long 0x04 14.--15. "TXRQSTREG8,Transmission request bits (aggregate for 113-128 message objects)" "0,1,2,3" bitfld.long 0x04 12.--13. "TXRQSTREG7,Transmission request bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x04 10.--11. "TXRQSTREG6,Transmission request bits (aggregate for 81-96 message objects)" "0,1,2,3" bitfld.long 0x04 8.--9. "TXRQSTREG5,Transmission request bits (aggregate for 65-80 message objects)" "0,1,2,3" newline bitfld.long 0x04 6.--7. "TXRQSTREG4,Transmission request bits (aggregate for 49-64 message objects)" "0,1,2,3" bitfld.long 0x04 4.--5. "TXRQSTREG3,Transmission request bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x04 2.--3. "TXRQSTREG2,Transmission request bits (aggregate for 17-32 message objects)" "0,1,2,3" bitfld.long 0x04 0.--1. "TXRQSTREG1,Transmission request bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x08 "DCAN_TXRQ12,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x0C "DCAN_TXRQ34,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x10 "DCAN_TXRQ56,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x14 "DCAN_TXRQ78,Transmission Request Register This register holds the TxRqst bits of the implemented message objects" line.long 0x18 "DCAN_NWDAT_X,New Data X Register With the new data X register. the software can detect if one or more bits in the different new data registers are set" bitfld.long 0x18 14.--15. "NEWDATREG8,New data bits (aggregate for 113-128 message objects)" "0,1,2,3" bitfld.long 0x18 12.--13. "NEWDATREG7,New data bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x18 10.--11. "NEWDATREG6,New data bits (aggregate for 81-96 message objects)" "0,1,2,3" bitfld.long 0x18 8.--9. "NEWDATREG5,New data bits (aggregate for 65-80 message objects)" "0,1,2,3" newline bitfld.long 0x18 6.--7. "NEWDATREG4,New data bits (aggregate for 49-64 message objects)" "0,1,2,3" bitfld.long 0x18 4.--5. "NEWDATREG3,New data bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x18 2.--3. "NEWDATREG2,New data bits (aggregate for 17-32 message objects)" "0,1,2,3" bitfld.long 0x18 0.--1. "NEWDATREG1,New data bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x1C "DCAN_NWDAT12,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x20 "DCAN_NWDAT34,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x24 "DCAN_NWDAT56,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x28 "DCAN_NWDAT78,New Data Register This register hold the NewDat bits of the implemented message objects" line.long 0x2C "DCAN_INTPND_X,Interrupt Pending X Register With the interrupt pending X register. the software can detect if one or more bits in the different interrupt pending registers are set" bitfld.long 0x2C 14.--15. "INTPNDREG8,Interrupt Pending bits (aggregate for 113-128 message objects)" "0,1,2,3" bitfld.long 0x2C 12.--13. "INTPNDREG7,Interrupt Pending bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x2C 10.--11. "INTPNDREG6,Interrupt Pendingbits (aggregate for 81-96 message objects)" "0,1,2,3" bitfld.long 0x2C 8.--9. "INTPNDREG5,Interrupt Pending bits (aggregate for 65-80 message objects)" "0,1,2,3" newline bitfld.long 0x2C 6.--7. "INTPNDREG4,Interrupt Pending bits (aggregate for 49-64 message objects)" "0,1,2,3" bitfld.long 0x2C 4.--5. "INTPNDREG3,Interrupt Pending bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x2C 2.--3. "INTPNDREG2,Interrupt Pending bits (aggregate for 17-32 message objects)" "0,1,2,3" bitfld.long 0x2C 0.--1. "INTPNDREG1,Interrupt Pending bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x30 "DCAN_INTPND12,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x34 "DCAN_INTPND34,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x38 "DCAN_INTPND56,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x3C "DCAN_INTPND78,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects" line.long 0x40 "DCAN_MSGVAL_X,Message Valid X Register With the message valid X register. the software can detect if one or more bits in the different message valid registers are set" bitfld.long 0x40 14.--15. "MSGVALREG8,Message valid bits (aggregate for 113-128 message objects)" "0,1,2,3" bitfld.long 0x40 12.--13. "MSGVALREG7,Message valid bits (aggregate for 97-112 message objects)" "0,1,2,3" bitfld.long 0x40 10.--11. "MSGVALREG6,Message valid bits (aggregate for 81-96 message objects)" "0,1,2,3" bitfld.long 0x40 8.--9. "MSGVALREG5,Message valid bits (aggregate for 65-80 message objects)" "0,1,2,3" newline bitfld.long 0x40 6.--7. "MSGVALREG4,Message valid bits (aggregate for 49-64 message objects)" "0,1,2,3" bitfld.long 0x40 4.--5. "MSGVALREG3,Message valid bits (aggregate for 33-48 message objects)" "0,1,2,3" bitfld.long 0x40 2.--3. "MSGVALREG2,Message valid bits (aggregate for 17-32 message objects)" "0,1,2,3" bitfld.long 0x40 0.--1. "MSGVALREG1,Message valid bits (aggregate for 1-16 message objects)" "0,1,2,3" line.long 0x44 "DCAN_MSGVAL12,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x48 "DCAN_MSGVAL34,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x4C "DCAN_MSGVAL56,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" line.long 0x50 "DCAN_MSGVAL78,Message Valid Register These registers hold the MsgVal bits of the implemented message objects" group.long 0xD8++0x0F line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer Register The IntMux flag determine for each message object. which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set" group.long 0x100++0x17 line.long 0x00 "DCAN_IF1CMD,IF1 Command Register The IF1 Command Register () configure and initiate the transfer between the IF1 register set and the message RAM" bitfld.long 0x00 23. "WR_RD,Write/Read" "WR_RD_0,WR_RD_1" bitfld.long 0x00 22. "MASK,Access mask bits" "MASK_0,MASK_1" bitfld.long 0x00 21. "ARB,Access arbitration bits" "ARB_0,ARB_1" bitfld.long 0x00 20. "CONTROL,Access control bits" "CONTROL_0,CONTROL_1" newline bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit" "CLRINTPND_0,CLRINTPND_1" bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bit" "TXRQST_NEWDAT_0,TXRQST_NEWDAT_1" bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "DATA_A_0,DATA_A_1" bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "DATA_B_0,DATA_B_1" newline bitfld.long 0x00 15. "BUSY,Busy flag" "BUSY_0,BUSY_1" bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF1 update" "DMAACTIVE_0,DMAACTIVE_1" hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer" line.long 0x04 "DCAN_IF1MSK,IF1 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object" bitfld.long 0x04 31. "MXTD,Mask Extended Identifier" "MXTD_0,MXTD_1" bitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF1ARB,IF1 arbitration register The Arbitration bits ID[28:0]. XTD. and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0]. MXTD. and MDIR) for acceptance filtering of incoming messages" bitfld.long 0x08 31. "MSGVAL,Message valid" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended identifier" "XTD_0,XTD_1" bitfld.long 0x08 29. "DIR,Message direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28:0]: 29-bit identifier (extended frame)" line.long 0x0C "DCAN_IF1MCTL,IF1 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object" bitfld.long 0x0C 15. "NEWDAT,New data" "NEWDAT_0,NEWDAT_1" bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt pending" "INTPND_0,INTPND_1" bitfld.long 0x0C 12. "UMASK,Use acceptance mask" "UMASK_0,UMASK_1" newline bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable" "TXIE_0,TXIE_1" bitfld.long 0x0C 10. "RXIE,Receive interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" bitfld.long 0x0C 8. "TXRQST,Transmit request" "TXRQST_0,TXRQST_1" newline bitfld.long 0x0C 7. "EOB,End of Block" "EOB_0,EOB_1" bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF1DATA,IF1 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF1DATB,IF1 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x120++0x17 line.long 0x00 "DCAN_IF2CMD,IF2 Command Register The IF2 Command Register () configure and initiate the transfer between the IF2 register set and the message RAM" bitfld.long 0x00 23. "WR_RD,Write/Read" "WR_RD_0,WR_RD_1" bitfld.long 0x00 22. "MASK,Access mask bits" "MASK_0,MASK_1" bitfld.long 0x00 21. "ARB,Access arbitration bits" "ARB_0,ARB_1" bitfld.long 0x00 20. "CONTROL,Access control bits" "CONTROL_0,CONTROL_1" newline bitfld.long 0x00 19. "CLRINTPND,Clear interrupt pending bit" "CLRINTPND_0,CLRINTPND_1" bitfld.long 0x00 18. "TXRQST_NEWDAT,Access transmission request bit" "TXRQST_NEWDAT_0,TXRQST_NEWDAT_1" bitfld.long 0x00 17. "DATA_A,Access Data Bytes" "DATA_A_0,DATA_A_1" bitfld.long 0x00 16. "DATA_B,Access Data Bytes" "DATA_B_0,DATA_B_1" newline bitfld.long 0x00 15. "BUSY,Busy flag" "BUSY_0,BUSY_1" bitfld.long 0x00 14. "DMAACTIVE,Activation of DMA feature for subsequent internal IF2 update" "DMAACTIVE_0,DMAACTIVE_1" hexmask.long.byte 0x00 0.--7. 1. "MESSAGE_NUMBER,Number of message object in message RAM which is used for data transfer" line.long 0x04 "DCAN_IF2MSK,IF2 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object" bitfld.long 0x04 31. "MXTD,Mask Extended Identifier" "MXTD_0,MXTD_1" bitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF2ARB,IF2 arbitration register The Arbitration bits ID[28:0]. XTD. and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0]. MXTD. and MDIR) for acceptance filtering of incoming messages" bitfld.long 0x08 31. "MSGVAL,Message valid" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended identifier" "XTD_0,XTD_1" bitfld.long 0x08 29. "DIR,Message direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message identifierID[28:0]: 29-bit identifier (extended frame)" line.long 0x0C "DCAN_IF2MCTL,IF2 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object" bitfld.long 0x0C 15. "NEWDAT,New data" "NEWDAT_0,NEWDAT_1" bitfld.long 0x0C 14. "MSGLST,Message lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt pending" "INTPND_0,INTPND_1" bitfld.long 0x0C 12. "UMASK,Use acceptance mask" "UMASK_0,UMASK_1" newline bitfld.long 0x0C 11. "TXIE,Transmit interrupt enable" "TXIE_0,TXIE_1" bitfld.long 0x0C 10. "RXIE,Receive interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" bitfld.long 0x0C 8. "TXRQST,Transmit request" "TXRQST_0,TXRQST_1" newline bitfld.long 0x0C 7. "EOB,End of Block" "EOB_0,EOB_1" bitfld.long 0x0C 0.--3. "DLC,Data length code0-8: Data frame has 0-8 data bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF2DATA,IF2 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF2DATB,IF2 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x140++0x17 line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from message RAM by software (Additional information can be found in NOTE: If IF3 Update.." rbitfld.long 0x00 15. "IF3_UPD,IF3 Update Data" "IF3_UPD_0,IF3_UPD_1" rbitfld.long 0x00 12. "IF3_SDB,IF3 Status of Data B read access" "IF3_SDB_0,IF3_SDB_1" rbitfld.long 0x00 11. "IF3_SDA,IF3 Status of Data A read access" "IF3_SDA_0,IF3_SDA_1" rbitfld.long 0x00 10. "IF3_SC,IF3 Status of control bits read access" "IF3_SC_0,IF3_SC_1" newline rbitfld.long 0x00 9. "IF3_SA,IF3 Status of Arbitration data read access" "IF3_SA_0,IF3_SA_1" rbitfld.long 0x00 8. "IF3_SM,IF3 Status of Mask data read access" "IF3_SM_0,IF3_SM_1" bitfld.long 0x00 4. "DATAB,Data B read observation" "DATAB_0,DATAB_1" bitfld.long 0x00 3. "DATAA,Data A read observation" "DATAA_0,DATAA_1" newline bitfld.long 0x00 2. "CTRL,Ctrl read observation" "CTRL_0,CTRL_1" bitfld.long 0x00 1. "ARB,Arbitration data read observation" "ARB_0,ARB_1" bitfld.long 0x00 0. "MASK,Mask data read observation" "MASK_0,MASK_1" line.long 0x04 "DCAN_IF3MSK,IF3 Mask Register" rbitfld.long 0x04 31. "MXTD,Mask Extended Identifier" "MXTD_0,MXTD_1" rbitfld.long 0x04 30. "MDIR,Mask Message Direction" "MDIR_0,MDIR_1" hexmask.long 0x04 0.--28. 1. "MSK,Identifier Mask" line.long 0x08 "DCAN_IF3ARB,IF3 Arbitration Register" bitfld.long 0x08 31. "MSGVAL,Message Valid" "MSGVAL_0,MSGVAL_1" bitfld.long 0x08 30. "XTD,Extended Identifier" "XTD_0,XTD_1" bitfld.long 0x08 29. "DIR,Message Direction" "DIR_0,DIR_1" hexmask.long 0x08 0.--28. 1. "ID,Message IdentifierID[28:0]: 29-bit Identifier ('extended frame')" line.long 0x0C "DCAN_IF3MCTL,IF3 Message Control Register" bitfld.long 0x0C 15. "NEWDAT,New Data" "NEWDAT_0,NEWDAT_1" bitfld.long 0x0C 14. "MSGLST,Message Lost (only valid for message objects with direction = receive)" "MSGLST_0,MSGLST_1" bitfld.long 0x0C 13. "INTPND,Interrupt Pending" "INTPND_0,INTPND_1" bitfld.long 0x0C 12. "UMASK,Use Acceptance Mask" "UMASK_0,UMASK_1" newline bitfld.long 0x0C 11. "TXIE,Transmit Interrupt enable" "TXIE_0,TXIE_1" bitfld.long 0x0C 10. "RXIE,Receive Interrupt enable" "RXIE_0,RXIE_1" bitfld.long 0x0C 9. "RMTEN,Remote enable" "RMTEN_0,RMTEN_1" bitfld.long 0x0C 8. "TXRQST,Transmit Request" "TXRQST_0,TXRQST_1" newline bitfld.long 0x0C 7. "EOB,End of Block" "EOB_0,EOB_1" bitfld.long 0x0C 0.--3. "DLC,Data Length Code0-8: Data frame has 0-8 data bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DCAN_IF3DATA,IF3 Data A The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x10 24.--31. 1. "DATA_3,Data byte 3" hexmask.long.byte 0x10 16.--23. 1. "DATA_2,Data byte 2" hexmask.long.byte 0x10 8.--15. 1. "DATA_1,Data byte 1" hexmask.long.byte 0x10 0.--7. 1. "DATA_0,Data byte 0" line.long 0x14 "DCAN_IF3DATB,IF3 Data B The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame. Data 0 is the first. and Data 7 is the last byte to be transmitted or received" hexmask.long.byte 0x14 24.--31. 1. "DATA_7,Data byte 7" hexmask.long.byte 0x14 16.--23. 1. "DATA_6,Data byte 6" hexmask.long.byte 0x14 8.--15. 1. "DATA_5,Data byte 5" hexmask.long.byte 0x14 0.--7. 1. "DATA_4,Data byte 4" group.long 0x160++0x0F line.long 0x00 "DCAN_IF3UPD12,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x04 "DCAN_IF3UPD34,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x08 "DCAN_IF3UPD56,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" line.long 0x0C "DCAN_IF3UPD78,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object" group.long 0x1E0++0x07 line.long 0x00 "DCAN_TIOC,TX I/O Control Register The CAN_TX pin of the DCAN module can be used as general purpose IO pin if CAN function is not needed" bitfld.long 0x00 18. "PU,CAN_TX pull up/pull down select" "PU_0,PU_1" bitfld.long 0x00 17. "PD,CAN_TX pull disable" "PD_0,PD_1" bitfld.long 0x00 16. "OD,CAN_TX open drain enable" "OD_0,OD_1" bitfld.long 0x00 3. "FUNC,CAN_TX function" "FUNC_0,FUNC_1" newline bitfld.long 0x00 2. "DIR,CAN_TX data direction" "DIR_0,DIR_1" bitfld.long 0x00 1. "OUT,CAN_TX data out" "OUT_0,OUT_1" bitfld.long 0x00 0. "IN,CAN_TX data in" "IN_0,IN_1" line.long 0x04 "DCAN_RIOC,RX I/O Control Register The CAN_RX pin of the DCAN_module can be used as general purpose IO pin if CAN function is not needed" bitfld.long 0x04 18. "PU,CAN_RX pull up/pull down select" "PU_0,PU_1" bitfld.long 0x04 17. "PD,CAN_RX pull disable" "PD_0,PD_1" bitfld.long 0x04 16. "OD,CAN_RX open drain enable" "OD_0,OD_1" bitfld.long 0x04 3. "FUNC,CAN_RX function" "FUNC_0,FUNC_1" newline bitfld.long 0x04 2. "DIR,CAN_RX data direction" "DIR_0,DIR_1" bitfld.long 0x04 1. "OUT,CAN_RX data out" "OUT_0,OUT_1" bitfld.long 0x04 0. "IN,CAN_RX data in" "IN_0,IN_1" tree.end repeat.end tree.end tree.open "Display_Controller" tree "DISPC" base ad:0x58001000 rgroup.long 0x00++0x03 line.long 0x00 "DISPC_REVISION,IP Revision" group.long 0x10++0x0F line.long 0x00 "DISPC_SYSCONFIG,This register allows to control various parameters of the OCP interface" bitfld.long 0x00 12.--13. "MIDLEMODE,Master interface power management standby/wait control - fStandBy" "MIDLEMODE_0,MIDLEMODE_1,MIDLEMODE_2,MIDLEMODE_3" newline bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period - OCPFuncOff" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" newline bitfld.long 0x00 5. "WARMRESET,Warm reset" "WARMRESET_0,WARMRESET_1" newline bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management Idle req/ack control - fIdle" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" newline bitfld.long 0x00 2. "ENWAKEUP,WakeUp feature control - WakeUpDis" "ENWAKEUP_0,ENWAKEUP_1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock gating strategy - ClkFree" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "DISPC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - rstongoing" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "DISPC_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt" bitfld.long 0x08 31. "FLIPIMMEDIATEDONE_IRQ,Flip Immediate Done" "FLIPIMMEDIATEDONE_IRQ_0,FLIPIMMEDIATEDONE_IRQ_1" newline bitfld.long 0x08 30. "FRAMEDONE3_IRQ,Frame done for the third LCD" "FRAMEDONE3_IRQ_0,FRAMEDONE3_IRQ_1" newline bitfld.long 0x08 29. "ACBIASCOUNT STATUS3_IRQ,AC bias count status for the third LCD - False" "ACBIASCOUNT STATUS3_IRQ_0,ACBIASCOUNT STATUS3_IRQ_1" newline bitfld.long 0x08 28. "VSYNC3_IRQ,Vertical synchronization for the third LCD - False" "VSYNC3_IRQ_0,VSYNC3_IRQ_1" newline bitfld.long 0x08 27. "SYNCLOST3_IRQ,Synchronization lost on the third LCD output" "SYNCLOST3_IRQ_0,SYNCLOST3_IRQ_1" newline bitfld.long 0x08 26. "WBUNCOMPLETE ERROR_IRQ,Write-back DMA buffer is flushed before it is completely drained" "WBUNCOMPLETE ERROR_IRQ_0,WBUNCOMPLETE ERROR_IRQ_1" newline bitfld.long 0x08 25. "WBBUFFER OVERFLOW_IRQ,Write-back DMA buffer overflow" "WBBUFFER OVERFLOW_IRQ_0,WBBUFFER OVERFLOW_IRQ_1" newline bitfld.long 0x08 24. "FRAME DONETV_IRQ,Frame done for the TV" "FRAME DONETV_IRQ_0,FRAME DONETV_IRQ_1" newline bitfld.long 0x08 23. "FRAME DONEWB_IRQ,Frame done for the write-back channel" "FRAME DONEWB_IRQ_0,FRAME DONEWB_IRQ_1" newline bitfld.long 0x08 22. "FRAME DONE2_IRQ,Frame done for the secondary LCD" "FRAME DONE2_IRQ_0,FRAME DONE2_IRQ_1" newline bitfld.long 0x08 21. "ACBIASCOUNT STATUS2_IRQ,AC bias count status for the secondary LCD - False" "ACBIASCOUNT STATUS2_IRQ_0,ACBIASCOUNT STATUS2_IRQ_1" newline bitfld.long 0x08 20. "VID3BUFFER UNDERFLOW_IRQ,Video 3 DMA buffer underflow" "VID3BUFFER UNDERFLOW_IRQ_0,VID3BUFFER UNDERFLOW_IRQ_1" newline bitfld.long 0x08 19. "VID3END WINDOW_IRQ,The end of the video 3 window has been reached" "VID3END WINDOW_IRQ_0,VID3END WINDOW_IRQ_1" newline bitfld.long 0x08 18. "VSYNC2_IRQ,Vertical synchronization for the secondary LCD - False" "VSYNC2_IRQ_0,VSYNC2_IRQ_1" newline bitfld.long 0x08 17. "SYNC LOST2_IRQ,Synchronization lost on the secondary LCD output" "SYNC LOST2_IRQ_0,SYNC LOST2_IRQ_1" newline bitfld.long 0x08 16. "WAKEUP_IRQ,Wakeup - False" "WAKEUP_IRQ_0,WAKEUP_IRQ_1" newline bitfld.long 0x08 15. "SYNCLOST TV_IRQ,Synchronization lost on the TV output" "SYNCLOST TV_IRQ_0,SYNCLOST TV_IRQ_1" newline bitfld.long 0x08 14. "SYNC LOST1_IRQ,Synchronizationl ost on the primary LCD output" "SYNC LOST1_IRQ_0,SYNC LOST1_IRQ_1" newline bitfld.long 0x08 13. "VID2END WINDOW_IRQ,The end of the video 2 Window has been reached" "VID2END WINDOW_IRQ_0,VID2END WINDOW_IRQ_1" newline bitfld.long 0x08 12. "VID2BUFFER UNDERFLOW_IRQ,Video 2 DMA buffer underflow" "VID2BUFFER UNDERFLOW_IRQ_0,VID2BUFFER UNDERFLOW_IRQ_1" newline bitfld.long 0x08 11. "VID1END WINDOW_IRQ,The end of the video 1 Window has been reached" "VID1END WINDOW_IRQ_0,VID1END WINDOW_IRQ_1" newline bitfld.long 0x08 10. "VID1BUFFER UNDERFLOW_IRQ,Video 1 DMA buffer underflow" "VID1BUFFER UNDERFLOW_IRQ_0,VID1BUFFER UNDERFLOW_IRQ_1" newline bitfld.long 0x08 9. "OCPERROR_IRQ,OCP error" "OCPERROR_IRQ_0,OCPERROR_IRQ_1" newline bitfld.long 0x08 8. "PALETTEGAMMA LOADING_IRQ,Palette Gamma loading status" "PALETTEGAMMA LOADING_IRQ_0,PALETTEGAMMA LOADING_IRQ_1" newline bitfld.long 0x08 7. "GFXEND WINDOW_IRQ,The end of the graphics wndow has been reached" "GFXEND WINDOW_IRQ_0,GFXEND WINDOW_IRQ_1" newline bitfld.long 0x08 6. "GFXBUFFER UNDERFLOW_IRQ,Graphics DMA buffer underflow" "GFXBUFFER UNDERFLOW_IRQ_0,GFXBUFFER UNDERFLOW_IRQ_1" newline bitfld.long 0x08 5. "PROGRAMMED LINENUMBER_IRQ,Programmed line number" "PROGRAMMED LINENUMBER_IRQ_0,PROGRAMMED LINENUMBER_IRQ_1" newline bitfld.long 0x08 4. "ACBIASCOUNT STATUS1_IRQ,AC bias count status for the primary LCD - False" "ACBIASCOUNT STATUS1_IRQ_0,ACBIASCOUNT STATUS1_IRQ_1" newline bitfld.long 0x08 3. "EVSYNC_ ODD_IRQ,VSYNC for odd field from the TV encoder (HDMI) - False" "EVSYNC_ ODD_IRQ_0,EVSYNC_ ODD_IRQ_1" newline bitfld.long 0x08 2. "EVSYNC_ EVEN_IRQ,VSYNC for even field from the TV encoder (HDMI) - False" "EVSYNC_ EVEN_IRQ_0,EVSYNC_ EVEN_IRQ_1" newline bitfld.long 0x08 1. "VSYNC1_IRQ,Vertical synchronization for the primary LCD" "VSYNC1_IRQ_0,VSYNC1_IRQ_1" newline bitfld.long 0x08 0. "FRAME DONE1_IRQ,Frame done for the primary LCD" "FRAME DONE1_IRQ_0,FRAME DONE1_IRQ_1" line.long 0x0C "DISPC_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt. on an event-by-event basis" bitfld.long 0x0C 31. "FLIPIMMEDIATEDONE_EN,Flip Immediate Done" "FLIPIMMEDIATEDONE_EN_0,FLIPIMMEDIATEDONE_EN_1" newline bitfld.long 0x0C 30. "FRAME DONE3_EN,Frame done for the third LCD" "FRAME DONE3_EN_0,FRAME DONE3_EN_1" newline bitfld.long 0x0C 29. "ACBIASCOUNT STATUS3_EN,AC Bias count status for the third LCD - masked" "ACBIASCOUNT STATUS3_EN_0,ACBIASCOUNT STATUS3_EN_1" newline bitfld.long 0x0C 28. "VSYNC3_EN,Vertical synchronization for the third LCD - masked" "VSYNC3_EN_0,VSYNC3_EN_1" newline bitfld.long 0x0C 27. "SYNC LOST3_EN,Synchronization lost on the third LCD output" "SYNC LOST3_EN_0,SYNC LOST3_EN_1" newline bitfld.long 0x0C 26. "WBUNCOMPLETE ERROR_EN,The write back buffer has been flushed before been fully drained" "WBUNCOMPLETE ERROR_EN_0,WBUNCOMPLETE ERROR_EN_1" newline bitfld.long 0x0C 25. "WBBUFFER OVERFLOW_EN,Write-back DMA buffer overflow" "WBBUFFER OVERFLOW_EN_0,WBBUFFER OVERFLOW_EN_1" newline bitfld.long 0x0C 24. "FRAME DONETV_EN,Frame done for the TV" "FRAME DONETV_EN_0,FRAME DONETV_EN_1" newline bitfld.long 0x0C 23. "FRAME DONEWB_EN,Frame done for the write-back channel" "FRAME DONEWB_EN_0,FRAME DONEWB_EN_1" newline bitfld.long 0x0C 22. "FRAME DONE2_EN,Frame done for the secondary LCD" "FRAME DONE2_EN_0,FRAME DONE2_EN_1" newline bitfld.long 0x0C 21. "ACBIASCOUNT STATUS2_EN,AC Bias count status for the secondary LCD - masked" "ACBIASCOUNT STATUS2_EN_0,ACBIASCOUNT STATUS2_EN_1" newline bitfld.long 0x0C 20. "VID3BUFFER UNDERFLOW_EN,Video 3 DMA Buffer Underflow" "VID3BUFFER UNDERFLOW_EN_0,VID3BUFFER UNDERFLOW_EN_1" newline bitfld.long 0x0C 19. "VID3END WINDOW_EN,The end of the video 3 window has been reached" "VID3END WINDOW_EN_0,VID3END WINDOW_EN_1" newline bitfld.long 0x0C 18. "VSYNC2_EN,Vertical synchronization for the secondary LCD - masked" "VSYNC2_EN_0,VSYNC2_EN_1" newline bitfld.long 0x0C 17. "SYNC LOST2_EN,Synchronization lost on the secondary LCD output" "SYNC LOST2_EN_0,SYNC LOST2_EN_1" newline bitfld.long 0x0C 16. "WAKEUP_EN,Wake up mask - masked" "WAKEUP_EN_0,WAKEUP_EN_1" newline bitfld.long 0x0C 15. "SYNC LOSTTV_EN,Synchronization lost on the TV output" "SYNC LOSTTV_EN_0,SYNC LOSTTV_EN_1" newline bitfld.long 0x0C 14. "SYNC LOST1_EN,Synchronization lost for the primary LCD - masked" "SYNC LOST1_EN_0,SYNC LOST1_EN_1" newline bitfld.long 0x0C 13. "VID2END WINDOW_EN,The end of the video 2 Window has been reached" "VID2END WINDOW_EN_0,VID2END WINDOW_EN_1" newline bitfld.long 0x0C 12. "VID2BUFFER UNDERFLOW_EN,Video 2 DMA buffer underflow" "VID2BUFFER UNDERFLOW_EN_0,VID2BUFFER UNDERFLOW_EN_1" newline bitfld.long 0x0C 11. "ENDVID1 WINDOW_EN,The end of the video 1 window has been reached" "ENDVID1 WINDOW_EN_0,ENDVID1 WINDOW_EN_1" newline bitfld.long 0x0C 10. "VID1BUFFER UNDERFLOW_EN,Video 1 DMA buffer underflow" "VID1BUFFER UNDERFLOW_EN_0,VID1BUFFER UNDERFLOW_EN_1" newline bitfld.long 0x0C 9. "OCPERROR_EN,OCP Error" "OCPERROR_EN_0,OCPERROR_EN_1" newline bitfld.long 0x0C 8. "PALETTE GAMMA_EN,Palette gamma loading mask" "PALETTE GAMMA_EN_0,PALETTE GAMMA_EN_1" newline bitfld.long 0x0C 7. "GFXEND WINDOW_EN,The end of the graphics Window has been reached" "GFXEND WINDOW_EN_0,GFXEND WINDOW_EN_1" newline bitfld.long 0x0C 6. "GFXBUFFER UNDERFLOW_EN,Graphics DMA Buffer Underflow" "GFXBUFFER UNDERFLOW_EN_0,GFXBUFFER UNDERFLOW_EN_1" newline bitfld.long 0x0C 5. "PROGRAMMED LINENUMBER_EN,Programmed Line Number" "PROGRAMMED LINENUMBER_EN_0,PROGRAMMED LINENUMBER_EN_1" newline bitfld.long 0x0C 4. "ACBIASCOUNT STATUS1_EN,AC Bias count status for the primary LCD - masked" "ACBIASCOUNT STATUS1_EN_0,ACBIASCOUNT STATUS1_EN_1" newline bitfld.long 0x0C 3. "EVSYNC_ODD_EN,VSYNC for odd field from the TV encoder (HDMI) - masked" "EVSYNC_ODD_EN_0,EVSYNC_ODD_EN_1" newline bitfld.long 0x0C 2. "EVSYNC_EVEN_EN,VSYNC for even field from the TV encoder (HDMI) - masked" "EVSYNC_EVEN_EN_0,EVSYNC_EVEN_EN_1" newline bitfld.long 0x0C 1. "VSYNC1_EN,Vertical synchronization for the primary LCD" "VSYNC1_EN_0,VSYNC1_EN_1" newline bitfld.long 0x0C 0. "FRAMEDONE_EN,Frame done for the primary LCD" "FRAMEDONE_EN_0,FRAMEDONE_EN_1" group.long 0x40++0x07 line.long 0x00 "DISPC_CONTROL1,The control register configures the Display Controller module for the primary LCD and TV outputs" bitfld.long 0x00 30.--31. "SPATIALTEMPORAL DITHERINGFRAMES,Spatial/temporal dithering number of frames for the primary LCD output wr: VFP start period of primary LCD - OneFrame" "SPATIALTEMPORAL DITHERINGFRAMES_0,SPATIALTEMPORAL DITHERINGFRAMES_1,SPATIALTEMPORAL DITHERINGFRAMES_2,SPATIALTEMPORAL DITHERINGFRAMES_3" newline rbitfld.long 0x00 29. "LCDENABLEPOL,Write 0s for future compatibility" "LCDENABLEPOL_0,LCDENABLEPOL_1" newline rbitfld.long 0x00 28. "LCDENABLESIGNAL,Write 0s for future compatibility" "LCDENABLESIGNAL_0,LCDENABLESIGNAL_1" newline rbitfld.long 0x00 27. "PCKFREEENABLE,Write 0s for future compatibility" "PCKFREEENABLE_0,PCKFREEENABLE_1" newline bitfld.long 0x00 25.--26. "TDMUNUSEDBITS,State of unused bits (TDM mode only) for the primary LCD output" "TDMUNUSEDBITS_0,TDMUNUSEDBITS_1,TDMUNUSEDBITS_2,TDMUNUSEDBITS_3" newline bitfld.long 0x00 23.--24. "TDMCYCLEFORMAT,Cycle format (TDM mode only) for the primary LCD output WR: VFP start period of primary LCD - 1CycPerPix" "TDMCYCLEFORMAT_0,TDMCYCLEFORMAT_1,TDMCYCLEFORMAT_2,TDMCYCLEFORMAT_3" newline bitfld.long 0x00 21.--22. "TDMPARALLELMODE,Output interface width (TDM mode only) for the primary LCD output WR: VFP start period of primary LCD - 8bParaInt" "TDMPARALLELMODE_0,TDMPARALLELMODE_1,TDMPARALLELMODE_2,TDMPARALLELMODE_3" newline bitfld.long 0x00 20. "TDMENABLE,Enable the multiple cycle format for the primary LCD output" "TDMENABLE_0,TDMENABLE_1" newline bitfld.long 0x00 17.--19. "HT,Hold time for TV output WR: EVSYNC Encoded value (from 1 to 8) to specify the number of external digital clock periods to hold the data (programmed value = value minus 1)" "HT_0,HT_1,HT_2,HT_3,HT_4,HT_5,HT_6,HT_7" newline bitfld.long 0x00 16. "GPOUT1,General purpose output signal l WR: immediate - reset" "GPOUT1_0,GPOUT1_1" newline bitfld.long 0x00 15. "GPOUT0,General Purpose Output Signal WR:immediate - reset" "GPOUT0_0,GPOUT0_1" newline rbitfld.long 0x00 14. "GPIN1,General purpose input signal WR: immediately - reset" "GPIN1_0_r,GPIN1_1_r" newline rbitfld.long 0x00 13. "GPIN0,General purpose input signal WR: immediately - GPin0Rst" "GPIN0_0_r,GPIN0_1_r" newline bitfld.long 0x00 12. "OVERLAYOPTI MIZATION,Overlay optimization for the primary LCD output WR: VFP start period of the primary LCD - GDBVWfM" "OVERLAYOPTI MIZATION_0,OVERLAYOPTI MIZATION_1" newline bitfld.long 0x00 8.--9. "TFTDATALINES,Number of lines of the primary LCD interface WR: VFP start period of primary LCD - OaLSB12b" "TFTDATALINES_0,TFTDATALINES_1,TFTDATALINES_2,TFTDATALINES_3" newline bitfld.long 0x00 7. "STDITHERENABLE,Spatial temporal dithering enable for the primary LCD output WR: VFP start period of primary LCD - STDithDis" "STDITHERENABLE_0,STDITHERENABLE_1" newline bitfld.long 0x00 6. "GOTV,GO command for the TV output" "GOTV_0,GOTV_1" newline bitfld.long 0x00 5. "GOLCD,GO command for the primary LCD output" "GOLCD_0,GOLCD_1" newline bitfld.long 0x00 4. "M8B,Mono 8-bit mode of the primary LCD wr: VFP start period of primary LCD output - 4PixtoPanel" "M8B_0,M8B_1" newline bitfld.long 0x00 3. "STNTFT,LCD Display type of the primary LCD WR: VFP start period of primary LCD output - STNdispEnb" "STNTFT_0,STNTFT_1" newline bitfld.long 0x00 2. "MONOCOLOR,Monochrome/color selection for the primary LCD WR: VFP start period of primary LCD output - ColOpEnb" "MONOCOLOR_0,MONOCOLOR_1" newline bitfld.long 0x00 1. "TVENABLE,Enable the TV output wr: immediate effect only occurs at the end of the current frame" "TVENABLE_0,TVENABLE_1" newline bitfld.long 0x00 0. "LCDENABLE,Enable the primary LCD outputs wr: immediate Effect only occurs at the end of the current frame - LCDOpDis" "LCDENABLE_0,LCDENABLE_1" line.long 0x04 "DISPC_CONFIG1,The control register configures the Display Controller module for the primary LCD output and TV output" bitfld.long 0x04 28.--29. "TVINTERLEAVE,TV Interleave Pattern" "0,1,2,3" newline bitfld.long 0x04 26.--27. "PLCDINTERLEAVE,pLCD Interleave Pattern" "0,1,2,3" newline bitfld.long 0x04 25. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x04 24. "COLORCONV ENABLE,Enable the color space conversion" "COLORCONV ENABLE_0,COLORCONV ENABLE_1" newline bitfld.long 0x04 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "FIDFIRST_0,FIDFIRST_1" newline bitfld.long 0x04 22. "OUTPUTMODE ENABLE,Selects between progressive and interlace mode for the primary LCD output" "OUTPUTMODE ENABLE_0,OUTPUTMODE ENABLE_1" newline bitfld.long 0x04 21. "BT1120ENABLE,Selects BT.1120 format on the primary LCD output" "BT1120ENABLE_0,BT1120ENABLE_1" newline bitfld.long 0x04 20. "BT656ENABLE,Selects BT.656 format on the primary LCD output" "BT656ENABLE_0,BT656ENABLE_1" newline bitfld.long 0x04 19. "TVALPHABLENDER ENABLE,Selects the alpha blender overlay manager for the TV output instead of the color key alpha blender (LCD output)" "TVALPHABLENDER ENABLE_0,TVALPHABLENDER ENABLE_1" newline bitfld.long 0x04 18. "LCDALPHABLENDER ENABLE,Selects the alpha blender overlay manager for the primary LCD output instead of the color key alpha blender (LCD output)" "LCDALPHABLENDER ENABLE_0,LCDALPHABLENDER ENABLE_1" newline bitfld.long 0x04 17. "BUFFERFILLING,Controls if the DMA buffers are refilled only when the LOW threshold is reached or if all DMA buffers are refilled when at least one of them reaches the LOW threshold" "BUFFERFILLING_0,BUFFERFILLING_1" newline bitfld.long 0x04 15. "CPR,Color phase rotation control (primary LCD output)" "CPR_0,CPR_1" newline bitfld.long 0x04 14. "BUFFERMERGE,Buffer merge control wr: EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline)" "BUFFERMERGE_0,BUFFERMERGE_1" newline bitfld.long 0x04 13. "TCKTV SELECTION,Transparency color key selection (TV output) wr: EVSYNC - GDTCK" "TCKTV SELECTION_0,TCKTV SELECTION_1" newline bitfld.long 0x04 12. "TCKTVENABLE,Transparency color key enabled (TV output) WR: EVSYNC - DisTCK" "TCKTVENABLE_0,TCKTVENABLE_1" newline bitfld.long 0x04 11. "TCKLCD SELECTION,Transparency color key selection (primary LCD output) wr: VFP start period of primary LCD output - GDTK" "TCKLCD SELECTION_0,TCKLCD SELECTION_1" newline bitfld.long 0x04 10. "TCKLCDENABLE,Transparency color key enabled (primary LCD output) wr: VFP start period of primary LCD output - DisTCK" "TCKLCDENABLE_0,TCKLCDENABLE_1" newline bitfld.long 0x04 9. "GAMATABLE ENABLE,For backward compatibility an enable bit has been added on the 2 additional gamma tables (secondary display and TV)" "GAMATABLE ENABLE_0,GAMATABLE ENABLE_1" newline bitfld.long 0x04 8. "ACBIASGATED,ACBias Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - ACBGDis" "ACBIASGATED_0,ACBIASGATED_1" newline bitfld.long 0x04 7. "VSYNCGATED,VSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - VGDis" "VSYNCGATED_0,VSYNCGATED_1" newline bitfld.long 0x04 6. "HSYNCGATED,HSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - HGDis" "HSYNCGATED_0,HSYNCGATED_1" newline bitfld.long 0x04 5. "PIXELCLOCK GATED,Pixel Clock Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output - PCGDis" "PIXELCLOCK GATED_0,PIXELCLOCK GATED_1" newline bitfld.long 0x04 4. "PIXELDATAGATED,Pixel data gated enabled (primary LCD output) wr: VFP start period of primary LCD output - PDGDis" "PIXELDATAGATED_0,PIXELDATAGATED_1" newline bitfld.long 0x04 3. "PALETTEGAMMA TABLE,Palette/gamma table selection wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the.." "PALETTEGAMMA TABLE_0,PALETTEGAMMA TABLE_1" newline bitfld.long 0x04 1.--2. "LOADMODE,Loading mode for the palette/gamma table wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the.." "LOADMODE_0,LOADMODE_1,LOADMODE_2,LOADMODE_3" newline bitfld.long 0x04 0. "PIXELGATED,Pixel gated enable (only for TFT) (primary LCD output) wr: VFP start period of primary LCD output - PclkTogA" "PIXELGATED_0,PIXELGATED_1" group.long 0x4C++0x33 line.long 0x00 "DISPC_DEFAULT_COLOR0,The control register allows to configure the default solid background color for the primary LCD" hexmask.long.tbyte 0x00 0.--23. 1. "DEFAULTCOLOR,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" line.long 0x04 "DISPC_DEFAULT_COLOR1,The control register allows to configure the default solid background color for the TV output" hexmask.long.tbyte 0x04 0.--23. 1. "DEFAULTCOLOR,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" line.long 0x08 "DISPC_TRANS_COLOR0,The register sets the transparency color value for the video/graphics overlays for the primary LCD output" hexmask.long.tbyte 0x08 0.--23. 1. "TRANSCOLORKEY,Transparency color key value in RGB format [0] BITMAP 1 (CLUT) [23 1] set to 0s [1:0] BITMAP 2 (CLUT) [23 2] set to 0s [3:0] BITMAP 4 (CLUT) [23 4] set to 0s [7:0] BITMAP 8 (CLUT) [23 8] set to 0s [11:0] RGB 12 [23 12] set to 0s [15:0] RGB.." line.long 0x0C "DISPC_TRANS_COLOR1,The register sets the transparency color value for the video/graphics overlays for the TV output" hexmask.long.tbyte 0x0C 0.--23. 1. "TRANSCOLORKEY,Transparency color key value in RGB format [0] BITMAP 1 (CLUT) [23 1] set to 0s [1:0] BITMAP 2 (CLUT) [23 2] set to 0s [3:0] BITMAP 4 (CLUT) [23 4] set to 0s [7:0] BITMAP 8 (CLUT) [23 8] set to 0s [11:0] RGB 12 [23 12] set to 0s [15:0] RGB.." line.long 0x10 "DISPC_LINE_STATUS,The control register indicates the current primary LCD panel display line number" hexmask.long.word 0x10 0.--11. 1. "LINENUMBER,Current LCD panel line number Current display line number" line.long 0x14 "DISPC_LINE_NUMBER,The control register indicates the primary LCD panel display line number for the interrupt and the DMA request" hexmask.long.word 0x14 0.--11. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs" line.long 0x18 "DISPC_TIMING_H1,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x18 20.--31. 1. "HBP,Horizontal Back Porch" newline hexmask.long.word 0x18 8.--19. 1. "HFP,Horizontal front porch" newline hexmask.long.byte 0x18 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1)" line.long 0x1C "DISPC_TIMING_V1,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x1C 20.--31. 1. "VBP,Vertical back porch encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame" newline hexmask.long.word 0x1C 8.--19. 1. "VFP,Vertical front porch encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame" newline hexmask.long.byte 0x1C 0.--7. 1. "VSW,Vertical synchronization pulse width In active mode encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP).." line.long 0x20 "DISPC_POL_FREQ1,The register configures the signal configuration" bitfld.long 0x20 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "ALIGN_0,ALIGN_1" newline bitfld.long 0x20 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off - DOpEdPCk" "ONOFF_0,ONOFF_1" newline bitfld.long 0x20 16. "RF,Program HSYNC/VSYNC Rise or Fall - DFEdPCk" "RF_0,RF_1" newline bitfld.long 0x20 15. "IEO,Invert output enable - ACBaHigh" "IEO_0,IEO_1" newline bitfld.long 0x20 14. "IPC,Invert pixel clock - DrPCk" "IPC_0,IPC_1" newline bitfld.long 0x20 13. "IHS,Invert HSYNC - LCkpinAh" "IHS_0,IHS_1" newline bitfld.long 0x20 12. "IVS,Invert VSYNC - FCkpinAh" "IVS_0,IVS_1" newline bitfld.long 0x20 8.--11. "ACBI,AC Bias pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "ACBI_0,ACBI_1,ACBI_2,ACBI_3,ACBI_4,ACBI_5,ACBI_6,ACBI_7,ACBI_8,ACBI_9,ACBI_10,ACBI_11,ACBI_12,ACBI_13,ACBI_14,ACBI_15" newline hexmask.long.byte 0x20 0.--7. 1. "ACB,AC Bias pin frequency value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin" line.long 0x24 "DISPC_DIVISOR1,The register configures the divisors" hexmask.long.byte 0x24 16.--23. 1. "LCD,Display controller logic clock divisor value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD1_CLK" newline hexmask.long.byte 0x24 0.--7. 1. "PCD,Pixel clock divisor value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD1_CLK divided byDISPC_DIVISOR1.LCD value" line.long 0x28 "DISPC_GLOBAL_ALPHA,The register defines the global alpha value for the graphics and three video pipelines" hexmask.long.byte 0x28 24.--31. 1. "VID3GLOBALALPHA,Global alpha value from 0 to 255" newline hexmask.long.byte 0x28 16.--23. 1. "VID2GLOBALALPHA,Global alpha value from 0 to 255" newline hexmask.long.byte 0x28 8.--15. 1. "VID1GLOBALALPHA,Global alpha value from 0 to 255" newline hexmask.long.byte 0x28 0.--7. 1. "GFXGLOBALALPHA,Global alpha value from 0 to 255" line.long 0x2C "DISPC_SIZE_TV,The register configures the size of the TV output field (interlace). frame (progressive) (horizontal and vertical)" hexmask.long.word 0x2C 16.--27. 1. "LPP,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel" newline bitfld.long 0x2C 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field - same" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" newline hexmask.long.word 0x2C 0.--11. 1. "PPL,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display" line.long 0x30 "DISPC_SIZE_LCD1,The register configures the panel size (horizontal and vertical)" hexmask.long.word 0x30 16.--27. 1. "LPP,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)" newline bitfld.long 0x30 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field - Same" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" newline hexmask.long.word 0x30 0.--11. 1. "PPL,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus 1)" group.long 0x88++0x07 line.long 0x00 "DISPC_GFX_POSITION,The register configures the position of the graphics window" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the graphics window" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the graphics window" line.long 0x04 "DISPC_GFX_SIZE,The register configures the size of the graphics window" hexmask.long.word 0x04 16.--27. 1. "SIZEY,Number of lines of the graphics window" newline hexmask.long.word 0x04 0.--11. 1. "SIZEX,Number of pixels of the graphics window" group.long 0xA0++0x13 line.long 0x00 "DISPC_GFX_ATTRIBUTES,The register configures the graphics attributes" bitfld.long 0x00 30.--31. "CHANNELOUT2,It is not used if CHANNELOUT is set to TV" "CHANNELOUT2_0,CHANNELOUT2_1,CHANNELOUT2_2,CHANNELOUT2_3" newline bitfld.long 0x00 29. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x00 26.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3" newline bitfld.long 0x00 25. "ZORDERENABLE,Z-order Enable" "ZORDERENABLE_0,ZORDERENABLE_1" newline bitfld.long 0x00 24. "ANTIFLICKER,Antiflicker filtering using a 3-tap filter with hardcoded coefficients (1/4 1/2 " "ANTIFLICKER_0,ANTIFLICKER_1" newline bitfld.long 0x00 18.--20. "SUBSAMPLINGPATTERN,Subsampling pattern setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self-refresh mode - SelfRefreshAutoDis" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" newline bitfld.long 0x00 16. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x00 15. "SELFREFRESH,Enables the self refresh of the graphics window from its own DMA buffer" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x00 14. "ARBITRATION,Determines the priority of the graphics pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x00 12.--13. "ROTATION,Graphics rotation flag - NoRot" "ROTATION_0,ROTATION_1,ROTATION_2,ROTATION_3" newline bitfld.long 0x00 11. "BUFPRELOAD,Graphics preload value - DefVal" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x00 10. "FRAMEPACKINGMODE,Frame packing mode control" "FRAMEPACKINGMODE_0,FRAMEPACKINGMODE_1" newline bitfld.long 0x00 9. "NIBBLEMODE,Graphics nibble mode (only for 1- 2- and 4 bpp) - NibMDis" "NIBBLEMODE_0,NIBBLEMODE_1" newline bitfld.long 0x00 8. "CHANNELOUT,Graphics Channel Out configuration: LCD WB or TV" "CHANNELOUT_0,CHANNELOUT_1" newline bitfld.long 0x00 6.--7. "BURSTSIZE,Graphics DMA burst size - Burst2x128" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 5. "REPLICATIONENABLE,Graphics replication enabled: RGB" "REPLICATIONENABLE_0,REPLICATIONENABLE_1" newline bitfld.long 0x00 1.--4. "FORMAT,Graphics format" "?,?,?,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x00 0. "ENABLE,Graphics enable - GraphicsDis" "ENABLE_0,ENABLE_1" line.long 0x04 "DISPC_GFX_BUF_THRESHOLD,The register configures the graphics buffer" hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128bits defining the threshold value" line.long 0x08 "DISPC_GFX_BUF_SIZE_STATUS,The register defines the Graphics buffer size" hexmask.long.word 0x08 0.--15. 1. "BUFSIZE,DMA buffer size in number of 128 bits" line.long 0x0C "DISPC_GFX_ROW_INC,The register configures the number of bytes to increment at the end of the row" line.long 0x10 "DISPC_GFX_PIXEL_INC,The register configures the number of bytes to increment between two pixels" hexmask.long.byte 0x10 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" group.long 0xB8++0x03 line.long 0x00 "DISPC_GFX_TABLE_BA,The register configures the base address of the palette buffer or the gamma table buffer" group.long 0xC4++0x23 line.long 0x00 "DISPC_VID1_POSITION,The register configures the position of the video window 1" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the video window 1 Encoded value (from 0 to 2047) to specify the Y position of the video window 1 .The line at the top has the Y-position 0" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the video window 1 Encoded value (from 0 to 2047) to specify the X position of the video window 1" line.long 0x04 "DISPC_VID1_SIZE,The register configures the size of the video window 1" hexmask.long.word 0x04 16.--27. 1. "SIZEY,Number of lines of the video 1 Encoded value (from 1 to 4096) to specify the number of lines of the video window 1" newline hexmask.long.word 0x04 0.--11. 1. "SIZEX,Number of pixels of the video window 1 Encoded value (from 1 to 4096) to specify the number of pixels of the video window 1" line.long 0x08 "DISPC_VID1_ATTRIBUTES,The register configures the attributes of the video window 1" bitfld.long 0x08 30.--31. "CHANNELOUT2,It is not used if CHANNELOUT is set to TV" "CHANNELOUT2_0,CHANNELOUT2_1,CHANNELOUT2_2,CHANNELOUT2_3" newline bitfld.long 0x08 29. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x08 28. "PREMULTIPHYALPHA,The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPHYALPHA_0,PREMULTIPHYALPHA_1" newline bitfld.long 0x08 26.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3" newline bitfld.long 0x08 25. "ZORDERENABLE,Z-order Enable" "ZORDERENABLE_0,ZORDERENABLE_1" newline bitfld.long 0x08 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x08 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x08 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x08 21. "VERTICALTAPS,Video vertical resize tap number" "VERTICALTAPS_0,VERTICALTAPS_1" newline bitfld.long 0x08 20. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x08 19. "BUFPRELOAD,Video Preload Value - DefVal" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x08 17. "SELFREFRESHAUTO,Automatic self-refresh mode - SelfRefreshAutoDis" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" newline bitfld.long 0x08 16. "CHANNELOUT,Video channel out configuration: LCD WB or TV" "CHANNELOUT_0,CHANNELOUT_1" newline bitfld.long 0x08 14.--15. "BURSTSIZE,Video DMA burst size - Burst2x128b" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x08 12.--13. "ROTATION,Video rotation flag - NoRot" "ROTATION_0,ROTATION_1,ROTATION_2,ROTATION_3" newline bitfld.long 0x08 11. "FULLRANGE,Color space conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x08 10. "REPLICATIONENABLE,Replication enable - VRepLDis" "REPLICATIONENABLE_0,REPLICATIONENABLE_1" newline bitfld.long 0x08 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x08 8. "FRAMEPACKINGMODE,Frame packing mode control" "FRAMEPACKINGMODE_0,FRAMEPACKINGMODE_1" newline rbitfld.long 0x08 7. "HRESIZECONF,Write 0s for future compatibility" "HRESIZECONF_0,HRESIZECONF_1" newline bitfld.long 0x08 5.--6. "RESIZEENABLE,Video Resize Enable - ReSizeProc" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" newline bitfld.long 0x08 1.--4. "FORMAT,Video Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x08 0. "ENABLE,Video Enable - VideoDis" "ENABLE_0,ENABLE_1" line.long 0x0C "DISPC_VID1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline 1" hexmask.long.word 0x0C 16.--31. 1. "BUFHIGHTHRESHOLD,Video DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x0C 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" line.long 0x10 "DISPC_VID1_BUF_SIZE_STATUS,The register defines the Video buffer size for the video pipeline 1" hexmask.long.word 0x10 0.--15. 1. "BUFSIZE,Video 1 DMA buffer size in number of 128-bits" line.long 0x14 "DISPC_VID1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 1" line.long 0x18 "DISPC_VID1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2" hexmask.long.byte 0x18 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" line.long 0x1C "DISPC_VID1_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1" hexmask.long.word 0x1C 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter" newline hexmask.long.word 0x1C 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter" line.long 0x20 "DISPC_VID1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 1 before up/down-scaling" hexmask.long.word 0x20 16.--27. 1. "MEMSIZEY,Number of lines of the video picture" newline hexmask.long.word 0x20 0.--10. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1)" group.long 0x130++0x13 line.long 0x00 "DISPC_VID1_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x00 16.--26. 1. "RCR,RCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x00 0.--10. 1. "RY,RY coefficient encoded signed value (from -1024 to 1023)" line.long 0x04 "DISPC_VID1_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x04 16.--26. 1. "GY,GY coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x04 0.--10. 1. "RCB,RCb coefficient encoded signed value (from -1024 to 1023)" line.long 0x08 "DISPC_VID1_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x08 16.--26. 1. "GCB,GCb coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x08 0.--10. 1. "GCR,GCr coefficient encoded signed value (from -1024 to 1023)" line.long 0x0C "DISPC_VID1_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x0C 16.--26. 1. "BCR,BCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x0C 0.--10. 1. "BY,BY coefficient encoded signed value (from -1024 to 1023)" line.long 0x10 "DISPC_VID1_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 1" hexmask.long.word 0x10 0.--10. 1. "BCB,BCb coefficient encoded signed value (from -1024 to 1023)" group.long 0x154++0x23 line.long 0x00 "DISPC_VID2_POSITION,The register configures the position of the video window 2" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the video window 2 encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the video window 2 encoded value (from 0 to 2047) to specify the X position of the video window 2" line.long 0x04 "DISPC_VID2_SIZE,The register configures the size of the video window 2" hexmask.long.word 0x04 16.--27. 1. "SIZEY,Number of lines of the video 2 encoded value (from 1 to 4096) to specify the number of lines of the video window 2" newline hexmask.long.word 0x04 0.--11. 1. "SIZEX,Number of pixels of the video window 2 encoded value (from 1 to 4096) to specify the number of pixels of the video window 2" line.long 0x08 "DISPC_VID2_ATTRIBUTES,The register configures the attributes of the video window 2" bitfld.long 0x08 30.--31. "CHANNELOUT2,It is not used if CHANNELOUT is set to TV" "CHANNELOUT2_0,CHANNELOUT2_1,CHANNELOUT2_2,CHANNELOUT2_3" newline bitfld.long 0x08 29. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x08 28. "PREMULTIPLYALPHA,The field configures the DISPC VID2 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x08 26.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3" newline bitfld.long 0x08 25. "ZORDERENABLE,Z-order Enable" "ZORDERENABLE_0,ZORDERENABLE_1" newline bitfld.long 0x08 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x08 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x08 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x08 21. "VERTICALTAPS,Video Vertical Resize Tap Number - taps3" "VERTICALTAPS_0,VERTICALTAPS_1" newline bitfld.long 0x08 20. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x08 19. "BUFPRELOAD,Video Preload Value - DefVal" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x08 17. "SELFREFRESHAUTO,Automatic self-refresh mode - SelfRefreshAutoDis" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" newline bitfld.long 0x08 16. "CHANNELOUT,Video Channel Out configuration: LCD WB or TV" "CHANNELOUT_0,CHANNELOUT_1" newline bitfld.long 0x08 14.--15. "BURSTSIZE,Video DMA burst size - Burst2x128b" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x08 12.--13. "ROTATION,Video Rotation Flag - NoRot" "ROTATION_0,ROTATION_1,ROTATION_2,ROTATION_3" newline bitfld.long 0x08 11. "FULLRANGE,Color space conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x08 10. "REPLICATIONENABLE,Replication Enable - VRepLDis" "REPLICATIONENABLE_0,REPLICATIONENABLE_1" newline bitfld.long 0x08 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x08 8. "FRAMEPACKINGMODE,Frame packing mode control" "FRAMEPACKINGMODE_0,FRAMEPACKINGMODE_1" newline rbitfld.long 0x08 7. "HRESIZECONF,Write 0s for future compatibility" "HRESIZECONF_0,HRESIZECONF_1" newline bitfld.long 0x08 5.--6. "RESIZEENABLE,Video Resize Enable - ReSizeProc" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" newline bitfld.long 0x08 1.--4. "FORMAT,Video Format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x08 0. "ENABLE,VidEnable - VideoDis" "ENABLE_0,ENABLE_1" line.long 0x0C "DISPC_VID2_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 2" hexmask.long.word 0x0C 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x0C 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" line.long 0x10 "DISPC_VID2_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 2" hexmask.long.word 0x10 0.--15. 1. "BUFSIZE,DMA buffer size in number of 128 bits" line.long 0x14 "DISPC_VID2_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 2" line.long 0x18 "DISPC_VID2_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2" hexmask.long.byte 0x18 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" line.long 0x1C "DISPC_VID2_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2" hexmask.long.word 0x1C 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096)" newline hexmask.long.word 0x1C 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096)" line.long 0x20 "DISPC_VID2_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 2 before up/down-scaling" hexmask.long.word 0x20 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1)" newline hexmask.long.word 0x20 0.--10. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1)" group.long 0x1C0++0x1F line.long 0x00 "DISPC_VID2_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x00 16.--26. 1. "RCR,RCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x00 0.--10. 1. "RY,RY coefficient encoded signed value (from -1024 to 1023)" line.long 0x04 "DISPC_VID2_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x04 16.--26. 1. "GY,GY coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x04 0.--10. 1. "RCB,RCb coefficient encoded signed value (from -1024 to 1023)" line.long 0x08 "DISPC_VID2_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x08 16.--26. 1. "GCB,GCb coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x08 0.--10. 1. "GCR,GCr coefficient encoded signed value (from -1024 to 1023)" line.long 0x0C "DISPC_VID2_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x0C 16.--26. 1. "BCR,BCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x0C 0.--10. 1. "BY,BY coefficient encoded signed value (from -1024 to 1023)" line.long 0x10 "DISPC_VID2_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 2" hexmask.long.word 0x10 0.--10. 1. "BCB,BCb coefficient encoded signed value (from -1024 to 1023)" line.long 0x14 "DISPC_DATA1_CYCLE1,The control register configures the output data format for 1st cycle" bitfld.long 0x14 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x14 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x14 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x14 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x18 "DISPC_DATA1_CYCLE2,The control register configures the output data format for 2nd cycle" bitfld.long 0x18 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x18 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x18 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x18 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x1C "DISPC_DATA1_CYCLE3,The control register configures the output data format for 3rd cycle" bitfld.long 0x1C 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x1C 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x1C 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x1C 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" group.long 0x220++0x1B line.long 0x00 "DISPC_CPR1_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component" hexmask.long.word 0x00 22.--31. 1. "RR,RR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 11.--20. 1. "RG,RG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x00 0.--9. 1. "RB,RB coefficient encoded signed value (from -512 to 511)" line.long 0x04 "DISPC_CPR1_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component" hexmask.long.word 0x04 22.--31. 1. "GR,GR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x04 11.--20. 1. "GG,GG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x04 0.--9. 1. "GB,GB coefficient encoded signed value (from -512 to 511)" line.long 0x08 "DISPC_CPR1_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component" hexmask.long.word 0x08 22.--31. 1. "BR,BR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x08 11.--20. 1. "BG,BG coefficient encoded signed value (from -512 to 511" newline hexmask.long.word 0x08 0.--9. 1. "BB,BB coefficient encoded signed value (from -512 to 511)" line.long 0x0C "DISPC_GFX_PRELOAD,The register configures the graphics DMA buffer Shadow register. updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software.." hexmask.long.word 0x0C 0.--11. 1. "PRELOAD,DMA buffer preload value number of 128-bit words defining the preload value" line.long 0x10 "DISPC_VID1_PRELOAD,The register configures the DMA buffer of the video 1 pipeline" hexmask.long.word 0x10 0.--11. 1. "PRELOAD,DMA buffer preload value number of 128-bit words defining the preload value" line.long 0x14 "DISPC_VID2_PRELOAD,The register configures the DMA buffer of the video 2 pipeline" hexmask.long.word 0x14 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x18 "DISPC_CONTROL2,The control register configures the Display Controller module for the secondary LCD output" bitfld.long 0x18 30.--31. "SPATIALTEMPORAL DITHERINGFRAMES,Spatial/temporal dithering number of frames for the secondary LCD output wr: VFP start period of secondary LCD output - OneFrame" "SPATIALTEMPORAL DITHERINGFRAMES_0,SPATIALTEMPORAL DITHERINGFRAMES_1,SPATIALTEMPORAL DITHERINGFRAMES_2,SPATIALTEMPORAL DITHERINGFRAMES_3" newline bitfld.long 0x18 25.--26. "TDMUNUSED BITS,State of unused bits (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - LowLevel" "TDMUNUSED BITS_0,TDMUNUSED BITS_1,TDMUNUSED BITS_2,TDMUNUSED BITS_3" newline bitfld.long 0x18 23.--24. "TDMCYCLE FORMAT,Cycle format (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - 1CycPerPix" "TDMCYCLE FORMAT_0,TDMCYCLE FORMAT_1,TDMCYCLE FORMAT_2,TDMCYCLE FORMAT_3" newline bitfld.long 0x18 21.--22. "TDMPARALLEL MODE,Output Interface width (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output - 8bParaInt" "TDMPARALLEL MODE_0,TDMPARALLEL MODE_1,TDMPARALLEL MODE_2,TDMPARALLEL MODE_3" newline bitfld.long 0x18 20. "TDMENABLE,Enable the multiple cycle format for the secondary LCD output wr: VFP start period of secondary LCD output - TDMDis" "TDMENABLE_0,TDMENABLE_1" newline bitfld.long 0x18 13. "TVOVERLAY OPTIMIZATION,Overlay optimization for the TV output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline)" "TVOVERLAY OPTIMIZATION_0,TVOVERLAY OPTIMIZATION_1" newline bitfld.long 0x18 12. "OVERLAY OPTIMIZATION,Overlay optimization for the secondary LCD output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline)" "OVERLAY OPTIMIZATION_0,OVERLAY OPTIMIZATION_1" newline bitfld.long 0x18 11. "STALLMODE,STALL mode for the secondary LCD output wr: VFP start period of secondary LCD output - nMode" "STALLMODE_0,STALLMODE_1" newline bitfld.long 0x18 8.--9. "TFTDATALINES,Number of lines of the secondary LCD interface wr: VFP start period of secondary LCD output - OaLSB12b" "TFTDATALINES_0,TFTDATALINES_1,TFTDATALINES_2,TFTDATALINES_3" newline bitfld.long 0x18 7. "STDITHER ENABLE,Spatial temporal dithering enable for the secondary LCD output wr: VFP start period of secondary LCD output - STDithDis" "STDITHER ENABLE_0,STDITHER ENABLE_1" newline bitfld.long 0x18 6. "GOWB,GO command for the write-back output" "GOWB_0,GOWB_1" newline bitfld.long 0x18 5. "GOLCD,GO command for the secondary LCD output" "GOLCD_0,GOLCD_1" newline bitfld.long 0x18 4. "M8B,Mono 8-bit mode of the secondary LCD wr: VFP start period of secondary LCD output - 4PixtoPanel" "M8B_0,M8B_1" newline bitfld.long 0x18 3. "STNTFT,LCD Display type of the secondary LCD wr: VFP start period of secondary LCD output - STNdispEnb" "STNTFT_0,STNTFT_1" newline bitfld.long 0x18 2. "MONOCOLOR,Monochrome/Color selection for the secondary LCD wr: VFP start period of secondary LCD output - ColOpEnb" "MONOCOLOR_0,MONOCOLOR_1" newline bitfld.long 0x18 0. "LCDENABLE,Enable the secondary LCD output wr:immediate - LCDOpDis" "LCDENABLE_0,LCDENABLE_1" group.long 0x240++0x0F line.long 0x00 "DISPC_GFX_POSITION2,The register configures the position of the 2nd graphics window in FramePacking mode" hexmask.long.word 0x00 16.--26. 1. "POSY,Y position of the 2nd graphics window" newline hexmask.long.word 0x00 0.--10. 1. "POSX,X position of the 2nd graphics window" line.long 0x04 "DISPC_VID1_POSITION2,The register configures the position of the 2nd video window #1 in FramePacking mode" hexmask.long.word 0x04 16.--26. 1. "POSY,Y position of the 2nd video window #1 Encoded value (from 0 to 2047) to specify the Y position of the video window #1 .The line at the top has the Y-position 0" newline hexmask.long.word 0x04 0.--10. 1. "POSX,X position of the 2nd video window #1 Encoded value (from 0 to 2047) to specify the X position of the video window #1" line.long 0x08 "DISPC_VID2_POSITION2,The register configures the position of the 2nd video window #2 in FramePacking mode" hexmask.long.word 0x08 16.--26. 1. "POSY,Y position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the Y position of the video window #2 .The line at the top has the Y-position 0" newline hexmask.long.word 0x08 0.--10. 1. "POSX,X position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the X position of the video window #2" line.long 0x0C "DISPC_VID3_POSITION2,The register configures the position of the 2nd video window #3 in FramePacking mode" hexmask.long.word 0x0C 16.--26. 1. "POSY,Y position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the Y position of the video window #2 .The line at the top has the Y-position 0" newline hexmask.long.word 0x0C 0.--10. 1. "POSX,X position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the X position of the video window #2" group.long 0x370++0x5F line.long 0x00 "DISPC_VID3_ATTRIBUTES,The register configures the attributes of the video window 3" bitfld.long 0x00 30.--31. "CHANNELOUT2,It is not used if CHANNELOUT is set to TV" "CHANNELOUT2_0,CHANNELOUT2_1,CHANNELOUT2_2,CHANNELOUT2_3" newline bitfld.long 0x00 29. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC VID3 to process incoming data as premultiplied alpha data or non premultiplied alpha data" "PREMULTIPLYALPHA_0,PREMULTIPLYALPHA_1" newline bitfld.long 0x00 26.--27. "ZORDER,Z-Order defining the priority of the layer compared to others when overlaying" "ZORDER_0,ZORDER_1,ZORDER_2,ZORDER_3" newline bitfld.long 0x00 25. "ZORDERENABLE,Z-order Enable" "ZORDERENABLE_0,ZORDERENABLE_1" newline bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "SELFREFRESH_0,SELFREFRESH_1" newline bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x00 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x00 21. "VERTICALTAPS,Video vertical resize tap number - taps3" "VERTICALTAPS_0,VERTICALTAPS_1" newline bitfld.long 0x00 20. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x00 19. "BUFPRELOAD,Video Preload Value - DefVal" "BUFPRELOAD_0,BUFPRELOAD_1" newline bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self-refresh mode - SelfRefreshAutoDis" "SELFREFRESHAUTO_0,SELFREFRESHAUTO_1" newline bitfld.long 0x00 16. "CHANNELOUT,Video channel out configuration: LCD WB or TV" "CHANNELOUT_0,CHANNELOUT_1" newline bitfld.long 0x00 14.--15. "BURSTSIZE,Video DMA burst size - Burst2x128b" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 12.--13. "ROTATION,Video rotation flag - NoRot" "ROTATION_0,ROTATION_1,ROTATION_2,ROTATION_3" newline bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 10. "REPLICATIONENABLE,Replication enable - VRepLDis" "REPLICATIONENABLE_0,REPLICATIONENABLE_1" newline bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x00 8. "FRAMEPACKINGMODE,Frame packing mode control" "FRAMEPACKINGMODE_0,FRAMEPACKINGMODE_1" newline rbitfld.long 0x00 7. "HRESIZECONF,Write 0s for future compatibility" "HRESIZECONF_0,HRESIZECONF_1" newline bitfld.long 0x00 5.--6. "RESIZEENABLE,Video resize enable - ReSizeProc" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" newline bitfld.long 0x00 1.--4. "FORMAT,Video format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x00 0. "ENABLE,Video Enable - VideoDis" "ENABLE_0,ENABLE_1" line.long 0x04 "DISPC_VID3_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x04 16.--26. 1. "RCR,RCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x04 0.--10. 1. "RY,RY coefficient encoded signed value (from -1024 to 1023)" line.long 0x08 "DISPC_VID3_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x08 16.--26. 1. "GY,GY coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x08 0.--10. 1. "RCB,RCb coefficient encoded signed value (from -1024 to 1023)" line.long 0x0C "DISPC_VID3_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x0C 16.--26. 1. "GCB,GCb coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x0C 0.--10. 1. "GCR,GCr coefficient encoded signed value (from -1024 to 1023)" line.long 0x10 "DISPC_VID3_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x10 16.--26. 1. "BCR,BCr coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x10 0.--10. 1. "BY,BY coefficient encoded signed value (from -1024 to 1023)" line.long 0x14 "DISPC_VID3_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 3" hexmask.long.word 0x14 0.--10. 1. "BCB,BCb coefficient encoded signed value (from -1024 to 1023)" line.long 0x18 "DISPC_VID3_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 3" hexmask.long.word 0x18 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128 bits" line.long 0x1C "DISPC_VID3_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 3" hexmask.long.word 0x1C 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x1C 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" line.long 0x20 "DISPC_VID3_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3" hexmask.long.word 0x20 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096)" newline hexmask.long.word 0x20 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096)" line.long 0x24 "DISPC_VID3_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 3 before up/down-scaling" hexmask.long.word 0x24 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1)" newline hexmask.long.word 0x24 0.--10. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1)" line.long 0x28 "DISPC_VID3_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 3" hexmask.long.byte 0x28 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels" line.long 0x2C "DISPC_VID3_POSITION,The register configures the position of the video window 3" hexmask.long.word 0x2C 16.--26. 1. "POSY,Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0" newline hexmask.long.word 0x2C 0.--10. 1. "POSX,X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2" line.long 0x30 "DISPC_VID3_PRELOAD,The register configures the DMA buffer of the video 3 pipeline" hexmask.long.word 0x30 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value" line.long 0x34 "DISPC_VID3_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 3" line.long 0x38 "DISPC_VID3_SIZE,The register configures the size of the video window 3" hexmask.long.word 0x38 16.--27. 1. "SIZEY,Number of lines of the video 3 Encoded value (from 1 to 4096) to specify the number of lines of the video window 3" newline hexmask.long.word 0x38 0.--11. 1. "SIZEX,Number of pixels of the video window 3 Encoded value (from 1 to 4096) to specify the number of pixels of the video window 3" line.long 0x3C "DISPC_DEFAULT_COLOR2,The control register allows to configure the default solid background color for the secondary LCD Shadow register. updated on VFP start period of secondary LCD" hexmask.long.tbyte 0x3C 0.--23. 1. "DEFAULTCOLOR,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" line.long 0x40 "DISPC_TRANS_COLOR2,The register sets the transparency color value for the video/graphics overlays for the secondary LCD output" hexmask.long.tbyte 0x40 0.--23. 1. "TRANSCOLORKEY,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT) [23 1] set to 0s [1:0] BITMAP 2 (CLUT) [23 2] set to 0s [3:0] BITMAP 4 (CLUT) [23 4] set to 0s [7:0] BITMAP 8 (CLUT) [23 8] set to 0s [11:0] RGB 12 [23 12] set to 0s [15:0] RGB.." line.long 0x44 "DISPC_CPR2_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component" hexmask.long.word 0x44 22.--31. 1. "BR,BR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x44 11.--20. 1. "BG,BG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x44 0.--9. 1. "BB,BB coefficient encoded signed value (from -512 to 511)" line.long 0x48 "DISPC_CPR2_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component" hexmask.long.word 0x48 22.--31. 1. "GR,GR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x48 11.--20. 1. "GG,GG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x48 0.--9. 1. "GB,GB coefficient encoded signed value (from -512 to 511)" line.long 0x4C "DISPC_CPR2_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component" hexmask.long.word 0x4C 22.--31. 1. "RR,RR coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x4C 11.--20. 1. "RG,RG coefficient encoded signed value (from -512 to 511)" newline hexmask.long.word 0x4C 0.--9. 1. "RB,RB coefficient encoded signed value (from -512 to 511)" line.long 0x50 "DISPC_DATA2_CYCLE1,The control register configures the output data format for 1st cycle" bitfld.long 0x50 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x50 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x50 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x50 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x54 "DISPC_DATA2_CYCLE2,The control register configures the output data format for 2nd cycle" bitfld.long 0x54 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x54 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x54 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x54 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x58 "DISPC_DATA2_CYCLE3,The control register configures the output data format for 3rd cycle" bitfld.long 0x58 24.--27. "BITALIGNMENTPIXEL2,Bit alignment" "BITALIGNMENTPIXEL2_0,BITALIGNMENTPIXEL2_1,BITALIGNMENTPIXEL2_2,BITALIGNMENTPIXEL2_3,BITALIGNMENTPIXEL2_4,BITALIGNMENTPIXEL2_5,BITALIGNMENTPIXEL2_6,BITALIGNMENTPIXEL2_7,BITALIGNMENTPIXEL2_8,BITALIGNMENTPIXEL2_9,BITALIGNMENTPIXEL2_10,BITALIGNMENTPIXEL2_11,BITALIGNMENTPIXEL2_12,BITALIGNMENTPIXEL2_13,BITALIGNMENTPIXEL2_14,BITALIGNMENTPIXEL2_15" newline bitfld.long 0x58 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "NBBITSPIXEL2_0,NBBITSPIXEL2_1,NBBITSPIXEL2_2,NBBITSPIXEL2_3,NBBITSPIXEL2_4,NBBITSPIXEL2_5,NBBITSPIXEL2_6,NBBITSPIXEL2_7,NBBITSPIXEL2_8,NBBITSPIXEL2_9,NBBITSPIXEL2_10,NBBITSPIXEL2_11,NBBITSPIXEL2_12,NBBITSPIXEL2_13,NBBITSPIXEL2_14,NBBITSPIXEL2_15,NBBITSPIXEL2_16,NBBITSPIXEL2_17,NBBITSPIXEL2_18,NBBITSPIXEL2_19,NBBITSPIXEL2_20,NBBITSPIXEL2_21,NBBITSPIXEL2_22,NBBITSPIXEL2_23,NBBITSPIXEL2_24,NBBITSPIXEL2_25,NBBITSPIXEL2_26,NBBITSPIXEL2_27,NBBITSPIXEL2_28,NBBITSPIXEL2_29,NBBITSPIXEL2_30,NBBITSPIXEL2_31" newline bitfld.long 0x58 8.--11. "BITALIGNMENTPIXEL1,Bit alignment" "BITALIGNMENTPIXEL1_0,BITALIGNMENTPIXEL1_1,BITALIGNMENTPIXEL1_2,BITALIGNMENTPIXEL1_3,BITALIGNMENTPIXEL1_4,BITALIGNMENTPIXEL1_5,BITALIGNMENTPIXEL1_6,BITALIGNMENTPIXEL1_7,BITALIGNMENTPIXEL1_8,BITALIGNMENTPIXEL1_9,BITALIGNMENTPIXEL1_10,BITALIGNMENTPIXEL1_11,BITALIGNMENTPIXEL1_12,BITALIGNMENTPIXEL1_13,BITALIGNMENTPIXEL1_14,BITALIGNMENTPIXEL1_15" newline bitfld.long 0x58 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "NBBITSPIXEL1_0,NBBITSPIXEL1_1,NBBITSPIXEL1_2,NBBITSPIXEL1_3,NBBITSPIXEL1_4,NBBITSPIXEL1_5,NBBITSPIXEL1_6,NBBITSPIXEL1_7,NBBITSPIXEL1_8,NBBITSPIXEL1_9,NBBITSPIXEL1_10,NBBITSPIXEL1_11,NBBITSPIXEL1_12,NBBITSPIXEL1_13,NBBITSPIXEL1_14,NBBITSPIXEL1_15,NBBITSPIXEL1_16,NBBITSPIXEL1_17,NBBITSPIXEL1_18,NBBITSPIXEL1_19,NBBITSPIXEL1_20,NBBITSPIXEL1_21,NBBITSPIXEL1_22,NBBITSPIXEL1_23,NBBITSPIXEL1_24,NBBITSPIXEL1_25,NBBITSPIXEL1_26,NBBITSPIXEL1_27,NBBITSPIXEL1_28,NBBITSPIXEL1_29,NBBITSPIXEL1_30,NBBITSPIXEL1_31" line.long 0x5C "DISPC_SIZE_LCD2,The register configures the panel size (horizontal and vertical)" hexmask.long.word 0x5C 16.--27. 1. "LPP,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)" newline bitfld.long 0x5C 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field - Same" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" newline hexmask.long.word 0x5C 0.--11. 1. "PPL,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus 1)" group.long 0x400++0x0F line.long 0x00 "DISPC_TIMING_H2,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x00 20.--31. 1. "HBP,Horizontal back porch" newline hexmask.long.word 0x00 8.--19. 1. "HFP,Horizontal front porch" newline hexmask.long.byte 0x00 0.--7. 1. "HSW,Horizontal synchronization pulse width encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1)" line.long 0x04 "DISPC_TIMING_V2,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x04 20.--31. 1. "VBP,Vertical back porch encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display" newline hexmask.long.word 0x04 8.--19. 1. "VFP,Vertical front porch encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame" newline hexmask.long.byte 0x04 0.--7. 1. "VSW,Vertical synchronization pulse width In active mode encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP).." line.long 0x08 "DISPC_POL_FREQ2,The register configures the signal configuration" bitfld.long 0x08 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "ALIGN_0,ALIGN_1" newline bitfld.long 0x08 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off - DOpEdPCk" "ONOFF_0,ONOFF_1" newline bitfld.long 0x08 16. "RF,Program HSYNC/VSYNC Rise or Fall - DFEdPCk" "RF_0,RF_1" newline bitfld.long 0x08 15. "IEO,Invert output enable - ACBaHigh" "IEO_0,IEO_1" newline bitfld.long 0x08 14. "IPC,Invert pixel clock - DrPCk" "IPC_0,IPC_1" newline bitfld.long 0x08 13. "IHS,Invert HSYNC - LCkpinAh" "IHS_0,IHS_1" newline bitfld.long 0x08 12. "IVS,Invert VSYNC - FCkpinAh" "IVS_0,IVS_1" newline bitfld.long 0x08 8.--11. "ACBI,AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "ACBI_0,ACBI_1,ACBI_2,ACBI_3,ACBI_4,ACBI_5,ACBI_6,ACBI_7,ACBI_8,ACBI_9,ACBI_10,ACBI_11,ACBI_12,ACBI_13,ACBI_14,ACBI_15" newline hexmask.long.byte 0x08 0.--7. 1. "ACB,AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin" line.long 0x0C "DISPC_DIVISOR2,The register configures the divisors" hexmask.long.byte 0x0C 16.--23. 1. "LCD,Display controller logic clock divisor value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD2_CLK" newline hexmask.long.byte 0x0C 0.--7. 1. "PCD,Pixel clock divisor value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD2_CLK divided byDISPC_DIVISOR2.LCD value" group.long 0x570++0x2B line.long 0x00 "DISPC_WB_ATTRIBUTES,The register configures the attributes of the viwrite back pipeline" bitfld.long 0x00 28.--31. "IDLENUMBER,Determines the number of idles between requests on the L3_MAIN interconnect" "IDLENUMBER_0,IDLENUMBER_1,IDLENUMBER_2,IDLENUMBER_3,IDLENUMBER_4,IDLENUMBER_5,IDLENUMBER_6,IDLENUMBER_7,IDLENUMBER_8,IDLENUMBER_9,IDLENUMBER_10,IDLENUMBER_11,IDLENUMBER_12,IDLENUMBER_13,IDLENUMBER_14,IDLENUMBER_15" newline bitfld.long 0x00 27. "IDLESIZE,Determines if the IDLENUMBER corresponds to a number of bursts or singles" "IDLESIZE_0,IDLESIZE_1" newline bitfld.long 0x00 24.--26. "CAPTUREMODE,Defines the frame rate capture" "CAPTUREMODE_0,CAPTUREMODE_1,CAPTUREMODE_2,CAPTUREMODE_3,CAPTUREMODE_4,CAPTUREMODE_5,CAPTUREMODE_6,CAPTUREMODE_7" newline bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the write-back pipeline" "ARBITRATION_0,ARBITRATION_1" newline bitfld.long 0x00 22. "DOUBLESTRIDE,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride" "DOUBLESTRIDE_0,DOUBLESTRIDE_1" newline bitfld.long 0x00 21. "VERTICALTAPS,Video Vertical Resize Tap Number - taps3" "VERTICALTAPS_0,VERTICALTAPS_1" newline bitfld.long 0x00 20. "FORCE1DTILEDMODE,Force TILED regions access to 1D or 2D" "FORCE1DTILEDMODE_0,FORCE1DTILEDMODE_1" newline bitfld.long 0x00 19. "WRITEBACKMODE,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel" "0,1" newline bitfld.long 0x00 16.--18. "CHANNELIN,Video Channel In configuration WR: immediate - Vid3" "CHANNELIN_0,CHANNELIN_1,CHANNELIN_2,CHANNELIN_3,CHANNELIN_4,CHANNELIN_5,CHANNELIN_6,CHANNELIN_7" newline bitfld.long 0x00 14.--15. "BURSTSIZE,Write-back DMA Burst Size - Burst2x128b" "BURSTSIZE_0,BURSTSIZE_1,BURSTSIZE_2,BURSTSIZE_3" newline bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 10. "TRUNCATIONENABLE,It applies only when the input format to the write-back pipeline from the overlay or directly from one of the pipelines is ARGB32" "TRUNCATIONENABLE_0,TRUNCATIONENABLE_1" newline bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x00 8. "BURSTTYPE,The type of burst can be INCR (incremental) or BLCK (2D block)" "BURSTTYPE_0,BURSTTYPE_1" newline bitfld.long 0x00 7. "ALPHAENABLE,Premultiplied alpha enable" "0,1" newline bitfld.long 0x00 5.--6. "RESIZEENABLE,Resize Enable - ReSizeProc" "RESIZEENABLE_0,RESIZEENABLE_1,RESIZEENABLE_2,RESIZEENABLE_3" newline bitfld.long 0x00 1.--4. "FORMAT,Write-back format" "FORMAT_0,FORMAT_1,FORMAT_2,FORMAT_3,FORMAT_4,FORMAT_5,FORMAT_6,FORMAT_7,FORMAT_8,FORMAT_9,FORMAT_10,FORMAT_11,FORMAT_12,FORMAT_13,FORMAT_14,FORMAT_15" newline bitfld.long 0x00 0. "ENABLE,Write-back enable" "ENABLE_0,ENABLE_1" line.long 0x04 "DISPC_WB_CONV_COEF0,The register configures the color space conversion matrix coefficients for the write back pipeline (YUV4:4:4 to RGB24) Shadow register. updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the.." hexmask.long.word 0x04 16.--26. 1. "YG,YG coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x04 0.--10. 1. "YR,YR coefficient encoded signed value (from -1024 to 1023)" line.long 0x08 "DISPC_WB_CONV_COEF1,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.word 0x08 16.--26. 1. "CRR,CrR coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x08 0.--10. 1. "YB,YB coefficient encoded signed value (from -1024 to 1023)" line.long 0x0C "DISPC_WB_CONV_COEF2,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.word 0x0C 16.--26. 1. "CRB,CrB coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x0C 0.--10. 1. "CRG,CrG coefficient encoded signed value (from -1024 to 1023)" line.long 0x10 "DISPC_WB_CONV_COEF3,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.word 0x10 16.--26. 1. "CBG,CbG coefficient encoded signed value (from -1024 to 1023)" newline hexmask.long.word 0x10 0.--10. 1. "CBR,CbR coefficient encoded signed value (from -1024 to 1023)" line.long 0x14 "DISPC_WB_CONV_COEF4,The register configures the color space conversion matrix coefficients for the write back pipeline" hexmask.long.word 0x14 0.--10. 1. "CBB,CbB coefficient encoded signed value (from -1024 to 1023)" line.long 0x18 "DISPC_WB_BUF_SIZE_STATUS,The register defines the DMA buffer size for the write back pipeline" hexmask.long.word 0x18 0.--15. 1. "BUFSIZE,DMA buffer Size in number of 128 bits" line.long 0x1C "DISPC_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline" hexmask.long.word 0x1C 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer high threshold number of 128 bits defining the threshold value" newline hexmask.long.word 0x1C 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer low threshold number of 128 bits defining the threshold value" line.long 0x20 "DISPC_WB_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the write back pipeline" hexmask.long.word 0x20 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096)" newline hexmask.long.word 0x20 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096)" line.long 0x24 "DISPC_WB_PICTURE_SIZE,The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling" hexmask.long.word 0x24 16.--27. 1. "MEMSIZEY,Number of lines of the wb picture in memory" newline hexmask.long.word 0x24 0.--10. 1. "MEMSIZEX,Number of pixels of the wb picture in memory" line.long 0x28 "DISPC_WB_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the write back pipeline" hexmask.long.byte 0x28 0.--7. 1. "PIXELINC,Values other than 1 are invalid" group.long 0x5A4++0x07 line.long 0x00 "DISPC_WB_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the vwrite back pipeline" line.long 0x04 "DISPC_WB_SIZE,The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline" hexmask.long.word 0x04 16.--27. 1. "SIZEY,Number of lines of the Write-back picture Encoded value (from 1 to 4096) to specify the number of lines of the write-back picture from overlay or pipeline" newline hexmask.long.word 0x04 0.--10. 1. "SIZEX,Number of pixels of the Write-back picture Encoded value (from 1 to 2048) to specify the number of pixels of the write-back picture from overlay or pipeline" group.long 0x620++0x1F line.long 0x00 "DISPC_CONFIG2,The control register configures the Display Controller module for the secondary LCD output" bitfld.long 0x00 26.--27. "SLCDINTERLEAVE,sLCD Interleave Pattern" "0,1,2,3" newline bitfld.long 0x00 25. "FULLRANGE,Color space conversion full range setting" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x00 24. "COLORCONV ENABLE,Enable the color space conversion" "COLORCONV ENABLE_0,COLORCONV ENABLE_1" newline bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "FIDFIRST_0,FIDFIRST_1" newline bitfld.long 0x00 22. "OUTPUTMODE ENABLE,Selects between progressive and interlace mode for the secondary LCD output" "OUTPUTMODE ENABLE_0,OUTPUTMODE ENABLE_1" newline bitfld.long 0x00 21. "BT1120ENABLE,Selects BT.1120 format on the primary LCD output" "BT1120ENABLE_0,BT1120ENABLE_1" newline bitfld.long 0x00 20. "BT656ENABLE,Selects BT.656 format on the primary LCD output" "BT656ENABLE_0,BT656ENABLE_1" newline bitfld.long 0x00 15. "CPR,Color Phase Rotation Control secondary LCD output). It shall be reset when ColorConvEnable bit field is set to 1. wr: VFP start period of secondary LCD output - CPRDis. - CPREnb" "CPR_0,CPR_1" newline bitfld.long 0x00 11. "TCKLCD SELECTION,Transparency color key selection (secondary LCD output) wr: VFP start period of secondary LCD output - GDTK" "TCKLCD SELECTION_0,TCKLCD SELECTION_1" newline bitfld.long 0x00 10. "TCKLCDENABLE,Transparency color key enabled (secondary LCD output) wr: VFP start period of secondary LCD output - DisTCK" "TCKLCDENABLE_0,TCKLCDENABLE_1" newline bitfld.long 0x00 8. "ACBIASGATED,ACBias gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - ACBGDis" "ACBIASGATED_0,ACBIASGATED_1" newline bitfld.long 0x00 7. "VSYNCGATED,VSYNC gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - VGDis" "VSYNCGATED_0,VSYNCGATED_1" newline bitfld.long 0x00 6. "HSYNCGATED,HSYNC gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - HGDis" "HSYNCGATED_0,HSYNCGATED_1" newline bitfld.long 0x00 5. "PIXELCLOCK GATED,Pixel clock gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - PCGDis" "PIXELCLOCK GATED_0,PIXELCLOCK GATED_1" newline bitfld.long 0x00 4. "PIXELDATA GATED,Pixel data gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output - PDGDis" "PIXELDATA GATED_0,PIXELDATA GATED_1" newline bitfld.long 0x00 0. "PIXELGATED,Pixel gated enable (only for active matrix) (secondary LCD output) wr: VFP start period of secondary LCD output - PclkTogA" "PIXELGATED_0,PIXELGATED_1" line.long 0x04 "DISPC_VID1_ATTRIBUTES2,The register configures the attributes of the video window 1" bitfld.long 0x04 9.--11. "SUBSAMPLINGPATTERN,Subsampling pattern setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 8. "YUVCHROMARE SAMPLING,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0" "YUVCHROMARE SAMPLING_0,YUVCHROMARE SAMPLING_1" newline bitfld.long 0x04 4.--6. "VC1_RANGE_ CBCR,Defines the VC-1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 1.--3. "VC1_RANGE_Y,Defines the VC-1 range value for the Y component from 0 to 7" "VC1_RANGE_Y_0,VC1_RANGE_Y_1,VC1_RANGE_Y_2,VC1_RANGE_Y_3,VC1_RANGE_Y_4,VC1_RANGE_Y_5,VC1_RANGE_Y_6,VC1_RANGE_Y_7" newline bitfld.long 0x04 0. "VC1ENABLE,Enable/disable the VC-1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1" line.long 0x08 "DISPC_VID2_ATTRIBUTES2,The register configures the attributes of the video window 2" bitfld.long 0x08 9.--11. "SUBSAMPLINGPATTERN,Subsampling pattern setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 8. "YUVCHROMARE SAMPLING,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0" "YUVCHROMARE SAMPLING_0,YUVCHROMARE SAMPLING_1" newline bitfld.long 0x08 4.--6. "VC1_RANGE_ CBCR,Defines the VC-1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 1.--3. "VC1_RANGE_Y,Defines the VC-1 range value for the Y component from 0 to 7" "VC1_RANGE_Y_0,VC1_RANGE_Y_1,VC1_RANGE_Y_2,VC1_RANGE_Y_3,VC1_RANGE_Y_4,VC1_RANGE_Y_5,VC1_RANGE_Y_6,VC1_RANGE_Y_7" newline bitfld.long 0x08 0. "VC1ENABLE,Enable/disable the VC-1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1" line.long 0x0C "DISPC_VID3_ATTRIBUTES2,The register configures the attributes of the video window 3" bitfld.long 0x0C 9.--11. "SUBSAMPLINGPATTERN,Subsampling pattern setting" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 8. "YUVCHROMARE SAMPLING,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0" "YUVCHROMARE SAMPLING_0,YUVCHROMARE SAMPLING_1" newline bitfld.long 0x0C 4.--6. "VC1_RANGE_ CBCR,Defines the VC-1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 1.--3. "VC1_RANGE_Y,Defines the VC-1 range value for the Y component from 0 to 7" "VC1_RANGE_Y_0,VC1_RANGE_Y_1,VC1_RANGE_Y_2,VC1_RANGE_Y_3,VC1_RANGE_Y_4,VC1_RANGE_Y_5,VC1_RANGE_Y_6,VC1_RANGE_Y_7" newline bitfld.long 0x0C 0. "VC1ENABLE,Enable/disable the VC-1 range mapping processing" "VC1ENABLE_0,VC1ENABLE_1" line.long 0x10 "DISPC_GAMMA_TABLE0,The register configures the look up table used as color look up table for BITMAP formats (1-. 2-. 4. and 8-bpp) on the graphics pipeline or as gamma table on the primary LCD output" hexmask.long.byte 0x10 24.--31. 1. "INDEX,Defines the location in the table where the bit field VALUE is stored" newline hexmask.long.byte 0x10 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" newline hexmask.long.byte 0x10 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" newline hexmask.long.byte 0x10 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" line.long 0x14 "DISPC_GAMMA_TABLE1,The register configures the gamma table on the secondary LCD output" hexmask.long.byte 0x14 24.--31. 1. "INDEX,Defines the location in the table where the bit field VALUE is stored" newline hexmask.long.byte 0x14 16.--23. 1. "VALUE_R,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" newline hexmask.long.byte 0x14 8.--15. 1. "VALUE_G,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" newline hexmask.long.byte 0x14 0.--7. 1. "VALUE_B,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" line.long 0x18 "DISPC_GAMMA_TABLE2,The register configures the gamma table on the TV output" bitfld.long 0x18 31. "INDEX,Setting this bit to 1 resets the internal index counter to zero" "INDEX_0,INDEX_1" newline hexmask.long.word 0x18 20.--29. 1. "VALUE_R,10-bit color component value to store in the table" newline hexmask.long.word 0x18 10.--19. 1. "VALUE_G,10-bit color component value to store in the table" newline hexmask.long.word 0x18 0.--9. 1. "VALUE_B,10-bit color component value to store in the table" line.long 0x1C "DISPC_VID1_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1" hexmask.long.word 0x1C 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter for Cb and Cr" newline hexmask.long.word 0x1C 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter for Cb and Cr" group.long 0x6A8++0x03 line.long 0x00 "DISPC_VID2_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter for Cb and Cr" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter for Cb and Cr" group.long 0x724++0x03 line.long 0x00 "DISPC_VID3_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter for Cb and Cr" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter for Cb and Cr" group.long 0x790++0x03 line.long 0x00 "DISPC_WB_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the write-back pipeline" hexmask.long.word 0x00 16.--28. 1. "FIRVINC,Vertical increment of the up/downsampling filter for Cb and Cr" newline hexmask.long.word 0x00 0.--12. 1. "FIRHINC,Horizontal increment of the up/downsampling filter for Cb and Cr" group.long 0x800++0x07 line.long 0x00 "DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipeline (graphics. video1. video2. video3 and write-back)" bitfld.long 0x00 24.--29. "WB_BUFFER,Write-back DMA buffer allocation to one of the pipelines" "WB_BUFFER_0,?,?,?,?,?,?,?,?,WB_BUFFER_9,?,?,?,?,?,?,?,?,WB_BUFFER_18,?,?,?,?,?,?,?,?,WB_BUFFER_27,?,?,?,?,?,?,?,?,WB_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 18.--23. "VID3_BUFFER,Video3 DMA buffer allocation to one of the pipelines" "VID3_BUFFER_0,?,?,?,?,?,?,?,?,VID3_BUFFER_9,?,?,?,?,?,?,?,?,VID3_BUFFER_18,?,?,?,?,?,?,?,?,VID3_BUFFER_27,?,?,?,?,?,?,?,?,VID3_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 12.--17. "VID2_BUFFER,Video2 DMA buffer allocation to one of the pipelines" "VID2_BUFFER_0,?,?,?,?,?,?,?,?,VID2_BUFFER_9,?,?,?,?,?,?,?,?,VID2_BUFFER_18,?,?,?,?,?,?,?,?,VID2_BUFFER_27,?,?,?,?,?,?,?,?,VID2_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 6.--11. "VID1_BUFFER,Video1 DMA buffer allocation to one of the pipelines" "VID1_BUFFER_0,?,?,?,?,?,?,?,?,VID1_BUFFER_9,?,?,?,?,?,?,?,?,VID1_BUFFER_18,?,?,?,?,?,?,?,?,VID1_BUFFER_27,?,?,?,?,?,?,?,?,VID1_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 0.--5. "GFX_BUFFER,Graphics DMA buffer allocation to one of the pipelines" "GFX_BUFFER_0,?,?,?,?,?,?,?,?,GFX_BUFFER_9,?,?,?,?,?,?,?,?,GFX_BUFFER_18,?,?,?,?,?,?,?,?,GFX_BUFFER_27,?,?,?,?,?,?,?,?,GFX_BUFFER_36,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DISPC_DIVISOR,The register configures the divisor value for generating the core functional clock" hexmask.long.byte 0x04 16.--23. 1. "LCD,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the frequency of the Display Controller logic clock based on the function clock" newline bitfld.long 0x04 0. "ENABLE,When the bit field is set to 1 the bit field LCD is used to generated the core functional clock from the input clock" "ENABLE_0,ENABLE_1" group.long 0x810++0x47 line.long 0x00 "DISPC_WB_ATTRIBUTES2,The register set the counter to control the delay to flush the WB pipe after the end of the frame in capture mode" hexmask.long.byte 0x00 0.--7. 1. "WBDELAYCOUNT,Delays the WB pipe flush after the end of the frame.delay = n x (1/F_clk) n = 0:255" line.long 0x04 "DISPC_DEFAULT_COLOR3,The control register allows to configure the default solid background color for the third LCD" hexmask.long.tbyte 0x04 0.--23. 1. "DEFAULTCOLOR,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" line.long 0x08 "DISPC_TRANS_COLOR3,The register sets the transparency color value for the video/graphics overlays for the third LCD output" hexmask.long.tbyte 0x08 0.--23. 1. "TRANSCOLORKEY,Transparency color key value in RGB format [0] BITMAP 1 (CLUT) [23 1] set to 0s [1:0] BITMAP 2 (CLUT) [23 2] set to 0s [3:0] BITMAP 4 (CLUT) [23 4] set to 0s [7:0] BITMAP 8 (CLUT) [23 8] set to 0s [11:0] RGB 12 [23 12] set to 0s [15:0] RGB.." line.long 0x0C "DISPC_CPR3_COEF_B,The register configures the color phase rotation matrix coefficients for the blue component" hexmask.long.word 0x0C 22.--31. 1. "BR,BR coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x0C 11.--20. 1. "BG,BG coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x0C 0.--9. 1. "BB,BB coefficient Encoded signed value (from -512 to 511)" line.long 0x10 "DISPC_CPR3_COEF_G,The register configures the color phase rotation matrix coefficients for the green component" hexmask.long.word 0x10 22.--31. 1. "GR,GRcoefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x10 11.--20. 1. "GG,GG coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x10 0.--9. 1. "GB,GB coefficient Encoded signed value (from -512 to 511)" line.long 0x14 "DISPC_CPR3_COEF_R,The register configures the color phase rotation matrix coefficients for the red component" hexmask.long.word 0x14 22.--31. 1. "RR,RR coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x14 11.--20. 1. "RG,RG coefficient Encoded signed value (from -512 to 511)" newline hexmask.long.word 0x14 0.--9. 1. "RB,RB coefficient Encoded signed value (from -512 to 511)" line.long 0x18 "DISPC_DATA3_CYCLE1,The control register configures the output data format for the first cycle" bitfld.long 0x18 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1C "DISPC_DATA3_CYCLE2,The control register configures the output data format for the second cycle" bitfld.long 0x1C 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "DISPC_DATA3_CYCLE3,The control register configures the output data format for the third cycle" bitfld.long 0x20 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x20 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x20 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x24 "DISPC_SIZE_LCD3,The register configures the panel size (horizontal and vertical)" hexmask.long.word 0x24 16.--27. 1. "LPP,Lines per panel Encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)" newline bitfld.long 0x24 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field - Same" "DELTA_LPP_0,DELTA_LPP_1,DELTA_LPP_2,?" newline hexmask.long.word 0x24 0.--11. 1. "PPL,Pixels per line Encoded value (from 1 to 4096) to specify the number of pixels contained within each line on the display (program to value minus 1)" line.long 0x28 "DISPC_DIVISOR3,The register configures the divisors" hexmask.long.byte 0x28 16.--23. 1. "LCD,Display controller logic clock divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on LCD2_CLK" newline hexmask.long.byte 0x28 0.--7. 1. "PCD,Pixel clock divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on LCD2_CLK divided by the value of DISPC_DIVISOR2.LCD" line.long 0x2C "DISPC_POL_FREQ3,The register configures the signal configuration" bitfld.long 0x2C 18. "ALIGN,Defines the alignment betwwen HSYNC and VSYNC assertion - notAligned" "ALIGN_0,ALIGN_1" newline bitfld.long 0x2C 17. "ONOFF,HSYNC/VSYNC pixel clock control on/off - DOpEdPCk" "ONOFF_0,ONOFF_1" newline bitfld.long 0x2C 16. "RF,Program HSYNC/VSYNC rise or fall - DFEdPCk" "RF_0,RF_1" newline bitfld.long 0x2C 15. "IEO,Invert output enable - ACBaHigh" "IEO_0,IEO_1" newline bitfld.long 0x2C 14. "IPC,Invert pixel clock - DrPCk" "IPC_0,IPC_1" newline bitfld.long 0x2C 13. "IHS,Invert HSYNC - LCkpinAh" "IHS_0,IHS_1" newline bitfld.long 0x2C 12. "IVS,Invert VSYNC - FCkpinAh" "IVS_0,IVS_1" newline bitfld.long 0x2C 8.--11. "ACBI,AC bias pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x2C 0.--7. 1. "ACB,AC bias pin frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC bias pin" line.long 0x30 "DISPC_TIMING_H3,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x30 20.--31. 1. "HBP,Horizontal back porch Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1)" newline hexmask.long.word 0x30 8.--19. 1. "HFP,Horizontal front porch Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmissionbefore the line clock is asserted" newline hexmask.long.byte 0x30 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1)" line.long 0x34 "DISPC_TIMING_V3,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x34 20.--31. 1. "VBP,Vertical back porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display" newline hexmask.long.word 0x34 8.--19. 1. "VFP,Vertical front porch Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame" newline hexmask.long.byte 0x34 0.--7. 1. "VSW,Vertical synchronization pulse width In active mode encoded value (from 1 to 256) to specify the number of line clock periods to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses" line.long 0x38 "DISPC_CONTROL3,The control register configures the display controller module for the third LCD output" bitfld.long 0x38 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/temporal dithering number of frames for the third LCD output wr: VFP start period of the third LCD output - OneFrame" "SPATIALTEMPORALDITHERINGFRAMES_0,SPATIALTEMPORALDITHERINGFRAMES_1,SPATIALTEMPORALDITHERINGFRAMES_2,SPATIALTEMPORALDITHERINGFRAMES_3" newline bitfld.long 0x38 25.--26. "TDMUNUSEDBITS,State of unused bits (TDM mode only) for the third LCD output wr: VFP start period of the third LCD output - LowLevel" "TDMUNUSEDBITS_0,TDMUNUSEDBITS_1,TDMUNUSEDBITS_2,TDMUNUSEDBITS_3" newline bitfld.long 0x38 23.--24. "TDMCYCLEFORMAT,Cycle format (TDM mode only) for the third LCD output wr: VFP start period of third LCD output - 1CycPerPix" "TDMCYCLEFORMAT_0,TDMCYCLEFORMAT_1,TDMCYCLEFORMAT_2,TDMCYCLEFORMAT_3" newline bitfld.long 0x38 21.--22. "TDMPARALLELMODE,Output interface width (TDM mode only) for the third LCD output wr: VFP start period of the third LCD output - 8bParaInt" "TDMPARALLELMODE_0,TDMPARALLELMODE_1,TDMPARALLELMODE_2,TDMPARALLELMODE_3" newline bitfld.long 0x38 20. "TDMENABLE,Enable the multiple cycle format for the third LCD output wr: VFP start period of third LCD output - TDMDis" "TDMENABLE_0,TDMENABLE_1" newline bitfld.long 0x38 12. "OVERLAYOPTIMIZATION,Overlay optimization for the third LCD output wr: VFP or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline)" "OVERLAYOPTIMIZATION_0,OVERLAYOPTIMIZATION_1" newline bitfld.long 0x38 11. "STALLMODE,STALL mode for the third LCD output wr: VFP start period of the third LCD output - nMode" "STALLMODE_0,STALLMODE_1" newline bitfld.long 0x38 8.--9. "TFTDATALINES,Number of lines of the third LCD interface wr: VFP start period of the third LCD output - OaLSB12b" "TFTDATALINES_0,TFTDATALINES_1,TFTDATALINES_2,TFTDATALINES_3" newline bitfld.long 0x38 7. "STDITHERENABLE,Spatial temporal dithering enable for the third LCD output wr: VFP start period of the third LCD output - STDithDis" "STDITHERENABLE_0,STDITHERENABLE_1" newline bitfld.long 0x38 5. "GOLCD,GO command for the third LCD output" "GOLCD_0,GOLCD_1" newline bitfld.long 0x38 4. "M8B,Mono 8-bit mode of the third LCD wr: VFP start period of the third LCD output - 4PixtoPanel" "M8B_0,M8B_1" newline bitfld.long 0x38 3. "STNTFT,LCD Display type of the third LCD wr: VFP start period of the third LCD output - STNdispEnb" "STNTFT_0,STNTFT_1" newline bitfld.long 0x38 2. "MONOCOLOR,Monochrome/color selection for the third LCD wr: VFP start period of the third LCD output - ColOpEnb" "MONOCOLOR_0,MONOCOLOR_1" newline bitfld.long 0x38 0. "LCDENABLE,Enable the third LCD output wr: Immediate - LCDOpDis" "LCDENABLE_0,LCDENABLE_1" line.long 0x3C "DISPC_CONFIG3,The control register configures the display controller module for the third LCD output" bitfld.long 0x3C 26.--27. "TLCDINTERLEAVE,tLCD interleave Pattern" "0,1,2,3" newline bitfld.long 0x3C 25. "FULLRANGE,Color space conversion full range setting - Limrange" "FULLRANGE_0,FULLRANGE_1" newline bitfld.long 0x3C 24. "COLORCONVENABLE,Enable the color space conversion" "COLORCONVENABLE_0,COLORCONVENABLE_1" newline bitfld.long 0x3C 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "FIDFIRST_0,FIDFIRST_1" newline bitfld.long 0x3C 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the third LCD output - Disable" "OUTPUTMODEENABLE_0,OUTPUTMODEENABLE_1" newline bitfld.long 0x3C 21. "BT1120ENABLE,Selects BT.1120 format on the third LCD output" "BT1120ENABLE_0,BT1120ENABLE_1" newline bitfld.long 0x3C 20. "BT656ENABLE,Selects BT.656 format on the third LCD output" "BT656ENABLE_0,BT656ENABLE_1" newline bitfld.long 0x3C 15. "CPR,Color phase rotation control ( third LCD output)" "CPR_0,CPR_1" newline bitfld.long 0x3C 11. "TCKLCDSELECTION,Transparency color key selection (third LCD output) wr: VFP start period of the third LCD output - GDTK" "TCKLCDSELECTION_0,TCKLCDSELECTION_1" newline bitfld.long 0x3C 10. "TCKLCDENABLE,Transparency color key enabled (third LCD output) wr: VFP start period of the third LCD output - DisTCK" "TCKLCDENABLE_0,TCKLCDENABLE_1" newline bitfld.long 0x3C 8. "ACBIASGATED,ACBias gated enabled (third LCD output) wr: VFP start period of the third LCD output - ACBGDis" "ACBIASGATED_0,ACBIASGATED_1" newline bitfld.long 0x3C 7. "VSYNCGATED,VSYNC gated enabled (third LCD output) wr: VFP start period of the third LCD output - VGDis" "VSYNCGATED_0,VSYNCGATED_1" newline bitfld.long 0x3C 6. "HSYNCGATED,HSYNC gated enabled (third LCD output) wr: VFP start period of the third LCD output - HGDis" "HSYNCGATED_0,HSYNCGATED_1" newline bitfld.long 0x3C 5. "PIXELCLOCKGATED,Pixel clock gated enabled (third LCD output) wr: VFP start period of the third LCD output - PCGDis" "PIXELCLOCKGATED_0,PIXELCLOCKGATED_1" newline bitfld.long 0x3C 4. "PIXELDATAGATED,Pixel data gated enabled (third LCD output) wr: VFP start period of the third LCD output - PDGDis" "PIXELDATAGATED_0,PIXELDATAGATED_1" newline bitfld.long 0x3C 0. "PIXELGATED,Pixel gated enable (only for TFT) (third LCD output) wr: VFP start period of the third LCD output - PclkTogA" "PIXELGATED_0,PIXELGATED_1" line.long 0x40 "DISPC_GAMMA_TABLE3,The register configures the gamma table on the third LCD output" hexmask.long.byte 0x40 24.--31. 1. "INDEX,Defines the location in the table where the VALUE bit field is stored" newline hexmask.long.byte 0x40 16.--23. 1. "VALUE_R,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" newline hexmask.long.byte 0x40 8.--15. 1. "VALUE_G,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" newline hexmask.long.byte 0x40 0.--7. 1. "VALUE_B,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" line.long 0x44 "DISPC_BA0_FLIPIMMEDIATE_EN,Thsi regster enables the flip immediate" bitfld.long 0x44 3. "VID3,Enable flip immediate for video3 pipeline" "0,1" newline bitfld.long 0x44 2. "VID2,Enable flip immediate for video2 pipeline" "0,1" newline bitfld.long 0x44 1. "VID1,Enable flip immediate for video1 pipeline" "0,1" newline bitfld.long 0x44 0. "GFX,Enable flip immediate for gfx pipeline" "0,1" group.long 0x85C++0x17 line.long 0x00 "DISPC_GLOBAL_MFLAG_ATTRIBUTE,Global MFLAG atrribute control register" bitfld.long 0x00 2. "MFLAG_START,MFLAG Start - Inactive" "MFLAG_START_0,MFLAG_START_1" newline bitfld.long 0x00 0.--1. "MFLAG_CTRL,MFLAG control - MFLAG_Dis" "MFLAG_CTRL_0,MFLAG_CTRL_1,MFLAG_CTRL_2,?" line.long 0x04 "DISPC_GFX_MFLAG_THRESHOLD,MFLAG thresholds for graphics pipeline" hexmask.long.word 0x04 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x04 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" line.long 0x08 "DISPC_VID1_MFLAG_THRESHOLD,MFLAG thresholds for video1 pipeline" hexmask.long.word 0x08 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x08 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" line.long 0x0C "DISPC_VID2_MFLAG_THRESHOLD,MFLAG thresholds for video2 pipeline" hexmask.long.word 0x0C 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x0C 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" line.long 0x10 "DISPC_VID3_MFLAG_THRESHOLD,MFLAG thresholds for video3 pipeline" hexmask.long.word 0x10 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x10 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" line.long 0x14 "DISPC_WB_MFLAG_THRESHOLD,MFLAG thresholds for write-back pipeline" hexmask.long.word 0x14 16.--31. 1. "HT_MFLAG,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level MFLAG is reset to 0" newline hexmask.long.word 0x14 0.--15. 1. "LT_MFLAG,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level MFLAG is set to 1" repeat 6. (list 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" group.long 0x658++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x104++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x100++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x690++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E8++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6C4++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x194++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x190++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6FC++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x208++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x740++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x324++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x320++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x778++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x358++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x7B0++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x524++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x520++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E8++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x558++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end repeat.end repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x80++0x03 line.long 0x00 "DISPC_GFX_BA_j_0,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger. based on the field polarity. 0 only used when graphics pipeline on the LCD output.." group.long 0x640++0x03 line.long 0x00 "DISPC_VID1_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0xE8++0x03 line.long 0x00 "DISPC_VID1_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x600++0x03 line.long 0x00 "DISPC_VID1_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 1" group.long 0xBC++0x03 line.long 0x00 "DISPC_VID1_BA_j_0,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID1_BA_0 is used)" group.long 0x648++0x07 line.long 0x00 "DISPC_VID1_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID1_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF4++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0xF0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x688++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x1E0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x6AC++0x03 line.long 0x00 "DISPC_VID2_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x178++0x03 line.long 0x00 "DISPC_VID2_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x608++0x03 line.long 0x00 "DISPC_VID2_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 2" group.long 0x14C++0x03 line.long 0x00 "DISPC_VID2_BA_j_0,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID2_BA_0 is.." group.long 0x6B4++0x07 line.long 0x00 "DISPC_VID2_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID2_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x184++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x180++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x6F4++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x200++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x728++0x03 line.long 0x00 "DISPC_VID3_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger. based on the.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x300++0x03 line.long 0x00 "DISPC_VID3_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x610++0x03 line.long 0x00 "DISPC_VID3_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 3" group.long 0x308++0x03 line.long 0x00 "DISPC_VID3_BA_j_0,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_VID3_BA_0 is.." group.long 0x730++0x07 line.long 0x00 "DISPC_VID3_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_VID3_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x314++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x310++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x770++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x350++0x03 line.long 0x00 "DISPC_VID3_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x794++0x03 line.long 0x00 "DISPC_WB_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accu value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accu value Encoded value (from -1024 to 1023)" group.long 0x500++0x03 line.long 0x00 "DISPC_WB_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger. based on the field.." hexmask.long.word 0x00 16.--26. 1. "VERTICALACCU,Vertical initialization accumulator value Encoded value (from -1024 to 1023)" hexmask.long.word 0x00 0.--10. 1. "HORIZONTALACCU,Horizontal initialization accumulator value encoded value (from -1024 to 1023)" group.long 0x618++0x03 line.long 0x00 "DISPC_WB_BA_UV_j_0,The register configures the base address of the UV buffer for the write-back pipeline" group.long 0x508++0x03 line.long 0x00 "DISPC_WB_BA_j_0,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger. based on the field polarity otherwise only DISPC_WB_BA_0 is used)" group.long 0x7A0++0x07 line.long 0x00 "DISPC_WB_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" line.long 0x04 "DISPC_WB_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x04 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x04 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x514++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRVC1,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRVC0,Signed coefficient C0 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC4,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" group.long 0x510++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 24.--31. 1. "FIRHC3,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 16.--23. 1. "FIRHC2,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 8.--15. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRHC0,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" group.long 0x7E0++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" group.long 0x550++0x03 line.long 0x00 "DISPC_WB_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7" hexmask.long.byte 0x00 8.--15. 1. "FIRVC22,Signed coefficient C22 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x00 0.--7. 1. "FIRVC00,Signed coefficient C00 for the vertical up/down-scaling with the phase n" tree.end repeat.end tree.end tree.end tree.open "Display_Subsystem_Overview" tree "DPLL_HDMI_L3_MAIN" base ad:0x58040000 group.long 0x200++0x23 line.long 0x00 "PLLCTRL_HDMI_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESETN,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESETN_0,HSDIV_SYSRESETN_1" bitfld.long 0x00 3. "PLL_SYSRESETN,Force SYSRESETN" "PLL_SYSRESETN_0,PLL_SYSRESETN_1" line.long 0x04 "PLLCTRL_HDMI_STATUS,This register contains the status information" bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_INACT" "SSC_EN_ACK_0,SSC_EN_ACK_1" bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on HDMI_PHY - BYPASS_ACK" "BYPASSACKZ_MERGED_0,BYPASSACKZ_MERGED_1" bitfld.long 0x04 6. "PLL_BYPASS,DPLL_HDMI Bypass status - BYPASS_IN" "PLL_BYPASS_0,PLL_BYPASS_1" newline bitfld.long 0x04 5. "PLL_HIGHJITTER,DPLL_HDMI High Jitter status - NORMAL_JITTER" "PLL_HIGHJITTER_0,PLL_HIGHJITTER_1" bitfld.long 0x04 3. "PLL_LOSSREF,DPLL_HDMI Reference Loss status - REF_INP_ACT" "PLL_LOSSREF_0,PLL_LOSSREF_1" bitfld.long 0x04 2. "PLL_RECAL,DPLL_HDMI re-calibration status If this bit is active the DPLL_HDMI needs to be re-calibrated - RECAL_NOT_REQUIRED" "PLL_RECAL_0,PLL_RECAL_1" newline bitfld.long 0x04 1. "PLL_LOCK,DPLL_HDMI Lock status See the programming guide for the use of this bit - DSI_PLL_NOLOCK" "PLL_LOCK_0,PLL_LOCK_1" bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,DPLL_HDMI reset done status - NOTRD" "PLLCTRL_RESET_DONE_0,PLLCTRL_RESET_DONE_1" line.long 0x08 "PLLCTRL_HDMI_GO,This register contains the GO bit" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the DPLL_HDMI" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLLCTRL_HDMI_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for DPLL_HDMI" hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for DPLL_HDMI (Reference)" line.long 0x10 "PLLCTRL_HDMI_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_NORMAL" "HSDIVBYPASS_0,HSDIVBYPASS_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - CLK_PLL" "BYPASSEN_0,BYPASSEN_1" newline bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_CLK_DIS" "PHY_CLKINEN_0,PHY_CLKINEN_1" bitfld.long 0x10 13. "PLL_REFEN,DPLL_HDMI reference clock control - REF_DIS" "PLL_REFEN_0,PLL_REFEN_1" bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the DPLL_HDMI Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" newline bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_REF" "PLL_CLKSEL_0,PLL_CLKSEL_1" bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the DPLL_HDMI - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,DPLL_HDMI DRIFTGUARDEN - DRIFT_GUARD_DIS" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" newline bitfld.long 0x10 6. "PLL_LOWCURRSTBY,DPLL_HDMI LOW CURRENT STANDBY - LOWCURRSTBY_NOTSEL" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the DPLL_HDMI - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" bitfld.long 0x10 1.--3. "PLL_SELFREQDCO,DCO frequency range selector for DPLL_HDMI" "?,?,PLL_SELFREQDCO_2,?,PLL_SELFREQDCO_4,?,?,?" newline bitfld.long 0x10 0. "PLL_IDLE,DPLL_HDMI IDLE: - IDLE_NOTSEL" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLLCTRL_HDMI_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.byte 0x14 10.--17. 1. "PLL_SD,Sigma delta divider setting for DPLL_HDMI based on the DPLL_HDMI lock configuration" line.long 0x18 "PLLCTRL_HDMI_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable - SSC_OFF" "EN_SSC_0,EN_SSC_1" line.long 0x1C "PLLCTRL_HDMI_SSC_CONFIGURATION2," bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for dithering.The ModFreqDivider is split into Mantissa and 2(ModFreqDivider = ModFreqDividerMantissa * 2).Bits [29:23] define the Mantissa" hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for dithering" line.long 0x20 "PLLCTRL_HDMI_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.byte 0x20 18.--24. 1. "PLL_REGM2,M2 divider to configure DPLL_HDMI M2 divider factor" hexmask.long.tbyte 0x20 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" tree.end tree "DPLL_HDMI_L4_CFG" base ad:0x4A0A6000 group.long 0x00++0x23 line.long 0x00 "PLLCTRL_HDMI_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESETN,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESETN_0,HSDIV_SYSRESETN_1" bitfld.long 0x00 3. "PLL_SYSRESETN,Force SYSRESETN" "PLL_SYSRESETN_0,PLL_SYSRESETN_1" line.long 0x04 "PLLCTRL_HDMI_STATUS,This register contains the status information" bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_INACT" "SSC_EN_ACK_0,SSC_EN_ACK_1" bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on HDMI_PHY - BYPASS_ACK" "BYPASSACKZ_MERGED_0,BYPASSACKZ_MERGED_1" bitfld.long 0x04 6. "PLL_BYPASS,DPLL_HDMI Bypass status - BYPASS_IN" "PLL_BYPASS_0,PLL_BYPASS_1" newline bitfld.long 0x04 5. "PLL_HIGHJITTER,DPLL_HDMI High Jitter status - NORMAL_JITTER" "PLL_HIGHJITTER_0,PLL_HIGHJITTER_1" bitfld.long 0x04 3. "PLL_LOSSREF,DPLL_HDMI Reference Loss status - REF_INP_ACT" "PLL_LOSSREF_0,PLL_LOSSREF_1" bitfld.long 0x04 2. "PLL_RECAL,DPLL_HDMI re-calibration status If this bit is active the DPLL_HDMI needs to be re-calibrated - RECAL_NOT_REQUIRED" "PLL_RECAL_0,PLL_RECAL_1" newline bitfld.long 0x04 1. "PLL_LOCK,DPLL_HDMI Lock status See the programming guide for the use of this bit - DSI_PLL_NOLOCK" "PLL_LOCK_0,PLL_LOCK_1" bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,DPLL_HDMI reset done status - NOTRD" "PLLCTRL_RESET_DONE_0,PLLCTRL_RESET_DONE_1" line.long 0x08 "PLLCTRL_HDMI_GO,This register contains the GO bit" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the DPLL_HDMI" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLLCTRL_HDMI_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for DPLL_HDMI" hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for DPLL_HDMI (Reference)" line.long 0x10 "PLLCTRL_HDMI_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_NORMAL" "HSDIVBYPASS_0,HSDIVBYPASS_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - CLK_PLL" "BYPASSEN_0,BYPASSEN_1" newline bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_CLK_DIS" "PHY_CLKINEN_0,PHY_CLKINEN_1" bitfld.long 0x10 13. "PLL_REFEN,DPLL_HDMI reference clock control - REF_DIS" "PLL_REFEN_0,PLL_REFEN_1" bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the DPLL_HDMI Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" newline bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_REF" "PLL_CLKSEL_0,PLL_CLKSEL_1" bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the DPLL_HDMI - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,DPLL_HDMI DRIFTGUARDEN - DRIFT_GUARD_DIS" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" newline bitfld.long 0x10 6. "PLL_LOWCURRSTBY,DPLL_HDMI LOW CURRENT STANDBY - LOWCURRSTBY_NOTSEL" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the DPLL_HDMI - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" bitfld.long 0x10 1.--3. "PLL_SELFREQDCO,DCO frequency range selector for DPLL_HDMI" "?,?,PLL_SELFREQDCO_2,?,PLL_SELFREQDCO_4,?,?,?" newline bitfld.long 0x10 0. "PLL_IDLE,DPLL_HDMI IDLE: - IDLE_NOTSEL" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLLCTRL_HDMI_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.byte 0x14 10.--17. 1. "PLL_SD,Sigma delta divider setting for DPLL_HDMI based on the DPLL_HDMI lock configuration" line.long 0x18 "PLLCTRL_HDMI_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable - SSC_OFF" "EN_SSC_0,EN_SSC_1" line.long 0x1C "PLLCTRL_HDMI_SSC_CONFIGURATION2," bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for dithering.The ModFreqDivider is split into Mantissa and 2(ModFreqDivider = ModFreqDividerMantissa * 2).Bits [29:23] define the Mantissa" hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for dithering" line.long 0x20 "PLLCTRL_HDMI_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.byte 0x20 18.--24. 1. "PLL_REGM2,M2 divider to configure DPLL_HDMI M2 divider factor" hexmask.long.tbyte 0x20 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" tree.end tree "DPLL_VIDEO1_L3_MAIN" base ad:0x58004300 group.long 0x00++0x1F line.long 0x00 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESET,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESET_0,HSDIV_SYSRESET_1" bitfld.long 0x00 3. "PLL_SYSRESET,Force DPLL SYSRESETN" "PLL_SYSRESET_0,PLL_SYSRESET_1" bitfld.long 0x00 2. "PLL_HALTMODE,Allow PLL to be halted if no activity" "PLL_HALTMODE_0,PLL_HALTMODE_1" newline bitfld.long 0x00 1. "PLL_GATEMODE,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0" "PLL_GATEMODE_0,PLL_GATEMODE_1" bitfld.long 0x00 0. "PLL_AUTOMODE,Automatic update mode" "PLL_AUTOMODE_0,PLL_AUTOMODE_1" line.long 0x04 "PLL_STATUS,This register contains the status information" bitfld.long 0x04 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x04 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" bitfld.long 0x04 13.--14. "BYPASSACKZ,State of bypass mode on PHY and HSDIVIDER" "BYPASSACKZ_0_r,BYPASSACKZ_1_r,?,?" newline bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" bitfld.long 0x04 10. "M6_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M6_Clk_Act" "M6_CLOCK_ACK_0_r,M6_CLOCK_ACK_1_r" bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on PHY and HSDIVIDER - Bypass_Nak" "BYPASSACKZ_MERGED_0_r,BYPASSACKZ_MERGED_1_r" newline bitfld.long 0x04 7. "M4_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M4_Clk_Act" "M4_CLOCK_ACK_0_r,M4_CLOCK_ACK_1_r" bitfld.long 0x04 6. "PLL_BYPASS,PLL Bypass status - Bypass_Act" "PLL_BYPASS_0_r,PLL_BYPASS_1_r" bitfld.long 0x04 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" newline bitfld.long 0x04 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x04 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" bitfld.long 0x04 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" newline bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x08 "PLL_GO,This register contains the GO bit" bitfld.long 0x08 1. "HSDIVLOAD,In manual mode start HSDIVIDER update sequence" "0,1" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0C 21.--25. "M4_CLOCK_DIV,Divider value for clock source M4REG" "M4_CLOCK_DIV_0,M4_CLOCK_DIV_1,M4_CLOCK_DIV_2,M4_CLOCK_DIV_3,M4_CLOCK_DIV_4,M4_CLOCK_DIV_5,M4_CLOCK_DIV_6,M4_CLOCK_DIV_7,M4_CLOCK_DIV_8,M4_CLOCK_DIV_9,M4_CLOCK_DIV_10,M4_CLOCK_DIV_11,M4_CLOCK_DIV_12,M4_CLOCK_DIV_13,M4_CLOCK_DIV_14,M4_CLOCK_DIV_15,M4_CLOCK_DIV_16,M4_CLOCK_DIV_17,M4_CLOCK_DIV_18,M4_CLOCK_DIV_19,M4_CLOCK_DIV_20,M4_CLOCK_DIV_21,M4_CLOCK_DIV_22,M4_CLOCK_DIV_23,M4_CLOCK_DIV_24,M4_CLOCK_DIV_25,M4_CLOCK_DIV_26,M4_CLOCK_DIV_27,M4_CLOCK_DIV_28,M4_CLOCK_DIV_29,M4_CLOCK_DIV_30,M4_CLOCK_DIV_31" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for PLL" hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x10 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 23. "M6_CLOCK_EN,Enable for M6 clock source - M6_Clk_Dis" "M6_CLOCK_EN_0,M6_CLOCK_EN_1" bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_Normal" "HSDIVBYPASS_0,HSDIVBYPASS_1" newline bitfld.long 0x10 16. "M4_CLOCK_EN,Enable for M4 clock source - SS_Clk_Dis" "M4_CLOCK_EN_0,M4_CLOCK_EN_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - Clk_PLL" "BYPASSEN_0,BYPASSEN_1" bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_Clk_Dis" "PHY_CLKINEN_0,PHY_CLKINEN_1" newline bitfld.long 0x10 13. "PLL_REFEN,PLL reference clock control - Ref_dis" "PLL_REFEN_0,PLL_REFEN_1" bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_Ref" "PLL_CLKSEL_0,PLL_CLKSEL_1" newline bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,PLL DRIFTGUARDEN - Drift_Guard_Dis" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" bitfld.long 0x10 6. "PLL_LOWCURRSTBY,PLL LOW CURRENT STANDBY - LOWCURRSTBY_notsel" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" newline bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the PLL - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" bitfld.long 0x10 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x14 0.--4. "M6_CLOCK_DIV,Divider value for M6 divider" "M6_CLOCK_DIV_0,M6_CLOCK_DIV_1,M6_CLOCK_DIV_2,M6_CLOCK_DIV_3,M6_CLOCK_DIV_4,M6_CLOCK_DIV_5,M6_CLOCK_DIV_6,M6_CLOCK_DIV_7,M6_CLOCK_DIV_8,M6_CLOCK_DIV_9,M6_CLOCK_DIV_10,M6_CLOCK_DIV_11,M6_CLOCK_DIV_12,M6_CLOCK_DIV_13,M6_CLOCK_DIV_14,M6_CLOCK_DIV_15,M6_CLOCK_DIV_16,M6_CLOCK_DIV_17,M6_CLOCK_DIV_18,M6_CLOCK_DIV_19,M6_CLOCK_DIV_20,M6_CLOCK_DIV_21,M6_CLOCK_DIV_22,M6_CLOCK_DIV_23,M6_CLOCK_DIV_24,M6_CLOCK_DIV_25,M6_CLOCK_DIV_26,M6_CLOCK_DIV_27,M6_CLOCK_DIV_28,M6_CLOCK_DIV_29,M6_CLOCK_DIV_30,M6_CLOCK_DIV_31" line.long 0x18 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable" "EN_SSC_0,EN_SSC_1" line.long 0x1C "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for SSC" hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for SSC" tree.end tree "DPLL_VIDEO1_L4_CFG" base ad:0x4A0A4000 group.long 0x00++0x1F line.long 0x00 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESET,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESET_0,HSDIV_SYSRESET_1" bitfld.long 0x00 3. "PLL_SYSRESET,Force DPLL SYSRESETN" "PLL_SYSRESET_0,PLL_SYSRESET_1" bitfld.long 0x00 2. "PLL_HALTMODE,Allow PLL to be halted if no activity" "PLL_HALTMODE_0,PLL_HALTMODE_1" newline bitfld.long 0x00 1. "PLL_GATEMODE,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0" "PLL_GATEMODE_0,PLL_GATEMODE_1" bitfld.long 0x00 0. "PLL_AUTOMODE,Automatic update mode" "PLL_AUTOMODE_0,PLL_AUTOMODE_1" line.long 0x04 "PLL_STATUS,This register contains the status information" bitfld.long 0x04 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x04 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" bitfld.long 0x04 13.--14. "BYPASSACKZ,State of bypass mode on PHY and HSDIVIDER" "BYPASSACKZ_0_r,BYPASSACKZ_1_r,?,?" newline bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" bitfld.long 0x04 10. "M6_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M6_Clk_Act" "M6_CLOCK_ACK_0_r,M6_CLOCK_ACK_1_r" bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on PHY and HSDIVIDER - Bypass_Nak" "BYPASSACKZ_MERGED_0_r,BYPASSACKZ_MERGED_1_r" newline bitfld.long 0x04 7. "M4_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M4_Clk_Act" "M4_CLOCK_ACK_0_r,M4_CLOCK_ACK_1_r" bitfld.long 0x04 6. "PLL_BYPASS,PLL Bypass status - Bypass_Act" "PLL_BYPASS_0_r,PLL_BYPASS_1_r" bitfld.long 0x04 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" newline bitfld.long 0x04 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x04 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" bitfld.long 0x04 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" newline bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x08 "PLL_GO,This register contains the GO bit" bitfld.long 0x08 1. "HSDIVLOAD,In manual mode start HSDIVIDER update sequence" "0,1" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0C 21.--25. "M4_CLOCK_DIV,Divider value for clock source M4REG" "M4_CLOCK_DIV_0,M4_CLOCK_DIV_1,M4_CLOCK_DIV_2,M4_CLOCK_DIV_3,M4_CLOCK_DIV_4,M4_CLOCK_DIV_5,M4_CLOCK_DIV_6,M4_CLOCK_DIV_7,M4_CLOCK_DIV_8,M4_CLOCK_DIV_9,M4_CLOCK_DIV_10,M4_CLOCK_DIV_11,M4_CLOCK_DIV_12,M4_CLOCK_DIV_13,M4_CLOCK_DIV_14,M4_CLOCK_DIV_15,M4_CLOCK_DIV_16,M4_CLOCK_DIV_17,M4_CLOCK_DIV_18,M4_CLOCK_DIV_19,M4_CLOCK_DIV_20,M4_CLOCK_DIV_21,M4_CLOCK_DIV_22,M4_CLOCK_DIV_23,M4_CLOCK_DIV_24,M4_CLOCK_DIV_25,M4_CLOCK_DIV_26,M4_CLOCK_DIV_27,M4_CLOCK_DIV_28,M4_CLOCK_DIV_29,M4_CLOCK_DIV_30,M4_CLOCK_DIV_31" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for PLL" hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x10 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 23. "M6_CLOCK_EN,Enable for M6 clock source - M6_Clk_Dis" "M6_CLOCK_EN_0,M6_CLOCK_EN_1" bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_Normal" "HSDIVBYPASS_0,HSDIVBYPASS_1" newline bitfld.long 0x10 16. "M4_CLOCK_EN,Enable for M4 clock source - SS_Clk_Dis" "M4_CLOCK_EN_0,M4_CLOCK_EN_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - Clk_PLL" "BYPASSEN_0,BYPASSEN_1" bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_Clk_Dis" "PHY_CLKINEN_0,PHY_CLKINEN_1" newline bitfld.long 0x10 13. "PLL_REFEN,PLL reference clock control - Ref_dis" "PLL_REFEN_0,PLL_REFEN_1" bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_Ref" "PLL_CLKSEL_0,PLL_CLKSEL_1" newline bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,PLL DRIFTGUARDEN - Drift_Guard_Dis" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" bitfld.long 0x10 6. "PLL_LOWCURRSTBY,PLL LOW CURRENT STANDBY - LOWCURRSTBY_notsel" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" newline bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the PLL - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" bitfld.long 0x10 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x14 0.--4. "M6_CLOCK_DIV,Divider value for M6 divider" "M6_CLOCK_DIV_0,M6_CLOCK_DIV_1,M6_CLOCK_DIV_2,M6_CLOCK_DIV_3,M6_CLOCK_DIV_4,M6_CLOCK_DIV_5,M6_CLOCK_DIV_6,M6_CLOCK_DIV_7,M6_CLOCK_DIV_8,M6_CLOCK_DIV_9,M6_CLOCK_DIV_10,M6_CLOCK_DIV_11,M6_CLOCK_DIV_12,M6_CLOCK_DIV_13,M6_CLOCK_DIV_14,M6_CLOCK_DIV_15,M6_CLOCK_DIV_16,M6_CLOCK_DIV_17,M6_CLOCK_DIV_18,M6_CLOCK_DIV_19,M6_CLOCK_DIV_20,M6_CLOCK_DIV_21,M6_CLOCK_DIV_22,M6_CLOCK_DIV_23,M6_CLOCK_DIV_24,M6_CLOCK_DIV_25,M6_CLOCK_DIV_26,M6_CLOCK_DIV_27,M6_CLOCK_DIV_28,M6_CLOCK_DIV_29,M6_CLOCK_DIV_30,M6_CLOCK_DIV_31" line.long 0x18 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable" "EN_SSC_0,EN_SSC_1" line.long 0x1C "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for SSC" hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for SSC" tree.end tree "DPLL_VIDEO2_L3_MAIN" base ad:0x58005300 group.long 0x00++0x1F line.long 0x00 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESET,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESET_0,HSDIV_SYSRESET_1" bitfld.long 0x00 3. "PLL_SYSRESET,Force DPLL SYSRESETN" "PLL_SYSRESET_0,PLL_SYSRESET_1" bitfld.long 0x00 2. "PLL_HALTMODE,Allow PLL to be halted if no activity" "PLL_HALTMODE_0,PLL_HALTMODE_1" newline bitfld.long 0x00 1. "PLL_GATEMODE,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0" "PLL_GATEMODE_0,PLL_GATEMODE_1" bitfld.long 0x00 0. "PLL_AUTOMODE,Automatic update mode" "PLL_AUTOMODE_0,PLL_AUTOMODE_1" line.long 0x04 "PLL_STATUS,This register contains the status information" bitfld.long 0x04 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x04 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" bitfld.long 0x04 13.--14. "BYPASSACKZ,State of bypass mode on PHY and HSDIVIDER" "BYPASSACKZ_0_r,BYPASSACKZ_1_r,?,?" newline bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" bitfld.long 0x04 10. "M6_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M6_Clk_Act" "M6_CLOCK_ACK_0_r,M6_CLOCK_ACK_1_r" bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on PHY and HSDIVIDER - Bypass_Nak" "BYPASSACKZ_MERGED_0_r,BYPASSACKZ_MERGED_1_r" newline bitfld.long 0x04 7. "M4_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M4_Clk_Act" "M4_CLOCK_ACK_0_r,M4_CLOCK_ACK_1_r" bitfld.long 0x04 6. "PLL_BYPASS,PLL Bypass status - Bypass_Act" "PLL_BYPASS_0_r,PLL_BYPASS_1_r" bitfld.long 0x04 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" newline bitfld.long 0x04 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x04 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" bitfld.long 0x04 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" newline bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x08 "PLL_GO,This register contains the GO bit" bitfld.long 0x08 1. "HSDIVLOAD,In manual mode start HSDIVIDER update sequence" "0,1" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0C 21.--25. "M4_CLOCK_DIV,Divider value for clock source M4REG" "M4_CLOCK_DIV_0,M4_CLOCK_DIV_1,M4_CLOCK_DIV_2,M4_CLOCK_DIV_3,M4_CLOCK_DIV_4,M4_CLOCK_DIV_5,M4_CLOCK_DIV_6,M4_CLOCK_DIV_7,M4_CLOCK_DIV_8,M4_CLOCK_DIV_9,M4_CLOCK_DIV_10,M4_CLOCK_DIV_11,M4_CLOCK_DIV_12,M4_CLOCK_DIV_13,M4_CLOCK_DIV_14,M4_CLOCK_DIV_15,M4_CLOCK_DIV_16,M4_CLOCK_DIV_17,M4_CLOCK_DIV_18,M4_CLOCK_DIV_19,M4_CLOCK_DIV_20,M4_CLOCK_DIV_21,M4_CLOCK_DIV_22,M4_CLOCK_DIV_23,M4_CLOCK_DIV_24,M4_CLOCK_DIV_25,M4_CLOCK_DIV_26,M4_CLOCK_DIV_27,M4_CLOCK_DIV_28,M4_CLOCK_DIV_29,M4_CLOCK_DIV_30,M4_CLOCK_DIV_31" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for PLL" hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x10 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 23. "M6_CLOCK_EN,Enable for M6 clock source - M6_Clk_Dis" "M6_CLOCK_EN_0,M6_CLOCK_EN_1" bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_Normal" "HSDIVBYPASS_0,HSDIVBYPASS_1" newline bitfld.long 0x10 16. "M4_CLOCK_EN,Enable for M4 clock source - SS_Clk_Dis" "M4_CLOCK_EN_0,M4_CLOCK_EN_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - Clk_PLL" "BYPASSEN_0,BYPASSEN_1" bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_Clk_Dis" "PHY_CLKINEN_0,PHY_CLKINEN_1" newline bitfld.long 0x10 13. "PLL_REFEN,PLL reference clock control - Ref_dis" "PLL_REFEN_0,PLL_REFEN_1" bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_Ref" "PLL_CLKSEL_0,PLL_CLKSEL_1" newline bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,PLL DRIFTGUARDEN - Drift_Guard_Dis" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" bitfld.long 0x10 6. "PLL_LOWCURRSTBY,PLL LOW CURRENT STANDBY - LOWCURRSTBY_notsel" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" newline bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the PLL - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" bitfld.long 0x10 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x14 0.--4. "M6_CLOCK_DIV,Divider value for M6 divider" "M6_CLOCK_DIV_0,M6_CLOCK_DIV_1,M6_CLOCK_DIV_2,M6_CLOCK_DIV_3,M6_CLOCK_DIV_4,M6_CLOCK_DIV_5,M6_CLOCK_DIV_6,M6_CLOCK_DIV_7,M6_CLOCK_DIV_8,M6_CLOCK_DIV_9,M6_CLOCK_DIV_10,M6_CLOCK_DIV_11,M6_CLOCK_DIV_12,M6_CLOCK_DIV_13,M6_CLOCK_DIV_14,M6_CLOCK_DIV_15,M6_CLOCK_DIV_16,M6_CLOCK_DIV_17,M6_CLOCK_DIV_18,M6_CLOCK_DIV_19,M6_CLOCK_DIV_20,M6_CLOCK_DIV_21,M6_CLOCK_DIV_22,M6_CLOCK_DIV_23,M6_CLOCK_DIV_24,M6_CLOCK_DIV_25,M6_CLOCK_DIV_26,M6_CLOCK_DIV_27,M6_CLOCK_DIV_28,M6_CLOCK_DIV_29,M6_CLOCK_DIV_30,M6_CLOCK_DIV_31" line.long 0x18 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable" "EN_SSC_0,EN_SSC_1" line.long 0x1C "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for SSC" hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for SSC" tree.end tree "DPLL_VIDEO2_L4_CFG" base ad:0x4A0A5000 group.long 0x00++0x1F line.long 0x00 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x00 4. "HSDIV_SYSRESET,Force HSDIVIDER SYSRESETN" "HSDIV_SYSRESET_0,HSDIV_SYSRESET_1" bitfld.long 0x00 3. "PLL_SYSRESET,Force DPLL SYSRESETN" "PLL_SYSRESET_0,PLL_SYSRESET_1" bitfld.long 0x00 2. "PLL_HALTMODE,Allow PLL to be halted if no activity" "PLL_HALTMODE_0,PLL_HALTMODE_1" newline bitfld.long 0x00 1. "PLL_GATEMODE,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0" "PLL_GATEMODE_0,PLL_GATEMODE_1" bitfld.long 0x00 0. "PLL_AUTOMODE,Automatic update mode" "PLL_AUTOMODE_0,PLL_AUTOMODE_1" line.long 0x04 "PLL_STATUS,This register contains the status information" bitfld.long 0x04 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x04 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" bitfld.long 0x04 13.--14. "BYPASSACKZ,State of bypass mode on PHY and HSDIVIDER" "BYPASSACKZ_0_r,BYPASSACKZ_1_r,?,?" newline bitfld.long 0x04 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" bitfld.long 0x04 10. "M6_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M6_Clk_Act" "M6_CLOCK_ACK_0_r,M6_CLOCK_ACK_1_r" bitfld.long 0x04 9. "BYPASSACKZ_MERGED,Merged state of bypass mode on PHY and HSDIVIDER - Bypass_Nak" "BYPASSACKZ_MERGED_0_r,BYPASSACKZ_MERGED_1_r" newline bitfld.long 0x04 7. "M4_CLOCK_ACK,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux - M4_Clk_Act" "M4_CLOCK_ACK_0_r,M4_CLOCK_ACK_1_r" bitfld.long 0x04 6. "PLL_BYPASS,PLL Bypass status - Bypass_Act" "PLL_BYPASS_0_r,PLL_BYPASS_1_r" bitfld.long 0x04 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" newline bitfld.long 0x04 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x04 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" bitfld.long 0x04 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" newline bitfld.long 0x04 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x08 "PLL_GO,This register contains the GO bit" bitfld.long 0x08 1. "HSDIVLOAD,In manual mode start HSDIVIDER update sequence" "0,1" bitfld.long 0x08 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x0C "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0C 21.--25. "M4_CLOCK_DIV,Divider value for clock source M4REG" "M4_CLOCK_DIV_0,M4_CLOCK_DIV_1,M4_CLOCK_DIV_2,M4_CLOCK_DIV_3,M4_CLOCK_DIV_4,M4_CLOCK_DIV_5,M4_CLOCK_DIV_6,M4_CLOCK_DIV_7,M4_CLOCK_DIV_8,M4_CLOCK_DIV_9,M4_CLOCK_DIV_10,M4_CLOCK_DIV_11,M4_CLOCK_DIV_12,M4_CLOCK_DIV_13,M4_CLOCK_DIV_14,M4_CLOCK_DIV_15,M4_CLOCK_DIV_16,M4_CLOCK_DIV_17,M4_CLOCK_DIV_18,M4_CLOCK_DIV_19,M4_CLOCK_DIV_20,M4_CLOCK_DIV_21,M4_CLOCK_DIV_22,M4_CLOCK_DIV_23,M4_CLOCK_DIV_24,M4_CLOCK_DIV_25,M4_CLOCK_DIV_26,M4_CLOCK_DIV_27,M4_CLOCK_DIV_28,M4_CLOCK_DIV_29,M4_CLOCK_DIV_30,M4_CLOCK_DIV_31" hexmask.long.word 0x0C 9.--20. 1. "PLL_REGM,M Divider for PLL" hexmask.long.byte 0x0C 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x10 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x10 23. "M6_CLOCK_EN,Enable for M6 clock source - M6_Clk_Dis" "M6_CLOCK_EN_0,M6_CLOCK_EN_1" bitfld.long 0x10 21.--22. "REFSEL,Selects the reference clock with optional divide by" "REFSEL_0,REFSEL_1,REFSEL_2,REFSEL_3" bitfld.long 0x10 20. "HSDIVBYPASS,Forces HSDIVIDER to bypass mode - HSDIV_Normal" "HSDIVBYPASS_0,HSDIVBYPASS_1" newline bitfld.long 0x10 16. "M4_CLOCK_EN,Enable for M4 clock source - SS_Clk_Dis" "M4_CLOCK_EN_0,M4_CLOCK_EN_1" bitfld.long 0x10 15. "BYPASSEN,Selects sub-system functional clock as PHY clock source - Clk_PLL" "BYPASSEN_0,BYPASSEN_1" bitfld.long 0x10 14. "PHY_CLKINEN,PHY clock control - PHY_Clk_Dis" "PHY_CLKINEN_0,PHY_CLKINEN_1" newline bitfld.long 0x10 13. "PLL_REFEN,PLL reference clock control - Ref_dis" "PLL_REFEN_0,PLL_REFEN_1" bitfld.long 0x10 12. "PLL_HIGHFREQ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N =" "PLL_HIGHFREQ_0,PLL_HIGHFREQ_1" bitfld.long 0x10 11. "PLL_CLKSEL,Reference clock selection - SYSCLK_Ref" "PLL_CLKSEL_0,PLL_CLKSEL_1" newline bitfld.long 0x10 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,PLL_LOCKSEL_2,?" bitfld.long 0x10 8. "PLL_DRIFTGUARDEN,PLL DRIFTGUARDEN - Drift_Guard_Dis" "PLL_DRIFTGUARDEN_0,PLL_DRIFTGUARDEN_1" bitfld.long 0x10 6. "PLL_LOWCURRSTBY,PLL LOW CURRENT STANDBY - LOWCURRSTBY_notsel" "PLL_LOWCURRSTBY_0,PLL_LOWCURRSTBY_1" newline bitfld.long 0x10 5. "PLL_PLLLPMODE,Select the power / performance of the PLL - FULL_PERF" "PLL_PLLLPMODE_0,PLL_PLLLPMODE_1" bitfld.long 0x10 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x14 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x14 0.--4. "M6_CLOCK_DIV,Divider value for M6 divider" "M6_CLOCK_DIV_0,M6_CLOCK_DIV_1,M6_CLOCK_DIV_2,M6_CLOCK_DIV_3,M6_CLOCK_DIV_4,M6_CLOCK_DIV_5,M6_CLOCK_DIV_6,M6_CLOCK_DIV_7,M6_CLOCK_DIV_8,M6_CLOCK_DIV_9,M6_CLOCK_DIV_10,M6_CLOCK_DIV_11,M6_CLOCK_DIV_12,M6_CLOCK_DIV_13,M6_CLOCK_DIV_14,M6_CLOCK_DIV_15,M6_CLOCK_DIV_16,M6_CLOCK_DIV_17,M6_CLOCK_DIV_18,M6_CLOCK_DIV_19,M6_CLOCK_DIV_20,M6_CLOCK_DIV_21,M6_CLOCK_DIV_22,M6_CLOCK_DIV_23,M6_CLOCK_DIV_24,M6_CLOCK_DIV_25,M6_CLOCK_DIV_26,M6_CLOCK_DIV_27,M6_CLOCK_DIV_28,M6_CLOCK_DIV_29,M6_CLOCK_DIV_30,M6_CLOCK_DIV_31" line.long 0x18 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x18 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x18 0. "EN_SSC,Spread Spectrum Clocking enable" "EN_SSC_0,EN_SSC_1" line.long 0x1C "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x1C 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x1C 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider (ModFreqDivider) control for SSC" hexmask.long.tbyte 0x1C 0.--19. 1. "DELTAM,DeltaM control for SSC" tree.end tree "DSI1_A_L3_MAIN" base ad:0x58004000 group.long 0x54++0x03 line.long 0x00 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION" bitfld.long 0x00 30.--31. "PLL_PWR_CMD,Command for power control of the DSI PLL Control Module" "PLL_PWR_CMD_0,PLL_PWR_CMD_1,PLL_PWR_CMD_2,PLL_PWR_CMD_3" rbitfld.long 0x00 28.--29. "PLL_PWR_STATUS,Status of the power control of the DSI PLL Control module" "PLL_PWR_STATUS_0,PLL_PWR_STATUS_1,PLL_PWR_STATUS_2,PLL_PWR_STATUS_3" tree.end tree "DSI1_B_L3_MAIN" base ad:0x58005000 group.long 0x54++0x03 line.long 0x00 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION" bitfld.long 0x00 30.--31. "PLL_PWR_CMD,Command for power control of the DSI PLL Control Module" "PLL_PWR_CMD_0,PLL_PWR_CMD_1,PLL_PWR_CMD_2,PLL_PWR_CMD_3" rbitfld.long 0x00 28.--29. "PLL_PWR_STATUS,Status of the power control of the DSI PLL Control module" "PLL_PWR_STATUS_0,PLL_PWR_STATUS_1,PLL_PWR_STATUS_2,PLL_PWR_STATUS_3" tree.end tree "DSS_L3_MAIN" base ad:0x58000000 rgroup.long 0x00++0x03 line.long 0x00 "DSS_REVISION,This register contains the DSS revision number" rgroup.long 0x14++0x03 line.long 0x00 "DSS_SYSSTATUS,This register provides status information about the module" bitfld.long 0x00 0. "RESETDONE,Internal reset monitoring - rstact" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x40++0x03 line.long 0x00 "DSS_CTRL,This register contains the DSS control bits" bitfld.long 0x00 19. "LCD3_CLK_SWITCH,DSS_CLK/DPLL_DSI1_C_CLK1 clock switch (multiplexer 10) Selects the clock source for the DISPC LCD3_CLK clock - DSS_CLK_Sel" "LCD3_CLK_SWITCH_0,LCD3_CLK_SWITCH_1" bitfld.long 0x00 16.--18. "PARALLEL_SEL,Selection between LCD1 LCD2 LCD3 and TV channel out on the parallel output (multiplexer" "PARALLEL_SEL_0,PARALLEL_SEL_1,PARALLEL_SEL_2,PARALLEL_SEL_3,?,?,?,?" bitfld.long 0x00 12. "LCD2_CLK_SWITCH,DSS_CLK clock switch (multiplexer 3) Selects the clock source for the DISPC LCD2_CLK clock - DSS_CLK_Sel" "LCD2_CLK_SWITCH_0,LCD2_CLK_SWITCH_1" newline bitfld.long 0x00 7.--9. "F_CLK_SWITCH,Selects the clock source for the DISPC functional clock F_CLK" "F_CLK_SWITCH_0,F_CLK_SWITCH_1,F_CLK_SWITCH_2,F_CLK_SWITCH_3,F_CLK_SWITCH_4,?,?,?" bitfld.long 0x00 0. "LCD1_CLK_SWITCH,DSS_CLK/DPLL_DSI1_A_CLK1 clock switch (multiplexer 2) Selects the clock source for the DISPC LCD1_CLK clock - DSS_CLK_Sel" "LCD1_CLK_SWITCH_0,LCD1_CLK_SWITCH_1" rgroup.long 0x5C++0x03 line.long 0x00 "DSS_STATUS,This register contains the DSS status" bitfld.long 0x00 24.--25. "LCD3_CLK_STATUS,LCD3_CLK clock selection status (multiplexer 10) indicates which clock is used by the glitch free mux selecting the source of LCD3_CLK" "LCD3_CLK_STATUS_0_r,LCD3_CLK_STATUS_1_r,LCD3_CLK_STATUS_2_r,?" bitfld.long 0x00 15.--19. "F_CLK_STATUS,F_CLK clock selection status (multiplexer 1) indicates which clock is used by the glitch free mux selecting the source of F_CLK" "F_CLK_STATUS_0_r,F_CLK_STATUS_1_r,F_CLK_STATUS_2_r,?,F_CLK_STATUS_4_r,?,?,?,F_CLK_STATUS_8_r,?,?,?,?,?,?,?,F_CLK_STATUS_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 11.--12. "LCD2_CLK_STATUS,LCD2_CLK clock selection status (multiplexer 3) indicates which clock is used by the glitch free mux selecting the source of LCD2_CLK" "LCD2_CLK_STATUS_0_r,LCD2_CLK_STATUS_1_r,LCD2_CLK_STATUS_2_r,?" newline bitfld.long 0x00 0.--1. "LCD1_CLK_STATUS,LCD1_CLK clock selection status (multiplexer 2) indicates which clock is used by the glitch free mux selecting the source of LCD1_CLK" "LCD1_CLK_STATUS_0_r,LCD1_CLK_STATUS_1_r,LCD1_CLK_STATUS_2_r,?" tree.end tree "HDMI_WP_L3_MAIN" base ad:0x58060000 group.long 0x40++0x03 line.long 0x00 "HDMI_WP_PWR_CTRL,Power control" bitfld.long 0x00 2.--3. "PLL_PWR_CMD,Command for power control of the HDMI PLL Control module - STATE_OFF" "PLL_PWR_CMD_0,PLL_PWR_CMD_1,PLL_PWR_CMD_2,PLL_PWR_CMD_3" rbitfld.long 0x00 0.--1. "PLL_PWR_STATUS,Status of the power control of the HDMI PLL Control module - STATE_OFF" "PLL_PWR_STATUS_0,PLL_PWR_STATUS_1,PLL_PWR_STATUS_2,PLL_PWR_STATUS_3" tree.end tree "OCP2SCP2_L4_CFG" base ad:0x4A0A0000 rgroup.long 0x00++0x03 line.long 0x00 "OCP2SCP_REVISION,IP Revision Identifier (X.Y.R)" group.long 0x10++0x0B line.long 0x00 "OCP2SCP_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 3.--4. "IDLEMODE,00 Force Idle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3_r" bitfld.long 0x00 1. "SOFTRESET,Software Reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,OCP clock gating control" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "OCP2SCP_SYSSTATUS,System Status register" bitfld.long 0x04 0. "RESETDONE,- Complete" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "OCP2SCP_TIMING,Interrupt Status Register (legacy) for first line of interrupt" bitfld.long 0x08 7.--9. "DIVISIONRATIO,Division Ration of the SCP clock in relation to OCP input clock" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "SYNC1,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--3. "SYNC2,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end tree.open "DSP_Subsystem" tree "DSP1_FW_L2_NOC_CFG" base ad:0x40D03000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" tree.end tree "DSP2_FW_L2_NOC_CFG" base ad:0x41503000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" tree.end tree "DSP_FW_L2_NOC_CFG" base ad:0x1D03000 group.long 0x00++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x40++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x88++0x17 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" line.long 0x08 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x08 0.--3. "START_REGION_1,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0C 31. "END_REGION_1_ENABLE,End Region 1 enable" "0,1" bitfld.long 0x0C 0.--3. "END_REGION_1,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x10 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x10 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x10 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x10 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x10 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x10 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x10 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x10 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x14 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x14 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x14 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x14 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x14 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x14 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x14 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x14 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x14 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x14 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x14 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x14 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x14 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x14 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x14 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x14 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x14 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x14 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x14 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x14 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x14 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x14 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x14 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x14 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x14 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x14 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x14 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x14 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x14 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x14 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x14 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x14 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x14 0. "R0,Initiator ID0 permission" "0,1" group.long 0x1000++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" bitfld.long 0x00 27. "BLK_BURST_VIOLATION,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x00 21.--25. "REGION_START_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 16.--20. "REGION_END_ERRLOG,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "REQINFO_ERRLOG,Error in reqinfo vector" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x04 0.--27. 1. "SLVOFS_LOGICAL,Address generated by the ARM before being translated" group.long 0x1040++0x03 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x00 1. "FW_LOAD_REQ,HW set/SW clear" "0,1" bitfld.long 0x00 0. "FW_UPDATE_REQ,HW set/SW clear" "0,1" group.long 0x1088++0x07 line.long 0x00 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Domain Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Domain Debug Allowed" "0,1" newline bitfld.long 0x00 11. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 7. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x04 31. "W15,Initiator ID15 permission" "0,1" bitfld.long 0x04 30. "R15,Initiator ID15 permission" "0,1" newline bitfld.long 0x04 29. "W14,Initiator ID14 permission" "0,1" bitfld.long 0x04 28. "R14,Initiator ID14 permission" "0,1" newline bitfld.long 0x04 27. "W13,Initiator ID13 permission" "0,1" bitfld.long 0x04 26. "R13,Initiator ID13 permission" "0,1" newline bitfld.long 0x04 25. "W12,Initiator ID12 permission" "0,1" bitfld.long 0x04 24. "R12,Initiator ID12 permission" "0,1" newline bitfld.long 0x04 23. "W11,Initiator ID11 permission" "0,1" bitfld.long 0x04 22. "R11,Initiator ID11 permission" "0,1" newline bitfld.long 0x04 21. "W10,Initiator ID10 permission" "0,1" bitfld.long 0x04 20. "R10,Initiator ID10 permission" "0,1" newline bitfld.long 0x04 19. "W9,Initiator ID9 permission" "0,1" bitfld.long 0x04 18. "R9,Initiator ID9 permission" "0,1" newline bitfld.long 0x04 17. "W8,Initiator ID8 permission" "0,1" bitfld.long 0x04 16. "R8,Initiator ID8 permission" "0,1" newline bitfld.long 0x04 15. "W7,Initiator ID7 permission" "0,1" bitfld.long 0x04 14. "R7,Initiator ID7 permission" "0,1" newline bitfld.long 0x04 13. "W6,Initiator ID6 permission" "0,1" bitfld.long 0x04 12. "R6,Initiator ID6 permission" "0,1" newline bitfld.long 0x04 11. "W5,Initiator ID5 permission" "0,1" bitfld.long 0x04 10. "R5,Initiator ID5 permission" "0,1" newline bitfld.long 0x04 9. "W4,Initiator ID4 permission" "0,1" bitfld.long 0x04 8. "R4,Initiator ID4 permission" "0,1" newline bitfld.long 0x04 7. "W3,Initiator ID3 permission" "0,1" bitfld.long 0x04 6. "R3,Initiator ID3 permission" "0,1" newline bitfld.long 0x04 5. "W2,Initiator ID2 permission" "0,1" bitfld.long 0x04 4. "R2,Initiator ID2 permission" "0,1" newline bitfld.long 0x04 3. "W1,Initiator ID1 permission" "0,1" bitfld.long 0x04 2. "R1,Initiator ID1 permission" "0,1" newline bitfld.long 0x04 1. "W0,Initiator ID0 permission" "0,1" bitfld.long 0x04 0. "R0,Initiator ID0 permission" "0,1" rgroup.long 0x4000++0x17 line.long 0x00 "DSPNOC_FLAGMUX_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_FLAGMUX_ID_REVISIONID," line.long 0x08 "DSPNOC_FLAGMUX_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x0C "DSPNOC_FLAGMUX_FAULTSTATUS," bitfld.long 0x0C 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x10 "DSPNOC_FLAGMUX_FLAGINEN0," bitfld.long 0x10 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x14 "DSPNOC_FLAGMUX_FLAGINSTATUS0," bitfld.long 0x14 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x4200++0x1B line.long 0x00 "DSPNOC_ERRORLOG_ID_COREID," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "DSPNOC_ERRORLOG_ID_REVISIONID," line.long 0x08 "DSPNOC_ERRORLOG_FAULTEN," bitfld.long 0x08 0. "FAULTEN,Enable Fault output" "0,1" line.long 0x0C "DSPNOC_ERRORLOG_ERRVLD," bitfld.long 0x0C 0. "ERRVLD,Error logged Valid" "0,1" line.long 0x10 "DSPNOC_ERRORLOG_ERRCLR," bitfld.long 0x10 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x14 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x14 31. "FORMAT,Format of ErrLog0 register" "0,1" hexmask.long.word 0x14 16.--27. 1. "LEN1,Header: Len1 value" newline bitfld.long 0x14 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x14 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x18 "DSPNOC_ERRORLOG_ERRLOG1," hexmask.long.word 0x18 0.--14. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x4220++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG3," hexmask.long 0x00 0.--30. 1. "ERRLOG3,Header: Addr lsb value" rgroup.long 0x4228++0x03 line.long 0x00 "DSPNOC_ERRORLOG_ERRLOG5," hexmask.long.tbyte 0x00 0.--21. 1. "ERRLOG5,Header: User lsb value" tree.end tree "DSP1_SYSTEM" base ad:0x40D00000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," bitfld.long 0x08 8. "DSP_IDLEREQ,- NOREQ" "DSP_IDLEREQ_0,DSP_IDLEREQ_1" bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status - IDLE" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status - IDLE" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 0. "C66X_STAT,C66x Status - IDLE" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override - MIX" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort - NOABORT" "MMU1_ABORT_0,MMU1_ABORT_1" bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort - NOABORT" "MMU0_ABORT_0,MMU0_ABORT_1" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable - DISABLED" "MMU1_EN_0,MMU1_EN_1" newline bitfld.long 0x18 0. "MMU0_EN,MU1 Enable - DISABLED" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the IDLE handshake)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the IDLE handshake)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the IDLE handshake)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the IDLE handshake)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux select" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" tree.end tree "DSP2_SYSTEM" base ad:0x41500000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," bitfld.long 0x08 8. "DSP_IDLEREQ,- NOREQ" "DSP_IDLEREQ_0,DSP_IDLEREQ_1" bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status - IDLE" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status - IDLE" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 0. "C66X_STAT,C66x Status - IDLE" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override - MIX" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort - NOABORT" "MMU1_ABORT_0,MMU1_ABORT_1" bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort - NOABORT" "MMU0_ABORT_0,MMU0_ABORT_1" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable - DISABLED" "MMU1_EN_0,MMU1_EN_1" newline bitfld.long 0x18 0. "MMU0_EN,MU1 Enable - DISABLED" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the IDLE handshake)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the IDLE handshake)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the IDLE handshake)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the IDLE handshake)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux select" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" tree.end tree "DSP_SYSTEM" base ad:0x1D00000 rgroup.long 0x00++0x1B line.long 0x00 "DSP_SYS_REVISION," line.long 0x04 "DSP_SYS_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "NUM,Instance Number Set by subsystem input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DSP_SYS_SYSCONFIG," bitfld.long 0x08 8. "DSP_IDLEREQ,- NOREQ" "DSP_IDLEREQ_0,DSP_IDLEREQ_1" bitfld.long 0x08 4.--5. "STANDBYMODE," "?,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x08 2.--3. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x0C "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode" bitfld.long 0x0C 4.--5. "OCPI_DISC_STAT,L3_MAIN (OCP) Initiator(s) Disconnect Status" "OCPI_DISC_STAT_0_r,OCPI_DISC_STAT_1_r,OCPI_DISC_STAT_2_r,?" bitfld.long 0x0C 2. "TC1_STAT,EDMA TC1 Status - IDLE" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 1. "TC0_STAT,EDMA TC0 Status - IDLE" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 0. "C66X_STAT,C66x Status - IDLE" "C66X_STAT_0,C66X_STAT_1" line.long 0x10 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses" bitfld.long 0x10 0. "OCPI_DISC,OCP Initiator (on L3_MAIN) Disconnect request" "OCPI_DISC_0_w,OCPI_DISC_1_w" line.long 0x14 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators" bitfld.long 0x14 28.--30. "SDMA_PRI,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24. "NOPOSTOVERRIDE,OCP Posted Write vs Non-Posted Write override - MIX" "NOPOSTOVERRIDE_0,NOPOSTOVERRIDE_1" bitfld.long 0x14 20.--21. "SDMA_L2PRES,OCP Target port L2 Interconnect Pressure" "SDMA_L2PRES_0,SDMA_L2PRES_1,SDMA_L2PRES_2,SDMA_L2PRES_3" newline bitfld.long 0x14 16.--17. "CFG_L2PRES,DSP CFG L2 Interconnect Pressure" "CFG_L2PRES_0,CFG_L2PRES_1,CFG_L2PRES_2,CFG_L2PRES_3" bitfld.long 0x14 12.--13. "TC1_L2PRES,TC1 L2 Interconnect Pressure" "TC1_L2PRES_0,TC1_L2PRES_1,TC1_L2PRES_2,TC1_L2PRES_3" bitfld.long 0x14 8.--9. "TC0_L2PRES,TC0 L2 Interconnect Pressure" "TC0_L2PRES_0,TC0_L2PRES_1,TC0_L2PRES_2,TC0_L2PRES_3" newline bitfld.long 0x14 4.--5. "TC1_DBS,TC1 Default Burst size" "TC1_DBS_0,TC1_DBS_1,TC1_DBS_2,TC1_DBS_3" bitfld.long 0x14 0.--1. "TC0_DBS,TC0 Default Burst size" "TC0_DBS_0,TC0_DBS_1,TC0_DBS_2,TC0_DBS_3" line.long 0x18 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs" bitfld.long 0x18 12. "MMU1_ABORT,MU1 Abort - NOABORT" "MMU1_ABORT_0,MMU1_ABORT_1" bitfld.long 0x18 8. "MMU0_ABORT,MU0 Abort - NOABORT" "MMU0_ABORT_0,MMU0_ABORT_1" bitfld.long 0x18 4. "MMU1_EN,MU1 Enable - DISABLED" "MMU1_EN_0,MMU1_EN_1" newline bitfld.long 0x18 0. "MMU0_EN,MU1 Enable - DISABLED" "MMU0_EN_0,MMU0_EN_1" group.long 0x20++0x07 line.long 0x00 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the IDLE handshake)" line.long 0x04 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the IDLE handshake)" group.long 0x30++0x07 line.long 0x00 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the IDLE handshake)" line.long 0x04 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the IDLE handshake)" group.long 0x40++0x07 line.long 0x00 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state" line.long 0x04 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state" group.long 0x50++0x2F line.long 0x00 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x00 0.--18. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector" hexmask.long.tbyte 0x04 0.--18. 1. "EVENT,Clearable enabled status for event #n" line.long 0x08 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x08 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x0C "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" hexmask.long.tbyte 0x0C 0.--18. 1. "ENABLE,Enable for event #n" line.long 0x10 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x14 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x18 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x1C "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" line.long 0x20 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" line.long 0x24 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector" line.long 0x28 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector" line.long 0x2C "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector" group.long 0xF8++0x07 line.long 0x00 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus" bitfld.long 0x00 0.--3. "GROUP,Debug Group output control mux select" "GROUP_0,GROUP_1,GROUP_2,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group" tree.end tree.end tree.open "Dual_Cortex_A15_MPU_Subsystem" tree "MPU_AXI2OCP_MISC" base ad:0x482A2000 group.long 0x00++0x03 line.long 0x00 "MA_PRIORITY,Memory adapter priority register" bitfld.long 0x00 8. "HIMEM_INTERLEAVE_UN,HIMEM_INTERLEAVE_UN" "0,1" bitfld.long 0x00 0.--2. "PRIORITY,MPU_MA priority value" "0,1,2,3,4,5,6,7" tree.end tree "MPU_PRCM_CM_C0" base ad:0x48243600 group.long 0x00++0x03 line.long 0x00 "CM_CPU0_CLKSTCTRL,This register enables the CPU domain power state transition" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the full domain transition of the CPU domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x20++0x03 line.long 0x00 "CM_CPU0_CPU0_CLKCTRL,This register manages the CPU clocks" bitfld.long 0x00 0. "STBYST,Module standby status" "STBYST_0_r,STBYST_1_r" tree.end tree "MPU_PRCM_CM_C1" base ad:0x48243A00 group.long 0x00++0x03 line.long 0x00 "CM_CPU1_CLKSTCTRL,This register enables the MPU domain power state transition" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the full domain transition of the CPU domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x20++0x03 line.long 0x00 "CM_CPU1_CPU1_CLKCTRL,This register manages the MPU clocks" bitfld.long 0x00 0. "STBYST,Module standby status" "STBYST_0_r,STBYST_1_r" tree.end tree "MPU_PRCM_DEVICE" base ad:0x48243200 group.long 0x00++0x07 line.long 0x00 "PRM_RSTST,This register logs the global reset sources. thus contains information regarding the cold/warm reset events generated by global PRCM" bitfld.long 0x00 1. "GLOBAL_WARM_RST,Global warm reset event generated by global PRCM - _0x0" "GLOBAL_WARM_RST_0,GLOBAL_WARM_RST_1" bitfld.long 0x00 0. "GLOBAL_COLD_RST,Power-on (cold) reset event generated by global PRCM - _0x0" "GLOBAL_COLD_RST_0,GLOBAL_COLD_RST_1" line.long 0x04 "PRM_PSCON_COUNT,Programmable precharge count for L1cache" bitfld.long 0x04 25. "HG_RAMPUP,Ramp-up mode selection of HG power chain switch - SLOW" "HG_RAMPUP_0,HG_RAMPUP_1" bitfld.long 0x04 24. "HG_EN,HG power chain switch enable - HG_DISABLE" "HG_EN_0,HG_EN_1" hexmask.long.byte 0x04 16.--23. 1. "HG_PONOUT_2_PGDOODIN_TIME,The value set in this field determines the slow ramp-up time and the duration (number of cycles) of the PONOUTHG to PGOODINHG (transition for power domain without DPS)" newline hexmask.long.byte 0x04 0.--7. 1. "PCHARGE_TIME,Programmable precharge count during retention" group.long 0x10++0x07 line.long 0x00 "PRM_FRAC_INCREMENTER_NUMERATOR,Fractional incrementor" hexmask.long.word 0x00 16.--27. 1. "ABE_LP_MODE_NUMERATOR,Numerator to be used in fractional incrementor when ABE_LP_CLK clock is used as PRCM clock" hexmask.long.word 0x00 0.--11. 1. "SYS_MODE_NUMERATOR,Numerator to be used in fractional incrementor when SYS_CLK is used as PRCM clock" line.long 0x04 "PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD,Reload command and denominator to be used in fractional incrementor" bitfld.long 0x04 16. "RELOAD,Reload counter value from coarse counter" "0,1" hexmask.long.word 0x04 0.--11. 1. "DENOMINATOR,Denominator to be used in fractional incrementor when when SYS_CLK is used as PRCM clock" tree.end tree "MPU_PRCM_OCP_SOCKET" base ad:0x48243000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_PRCM_MPU,IP Revision register" tree.end tree "MPU_PRCM_PRM_C0" base ad:0x48243400 group.long 0x00++0x07 line.long 0x00 "PM_CPU0_PWRSTCTRL,This register controls the CPU domain power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "L1_BANK_ONSTATE,CPU_L1 memory state when domain is ON" "?,?,?,L1_BANK_ONSTATE_3_r" rbitfld.long 0x00 8. "L1_BANK_RETSTATE,CPU_L1 memory state when domain is RETENTION" "?,L1_BANK_RETSTATE_1_r" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_RET" "?,LOGICRETSTATE_1_r" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CPU0_PWRSTST,This register provides a status on the CPU domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered - OFF" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0_r,INTRANSITION_1_r" rbitfld.long 0x04 4.--5. "L1_BANK_STATEST,CPU_L1 memory state status - MEM_OFF" "L1_BANK_STATEST_0_r,L1_BANK_STATEST_1_r,L1_BANK_STATEST_2_r,L1_BANK_STATEST_3_r" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0_r,LOGICSTATEST_1_r" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0_r,POWERSTATEST_1_r,POWERSTATEST_2_r,POWERSTATEST_3_r" group.long 0x10++0x07 line.long 0x00 "RM_CPU0_CPU0_RSTCTRL,This register controls the assertion/release of the CPU CORE reset" bitfld.long 0x00 0. "RST,CPU warm local reset control - CLEAR" "RST_0,RST_1" line.long 0x04 "RM_CPU0_CPU0_RSTST,This register logs the different reset sources of the MPU domain" bitfld.long 0x04 1. "DBGRST_REQ_RSTST,MPU_C0 processor has been reset due to MPU_C0 emulation reset request driven from MPUSS" "DBGRST_REQ_RSTST_0_r,DBGRST_REQ_RSTST_1_r" bitfld.long 0x04 0. "RSTST,MPU_C0 software reset - CLEAR" "RSTST_0_r,RSTST_1_r" group.long 0x24++0x03 line.long 0x00 "RM_CPU0_CPU0_CONTEXT,This register contains dedicated CPU context statuses" bitfld.long 0x00 8. "LOSTMEM_CPU_L1,Specify if memory-based context in CPU_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CPU_L1_0,LOSTMEM_CPU_L1_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "MPU_PRCM_PRM_C1" base ad:0x48243800 group.long 0x00++0x07 line.long 0x00 "PM_CPU1_PWRSTCTRL,This register controls the CPU domain power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "L1_BANK_ONSTATE,CPU_L1 memory state when domain is ON" "?,?,?,L1_BANK_ONSTATE_3_r" rbitfld.long 0x00 8. "L1_BANK_RETSTATE,CPU L1 memory state when domain is RETENTION" "?,L1_BANK_RETSTATE_1_r" bitfld.long 0x00 7. "FORCED_OFF,Selects if logic must be forced in OFF state" "FORCED_OFF_0,FORCED_OFF_1" newline rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_RET" "?,LOGICRETSTATE_1_r" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CPU1_PWRSTST,This register provides a status on the CPU domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low-power state entered - OFF" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0_r,INTRANSITION_1_r" rbitfld.long 0x04 4.--5. "L1_BANK_STATEST,CPU_L1 memory state status - MEM_OFF" "L1_BANK_STATEST_0_r,L1_BANK_STATEST_1_r,L1_BANK_STATEST_2_r,L1_BANK_STATEST_3_r" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0_r,LOGICSTATEST_1_r" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0_r,POWERSTATEST_1_r,POWERSTATEST_2_r,POWERSTATEST_3_r" group.long 0x10++0x07 line.long 0x00 "RM_CPU1_CPU1_RSTCTRL,This register controls the assertion/release of the CPU CORE reset" bitfld.long 0x00 0. "RST,CPU warm local reset control - CLEAR" "RST_0,RST_1" line.long 0x04 "RM_CPU1_CPU1_RSTST,This register logs the different reset sources of the MPU domain" bitfld.long 0x04 1. "DBGRST_REQ_RSTST,MPU_C1 processor has been reset due to MPU_C0 emulation reset request driven from MPUSS - CLEAR" "DBGRST_REQ_RSTST_0_r,DBGRST_REQ_RSTST_1_r" bitfld.long 0x04 0. "RSTST,MPU_C1 software reset - CLEAR" "RSTST_0_r,RSTST_1_r" group.long 0x24++0x03 line.long 0x00 "RM_CPU1_CPU1_CONTEXT,This register contains dedicated CPU context statuses" bitfld.long 0x00 8. "LOSTMEM_CPU_L1,Specify if memory-based context in CPU_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CPU_L1_0,LOSTMEM_CPU_L1_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "MPU_WD_TIMER" base ad:0x482A0000 repeat 2. (list 0. 1. ) tree "REG_Bundle_$1" group.long 0x10++0x03 line.long 0x00 "WDT_CONTROL_REGISTER_i_0,This register controls the behavior of the MPU_WD_TIMER_Cx" bitfld.long 0x00 8. "WARNEN,Warning Interrupt Enable" "0,1" bitfld.long 0x00 3. "MPUSSRSTEN,MPUSS Reset Enable" "0,1" bitfld.long 0x00 1. "INTREN,Interrupt Enable" "0,1" bitfld.long 0x00 0. "ENABLE,Enable for MPU_WD_TIMER_Cx" "0,1" rgroup.long 0x04++0x03 line.long 0x00 "WDT_COUNT_REGISTER_i_0,This register is a 32-bit decrementing counter" group.long 0x00++0x03 line.long 0x00 "WDT_LOAD_REGISTER_i_0,When a new value is stored in this register. the is immediately loaded with this value and the prescaler state is cleared" group.long 0x0C++0x03 line.long 0x00 "WDT_PRESCALER_REGISTER_i_0,This register is used to set the count rate of the MPU_WD_TIMER_Cx counter" hexmask.long.word 0x00 0.--9. 1. "PRESCALER,Sets the prescaler ratio.WDT_COUNT_REGISTER_i decrements every (PRESCALER + 1) MPU_DPLL_CLK clocks" group.long 0x14++0x03 line.long 0x00 "WDT_RESET_STATUS_REGISTER_i_0,The TO bit indicated that this MPU_WD_TIMER_Cx has timed out" bitfld.long 0x00 1. "WARN,Warning" "0,1" bitfld.long 0x00 0. "TO,Timeout" "0,1" group.long 0x08++0x03 line.long 0x00 "WDT_WARNING_REGISTER_i_0,The is compared to" tree.end repeat.end tree.end tree "MPU_WUGEN" base ad:0x48281000 group.long 0x00++0x03 line.long 0x00 "WKG_CONTROL_0,Wake-up generator control and status register for MPU_C0" rbitfld.long 0x00 15. "DOMAINRESET,MPU always-on power domain (PD_MPUAON) reset status bit" "0,1" bitfld.long 0x00 14. "MPU_WARM_RESET,This bit is set when the MPU_WARM_RESET signal is asserted" "0,1" bitfld.long 0x00 13. "MPU_COLD_RESET,This bit is set when the MPU_COLD_RESET signal is asserted" "0,1" bitfld.long 0x00 10. "EVENTO,EVENTO status bit" "0,1" bitfld.long 0x00 9. "STANDBYWFE,This bit gives software the visibility to track whether WFE mode have been entered" "0,1" newline bitfld.long 0x00 8. "STANDBYWFI,This bit gives software the visibility to track whether WFI mode have been entered" "0,1" group.long 0x10++0x13 line.long 0x00 "WKG_ENB_A_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_0 to MPU_IRQ_31)" bitfld.long 0x00 31. "WKG_ENB_FOR_INTR31,Wakeup enable for interrupt line MPU_IRQ_31" "0,1" bitfld.long 0x00 30. "WKG_ENB_FOR_INTR30,Wakeup enable for interrupt line MPU_IRQ_30" "0,1" bitfld.long 0x00 29. "WKG_ENB_FOR_INTR29,Wakeup enable for interrupt line MPU_IRQ_29" "0,1" bitfld.long 0x00 28. "WKG_ENB_FOR_INTR28,Wakeup enable for interrupt line MPU_IRQ_28" "0,1" bitfld.long 0x00 27. "WKG_ENB_FOR_INTR27,Wakeup enable for interrupt line MPU_IRQ_27" "0,1" newline bitfld.long 0x00 26. "WKG_ENB_FOR_INTR26,Wakeup enable for interrupt line MPU_IRQ_26" "0,1" bitfld.long 0x00 25. "WKG_ENB_FOR_INTR25,Wakeup enable for interrupt line MPU_IRQ_25" "0,1" bitfld.long 0x00 24. "WKG_ENB_FOR_INTR24,Wakeup enable for interrupt line MPU_IRQ_24" "0,1" bitfld.long 0x00 23. "WKG_ENB_FOR_INTR23,Wakeup enable for interrupt line MPU_IRQ_23" "0,1" bitfld.long 0x00 22. "WKG_ENB_FOR_INTR22,Wakeup enable for interrupt line MPU_IRQ_22" "0,1" newline bitfld.long 0x00 21. "WKG_ENB_FOR_INTR21,Wakeup enable for interrupt line MPU_IRQ_21" "0,1" bitfld.long 0x00 20. "WKG_ENB_FOR_INTR20,Wakeup enable for interrupt line MPU_IRQ_20" "0,1" bitfld.long 0x00 19. "WKG_ENB_FOR_INTR19,Wakeup enable for interrupt line MPU_IRQ_19" "0,1" bitfld.long 0x00 18. "WKG_ENB_FOR_INTR18,Wakeup enable for interrupt line MPU_IRQ_18" "0,1" bitfld.long 0x00 17. "WKG_ENB_FOR_INTR17,Wakeup enable for interrupt line MPU_IRQ_17" "0,1" newline bitfld.long 0x00 16. "WKG_ENB_FOR_INTR16,Wakeup enable for interrupt line MPU_IRQ_16" "0,1" bitfld.long 0x00 15. "WKG_ENB_FOR_INTR15,Wakeup enable for interrupt line MPU_IRQ_15" "0,1" bitfld.long 0x00 14. "WKG_ENB_FOR_INTR14,Wakeup enable for interrupt line MPU_IRQ_14" "0,1" bitfld.long 0x00 13. "WKG_ENB_FOR_INTR13,Wakeup enable for interrupt line MPU_IRQ_13" "0,1" bitfld.long 0x00 12. "WKG_ENB_FOR_INTR12,Wakeup enable for interrupt line MPU_IRQ_12" "0,1" newline bitfld.long 0x00 11. "WKG_ENB_FOR_INTR11,Wakeup enable for interrupt line MPU_IRQ_11" "0,1" bitfld.long 0x00 10. "WKG_ENB_FOR_INTR10,Wakeup enable for interrupt line MPU_IRQ_10" "0,1" bitfld.long 0x00 9. "WKG_ENB_FOR_INTR9,Wakeup enable for interrupt line MPU_IRQ_9" "0,1" bitfld.long 0x00 8. "WKG_ENB_FOR_INTR8,Wakeup enable for interrupt line MPU_IRQ_8" "0,1" bitfld.long 0x00 7. "WKG_ENB_FOR_INTR7,Wakeup enable for interrupt line MPU_IRQ_7" "0,1" newline bitfld.long 0x00 6. "WKG_ENB_FOR_INTR6,Wakeup enable for interrupt line MPU_IRQ_6" "0,1" bitfld.long 0x00 5. "WKG_ENB_FOR_INTR5,Wakeup enable for interrupt line MPU_IRQ_5" "0,1" bitfld.long 0x00 4. "WKG_ENB_FOR_INTR4,Wakeup enable for interrupt line MPU_IRQ_4" "0,1" bitfld.long 0x00 3. "WKG_ENB_FOR_INTR3,Wakeup enable for interrupt line MPU_IRQ_3" "0,1" bitfld.long 0x00 2. "WKG_ENB_FOR_INTR2,Wakeup enable for interrupt line MPU_IRQ_2" "0,1" newline bitfld.long 0x00 1. "WKG_ENB_FOR_INTR1,Wakeup enable for interrupt line MPU_IRQ_1" "0,1" bitfld.long 0x00 0. "WKG_ENB_FOR_INTR0,Wakeup enable for interrupt line MPU_IRQ_0" "0,1" line.long 0x04 "WKG_ENB_B_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_32 to MPU_IRQ_63)" bitfld.long 0x04 31. "WKG_ENB_FOR_INTR63,Wakeup enable for interrupt line MPU_IRQ_63" "0,1" bitfld.long 0x04 30. "WKG_ENB_FOR_INTR62,Wakeup enable for interrupt line MPU_IRQ_62" "0,1" bitfld.long 0x04 29. "WKG_ENB_FOR_INTR61,Wakeup enable for interrupt line MPU_IRQ_61" "0,1" bitfld.long 0x04 28. "WKG_ENB_FOR_INTR60,Wakeup enable for interrupt line MPU_IRQ_60" "0,1" bitfld.long 0x04 27. "WKG_ENB_FOR_INTR59,Wakeup enable for interrupt line MPU_IRQ_59" "0,1" newline bitfld.long 0x04 26. "WKG_ENB_FOR_INTR58,Wakeup enable for interrupt line MPU_IRQ_58" "0,1" bitfld.long 0x04 25. "WKG_ENB_FOR_INTR57,Wakeup enable for interrupt line MPU_IRQ_57" "0,1" bitfld.long 0x04 24. "WKG_ENB_FOR_INTR56,Wakeup enable for interrupt line MPU_IRQ_56" "0,1" bitfld.long 0x04 23. "WKG_ENB_FOR_INTR55,Wakeup enable for interrupt line MPU_IRQ_55" "0,1" bitfld.long 0x04 22. "WKG_ENB_FOR_INTR54,Wakeup enable for interrupt line MPU_IRQ_54" "0,1" newline bitfld.long 0x04 21. "WKG_ENB_FOR_INTR53,Wakeup enable for interrupt line MPU_IRQ_53" "0,1" bitfld.long 0x04 20. "WKG_ENB_FOR_INTR52,Wakeup enable for interrupt line MPU_IRQ_52" "0,1" bitfld.long 0x04 19. "WKG_ENB_FOR_INTR51,Wakeup enable for interrupt line MPU_IRQ_51" "0,1" bitfld.long 0x04 18. "WKG_ENB_FOR_INTR50,Wakeup enable for interrupt line MPU_IRQ_50" "0,1" bitfld.long 0x04 17. "WKG_ENB_FOR_INTR49,Wakeup enable for interrupt line MPU_IRQ_49" "0,1" newline bitfld.long 0x04 16. "WKG_ENB_FOR_INTR48,Wakeup enable for interrupt line MPU_IRQ_48" "0,1" bitfld.long 0x04 15. "WKG_ENB_FOR_INTR47,Wakeup enable for interrupt line MPU_IRQ_47" "0,1" bitfld.long 0x04 14. "WKG_ENB_FOR_INTR46,Wakeup enable for interrupt line MPU_IRQ_46" "0,1" bitfld.long 0x04 13. "WKG_ENB_FOR_INTR45,Wakeup enable for interrupt line MPU_IRQ_45" "0,1" bitfld.long 0x04 12. "WKG_ENB_FOR_INTR44,Wakeup enable for interrupt line MPU_IRQ_44" "0,1" newline bitfld.long 0x04 11. "WKG_ENB_FOR_INTR43,Wakeup enable for interrupt line MPU_IRQ_43" "0,1" bitfld.long 0x04 10. "WKG_ENB_FOR_INTR42,Wakeup enable for interrupt line MPU_IRQ_42" "0,1" bitfld.long 0x04 9. "WKG_ENB_FOR_INTR41,Wakeup enable for interrupt line MPU_IRQ_41" "0,1" bitfld.long 0x04 8. "WKG_ENB_FOR_INTR40,Wakeup enable for interrupt line MPU_IRQ_40" "0,1" bitfld.long 0x04 7. "WKG_ENB_FOR_INTR39,Wakeup enable for interrupt line MPU_IRQ_39" "0,1" newline bitfld.long 0x04 6. "WKG_ENB_FOR_INTR38,Wakeup enable for interrupt line MPU_IRQ_38" "0,1" bitfld.long 0x04 5. "WKG_ENB_FOR_INTR37,Wakeup enable for interrupt line MPU_IRQ_37" "0,1" bitfld.long 0x04 4. "WKG_ENB_FOR_INTR36,Wakeup enable for interrupt line MPU_IRQ_36" "0,1" bitfld.long 0x04 3. "WKG_ENB_FOR_INTR35,Wakeup enable for interrupt line MPU_IRQ_35" "0,1" bitfld.long 0x04 2. "WKG_ENB_FOR_INTR34,Wakeup enable for interrupt line MPU_IRQ_34" "0,1" newline bitfld.long 0x04 1. "WKG_ENB_FOR_INTR33,Wakeup enable for interrupt line MPU_IRQ_33" "0,1" bitfld.long 0x04 0. "WKG_ENB_FOR_INTR32,Wakeup enable for interrupt line MPU_IRQ_32" "0,1" line.long 0x08 "WKG_ENB_C_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_64 to MPU_IRQ_95)" bitfld.long 0x08 31. "WKG_ENB_FOR_INTR95,Wakeup enable for interrupt line MPU_IRQ_95" "0,1" bitfld.long 0x08 30. "WKG_ENB_FOR_INTR94,Wakeup enable for interrupt line MPU_IRQ_94" "0,1" bitfld.long 0x08 29. "WKG_ENB_FOR_INTR93,Wakeup enable for interrupt line MPU_IRQ_93" "0,1" bitfld.long 0x08 28. "WKG_ENB_FOR_INTR92,Wakeup enable for interrupt line MPU_IRQ_92" "0,1" bitfld.long 0x08 27. "WKG_ENB_FOR_INTR91,Wakeup enable for interrupt line MPU_IRQ_91" "0,1" newline bitfld.long 0x08 26. "WKG_ENB_FOR_INTR90,Wakeup enable for interrupt line MPU_IRQ_90" "0,1" bitfld.long 0x08 25. "WKG_ENB_FOR_INTR89,Wakeup enable for interrupt line MPU_IRQ_89" "0,1" bitfld.long 0x08 24. "WKG_ENB_FOR_INTR88,Wakeup enable for interrupt line MPU_IRQ_88" "0,1" bitfld.long 0x08 23. "WKG_ENB_FOR_INTR87,Wakeup enable for interrupt line MPU_IRQ_87" "0,1" bitfld.long 0x08 22. "WKG_ENB_FOR_INTR86,Wakeup enable for interrupt line MPU_IRQ_86" "0,1" newline bitfld.long 0x08 21. "WKG_ENB_FOR_INTR85,Wakeup enable for interrupt line MPU_IRQ_85" "0,1" bitfld.long 0x08 20. "WKG_ENB_FOR_INTR84,Wakeup enable for interrupt line MPU_IRQ_84" "0,1" bitfld.long 0x08 19. "WKG_ENB_FOR_INTR83,Wakeup enable for interrupt line MPU_IRQ_83" "0,1" bitfld.long 0x08 18. "WKG_ENB_FOR_INTR82,Wakeup enable for interrupt line MPU_IRQ_82" "0,1" bitfld.long 0x08 17. "WKG_ENB_FOR_INTR81,Wakeup enable for interrupt line MPU_IRQ_81" "0,1" newline bitfld.long 0x08 16. "WKG_ENB_FOR_INTR80,Wakeup enable for interrupt line MPU_IRQ_80" "0,1" bitfld.long 0x08 15. "WKG_ENB_FOR_INTR79,Wakeup enable for interrupt line MPU_IRQ_79" "0,1" bitfld.long 0x08 14. "WKG_ENB_FOR_INTR78,Wakeup enable for interrupt line MPU_IRQ_78" "0,1" bitfld.long 0x08 13. "WKG_ENB_FOR_INTR77,Wakeup enable for interrupt line MPU_IRQ_77" "0,1" bitfld.long 0x08 12. "WKG_ENB_FOR_INTR76,Wakeup enable for interrupt line MPU_IRQ_76" "0,1" newline bitfld.long 0x08 11. "WKG_ENB_FOR_INTR75,Wakeup enable for interrupt line MPU_IRQ_75" "0,1" bitfld.long 0x08 10. "WKG_ENB_FOR_INTR74,Wakeup enable for interrupt line MPU_IRQ_74" "0,1" bitfld.long 0x08 9. "WKG_ENB_FOR_INTR73,Wakeup enable for interrupt line MPU_IRQ_73" "0,1" bitfld.long 0x08 8. "WKG_ENB_FOR_INTR72,Wakeup enable for interrupt line MPU_IRQ_72" "0,1" bitfld.long 0x08 7. "WKG_ENB_FOR_INTR71,Wakeup enable for interrupt line MPU_IRQ_71" "0,1" newline bitfld.long 0x08 6. "WKG_ENB_FOR_INTR70,Wakeup enable for interrupt line MPU_IRQ_70" "0,1" bitfld.long 0x08 5. "WKG_ENB_FOR_INTR69,Wakeup enable for interrupt line MPU_IRQ_69" "0,1" bitfld.long 0x08 4. "WKG_ENB_FOR_INTR68,Wakeup enable for interrupt line MPU_IRQ_68" "0,1" bitfld.long 0x08 3. "WKG_ENB_FOR_INTR67,Wakeup enable for interrupt line MPU_IRQ_67" "0,1" bitfld.long 0x08 2. "WKG_ENB_FOR_INTR66,Wakeup enable for interrupt line MPU_IRQ_66" "0,1" newline bitfld.long 0x08 1. "WKG_ENB_FOR_INTR65,Wakeup enable for interrupt line MPU_IRQ_65" "0,1" bitfld.long 0x08 0. "WKG_ENB_FOR_INTR64,Wakeup enable for interrupt line MPU_IRQ_64" "0,1" line.long 0x0C "WKG_ENB_D_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_96 to MPU_IRQ_127)" bitfld.long 0x0C 31. "WKG_ENB_FOR_INTR127,Wakeup enable for interrupt line MPU_IRQ_127" "0,1" bitfld.long 0x0C 30. "WKG_ENB_FOR_INTR126,Wakeup enable for interrupt line MPU_IRQ_126" "0,1" bitfld.long 0x0C 29. "WKG_ENB_FOR_INTR125,Wakeup enable for interrupt line MPU_IRQ_125" "0,1" bitfld.long 0x0C 28. "WKG_ENB_FOR_INTR124,Wakeup enable for interrupt line MPU_IRQ_124" "0,1" bitfld.long 0x0C 27. "WKG_ENB_FOR_INTR123,Wakeup enable for interrupt line MPU_IRQ_123" "0,1" newline bitfld.long 0x0C 26. "WKG_ENB_FOR_INTR122,Wakeup enable for interrupt line MPU_IRQ_122" "0,1" bitfld.long 0x0C 25. "WKG_ENB_FOR_INTR121,Wakeup enable for interrupt line MPU_IRQ_121" "0,1" bitfld.long 0x0C 24. "WKG_ENB_FOR_INTR120,Wakeup enable for interrupt line MPU_IRQ_120" "0,1" bitfld.long 0x0C 23. "WKG_ENB_FOR_INTR119,Wakeup enable for interrupt line MPU_IRQ_119" "0,1" bitfld.long 0x0C 22. "WKG_ENB_FOR_INTR118,Wakeup enable for interrupt line MPU_IRQ_118" "0,1" newline bitfld.long 0x0C 21. "WKG_ENB_FOR_INTR117,Wakeup enable for interrupt line MPU_IRQ_117" "0,1" bitfld.long 0x0C 20. "WKG_ENB_FOR_INTR116,Wakeup enable for interrupt line MPU_IRQ_116" "0,1" bitfld.long 0x0C 19. "WKG_ENB_FOR_INTR115,Wakeup enable for interrupt line MPU_IRQ_115" "0,1" bitfld.long 0x0C 18. "WKG_ENB_FOR_INTR114,Wakeup enable for interrupt line MPU_IRQ_114" "0,1" bitfld.long 0x0C 17. "WKG_ENB_FOR_INTR113,Wakeup enable for interrupt line MPU_IRQ_113" "0,1" newline bitfld.long 0x0C 16. "WKG_ENB_FOR_INTR112,Wakeup enable for interrupt line MPU_IRQ_112" "0,1" bitfld.long 0x0C 15. "WKG_ENB_FOR_INTR111,Wakeup enable for interrupt line MPU_IRQ_111" "0,1" bitfld.long 0x0C 14. "WKG_ENB_FOR_INTR110,Wakeup enable for interrupt line MPU_IRQ_110" "0,1" bitfld.long 0x0C 13. "WKG_ENB_FOR_INTR109,Wakeup enable for interrupt line MPU_IRQ_109" "0,1" bitfld.long 0x0C 12. "WKG_ENB_FOR_INTR108,Wakeup enable for interrupt line MPU_IRQ_108" "0,1" newline bitfld.long 0x0C 11. "WKG_ENB_FOR_INTR107,Wakeup enable for interrupt line MPU_IRQ_107" "0,1" bitfld.long 0x0C 10. "WKG_ENB_FOR_INTR106,Wakeup enable for interrupt line MPU_IRQ_106" "0,1" bitfld.long 0x0C 9. "WKG_ENB_FOR_INTR105,Wakeup enable for interrupt line MPU_IRQ_105" "0,1" bitfld.long 0x0C 8. "WKG_ENB_FOR_INTR104,Wakeup enable for interrupt line MPU_IRQ_104" "0,1" bitfld.long 0x0C 7. "WKG_ENB_FOR_INTR103,Wakeup enable for interrupt line MPU_IRQ_103" "0,1" newline bitfld.long 0x0C 6. "WKG_ENB_FOR_INTR102,Wakeup enable for interrupt line MPU_IRQ_102" "0,1" bitfld.long 0x0C 5. "WKG_ENB_FOR_INTR101,Wakeup enable for interrupt line MPU_IRQ_101" "0,1" bitfld.long 0x0C 4. "WKG_ENB_FOR_INTR100,Wakeup enable for interrupt line MPU_IRQ_100" "0,1" bitfld.long 0x0C 3. "WKG_ENB_FOR_INTR99,Wakeup enable for interrupt line MPU_IRQ_99" "0,1" bitfld.long 0x0C 2. "WKG_ENB_FOR_INTR98,Wakeup enable for interrupt line MPU_IRQ_98" "0,1" newline bitfld.long 0x0C 1. "WKG_ENB_FOR_INTR97,Wakeup enable for interrupt line MPU_IRQ_97" "0,1" bitfld.long 0x0C 0. "WKG_ENB_FOR_INTR96,Wakeup enable for interrupt line MPU_IRQ_96" "0,1" line.long 0x10 "WKG_ENB_E_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_128 to MPU_IRQ_159)" bitfld.long 0x10 31. "WKG_ENB_FOR_INTR159,Wakeup enable for interrupt line MPU_IRQ_159" "0,1" bitfld.long 0x10 30. "WKG_ENB_FOR_INTR158,Wakeup enable for interrupt line MPU_IRQ_158" "0,1" bitfld.long 0x10 29. "WKG_ENB_FOR_INTR157,Wakeup enable for interrupt line MPU_IRQ_157" "0,1" bitfld.long 0x10 28. "WKG_ENB_FOR_INTR156,Wakeup enable for interrupt line MPU_IRQ_156" "0,1" bitfld.long 0x10 27. "WKG_ENB_FOR_INTR155,Wakeup enable for interrupt line MPU_IRQ_155" "0,1" newline bitfld.long 0x10 26. "WKG_ENB_FOR_INTR154,Wakeup enable for interrupt line MPU_IRQ_154" "0,1" bitfld.long 0x10 25. "WKG_ENB_FOR_INTR153,Wakeup enable for interrupt line MPU_IRQ_153" "0,1" bitfld.long 0x10 24. "WKG_ENB_FOR_INTR152,Wakeup enable for interrupt line MPU_IRQ_152" "0,1" bitfld.long 0x10 23. "WKG_ENB_FOR_INTR151,Wakeup enable for interrupt line MPU_IRQ_151" "0,1" bitfld.long 0x10 22. "WKG_ENB_FOR_INTR150,Wakeup enable for interrupt line MPU_IRQ_150" "0,1" newline bitfld.long 0x10 21. "WKG_ENB_FOR_INTR149,Wakeup enable for interrupt line MPU_IRQ_149" "0,1" bitfld.long 0x10 20. "WKG_ENB_FOR_INTR148,Wakeup enable for interrupt line MPU_IRQ_148" "0,1" bitfld.long 0x10 19. "WKG_ENB_FOR_INTR147,Wakeup enable for interrupt line MPU_IRQ_147" "0,1" bitfld.long 0x10 18. "WKG_ENB_FOR_INTR146,Wakeup enable for interrupt line MPU_IRQ_146" "0,1" bitfld.long 0x10 17. "WKG_ENB_FOR_INTR145,Wakeup enable for interrupt line MPU_IRQ_145" "0,1" newline bitfld.long 0x10 16. "WKG_ENB_FOR_INTR144,Wakeup enable for interrupt line MPU_IRQ_144" "0,1" bitfld.long 0x10 15. "WKG_ENB_FOR_INTR143,Wakeup enable for interrupt line MPU_IRQ_143" "0,1" bitfld.long 0x10 14. "WKG_ENB_FOR_INTR142,Wakeup enable for interrupt line MPU_IRQ_142" "0,1" bitfld.long 0x10 13. "WKG_ENB_FOR_INTR141,Wakeup enable for interrupt line MPU_IRQ_141" "0,1" bitfld.long 0x10 12. "WKG_ENB_FOR_INTR140,Wakeup enable for interrupt line MPU_IRQ_140" "0,1" newline bitfld.long 0x10 11. "WKG_ENB_FOR_INTR139,Wakeup enable for interrupt line MPU_IRQ_139" "0,1" bitfld.long 0x10 10. "WKG_ENB_FOR_INTR138,Wakeup enable for interrupt line MPU_IRQ_138" "0,1" bitfld.long 0x10 9. "WKG_ENB_FOR_INTR137,Wakeup enable for interrupt line MPU_IRQ_137" "0,1" bitfld.long 0x10 8. "WKG_ENB_FOR_INTR136,Wakeup enable for interrupt line MPU_IRQ_136" "0,1" bitfld.long 0x10 7. "WKG_ENB_FOR_INTR135,Wakeup enable for interrupt line MPU_IRQ_135" "0,1" newline bitfld.long 0x10 6. "WKG_ENB_FOR_INTR134,Wakeup enable for interrupt line MPU_IRQ_134" "0,1" bitfld.long 0x10 5. "WKG_ENB_FOR_INTR133,Wakeup enable for interrupt line MPU_IRQ_133" "0,1" bitfld.long 0x10 4. "WKG_ENB_FOR_INTR132,Wakeup enable for interrupt line MPU_IRQ_132" "0,1" bitfld.long 0x10 3. "WKG_ENB_FOR_INTR131,Wakeup enable for interrupt line MPU_IRQ_131" "0,1" bitfld.long 0x10 2. "WKG_ENB_FOR_INTR130,Wakeup enable for interrupt line MPU_IRQ_130" "0,1" newline bitfld.long 0x10 1. "WKG_ENB_FOR_INTR129,Wakeup enable for interrupt line MPU_IRQ_129" "0,1" bitfld.long 0x10 0. "WKG_ENB_FOR_INTR128,Wakeup enable for interrupt line MPU_IRQ_128" "0,1" group.long 0x400++0x03 line.long 0x00 "WKG_CONTROL_1,Wake-up generator control and status register for MPU_C1" rbitfld.long 0x00 15. "DOMAINRESET,MPU always-on power domain (PD_MPUAON) reset status bit" "0,1" bitfld.long 0x00 14. "MPU_WARM_RESET,This bit is set when the MPU_WARM_RESET signal is asserted" "0,1" bitfld.long 0x00 13. "MPU_COLD_RESET,This bit is set when the MPU_COLD_RESET signal is asserted" "0,1" bitfld.long 0x00 10. "EVENTO,EVENTO status bit" "0,1" bitfld.long 0x00 9. "STANDBYWFE,This bit gives software the visibility to track whether WFE mode have been entered" "0,1" newline bitfld.long 0x00 8. "STANDBYWFI,This bit gives software the visibility to track whether WFI mode have been entered" "0,1" group.long 0x410++0x13 line.long 0x00 "WKG_ENB_A_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_0 to MPU_IRQ_31)" bitfld.long 0x00 31. "WKG_ENB_FOR_INTR31,Wakeup enable for interrupt line MPU_IRQ_31" "0,1" bitfld.long 0x00 30. "WKG_ENB_FOR_INTR30,Wakeup enable for interrupt line MPU_IRQ_30" "0,1" bitfld.long 0x00 29. "WKG_ENB_FOR_INTR29,Wakeup enable for interrupt line MPU_IRQ_29" "0,1" bitfld.long 0x00 28. "WKG_ENB_FOR_INTR28,Wakeup enable for interrupt line MPU_IRQ_28" "0,1" bitfld.long 0x00 27. "WKG_ENB_FOR_INTR27,Wakeup enable for interrupt line MPU_IRQ_27" "0,1" newline bitfld.long 0x00 26. "WKG_ENB_FOR_INTR26,Wakeup enable for interrupt line MPU_IRQ_26" "0,1" bitfld.long 0x00 25. "WKG_ENB_FOR_INTR25,Wakeup enable for interrupt line MPU_IRQ_25" "0,1" bitfld.long 0x00 24. "WKG_ENB_FOR_INTR24,Wakeup enable for interrupt line MPU_IRQ_24" "0,1" bitfld.long 0x00 23. "WKG_ENB_FOR_INTR23,Wakeup enable for interrupt line MPU_IRQ_23" "0,1" bitfld.long 0x00 22. "WKG_ENB_FOR_INTR22,Wakeup enable for interrupt line MPU_IRQ_22" "0,1" newline bitfld.long 0x00 21. "WKG_ENB_FOR_INTR21,Wakeup enable for interrupt line MPU_IRQ_21" "0,1" bitfld.long 0x00 20. "WKG_ENB_FOR_INTR20,Wakeup enable for interrupt line MPU_IRQ_20" "0,1" bitfld.long 0x00 19. "WKG_ENB_FOR_INTR19,Wakeup enable for interrupt line MPU_IRQ_19" "0,1" bitfld.long 0x00 18. "WKG_ENB_FOR_INTR18,Wakeup enable for interrupt line MPU_IRQ_18" "0,1" bitfld.long 0x00 17. "WKG_ENB_FOR_INTR17,Wakeup enable for interrupt line MPU_IRQ_17" "0,1" newline bitfld.long 0x00 16. "WKG_ENB_FOR_INTR16,Wakeup enable for interrupt line MPU_IRQ_16" "0,1" bitfld.long 0x00 15. "WKG_ENB_FOR_INTR15,Wakeup enable for interrupt line MPU_IRQ_15" "0,1" bitfld.long 0x00 14. "WKG_ENB_FOR_INTR14,Wakeup enable for interrupt line MPU_IRQ_14" "0,1" bitfld.long 0x00 13. "WKG_ENB_FOR_INTR13,Wakeup enable for interrupt line MPU_IRQ_13" "0,1" bitfld.long 0x00 12. "WKG_ENB_FOR_INTR12,Wakeup enable for interrupt line MPU_IRQ_12" "0,1" newline bitfld.long 0x00 11. "WKG_ENB_FOR_INTR11,Wakeup enable for interrupt line MPU_IRQ_11" "0,1" bitfld.long 0x00 10. "WKG_ENB_FOR_INTR10,Wakeup enable for interrupt line MPU_IRQ_10" "0,1" bitfld.long 0x00 9. "WKG_ENB_FOR_INTR9,Wakeup enable for interrupt line MPU_IRQ_9" "0,1" bitfld.long 0x00 8. "WKG_ENB_FOR_INTR8,Wakeup enable for interrupt line MPU_IRQ_8" "0,1" bitfld.long 0x00 7. "WKG_ENB_FOR_INTR7,Wakeup enable for interrupt line MPU_IRQ_7" "0,1" newline bitfld.long 0x00 6. "WKG_ENB_FOR_INTR6,Wakeup enable for interrupt line MPU_IRQ_6" "0,1" bitfld.long 0x00 5. "WKG_ENB_FOR_INTR5,Wakeup enable for interrupt line MPU_IRQ_5" "0,1" bitfld.long 0x00 4. "WKG_ENB_FOR_INTR4,Wakeup enable for interrupt line MPU_IRQ_4" "0,1" bitfld.long 0x00 3. "WKG_ENB_FOR_INTR3,Wakeup enable for interrupt line MPU_IRQ_3" "0,1" bitfld.long 0x00 2. "WKG_ENB_FOR_INTR2,Wakeup enable for interrupt line MPU_IRQ_2" "0,1" newline bitfld.long 0x00 1. "WKG_ENB_FOR_INTR1,Wakeup enable for interrupt line MPU_IRQ_1" "0,1" bitfld.long 0x00 0. "WKG_ENB_FOR_INTR0,Wakeup enable for interrupt line MPU_IRQ_0" "0,1" line.long 0x04 "WKG_ENB_B_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_32 to MPU_IRQ_63)" bitfld.long 0x04 31. "WKG_ENB_FOR_INTR63,Wakeup enable for interrupt line MPU_IRQ_63" "0,1" bitfld.long 0x04 30. "WKG_ENB_FOR_INTR62,Wakeup enable for interrupt line MPU_IRQ_62" "0,1" bitfld.long 0x04 29. "WKG_ENB_FOR_INTR61,Wakeup enable for interrupt line MPU_IRQ_61" "0,1" bitfld.long 0x04 28. "WKG_ENB_FOR_INTR60,Wakeup enable for interrupt line MPU_IRQ_60" "0,1" bitfld.long 0x04 27. "WKG_ENB_FOR_INTR59,Wakeup enable for interrupt line MPU_IRQ_59" "0,1" newline bitfld.long 0x04 26. "WKG_ENB_FOR_INTR58,Wakeup enable for interrupt line MPU_IRQ_58" "0,1" bitfld.long 0x04 25. "WKG_ENB_FOR_INTR57,Wakeup enable for interrupt line MPU_IRQ_57" "0,1" bitfld.long 0x04 24. "WKG_ENB_FOR_INTR56,Wakeup enable for interrupt line MPU_IRQ_56" "0,1" bitfld.long 0x04 23. "WKG_ENB_FOR_INTR55,Wakeup enable for interrupt line MPU_IRQ_55" "0,1" bitfld.long 0x04 22. "WKG_ENB_FOR_INTR54,Wakeup enable for interrupt line MPU_IRQ_54" "0,1" newline bitfld.long 0x04 21. "WKG_ENB_FOR_INTR53,Wakeup enable for interrupt line MPU_IRQ_53" "0,1" bitfld.long 0x04 20. "WKG_ENB_FOR_INTR52,Wakeup enable for interrupt line MPU_IRQ_52" "0,1" bitfld.long 0x04 19. "WKG_ENB_FOR_INTR51,Wakeup enable for interrupt line MPU_IRQ_51" "0,1" bitfld.long 0x04 18. "WKG_ENB_FOR_INTR50,Wakeup enable for interrupt line MPU_IRQ_50" "0,1" bitfld.long 0x04 17. "WKG_ENB_FOR_INTR49,Wakeup enable for interrupt line MPU_IRQ_49" "0,1" newline bitfld.long 0x04 16. "WKG_ENB_FOR_INTR48,Wakeup enable for interrupt line MPU_IRQ_48" "0,1" bitfld.long 0x04 15. "WKG_ENB_FOR_INTR47,Wakeup enable for interrupt line MPU_IRQ_47" "0,1" bitfld.long 0x04 14. "WKG_ENB_FOR_INTR46,Wakeup enable for interrupt line MPU_IRQ_46" "0,1" bitfld.long 0x04 13. "WKG_ENB_FOR_INTR45,Wakeup enable for interrupt line MPU_IRQ_45" "0,1" bitfld.long 0x04 12. "WKG_ENB_FOR_INTR44,Wakeup enable for interrupt line MPU_IRQ_44" "0,1" newline bitfld.long 0x04 11. "WKG_ENB_FOR_INTR43,Wakeup enable for interrupt line MPU_IRQ_43" "0,1" bitfld.long 0x04 10. "WKG_ENB_FOR_INTR42,Wakeup enable for interrupt line MPU_IRQ_42" "0,1" bitfld.long 0x04 9. "WKG_ENB_FOR_INTR41,Wakeup enable for interrupt line MPU_IRQ_41" "0,1" bitfld.long 0x04 8. "WKG_ENB_FOR_INTR40,Wakeup enable for interrupt line MPU_IRQ_40" "0,1" bitfld.long 0x04 7. "WKG_ENB_FOR_INTR39,Wakeup enable for interrupt line MPU_IRQ_39" "0,1" newline bitfld.long 0x04 6. "WKG_ENB_FOR_INTR38,Wakeup enable for interrupt line MPU_IRQ_38" "0,1" bitfld.long 0x04 5. "WKG_ENB_FOR_INTR37,Wakeup enable for interrupt line MPU_IRQ_37" "0,1" bitfld.long 0x04 4. "WKG_ENB_FOR_INTR36,Wakeup enable for interrupt line MPU_IRQ_36" "0,1" bitfld.long 0x04 3. "WKG_ENB_FOR_INTR35,Wakeup enable for interrupt line MPU_IRQ_35" "0,1" bitfld.long 0x04 2. "WKG_ENB_FOR_INTR34,Wakeup enable for interrupt line MPU_IRQ_34" "0,1" newline bitfld.long 0x04 1. "WKG_ENB_FOR_INTR33,Wakeup enable for interrupt line MPU_IRQ_33" "0,1" bitfld.long 0x04 0. "WKG_ENB_FOR_INTR32,Wakeup enable for interrupt line MPU_IRQ_32" "0,1" line.long 0x08 "WKG_ENB_C_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_64 to MPU_IRQ_95)" bitfld.long 0x08 31. "WKG_ENB_FOR_INTR95,Wakeup enable for interrupt line MPU_IRQ_95" "0,1" bitfld.long 0x08 30. "WKG_ENB_FOR_INTR94,Wakeup enable for interrupt line MPU_IRQ_94" "0,1" bitfld.long 0x08 29. "WKG_ENB_FOR_INTR93,Wakeup enable for interrupt line MPU_IRQ_93" "0,1" bitfld.long 0x08 28. "WKG_ENB_FOR_INTR92,Wakeup enable for interrupt line MPU_IRQ_92" "0,1" bitfld.long 0x08 27. "WKG_ENB_FOR_INTR91,Wakeup enable for interrupt line MPU_IRQ_91" "0,1" newline bitfld.long 0x08 26. "WKG_ENB_FOR_INTR90,Wakeup enable for interrupt line MPU_IRQ_90" "0,1" bitfld.long 0x08 25. "WKG_ENB_FOR_INTR89,Wakeup enable for interrupt line MPU_IRQ_89" "0,1" bitfld.long 0x08 24. "WKG_ENB_FOR_INTR88,Wakeup enable for interrupt line MPU_IRQ_88" "0,1" bitfld.long 0x08 23. "WKG_ENB_FOR_INTR87,Wakeup enable for interrupt line MPU_IRQ_87" "0,1" bitfld.long 0x08 22. "WKG_ENB_FOR_INTR86,Wakeup enable for interrupt line MPU_IRQ_86" "0,1" newline bitfld.long 0x08 21. "WKG_ENB_FOR_INTR85,Wakeup enable for interrupt line MPU_IRQ_85" "0,1" bitfld.long 0x08 20. "WKG_ENB_FOR_INTR84,Wakeup enable for interrupt line MPU_IRQ_84" "0,1" bitfld.long 0x08 19. "WKG_ENB_FOR_INTR83,Wakeup enable for interrupt line MPU_IRQ_83" "0,1" bitfld.long 0x08 18. "WKG_ENB_FOR_INTR82,Wakeup enable for interrupt line MPU_IRQ_82" "0,1" bitfld.long 0x08 17. "WKG_ENB_FOR_INTR81,Wakeup enable for interrupt line MPU_IRQ_81" "0,1" newline bitfld.long 0x08 16. "WKG_ENB_FOR_INTR80,Wakeup enable for interrupt line MPU_IRQ_80" "0,1" bitfld.long 0x08 15. "WKG_ENB_FOR_INTR79,Wakeup enable for interrupt line MPU_IRQ_79" "0,1" bitfld.long 0x08 14. "WKG_ENB_FOR_INTR78,Wakeup enable for interrupt line MPU_IRQ_78" "0,1" bitfld.long 0x08 13. "WKG_ENB_FOR_INTR77,Wakeup enable for interrupt line MPU_IRQ_77" "0,1" bitfld.long 0x08 12. "WKG_ENB_FOR_INTR76,Wakeup enable for interrupt line MPU_IRQ_76" "0,1" newline bitfld.long 0x08 11. "WKG_ENB_FOR_INTR75,Wakeup enable for interrupt line MPU_IRQ_75" "0,1" bitfld.long 0x08 10. "WKG_ENB_FOR_INTR74,Wakeup enable for interrupt line MPU_IRQ_74" "0,1" bitfld.long 0x08 9. "WKG_ENB_FOR_INTR73,Wakeup enable for interrupt line MPU_IRQ_73" "0,1" bitfld.long 0x08 8. "WKG_ENB_FOR_INTR72,Wakeup enable for interrupt line MPU_IRQ_72" "0,1" bitfld.long 0x08 7. "WKG_ENB_FOR_INTR71,Wakeup enable for interrupt line MPU_IRQ_71" "0,1" newline bitfld.long 0x08 6. "WKG_ENB_FOR_INTR70,Wakeup enable for interrupt line MPU_IRQ_70" "0,1" bitfld.long 0x08 5. "WKG_ENB_FOR_INTR69,Wakeup enable for interrupt line MPU_IRQ_69" "0,1" bitfld.long 0x08 4. "WKG_ENB_FOR_INTR68,Wakeup enable for interrupt line MPU_IRQ_68" "0,1" bitfld.long 0x08 3. "WKG_ENB_FOR_INTR67,Wakeup enable for interrupt line MPU_IRQ_67" "0,1" bitfld.long 0x08 2. "WKG_ENB_FOR_INTR66,Wakeup enable for interrupt line MPU_IRQ_66" "0,1" newline bitfld.long 0x08 1. "WKG_ENB_FOR_INTR65,Wakeup enable for interrupt line MPU_IRQ_65" "0,1" bitfld.long 0x08 0. "WKG_ENB_FOR_INTR64,Wakeup enable for interrupt line MPU_IRQ_64" "0,1" line.long 0x0C "WKG_ENB_D_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_96 to MPU_IRQ_127)" bitfld.long 0x0C 31. "WKG_ENB_FOR_INTR127,Wakeup enable for interrupt line MPU_IRQ_127" "0,1" bitfld.long 0x0C 30. "WKG_ENB_FOR_INTR126,Wakeup enable for interrupt line MPU_IRQ_126" "0,1" bitfld.long 0x0C 29. "WKG_ENB_FOR_INTR125,Wakeup enable for interrupt line MPU_IRQ_125" "0,1" bitfld.long 0x0C 28. "WKG_ENB_FOR_INTR124,Wakeup enable for interrupt line MPU_IRQ_124" "0,1" bitfld.long 0x0C 27. "WKG_ENB_FOR_INTR123,Wakeup enable for interrupt line MPU_IRQ_123" "0,1" newline bitfld.long 0x0C 26. "WKG_ENB_FOR_INTR122,Wakeup enable for interrupt line MPU_IRQ_122" "0,1" bitfld.long 0x0C 25. "WKG_ENB_FOR_INTR121,Wakeup enable for interrupt line MPU_IRQ_121" "0,1" bitfld.long 0x0C 24. "WKG_ENB_FOR_INTR120,Wakeup enable for interrupt line MPU_IRQ_120" "0,1" bitfld.long 0x0C 23. "WKG_ENB_FOR_INTR119,Wakeup enable for interrupt line MPU_IRQ_119" "0,1" bitfld.long 0x0C 22. "WKG_ENB_FOR_INTR118,Wakeup enable for interrupt line MPU_IRQ_118" "0,1" newline bitfld.long 0x0C 21. "WKG_ENB_FOR_INTR117,Wakeup enable for interrupt line MPU_IRQ_117" "0,1" bitfld.long 0x0C 20. "WKG_ENB_FOR_INTR116,Wakeup enable for interrupt line MPU_IRQ_116" "0,1" bitfld.long 0x0C 19. "WKG_ENB_FOR_INTR115,Wakeup enable for interrupt line MPU_IRQ_115" "0,1" bitfld.long 0x0C 18. "WKG_ENB_FOR_INTR114,Wakeup enable for interrupt line MPU_IRQ_114" "0,1" bitfld.long 0x0C 17. "WKG_ENB_FOR_INTR113,Wakeup enable for interrupt line MPU_IRQ_113" "0,1" newline bitfld.long 0x0C 16. "WKG_ENB_FOR_INTR112,Wakeup enable for interrupt line MPU_IRQ_112" "0,1" bitfld.long 0x0C 15. "WKG_ENB_FOR_INTR111,Wakeup enable for interrupt line MPU_IRQ_111" "0,1" bitfld.long 0x0C 14. "WKG_ENB_FOR_INTR110,Wakeup enable for interrupt line MPU_IRQ_110" "0,1" bitfld.long 0x0C 13. "WKG_ENB_FOR_INTR109,Wakeup enable for interrupt line MPU_IRQ_109" "0,1" bitfld.long 0x0C 12. "WKG_ENB_FOR_INTR108,Wakeup enable for interrupt line MPU_IRQ_108" "0,1" newline bitfld.long 0x0C 11. "WKG_ENB_FOR_INTR107,Wakeup enable for interrupt line MPU_IRQ_107" "0,1" bitfld.long 0x0C 10. "WKG_ENB_FOR_INTR106,Wakeup enable for interrupt line MPU_IRQ_106" "0,1" bitfld.long 0x0C 9. "WKG_ENB_FOR_INTR105,Wakeup enable for interrupt line MPU_IRQ_105" "0,1" bitfld.long 0x0C 8. "WKG_ENB_FOR_INTR104,Wakeup enable for interrupt line MPU_IRQ_104" "0,1" bitfld.long 0x0C 7. "WKG_ENB_FOR_INTR103,Wakeup enable for interrupt line MPU_IRQ_103" "0,1" newline bitfld.long 0x0C 6. "WKG_ENB_FOR_INTR102,Wakeup enable for interrupt line MPU_IRQ_102" "0,1" bitfld.long 0x0C 5. "WKG_ENB_FOR_INTR101,Wakeup enable for interrupt line MPU_IRQ_101" "0,1" bitfld.long 0x0C 4. "WKG_ENB_FOR_INTR100,Wakeup enable for interrupt line MPU_IRQ_100" "0,1" bitfld.long 0x0C 3. "WKG_ENB_FOR_INTR99,Wakeup enable for interrupt line MPU_IRQ_99" "0,1" bitfld.long 0x0C 2. "WKG_ENB_FOR_INTR98,Wakeup enable for interrupt line MPU_IRQ_98" "0,1" newline bitfld.long 0x0C 1. "WKG_ENB_FOR_INTR97,Wakeup enable for interrupt line MPU_IRQ_97" "0,1" bitfld.long 0x0C 0. "WKG_ENB_FOR_INTR96,Wakeup enable for interrupt line MPU_IRQ_96" "0,1" line.long 0x10 "WKG_ENB_E_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_128 to MPU_IRQ_159)" bitfld.long 0x10 31. "WKG_ENB_FOR_INTR159,Wakeup enable for interrupt line MPU_IRQ_159" "0,1" bitfld.long 0x10 30. "WKG_ENB_FOR_INTR158,Wakeup enable for interrupt line MPU_IRQ_158" "0,1" bitfld.long 0x10 29. "WKG_ENB_FOR_INTR157,Wakeup enable for interrupt line MPU_IRQ_157" "0,1" bitfld.long 0x10 28. "WKG_ENB_FOR_INTR156,Wakeup enable for interrupt line MPU_IRQ_156" "0,1" bitfld.long 0x10 27. "WKG_ENB_FOR_INTR155,Wakeup enable for interrupt line MPU_IRQ_155" "0,1" newline bitfld.long 0x10 26. "WKG_ENB_FOR_INTR154,Wakeup enable for interrupt line MPU_IRQ_154" "0,1" bitfld.long 0x10 25. "WKG_ENB_FOR_INTR153,Wakeup enable for interrupt line MPU_IRQ_153" "0,1" bitfld.long 0x10 24. "WKG_ENB_FOR_INTR152,Wakeup enable for interrupt line MPU_IRQ_152" "0,1" bitfld.long 0x10 23. "WKG_ENB_FOR_INTR151,Wakeup enable for interrupt line MPU_IRQ_151" "0,1" bitfld.long 0x10 22. "WKG_ENB_FOR_INTR150,Wakeup enable for interrupt line MPU_IRQ_150" "0,1" newline bitfld.long 0x10 21. "WKG_ENB_FOR_INTR149,Wakeup enable for interrupt line MPU_IRQ_149" "0,1" bitfld.long 0x10 20. "WKG_ENB_FOR_INTR148,Wakeup enable for interrupt line MPU_IRQ_148" "0,1" bitfld.long 0x10 19. "WKG_ENB_FOR_INTR147,Wakeup enable for interrupt line MPU_IRQ_147" "0,1" bitfld.long 0x10 18. "WKG_ENB_FOR_INTR146,Wakeup enable for interrupt line MPU_IRQ_146" "0,1" bitfld.long 0x10 17. "WKG_ENB_FOR_INTR145,Wakeup enable for interrupt line MPU_IRQ_145" "0,1" newline bitfld.long 0x10 16. "WKG_ENB_FOR_INTR144,Wakeup enable for interrupt line MPU_IRQ_144" "0,1" bitfld.long 0x10 15. "WKG_ENB_FOR_INTR143,Wakeup enable for interrupt line MPU_IRQ_143" "0,1" bitfld.long 0x10 14. "WKG_ENB_FOR_INTR142,Wakeup enable for interrupt line MPU_IRQ_142" "0,1" bitfld.long 0x10 13. "WKG_ENB_FOR_INTR141,Wakeup enable for interrupt line MPU_IRQ_141" "0,1" bitfld.long 0x10 12. "WKG_ENB_FOR_INTR140,Wakeup enable for interrupt line MPU_IRQ_140" "0,1" newline bitfld.long 0x10 11. "WKG_ENB_FOR_INTR139,Wakeup enable for interrupt line MPU_IRQ_139" "0,1" bitfld.long 0x10 10. "WKG_ENB_FOR_INTR138,Wakeup enable for interrupt line MPU_IRQ_138" "0,1" bitfld.long 0x10 9. "WKG_ENB_FOR_INTR137,Wakeup enable for interrupt line MPU_IRQ_137" "0,1" bitfld.long 0x10 8. "WKG_ENB_FOR_INTR136,Wakeup enable for interrupt line MPU_IRQ_136" "0,1" bitfld.long 0x10 7. "WKG_ENB_FOR_INTR135,Wakeup enable for interrupt line MPU_IRQ_135" "0,1" newline bitfld.long 0x10 6. "WKG_ENB_FOR_INTR134,Wakeup enable for interrupt line MPU_IRQ_134" "0,1" bitfld.long 0x10 5. "WKG_ENB_FOR_INTR133,Wakeup enable for interrupt line MPU_IRQ_133" "0,1" bitfld.long 0x10 4. "WKG_ENB_FOR_INTR132,Wakeup enable for interrupt line MPU_IRQ_132" "0,1" bitfld.long 0x10 3. "WKG_ENB_FOR_INTR131,Wakeup enable for interrupt line MPU_IRQ_131" "0,1" bitfld.long 0x10 2. "WKG_ENB_FOR_INTR130,Wakeup enable for interrupt line MPU_IRQ_130" "0,1" newline bitfld.long 0x10 1. "WKG_ENB_FOR_INTR129,Wakeup enable for interrupt line MPU_IRQ_129" "0,1" bitfld.long 0x10 0. "WKG_ENB_FOR_INTR128,Wakeup enable for interrupt line MPU_IRQ_128" "0,1" group.long 0x800++0x0F line.long 0x00 "AUX_CORE_BOOT_0,This register is used by the ROM code and OS during SMP boot" line.long 0x04 "AUX_CORE_BOOT_1,This register is used by the ROM code and OS during SMP boot" line.long 0x08 "STM_HWEVENTS_INV,Gives programmable control of inverting or not inverting MPUHWDBGOUT[31:0] going to HWEVENTS[31:0] input of CS_STM" bitfld.long 0x08 31. "STM_HWEVENT_INV_ 31,Polarity inversion control for MPUHWDBGOUT31 signal" "0,1" bitfld.long 0x08 30. "STM_HWEVENT_INV_ 30,Polarity inversion control for MPUHWDBGOUT30 signal" "0,1" bitfld.long 0x08 29. "STM_HWEVENT_INV_ 29,Polarity inversion control for MPUHWDBGOUT29 signal" "0,1" bitfld.long 0x08 28. "STM_HWEVENT_INV_ 28,Polarity inversion control for MPUHWDBGOUT28 signal" "0,1" bitfld.long 0x08 27. "STM_HWEVENT_INV_ 27,Polarity inversion control for MPUHWDBGOUT27 signal" "0,1" newline bitfld.long 0x08 26. "STM_HWEVENT_INV_ 26,Polarity inversion control for MPUHWDBGOUT26 signal" "0,1" bitfld.long 0x08 25. "STM_HWEVENT_INV_ 25,Polarity inversion control for MPUHWDBGOUT25 signal" "0,1" bitfld.long 0x08 24. "STM_HWEVENT_INV_ 24,Polarity inversion control for MPUHWDBGOUT24 signal" "0,1" bitfld.long 0x08 23. "STM_HWEVENT_INV_ 23,Polarity inversion control for MPUHWDBGOUT23 signal" "0,1" bitfld.long 0x08 22. "STM_HWEVENT_INV_ 22,Polarity inversion control for MPUHWDBGOUT22 signal" "0,1" newline bitfld.long 0x08 21. "STM_HWEVENT_INV_ 21,Polarity inversion control for MPUHWDBGOUT21 signal" "0,1" bitfld.long 0x08 20. "STM_HWEVENT_INV_ 20,Polarity inversion control for MPUHWDBGOUT20 signal" "0,1" bitfld.long 0x08 19. "STM_HWEVENT_INV_ 19,Polarity inversion control for MPUHWDBGOUT19 signal" "0,1" bitfld.long 0x08 18. "STM_HWEVENT_INV_ 18,Polarity inversion control for MPUHWDBGOUT18 signal" "0,1" bitfld.long 0x08 17. "STM_HWEVENT_INV_ 17,Polarity inversion control for MPUHWDBGOUT17 signal" "0,1" newline bitfld.long 0x08 16. "STM_HWEVENT_INV_ 16,Polarity inversion control for MPUHWDBGOUT16 signal" "0,1" bitfld.long 0x08 15. "STM_HWEVENT_INV_ 15,Polarity inversion control for MPUHWDBGOUT15 signal" "0,1" bitfld.long 0x08 14. "STM_HWEVENT_INV_ 14,Polarity inversion control for MPUHWDBGOUT14 signal" "0,1" bitfld.long 0x08 13. "STM_HWEVENT_INV_ 13,Polarity inversion control for MPUHWDBGOUT13 signal" "0,1" bitfld.long 0x08 12. "STM_HWEVENT_INV_ 12,Polarity inversion control for MPUHWDBGOUT12 signal" "0,1" newline bitfld.long 0x08 11. "STM_HWEVENT_INV_ 11,Polarity inversion control for MPUHWDBGOUT11 signal" "0,1" bitfld.long 0x08 10. "STM_HWEVENT_INV_ 10,Polarity inversion control for MPUHWDBGOUT10 signal" "0,1" bitfld.long 0x08 9. "STM_HWEVENT_INV_ 9,Polarity inversion control for MPUHWDBGOUT9 signal" "0,1" bitfld.long 0x08 8. "STM_HWEVENT_INV_ 8,Polarity inversion control for MPUHWDBGOUT8 signal" "0,1" bitfld.long 0x08 7. "STM_HWEVENT_INV_ 7,Polarity inversion control for MPUHWDBGOUT7 signal" "0,1" newline bitfld.long 0x08 6. "STM_HWEVENT_INV_ 6,Polarity inversion control for MPUHWDBGOUT6 signal" "0,1" bitfld.long 0x08 5. "STM_HWEVENT_INV_ 5,Polarity inversion control for MPUHWDBGOUT5 signal" "0,1" bitfld.long 0x08 4. "STM_HWEVENT_INV_ 4,Polarity inversion control for MPUHWDBGOUT4 signal" "0,1" bitfld.long 0x08 3. "STM_HWEVENT_INV_ 3,Polarity inversion control for MPUHWDBGOUT3 signal" "0,1" bitfld.long 0x08 2. "STM_HWEVENT_INV_ 2,Polarity inversion control for MPUHWDBGOUT2 signal" "0,1" newline bitfld.long 0x08 1. "STM_HWEVENT_INV_ 1,Polarity inversion control for MPUHWDBGOUT1 signal" "0,1" bitfld.long 0x08 0. "STM_HWEVENT_INV_0,Polarity inversion control for MPUHWDBGOUT0 signal" "0,1" line.long 0x0C "AMBA_IF_MODE,This register controls the MPU core interface tie-off values for BI. BO. BCM and SBD" bitfld.long 0x0C 5. "ES2_PM_MODE,Enables OFF mode behavior" "0,1" bitfld.long 0x0C 4. "APB_FENCE_EN,Enables APB fencing logic" "0,1" bitfld.long 0x0C 3. "BI,BROADCASTINNER input of MPU core" "0,1" bitfld.long 0x0C 2. "BO,BROADCASTOUTER input of MPU core" "0,1" bitfld.long 0x0C 1. "BCM,BROADCASTMAINTENANCE input of MPU core" "0,1" newline bitfld.long 0x0C 0. "SBD,SYSBARDISABLE input of MPU core" "0,1" rgroup.long 0xC08++0x07 line.long 0x00 "TIMESTAMPCYCLELO,Lower 32 bits of the 48-bit timestamp counter value" line.long 0x04 "TIMESTAMPCYCLEHI,Higher 16 bits of the 48-bit timestamp counter value" hexmask.long.word 0x04 0.--15. 1. "COUNTER_47_32,Higher 16 bits of the timestamp counter value" tree.end tree.end tree.open "Dynamic_Memory_Manager" tree "DMM" base ad:0x4E000000 repeat 3. (list 0. 1. 2. ) tree "Channel_$1" group.long 0x40++0x03 line.long 0x00 "DMM_LISA_MAP_i_0,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. "SYS_ADDR,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. "SYS_SIZE,DMM system section size for view mapping i" "SYS_SIZE_0,SYS_SIZE_1,SYS_SIZE_2,SYS_SIZE_3,SYS_SIZE_4,SYS_SIZE_5,SYS_SIZE_6,SYS_SIZE_7" bitfld.long 0x00 18.--19. "SDRC_INTL,SDRAM controller interleaving mode" "0,1,2,3" bitfld.long 0x00 16.--17. "SDRC_ADDRSPC,SDRAM controller address space for view mapping i" "0,1,2,3" bitfld.long 0x00 8.--9. "SDRC_MAP,SDRAM controller mapping for view mapping i" "0,1,2,3" newline hexmask.long.byte 0x00 0.--7. 1. "SDRC_ADDR,SDRAM controller address MSB for view mapping i" group.long 0x504++0x0B line.long 0x00 "DMM_PAT_AREA_i_0,Area definition for DMM physical address translator n = 0 for the area register of the first engine. n = 1 for the area register of the second engine" hexmask.long.byte 0x00 24.--31. 1. "Y1,Y-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. "X1,X-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x00 8.--15. 1. "Y0,Y-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x00 0.--7. 1. "X0,X-coordinate of the top-left corner of the PAT area for engine n" line.long 0x04 "DMM_PAT_CTRL_i_0,DMM physical address translator control register n = 0 for the control register of the first engine. n = 1 for the control register of the second engine" bitfld.long 0x04 28.--31. "INITIATOR,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16. "SYNC,DMM PAT table reload synchronization for engine n" "SYNC_0,SYNC_1" bitfld.long 0x04 4.--6. "DIRECTION,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. "START,Starting a PAT table refill with engine n" "0,1" line.long 0x08 "DMM_PAT_DATA_i_0,Physical address of the current table refill entry data n = 0 for the data register of the first engine. n = 1 for the data register of the second engine" hexmask.long 0x08 4.--31. 1. "ADDR,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x500++0x03 line.long 0x00 "DMM_PAT_DESCR_i_0,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine. n = 1 for the descriptor register of the second engine" hexmask.long 0x00 4.--31. 1. "ADDR,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4C0++0x03 line.long 0x00 "DMM_PAT_STATUS_i_0,Status register for each refill engine n = 0 for the first engine status register. n = 1 for the second engine status register" hexmask.long.word 0x00 16.--24. 1. "CNT,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. "ERROR,Error happened in engine n" "ERROR_0_r,ERROR_1_r,ERROR_2_r,?,ERROR_4_r,?,?,?,ERROR_8_r,?,?,?,?,?,?,?,ERROR_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,ERROR_32_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 7. "BYPASSED,Engine n is bypassed" "0,1" bitfld.long 0x00 4. "LINKED,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x00 3. "DONE,Area reloading finished for engine n" "0,1" newline bitfld.long 0x00 2. "RUN,Area currently reloading for engine n" "0,1" bitfld.long 0x00 1. "VALID,Valid area description for engine n" "0,1" bitfld.long 0x00 0. "READY,Area registers ready for engine n" "0,1" group.long 0x440++0x03 line.long 0x00 "DMM_PAT_VIEW_MAP_i_0,PAT view mapping register" bitfld.long 0x00 31. "ACCESS_PAGE,Kind of access for this page mode container in view mapping i - DIRECT" "ACCESS_PAGE_0,ACCESS_PAGE_1" bitfld.long 0x00 24.--26. "CONT_PAGE,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. "ACCESS_32,Kind of access for this 32-bit mode container in view mapping i - DIRECT" "ACCESS_32_0,ACCESS_32_1" bitfld.long 0x00 16.--18. "CONT_32,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. "ACCESS_16,Kind of access for this 16-bit mode container in view mapping i - DIRECT" "ACCESS_16_0,ACCESS_16_1" newline bitfld.long 0x00 8.--10. "CONT_16,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "ACCESS_8,Kind of access for this 8-bit mode container in view mapping i - DIRECT" "ACCESS_8_0,ACCESS_8_1" bitfld.long 0x00 0.--2. "CONT_8,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" group.long 0x620++0x03 line.long 0x00 "DMM_PEG_PRIO_k_0,DMM PEG Priority register" bitfld.long 0x00 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" newline bitfld.long 0x00 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" newline bitfld.long 0x00 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" tree.end repeat.end tree "Channel_3" group.long 0x4C++0x03 line.long 0x00 "DMM_LISA_MAP_i_3,DMM memory mapping register" hexmask.long.byte 0x00 24.--31. 1. "SYS_ADDR,DMM system section address MSB for view mapping i" bitfld.long 0x00 20.--22. "SYS_SIZE,DMM system section size for view mapping i" "SYS_SIZE_0,SYS_SIZE_1,SYS_SIZE_2,SYS_SIZE_3,SYS_SIZE_4,SYS_SIZE_5,SYS_SIZE_6,SYS_SIZE_7" bitfld.long 0x00 18.--19. "SDRC_INTL,SDRAM controller interleaving mode" "0,1,2,3" bitfld.long 0x00 16.--17. "SDRC_ADDRSPC,SDRAM controller address space for view mapping i" "0,1,2,3" bitfld.long 0x00 8.--9. "SDRC_MAP,SDRAM controller mapping for view mapping i" "0,1,2,3" newline hexmask.long.byte 0x00 0.--7. 1. "SDRC_ADDR,SDRAM controller address MSB for view mapping i" group.long 0x534++0x0B line.long 0x00 "DMM_PAT_AREA_i_3,Area definition for DMM physical address translator n = 0 for the area register of the first engine. n = 1 for the area register of the second engine" hexmask.long.byte 0x00 24.--31. 1. "Y1,Y-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x00 16.--23. 1. "X1,X-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x00 8.--15. 1. "Y0,Y-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x00 0.--7. 1. "X0,X-coordinate of the top-left corner of the PAT area for engine n" line.long 0x04 "DMM_PAT_CTRL_i_3,DMM physical address translator control register n = 0 for the control register of the first engine. n = 1 for the control register of the second engine" bitfld.long 0x04 28.--31. "INITIATOR,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16. "SYNC,DMM PAT table reload synchronization for engine n" "SYNC_0,SYNC_1" bitfld.long 0x04 4.--6. "DIRECTION,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. "START,Starting a PAT table refill with engine n" "0,1" line.long 0x08 "DMM_PAT_DATA_i_3,Physical address of the current table refill entry data n = 0 for the data register of the first engine. n = 1 for the data register of the second engine" hexmask.long 0x08 4.--31. 1. "ADDR,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.long 0x530++0x03 line.long 0x00 "DMM_PAT_DESCR_i_3,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine. n = 1 for the descriptor register of the second engine" hexmask.long 0x00 4.--31. 1. "ADDR,Physical address of the next table refill descriptor of engine n" rgroup.long 0x4CC++0x03 line.long 0x00 "DMM_PAT_STATUS_i_3,Status register for each refill engine n = 0 for the first engine status register. n = 1 for the second engine status register" hexmask.long.word 0x00 16.--24. 1. "CNT,Counter of remaining lines to reload for engine n" bitfld.long 0x00 10.--15. "ERROR,Error happened in engine n" "ERROR_0_r,ERROR_1_r,ERROR_2_r,?,ERROR_4_r,?,?,?,ERROR_8_r,?,?,?,?,?,?,?,ERROR_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,ERROR_32_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 7. "BYPASSED,Engine n is bypassed" "0,1" bitfld.long 0x00 4. "LINKED,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x00 3. "DONE,Area reloading finished for engine n" "0,1" newline bitfld.long 0x00 2. "RUN,Area currently reloading for engine n" "0,1" bitfld.long 0x00 1. "VALID,Valid area description for engine n" "0,1" bitfld.long 0x00 0. "READY,Area registers ready for engine n" "0,1" group.long 0x44C++0x03 line.long 0x00 "DMM_PAT_VIEW_MAP_i_3,PAT view mapping register" bitfld.long 0x00 31. "ACCESS_PAGE,Kind of access for this page mode container in view mapping i - DIRECT" "ACCESS_PAGE_0,ACCESS_PAGE_1" bitfld.long 0x00 24.--26. "CONT_PAGE,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23. "ACCESS_32,Kind of access for this 32-bit mode container in view mapping i - DIRECT" "ACCESS_32_0,ACCESS_32_1" bitfld.long 0x00 16.--18. "CONT_32,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. "ACCESS_16,Kind of access for this 16-bit mode container in view mapping i - DIRECT" "ACCESS_16_0,ACCESS_16_1" newline bitfld.long 0x00 8.--10. "CONT_16,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. "ACCESS_8,Kind of access for this 8-bit mode container in view mapping i - DIRECT" "ACCESS_8_0,ACCESS_8_1" bitfld.long 0x00 0.--2. "CONT_8,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" repeat 5. (list 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 ) group.long ($2+0x62C)++0x03 line.long 0x00 "DMM_PEG_PRIO_k_$1,DMM PEG Priority register" bitfld.long 0x00 31. "W7,Write-enable for P7 bit field - KEEP" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--30. "P7,Priority for initiator ConnID = 8 x k + 7" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 27. "W6,Write-enable for P6 bit field - KEEP" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--26. "P6,Priority for initiator ConnID = 8 x k + 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "W5,Write-enable for P5 bit field - KEEP" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--22. "P5,Priority for initiator ConnID = 8 x k + 5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. "W4,Write-enable for P4 bit field - KEEP" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--18. "P4,Priority for initiator ConnID = 8 x k + 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "W3,Write-enable for P3 bit field - KEEP" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--14. "P3,Priority for initiator ConnID = 8 x k + 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. "W2,Write-enable for P2 bit field - KEEP" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--10. "P2,Priority for initiator ConnID = 8 x k + 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "W1,Write-enable for P1 bit field - KEEP" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--6. "P1,Priority for initiator ConnID = 8 x k + 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. "W0,Write-enable for P0 bit field - KEEP" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--2. "P0,Priority for initiator ConnID = 8 x k" "0,1,2,3,4,5,6,7" repeat.end tree.end group.long 0x20++0x03 line.long 0x00 "DMM_EMERGENCY,DMM memory mapping register" bitfld.long 0x00 16.--20. "WEIGHT,Weight for the LISA arbitration when any bit of the vector Mflag[63:0] is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 1.--15. 1. "Reserved,Reserved" bitfld.long 0x00 0. "ENABLE," "?,ENABLE_1" rgroup.long 0x04++0x07 line.long 0x00 "DMM_HWINFO,DMM hardware configuration" bitfld.long 0x00 16.--19. "ROBIN_CNT,Number of ROBIN in the DMM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "ELLA_CNT,Number of ELLA in the DMM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "TILER_CNT,Number of TILER in the DMM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DMM_LISA_HWINFO,DMM hardware configuration for LISA" bitfld.long 0x04 8.--11. "SDRC_CNT,Number of attached SDRAM controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--4. "SECTION_CNT,Number of DMM sections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C++0x03 line.long 0x00 "DMM_LISA_LOCK,DMM memory mapping lock" bitfld.long 0x00 0. "LOCK,DMM lock map - UNLOCKED" "LOCK_0_r,LOCK_1_w" group.long 0x410++0x03 line.long 0x00 "DMM_PAT_CONFIG,This is the PAT configuration register aimed at defining the major PAT configuration of each refill engine" bitfld.long 0x00 3. "MODE3,Mode of refill engine" "MODE3_0,MODE3_1" bitfld.long 0x00 2. "MODE2,Mode of refill engine" "MODE2_0,MODE2_1" bitfld.long 0x00 1. "MODE1,Mode of refill engine" "MODE1_0,MODE1_1" bitfld.long 0x00 0. "MODE0,Mode of refill engine" "MODE0_0,MODE0_1" rgroup.long 0x40C++0x03 line.long 0x00 "DMM_PAT_GEOMETRY,PAT geometry-related settings" bitfld.long 0x00 24.--26. "CONT_HGHT,Container height in pages - 32" "?,CONT_HGHT_1_r,CONT_HGHT_2_r,?,CONT_HGHT_4_r,?,?,?" bitfld.long 0x00 16.--19. "CONT_WDTH,Container width in pages - 64" "?,?,CONT_WDTH_2_r,?,CONT_WDTH_4_r,?,?,?,CONT_WDTH_8_r,?,?,?,?,?,?,?" bitfld.long 0x00 8.--13. "ADDR_RANGE,PAT output physical address range - 128MB" "?,ADDR_RANGE_1_r,ADDR_RANGE_2_r,?,ADDR_RANGE_4_r,?,?,?,ADDR_RANGE_8_r,?,?,?,?,?,?,?,ADDR_RANGE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,ADDR_RANGE_32_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--4. "PAGE_SZ,Page size in 4-kiB granularity - 4KB" "?,PAGE_SZ_1_r,?,?,PAGE_SZ_4_r,?,?,?,?,?,?,?,?,?,?,?,PAGE_SZ_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rgroup.long 0x408++0x03 line.long 0x00 "DMM_PAT_HWINFO,DMM hardware configuration for PAT" bitfld.long 0x00 24.--28. "ENGINE_CNT,Number of PAT refill engines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "LUT_CNT,Number of PAT LUT for page-grained physical address translation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. "VIEW_MAP_CNT,Number of internal PAT view mappings" "?,VIEW_MAP_CNT_1_r,VIEW_MAP_CNT_2_r,?,VIEW_MAP_CNT_4_r,?,?,?,VIEW_MAP_CNT_8_r,?,?,?,?,?,?,?" hexmask.long.byte 0x00 0.--6. 1. "VIEW_CNT,Number of PAT view entries - 1" group.long 0x478++0x03 line.long 0x00 "DMM_PAT_IRQ_EOI,PAT end of interrupt" bitfld.long 0x00 0. "EOI,End of PAT interrupt - ACK" "EOI_0,?" group.long 0x4B0++0x03 line.long 0x00 "DMM_PAT_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x00 31. "ERR_LUT_MISS3,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS3_0_r,ERR_LUT_MISS3_1_r" bitfld.long 0x00 30. "ERR_UPD_DATA3,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA3_0_r,ERR_UPD_DATA3_1_r" bitfld.long 0x00 29. "ERR_UPD_CTRL3,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL3_0_r,ERR_UPD_CTRL3_1_r" bitfld.long 0x00 28. "ERR_UPD_AREA3,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA3_0_r,ERR_UPD_AREA3_1_r" newline bitfld.long 0x00 27. "ERR_INV_DATA3,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA3_0_r,ERR_INV_DATA3_1_r" bitfld.long 0x00 26. "ERR_INV_DSC3,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC3_0_r,ERR_INV_DSC3_1_r" bitfld.long 0x00 25. "FILL_LST3,End of refill interrupt source mask for the last descriptior in area" "FILL_LST3_0_r,FILL_LST3_1_r" bitfld.long 0x00 24. "FILL_DSC3,End of refill interrupt source mask for any descriptior in area" "FILL_DSC3_0_r,FILL_DSC3_1_r" newline bitfld.long 0x00 23. "ERR_LUT_MISS2,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS2_0_r,ERR_LUT_MISS2_1_r" bitfld.long 0x00 22. "ERR_UPD_DATA2,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA2_0_r,ERR_UPD_DATA2_1_r" bitfld.long 0x00 21. "ERR_UPD_CTRL2,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL2_0_r,ERR_UPD_CTRL2_1_r" bitfld.long 0x00 20. "ERR_UPD_AREA2,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA2_0_r,ERR_UPD_AREA2_1_r" newline bitfld.long 0x00 19. "ERR_INV_DATA2,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA2_0_r,ERR_INV_DATA2_1_r" bitfld.long 0x00 18. "ERR_INV_DSC2,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC2_0_r,ERR_INV_DSC2_1_r" bitfld.long 0x00 17. "FILL_LST2,End of refill interrupt source mask for the last descriptior in area" "FILL_LST2_0_r,FILL_LST2_1_r" bitfld.long 0x00 16. "FILL_DSC2,End of refill interrupt source mask for any descriptior in area" "FILL_DSC2_0_r,FILL_DSC2_1_r" newline bitfld.long 0x00 15. "ERR_LUT_MISS1,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS1_0_r,ERR_LUT_MISS1_1_r" bitfld.long 0x00 14. "ERR_UPD_DATA1,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA1_0_r,ERR_UPD_DATA1_1_r" bitfld.long 0x00 13. "ERR_UPD_CTRL1,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL1_0_r,ERR_UPD_CTRL1_1_r" bitfld.long 0x00 12. "ERR_UPD_AREA1,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA1_0_r,ERR_UPD_AREA1_1_r" newline bitfld.long 0x00 11. "ERR_INV_DATA1,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA1_0_r,ERR_INV_DATA1_1_r" bitfld.long 0x00 10. "ERR_INV_DSC1,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC1_0_r,ERR_INV_DSC1_1_r" bitfld.long 0x00 9. "FILL_LST1,End of refill interrupt source mask for the last descriptior in area" "FILL_LST1_0_r,FILL_LST1_1_r" bitfld.long 0x00 8. "FILL_DSC1,End of refill interrupt source mask for any descriptior in area" "FILL_DSC1_0_r,FILL_DSC1_1_r" newline bitfld.long 0x00 7. "ERR_LUT_MISS0,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS0_0_r,ERR_LUT_MISS0_1_r" bitfld.long 0x00 6. "ERR_UPD_DATA0,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA0_0_r,ERR_UPD_DATA0_1_r" bitfld.long 0x00 5. "ERR_UPD_CTRL0,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL0_0_r,ERR_UPD_CTRL0_1_r" bitfld.long 0x00 4. "ERR_UPD_AREA0,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA0_0_r,ERR_UPD_AREA0_1_r" newline bitfld.long 0x00 3. "ERR_INV_DATA0,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA0_0_r,ERR_INV_DATA0_1_r" bitfld.long 0x00 2. "ERR_INV_DSC0,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC0_0_r,ERR_INV_DSC0_1_r" bitfld.long 0x00 1. "FILL_LST0,End of refill interrupt source mask for the last descriptior in area" "FILL_LST0_0_r,FILL_LST0_1_r" bitfld.long 0x00 0. "FILL_DSC0,End of refill interrupt source mask for any descriptior in area" "FILL_DSC0_0_r,FILL_DSC0_1_r" group.long 0x4A0++0x03 line.long 0x00 "DMM_PAT_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x00 31. "ERR_LUT_MISS3,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS3_0_r,ERR_LUT_MISS3_1_r" bitfld.long 0x00 30. "ERR_UPD_DATA3,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA3_0_r,ERR_UPD_DATA3_1_r" bitfld.long 0x00 29. "ERR_UPD_CTRL3,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL3_0_r,ERR_UPD_CTRL3_1_r" bitfld.long 0x00 28. "ERR_UPD_AREA3,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA3_0_r,ERR_UPD_AREA3_1_r" newline bitfld.long 0x00 27. "ERR_INV_DATA3,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA3_0_r,ERR_INV_DATA3_1_r" bitfld.long 0x00 26. "ERR_INV_DSC3,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC3_0_r,ERR_INV_DSC3_1_r" bitfld.long 0x00 25. "FILL_LST3,End of refill interrupt source mask for the last descriptior in area" "FILL_LST3_0_r,FILL_LST3_1_r" bitfld.long 0x00 24. "FILL_DSC3,End of refill interrupt source mask for any descriptior in area" "FILL_DSC3_0_r,FILL_DSC3_1_r" newline bitfld.long 0x00 23. "ERR_LUT_MISS2,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS2_0_r,ERR_LUT_MISS2_1_r" bitfld.long 0x00 22. "ERR_UPD_DATA2,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA2_0_r,ERR_UPD_DATA2_1_r" bitfld.long 0x00 21. "ERR_UPD_CTRL2,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL2_0_r,ERR_UPD_CTRL2_1_r" bitfld.long 0x00 20. "ERR_UPD_AREA2,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA2_0_r,ERR_UPD_AREA2_1_r" newline bitfld.long 0x00 19. "ERR_INV_DATA2,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA2_0_r,ERR_INV_DATA2_1_r" bitfld.long 0x00 18. "ERR_INV_DSC2,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC2_0_r,ERR_INV_DSC2_1_r" bitfld.long 0x00 17. "FILL_LST2,End of refill interrupt source mask for the last descriptior in area" "FILL_LST2_0_r,FILL_LST2_1_r" bitfld.long 0x00 16. "FILL_DSC2,End of refill interrupt source mask for any descriptior in area" "FILL_DSC2_0_r,FILL_DSC2_1_r" newline bitfld.long 0x00 15. "ERR_LUT_MISS1,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS1_0_r,ERR_LUT_MISS1_1_r" bitfld.long 0x00 14. "ERR_UPD_DATA1,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA1_0_r,ERR_UPD_DATA1_1_r" bitfld.long 0x00 13. "ERR_UPD_CTRL1,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL1_0_r,ERR_UPD_CTRL1_1_r" bitfld.long 0x00 12. "ERR_UPD_AREA1,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA1_0_r,ERR_UPD_AREA1_1_r" newline bitfld.long 0x00 11. "ERR_INV_DATA1,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA1_0_r,ERR_INV_DATA1_1_r" bitfld.long 0x00 10. "ERR_INV_DSC1,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC1_0_r,ERR_INV_DSC1_1_r" bitfld.long 0x00 9. "FILL_LST1,End of refill interrupt source mask for the last descriptior in area" "FILL_LST1_0_r,FILL_LST1_1_r" bitfld.long 0x00 8. "FILL_DSC1,End of refill interrupt source mask for any descriptior in area" "FILL_DSC1_0_r,FILL_DSC1_1_r" newline bitfld.long 0x00 7. "ERR_LUT_MISS0,Unexpected access to a yet-to-be-refilled area interrupt source mask for area" "ERR_LUT_MISS0_0_r,ERR_LUT_MISS0_1_r" bitfld.long 0x00 6. "ERR_UPD_DATA0,Unexpected data register update whilst refilling interrupt source mask for area" "ERR_UPD_DATA0_0_r,ERR_UPD_DATA0_1_r" bitfld.long 0x00 5. "ERR_UPD_CTRL0,Unexpected control register update whilst refilling interrupt source mask for area" "ERR_UPD_CTRL0_0_r,ERR_UPD_CTRL0_1_r" bitfld.long 0x00 4. "ERR_UPD_AREA0,Unexpected area register update whilst refilling interrupt source mask for area" "ERR_UPD_AREA0_0_r,ERR_UPD_AREA0_1_r" newline bitfld.long 0x00 3. "ERR_INV_DATA0,Invalid entry-table pointer interrupt source mask for area" "ERR_INV_DATA0_0_r,ERR_INV_DATA0_1_r" bitfld.long 0x00 2. "ERR_INV_DSC0,Invalid descriptor pointer interrupt source mask for area" "ERR_INV_DSC0_0_r,ERR_INV_DSC0_1_r" bitfld.long 0x00 1. "FILL_LST0,End of refill interrupt source mask for the last descriptior in area" "FILL_LST0_0_r,FILL_LST0_1_r" bitfld.long 0x00 0. "FILL_DSC0,End of refill interrupt source mask for any descriptior in area" "FILL_DSC0_0_r,FILL_DSC0_1_r" group.long 0x490++0x03 line.long 0x00 "DMM_PAT_IRQSTATUS,Per-event 'enabled' interrupt status vector" bitfld.long 0x00 31. "ERR_LUT_MISS3,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS3_0_r,ERR_LUT_MISS3_1_r" bitfld.long 0x00 30. "ERR_UPD_DATA3,Data register update whilst refilling error event in area" "ERR_UPD_DATA3_0_r,ERR_UPD_DATA3_1_r" bitfld.long 0x00 29. "ERR_UPD_CTRL3,Control register update whilst refilling error event in area" "ERR_UPD_CTRL3_0_r,ERR_UPD_CTRL3_1_r" bitfld.long 0x00 28. "ERR_UPD_AREA3,Area register update whilst refilling error event in area" "ERR_UPD_AREA3_0_r,ERR_UPD_AREA3_1_r" newline bitfld.long 0x00 27. "ERR_INV_DATA3,Invalid entry-table pointer error event in area" "ERR_INV_DATA3_0_r,ERR_INV_DATA3_1_r" bitfld.long 0x00 26. "ERR_INV_DSC3,Invalid descriptor pointer error event in area" "ERR_INV_DSC3_0_r,ERR_INV_DSC3_1_r" bitfld.long 0x00 25. "FILL_LST3,End of refill event for the last descriptor in area" "FILL_LST3_0_r,FILL_LST3_1_r" bitfld.long 0x00 24. "FILL_DSC3,End of refill event for any descriptor in area" "FILL_DSC3_0_r,FILL_DSC3_1_r" newline bitfld.long 0x00 23. "ERR_LUT_MISS2,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS2_0_r,ERR_LUT_MISS2_1_r" bitfld.long 0x00 22. "ERR_UPD_DATA2,Data register update whilst refilling error event in area" "ERR_UPD_DATA2_0_r,ERR_UPD_DATA2_1_r" bitfld.long 0x00 21. "ERR_UPD_CTRL2,Control register update whilst refilling error event in area" "ERR_UPD_CTRL2_0_r,ERR_UPD_CTRL2_1_r" bitfld.long 0x00 20. "ERR_UPD_AREA2,Area register update whilst refilling error event in area" "ERR_UPD_AREA2_0_r,ERR_UPD_AREA2_1_r" newline bitfld.long 0x00 19. "ERR_INV_DATA2,Invalid entry-table pointer error event in area" "ERR_INV_DATA2_0_r,ERR_INV_DATA2_1_r" bitfld.long 0x00 18. "ERR_INV_DSC2,Invalid descriptor pointer error event in area" "ERR_INV_DSC2_0_r,ERR_INV_DSC2_1_r" bitfld.long 0x00 17. "FILL_LST2,End of refill event for the last descriptor in area" "FILL_LST2_0_r,FILL_LST2_1_r" bitfld.long 0x00 16. "FILL_DSC2,End of refill event for any descriptor in area" "FILL_DSC2_0_r,FILL_DSC2_1_r" newline bitfld.long 0x00 15. "ERR_LUT_MISS1,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS1_0_r,ERR_LUT_MISS1_1_r" bitfld.long 0x00 14. "ERR_UPD_DATA1,Data register update whilst refilling error event in area" "ERR_UPD_DATA1_0_r,ERR_UPD_DATA1_1_r" bitfld.long 0x00 13. "ERR_UPD_CTRL1,Control register update whilst refilling error event in area" "ERR_UPD_CTRL1_0_r,ERR_UPD_CTRL1_1_r" bitfld.long 0x00 12. "ERR_UPD_AREA1,Area register update whilst refilling error event in area" "ERR_UPD_AREA1_0_r,ERR_UPD_AREA1_1_r" newline bitfld.long 0x00 11. "ERR_INV_DATA1,Invalid entry-table pointer error event in area" "ERR_INV_DATA1_0_r,ERR_INV_DATA1_1_r" bitfld.long 0x00 10. "ERR_INV_DSC1,Invalid descriptor pointer error event in area" "ERR_INV_DSC1_0_r,ERR_INV_DSC1_1_r" bitfld.long 0x00 9. "FILL_LST1,End of refill event for the last descriptor in area" "FILL_LST1_0_r,FILL_LST1_1_r" bitfld.long 0x00 8. "FILL_DSC1,End of refill event for any descriptor in area" "FILL_DSC1_0_r,FILL_DSC1_1_r" newline bitfld.long 0x00 7. "ERR_LUT_MISS0,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS0_0_r,ERR_LUT_MISS0_1_r" bitfld.long 0x00 6. "ERR_UPD_DATA0,Data register update whilst refilling error event in area" "ERR_UPD_DATA0_0_r,ERR_UPD_DATA0_1_r" bitfld.long 0x00 5. "ERR_UPD_CTRL0,Control register update whilst refilling error event in area" "ERR_UPD_CTRL0_0_r,ERR_UPD_CTRL0_1_r" bitfld.long 0x00 4. "ERR_UPD_AREA0,Area register update whilst refilling error event in area" "ERR_UPD_AREA0_0_r,ERR_UPD_AREA0_1_r" newline bitfld.long 0x00 3. "ERR_INV_DATA0,Invalid entry-table pointer error event in area" "ERR_INV_DATA0_0_r,ERR_INV_DATA0_1_r" bitfld.long 0x00 2. "ERR_INV_DSC0,Invalid descriptor pointer error event in area" "ERR_INV_DSC0_0_r,ERR_INV_DSC0_1_r" bitfld.long 0x00 1. "FILL_LST0,End of refill event for the last descriptor in area" "FILL_LST0_0_r,FILL_LST0_1_r" bitfld.long 0x00 0. "FILL_DSC0,End of refill event for any descriptor in area" "FILL_DSC0_0_r,FILL_DSC0_1_r" group.long 0x480++0x03 line.long 0x00 "DMM_PAT_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x00 31. "ERR_LUT_MISS3,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS3_0_r,ERR_LUT_MISS3_1_r" bitfld.long 0x00 30. "ERR_UPD_DATA3,Data register update whilst refilling error event in area" "ERR_UPD_DATA3_0_r,ERR_UPD_DATA3_1_r" bitfld.long 0x00 29. "ERR_UPD_CTRL3,Control register update whilst refilling error event in area" "ERR_UPD_CTRL3_0_r,ERR_UPD_CTRL3_1_r" bitfld.long 0x00 28. "ERR_UPD_AREA3,Area register update whilst refilling error event in area" "ERR_UPD_AREA3_0_r,ERR_UPD_AREA3_1_r" newline bitfld.long 0x00 27. "ERR_INV_DATA3,Invalid entry-table pointer error event in area" "ERR_INV_DATA3_0_r,ERR_INV_DATA3_1_r" bitfld.long 0x00 26. "ERR_INV_DSC3,Invalid descriptor pointer error event in area" "ERR_INV_DSC3_0_r,ERR_INV_DSC3_1_r" bitfld.long 0x00 25. "FILL_LST3,End of refill event for the last descriptor in area" "FILL_LST3_0_r,FILL_LST3_1_r" bitfld.long 0x00 24. "FILL_DSC3,End of refill event for any descriptor in area" "FILL_DSC3_0_r,FILL_DSC3_1_r" newline bitfld.long 0x00 23. "ERR_LUT_MISS2,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS2_0_r,ERR_LUT_MISS2_1_r" bitfld.long 0x00 22. "ERR_UPD_DATA2,Data register update whilst refilling error event in area" "ERR_UPD_DATA2_0_r,ERR_UPD_DATA2_1_r" bitfld.long 0x00 21. "ERR_UPD_CTRL2,Control register update whilst refilling error event in area" "ERR_UPD_CTRL2_0_r,ERR_UPD_CTRL2_1_r" bitfld.long 0x00 20. "ERR_UPD_AREA2,Area register update whilst refilling error event in area" "ERR_UPD_AREA2_0_r,ERR_UPD_AREA2_1_r" newline bitfld.long 0x00 19. "ERR_INV_DATA2,Invalid entry-table pointer error event in area" "ERR_INV_DATA2_0_r,ERR_INV_DATA2_1_r" bitfld.long 0x00 18. "ERR_INV_DSC2,Invalid descriptor pointer error event in area" "ERR_INV_DSC2_0_r,ERR_INV_DSC2_1_r" bitfld.long 0x00 17. "FILL_LST2,End of refill event for the last descriptor in area" "FILL_LST2_0_r,FILL_LST2_1_r" bitfld.long 0x00 16. "FILL_DSC2,End of refill event for any descriptor in area" "FILL_DSC2_0_r,FILL_DSC2_1_r" newline bitfld.long 0x00 15. "ERR_LUT_MISS1,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS1_0_r,ERR_LUT_MISS1_1_r" bitfld.long 0x00 14. "ERR_UPD_DATA1,Data register update whilst refilling error event in area" "ERR_UPD_DATA1_0_r,ERR_UPD_DATA1_1_r" bitfld.long 0x00 13. "ERR_UPD_CTRL1,Control register update whilst refilling error event in area" "ERR_UPD_CTRL1_0_r,ERR_UPD_CTRL1_1_r" bitfld.long 0x00 12. "ERR_UPD_AREA1,Area register update whilst refilling error event in area" "ERR_UPD_AREA1_0_r,ERR_UPD_AREA1_1_r" newline bitfld.long 0x00 11. "ERR_INV_DATA1,Invalid entry-table pointer error event in area" "ERR_INV_DATA1_0_r,ERR_INV_DATA1_1_r" bitfld.long 0x00 10. "ERR_INV_DSC1,Invalid descriptor pointer error event in area" "ERR_INV_DSC1_0_r,ERR_INV_DSC1_1_r" bitfld.long 0x00 9. "FILL_LST1,End of refill event for the last descriptor in area" "FILL_LST1_0_r,FILL_LST1_1_r" bitfld.long 0x00 8. "FILL_DSC1,End of refill event for any descriptor in area" "FILL_DSC1_0_r,FILL_DSC1_1_r" newline bitfld.long 0x00 7. "ERR_LUT_MISS0,Access to a yet-to-be-refilled area event in area" "ERR_LUT_MISS0_0_r,ERR_LUT_MISS0_1_r" bitfld.long 0x00 6. "ERR_UPD_DATA0,Data register update whilst refilling error event in area" "ERR_UPD_DATA0_0_r,ERR_UPD_DATA0_1_r" bitfld.long 0x00 5. "ERR_UPD_CTRL0,Control register update whilst refilling error event in area" "ERR_UPD_CTRL0_0_r,ERR_UPD_CTRL0_1_r" bitfld.long 0x00 4. "ERR_UPD_AREA0,Area register update whilst refilling error event in area" "ERR_UPD_AREA0_0_r,ERR_UPD_AREA0_1_r" newline bitfld.long 0x00 3. "ERR_INV_DATA0,Invalid entry-table pointer error event in area" "ERR_INV_DATA0_0_r,ERR_INV_DATA0_1_r" bitfld.long 0x00 2. "ERR_INV_DSC0,Invalid descriptor pointer error event in area" "ERR_INV_DSC0_0_r,ERR_INV_DSC0_1_r" bitfld.long 0x00 1. "FILL_LST0,End of refill event for the last descriptor in area" "FILL_LST0_0_r,FILL_LST0_1_r" bitfld.long 0x00 0. "FILL_DSC0,End of refill event for any descriptor in area" "FILL_DSC0_0_r,FILL_DSC0_1_r" group.long 0x420++0x07 line.long 0x00 "DMM_PAT_VIEW0,DMM PAT View register (initiators 0 to 7)" bitfld.long 0x00 31. "W7,Write-enable for V7 bit field" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--29. "V7,PAT view for initiator 7" "0,1,2,3" bitfld.long 0x00 27. "W6,Write-enable for V6 bit field" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--25. "V6,PAT view for initiator 6" "0,1,2,3" newline bitfld.long 0x00 23. "W5,Write-enable for V5 bit field" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--21. "V5,PAT view for initiator 5" "0,1,2,3" bitfld.long 0x00 19. "W4,Write-enable for V4 bit field" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--17. "V4,PAT view for initiator 4" "0,1,2,3" newline bitfld.long 0x00 15. "W3,Write-enable for V3 bit field" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--13. "V3,PAT view for initiator 3" "0,1,2,3" bitfld.long 0x00 11. "W2,Write-enable for V2 bit field" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--9. "V2,PAT view for initiator 2" "0,1,2,3" newline bitfld.long 0x00 7. "W1,Write-enable for V1 bit field" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--5. "V1,PAT view for initiator 1" "0,1,2,3" bitfld.long 0x00 3. "W0,Write-enable for V0 bit field" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--1. "V0,PAT view for initiator 0" "0,1,2,3" line.long 0x04 "DMM_PAT_VIEW1,DMM PAT view register (initiators 8 to 15)" bitfld.long 0x04 31. "W15,Write-enable for V15 bit field" "W15_0_w,W15_1_w" bitfld.long 0x04 28.--29. "V15,PAT view for initiator 15" "0,1,2,3" bitfld.long 0x04 27. "W14,Write-enable for V14 bit field" "W14_0_w,W14_1_w" bitfld.long 0x04 24.--25. "V14,PAT view for initiator 14" "0,1,2,3" newline bitfld.long 0x04 23. "W13,Write-enable for V13 bit field" "W13_0_w,W13_1_w" bitfld.long 0x04 20.--21. "V13,PAT view for initiator 13" "0,1,2,3" bitfld.long 0x04 19. "W12,Write-enable for V12 bit field" "W12_0_w,W12_1_w" bitfld.long 0x04 16.--17. "V12,PAT view for initiator 12" "0,1,2,3" newline bitfld.long 0x04 15. "W11,Write-enable for V11 bit field" "W11_0_w,W11_1_w" bitfld.long 0x04 12.--13. "V11,PAT view for initiator 11" "0,1,2,3" bitfld.long 0x04 11. "W10,Write-enable for V10 bit field" "W10_0_w,W10_1_w" bitfld.long 0x04 8.--9. "V10,PAT view for initiator 10" "0,1,2,3" newline bitfld.long 0x04 7. "W9,Write-enable for V9 bit field" "W9_0_w,W9_1_w" bitfld.long 0x04 4.--5. "V9,PAT view for initiator 9" "0,1,2,3" bitfld.long 0x04 3. "W8,Write-enable for V8 bit field" "W8_0_w,W8_1_w" bitfld.long 0x04 0.--1. "V8,PAT view for initiator 8" "0,1,2,3" group.long 0x460++0x03 line.long 0x00 "DMM_PAT_VIEW_MAP_BASE,Base address of all view mappings" bitfld.long 0x00 31. "BASE_ADDR,MSB of the PAT view mapping base address" "0,1" rgroup.long 0x608++0x03 line.long 0x00 "DMM_PEG_HWINFO,DMM hardware configuration for PEG" hexmask.long.byte 0x00 0.--6. 1. "PRIO_CNT,Number of PEG priority entries - 1" group.long 0x640++0x03 line.long 0x00 "DMM_PEG_PRIO_PAT,DMM PEG priority register for the internal PAT engine" bitfld.long 0x00 3. "W_PAT,Write-enable for P_PAT bit field - UPDATE" "W_PAT_0_w,W_PAT_1_w" bitfld.long 0x00 0.--2. "P_PAT,Priority for PAT engine" "0,1,2,3,4,5,6,7" rgroup.long 0x00++0x03 line.long 0x00 "DMM_REVISION,DMM revision number" group.long 0x10++0x03 line.long 0x00 "DMM_SYSCONFIG,DMM clock management configuration" bitfld.long 0x00 2.--3. "IDLE_MODE,Configuration of the local target state management mode" "IDLE_MODE_0,IDLE_MODE_1,IDLE_MODE_2,IDLE_MODE_3" rgroup.long 0x208++0x03 line.long 0x00 "DMM_TILER_HWINFO,DMM hardware configuration for TILER" hexmask.long.byte 0x00 0.--6. 1. "OR_CNT,Number of TILER orientation entries - 4" group.long 0x220++0x07 line.long 0x00 "DMM_TILER_OR0,DMM TILER orientation (initiators 0 to 7)" bitfld.long 0x00 31. "W7,Write-enable for OR7 bit field" "W7_0_w,W7_1_w" bitfld.long 0x00 28.--30. "OR7,Orientation for initiator 7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. "W6,Write-enable for OR6 bit field" "W6_0_w,W6_1_w" bitfld.long 0x00 24.--26. "OR6,Orientation for initiator 6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 23. "W5,Write-enable for OR5 bit field" "W5_0_w,W5_1_w" bitfld.long 0x00 20.--22. "OR5,Orientation for initiator 5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. "W4,Write-enable for OR4 bit field" "W4_0_w,W4_1_w" bitfld.long 0x00 16.--18. "OR4,Orientation for initiator 4" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15. "W3,Write-enable for OR3 bit field" "W3_0_w,W3_1_w" bitfld.long 0x00 12.--14. "OR3,Orientation for initiator 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. "W2,Write-enable for OR2 bit field" "W2_0_w,W2_1_w" bitfld.long 0x00 8.--10. "OR2,Orientation for initiator 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "W1,Write-enable for OR1 bit field" "W1_0_w,W1_1_w" bitfld.long 0x00 4.--6. "OR1,Orientation for initiator 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "W0,Write-enable for OR0 bit field" "W0_0_w,W0_1_w" bitfld.long 0x00 0.--2. "OR0,Orientation for initiator 0" "0,1,2,3,4,5,6,7" line.long 0x04 "DMM_TILER_OR1,DMM TILER orientation (initiators 8 to 15)" bitfld.long 0x04 31. "W15,Write-enable for OR15 bit field" "W15_0_w,W15_1_w" bitfld.long 0x04 28.--30. "OR15,Orientation for initiator 15" "0,1,2,3,4,5,6,7" bitfld.long 0x04 27. "W14,Write-enable for OR14 bit field" "W14_0_w,W14_1_w" bitfld.long 0x04 24.--26. "OR14,Orientation for initiator 14" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 23. "W13,Write-enable for OR13 bit field" "W13_0_w,W13_1_w" bitfld.long 0x04 20.--22. "OR13,Orientation for initiator 13" "0,1,2,3,4,5,6,7" bitfld.long 0x04 19. "W12,Write-enable for OR12 bit field" "W12_0_w,W12_1_w" bitfld.long 0x04 16.--18. "OR12,Orientation for initiator 12" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 15. "W11,Write-enable for OR11 bit field" "W11_0_w,W11_1_w" bitfld.long 0x04 12.--14. "OR11,Orientation for initiator 11" "0,1,2,3,4,5,6,7" bitfld.long 0x04 11. "W10,Write-enable for OR10 bit field" "W10_0_w,W10_1_w" bitfld.long 0x04 8.--10. "OR10,Orientation for initiator 10" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 7. "W9,Write-enable for OR9 bit field" "W9_0_w,W9_1_w" bitfld.long 0x04 4.--6. "OR9,Orientation for initiator 9" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. "W8,Write-enable for OR8 bit field" "W8_0_w,W8_1_w" bitfld.long 0x04 0.--2. "OR8,Orientation for initiator 8" "0,1,2,3,4,5,6,7" tree.end tree.end tree.open "Embedded_Vision_Engine_EVE_Subsystem" tree "EVE1" base ad:0x42000000 rgroup.long 0x80000++0x2F line.long 0x00 "EVE_REVISION," line.long 0x04 "EVE_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_SYSCONFIG," bitfld.long 0x08 4.--5. "STANDBYMODE," "0,1,2,3" bitfld.long 0x08 2.--3. "IDLEMODE," "0,1,2,3" rbitfld.long 0x08 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x08 0. "SOFTRESET,Reserved" "0,1" line.long 0x0C "EVE_STAT," bitfld.long 0x0C 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,?,?" bitfld.long 0x0C 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,?,?" bitfld.long 0x0C 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x0C 7. "ARP_INTC_STAT,Interrupt Controller Status" "ARP_INTC_STAT_0,ARP_INTC_STAT_1" bitfld.long 0x0C 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" bitfld.long 0x0C 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" bitfld.long 0x0C 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" line.long 0x10 "EVE_DISC_CONFIG,Color 0 noise threshold" bitfld.long 0x10 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" bitfld.long 0x10 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" line.long 0x14 "EVE_BUS_CONFIG,Color 0 noise threshold" bitfld.long 0x14 12.--13. "TC1_DBS,TC1 default burst size" "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_DBS,TC0 default burst size" "0,1,2,3" bitfld.long 0x14 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x14 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EVE_VCOP_HALT_CONFIG," bitfld.long 0x18 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns" "?,FORCE_ABORT_1_w" bitfld.long 0x18 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" bitfld.long 0x18 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" line.long 0x1C "EVE_MMU_CONFIG," bitfld.long 0x1C 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" bitfld.long 0x1C 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" bitfld.long 0x1C 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline bitfld.long 0x1C 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" line.long 0x20 "EVE_MEMMAP," bitfld.long 0x20 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" bitfld.long 0x20 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" line.long 0x24 "EVE_MSW_CTL,Memory switch control register" bitfld.long 0x24 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" bitfld.long 0x24 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" bitfld.long 0x24 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline bitfld.long 0x24 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" bitfld.long 0x24 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x28 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.word 0x28 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x28 3. "SYSERR," "0,1" bitfld.long 0x28 2. "DMAERR," "0,1" newline bitfld.long 0x28 1. "VERR," "0,1" bitfld.long 0x28 0. "ARP32ERR," "0,1" line.long 0x2C "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" bitfld.long 0x00 0. "I,Invalidate all" "I_0_w,?" group.long 0x80050++0x17 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" line.long 0x08 "EVE_PC_ISAR,Invalidate single address register" line.long 0x0C "EVE_PC_ISAR_DONE,Invalidate single address done register" bitfld.long 0x0C 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x10 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x14 "EVE_PC_PBC," hexmask.long.word 0x14 0.--15. 1. "BC,Preload Byte Count register" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" bitfld.long 0x00 1. "INV," "0,1" bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x04 3. "SYSERR," "0,1" bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" group.long 0x80090++0x2F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" bitfld.long 0x00 1. "INV," "0,1" bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x04 3. "SYSERR," "0,1" bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" line.long 0x10 "EVE_WBUF_ED_CTL,WBUF error detection control" bitfld.long 0x10 1. "INV," "0,1" bitfld.long 0x10 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x14 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.word 0x14 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x14 3. "SYSERR," "0,1" bitfld.long 0x14 2. "DMAERR," "0,1" newline bitfld.long 0x14 1. "VERR," "0,1" bitfld.long 0x14 0. "ARP32ERR," "0,1" line.long 0x18 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x1C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" line.long 0x20 "EVE_IBUF_ED_CTL,IBUF error detection control" bitfld.long 0x20 1. "INV," "0,1" bitfld.long 0x20 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x24 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.word 0x24 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x24 3. "SYSERR," "0,1" bitfld.long 0x24 2. "DMAERR," "0,1" newline bitfld.long 0x24 1. "VERR," "0,1" bitfld.long 0x24 0. "ARP32ERR," "0,1" line.long 0x28 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x2C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x800F8++0x07 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" hexmask.long.word 0x00 0.--15. 1. "ENABLE,Disconnect Enable for Event #n" line.long 0x04 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" hexmask.long.word 0x04 0.--15. 1. "ENABLE,Disconnect Enable for Event #n" group.long 0x80110++0x1F line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" bitfld.long 0x04 0.--3. "EVENT,Clearable / enabled status for event #N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" bitfld.long 0x08 0.--3. "ENABLE,Enable for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" bitfld.long 0x0C 0.--3. "ENABLE,Enable for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" hexmask.long.word 0x10 0.--15. 1. "EVENT,settable raw status for event #n" line.long 0x14 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" hexmask.long.word 0x14 0.--15. 1. "EVENT,Clearable / enabled status for event #N" line.long 0x18 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" hexmask.long.word 0x18 0.--15. 1. "ENABLE,Enable for event #n" line.long 0x1C "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" hexmask.long.word 0x1C 0.--15. 1. "ENABLE,Enable for event #n" group.long 0x80200++0x0F line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," line.long 0x04 "ARP32_NMI_IRQSTATUS," line.long 0x08 "ARP32_NMI_IRQENABLE_SET," line.long 0x0C "ARP32_NMI_IRQENABLE_CLR," group.long 0x802FC++0x03 line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" hexmask.long.tbyte 0x00 0.--23. 1. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" group.long 0x80400++0x07 line.long 0x00 "MISR_CTL," bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "0,1,2,3,4,5,6,7" line.long 0x04 "MISR_CLEAR," bitfld.long 0x04 0.--2. "CLEAR,MISR Clear #N" "0,1,2,3,4,5,6,7" group.long 0x80410++0x0F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80510++0x0F line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," hexmask.long.word 0x00 0.--15. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "EVE_ED_OUT_IRQSTATUS," hexmask.long.word 0x04 0.--15. 1. "EVENT,Clearable / enabled status for event #N" line.long 0x08 "EVE_ED_OUT_IRQENABLE_SET," hexmask.long.word 0x08 0.--15. 1. "ENABLE,Enable for event #n" line.long 0x0C "EVE_ED_OUT_IRQENABLE_CLR," hexmask.long.word 0x0C 0.--15. 1. "ENABLE,Enable for event #n" rgroup.long 0x80680++0x1F line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," line.long 0x04 "ARP32_INT14_IRQSTATUS," line.long 0x08 "ARP32_INT14_IRQENABLE_SET," line.long 0x0C "ARP32_INT14_IRQENABLE_CLR," line.long 0x10 "ARP32_INT15_IRQSTATUS_RAW," line.long 0x14 "ARP32_INT15_IRQSTATUS," line.long 0x18 "ARP32_INT15_IRQENABLE_SET," line.long 0x1C "ARP32_INT15_IRQENABLE_CLR," group.long 0x80780++0x17 line.long 0x00 "EVE_CME_DONE_GPOUT," hexmask.long.byte 0x00 0.--7. 1. "EVENT,Internal CME Done Output #n" line.long 0x04 "EVE_CME_DONE_GPOUT_SET," hexmask.long.byte 0x04 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x08 "EVE_CME_DONE_GPOUT_CLR," hexmask.long.byte 0x08 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x0C "EVE_CME_DONE_GPOUT_PULSE," hexmask.long.byte 0x0C 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x10 "EVE_CME_DONE_SEL," bitfld.long 0x10 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "EVE_CME_DONE_EN," hexmask.long.byte 0x14 0.--7. 1. "EN,EVE CME Done EN #n" rgroup.long 0x80FE0++0x0B line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" line.long 0x08 "EVE_DBGOUT," hexmask.long.tbyte 0x08 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" bitfld.long 0x08 0.--3. "GROUP,Debug Group Output control : mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end repeat 4. (list 10. 11. 12. 13. ) tree "IRQ_Line_$1" group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," tree.end repeat.end repeat 2. (list 8. 9. ) tree "IRQ_Line_$1" group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," group.long 0x80320++0x03 line.long 0x00 "MMR_LOCKi_8,MMR Lock/Unlock register" tree.end repeat.end repeat 4. (list 4. 5. 6. 7. ) tree "IRQ_Line_$1" group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80310++0x03 line.long 0x00 "MMR_LOCKi_4,MMR Lock/Unlock register" tree.end repeat.end repeat 2. (list 2. 3. ) tree "IRQ_Line_$1" group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80428++0x03 line.long 0x00 "MISR2_Dk_2," group.long 0x80308++0x03 line.long 0x00 "MMR_LOCKi_2,MMR Lock/Unlock register" tree.end repeat.end repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80708++0x07 line.long 0x00 "EVE_GPOUTm_CLR_0," line.long 0x04 "EVE_GPOUTm_PULSE_0," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80520++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80420++0x03 line.long 0x00 "MISR2_Dk_0," group.long 0x80300++0x03 line.long 0x00 "MMR_LOCKi_0,MMR Lock/Unlock register" tree.end repeat.end tree.end tree "EVE1_DSP" base ad:0x2000000 rgroup.long 0x80000++0x2F line.long 0x00 "EVE_REVISION," line.long 0x04 "EVE_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_SYSCONFIG," bitfld.long 0x08 4.--5. "STANDBYMODE," "0,1,2,3" bitfld.long 0x08 2.--3. "IDLEMODE," "0,1,2,3" rbitfld.long 0x08 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x08 0. "SOFTRESET,Reserved" "0,1" line.long 0x0C "EVE_STAT," bitfld.long 0x0C 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,?,?" bitfld.long 0x0C 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,?,?" bitfld.long 0x0C 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x0C 7. "ARP_INTC_STAT,Interrupt Controller Status" "ARP_INTC_STAT_0,ARP_INTC_STAT_1" bitfld.long 0x0C 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" bitfld.long 0x0C 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" bitfld.long 0x0C 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" line.long 0x10 "EVE_DISC_CONFIG,Color 0 noise threshold" bitfld.long 0x10 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" bitfld.long 0x10 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" line.long 0x14 "EVE_BUS_CONFIG,Color 0 noise threshold" bitfld.long 0x14 12.--13. "TC1_DBS,TC1 default burst size" "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_DBS,TC0 default burst size" "0,1,2,3" bitfld.long 0x14 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x14 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EVE_VCOP_HALT_CONFIG," bitfld.long 0x18 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns" "?,FORCE_ABORT_1_w" bitfld.long 0x18 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" bitfld.long 0x18 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" line.long 0x1C "EVE_MMU_CONFIG," bitfld.long 0x1C 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" bitfld.long 0x1C 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" bitfld.long 0x1C 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline bitfld.long 0x1C 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" line.long 0x20 "EVE_MEMMAP," bitfld.long 0x20 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" bitfld.long 0x20 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" line.long 0x24 "EVE_MSW_CTL,Memory switch control register" bitfld.long 0x24 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" bitfld.long 0x24 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" bitfld.long 0x24 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline bitfld.long 0x24 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" bitfld.long 0x24 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x28 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.word 0x28 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x28 3. "SYSERR," "0,1" bitfld.long 0x28 2. "DMAERR," "0,1" newline bitfld.long 0x28 1. "VERR," "0,1" bitfld.long 0x28 0. "ARP32ERR," "0,1" line.long 0x2C "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" bitfld.long 0x00 0. "I,Invalidate all" "I_0_w,?" group.long 0x80050++0x17 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" line.long 0x08 "EVE_PC_ISAR,Invalidate single address register" line.long 0x0C "EVE_PC_ISAR_DONE,Invalidate single address done register" bitfld.long 0x0C 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x10 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x14 "EVE_PC_PBC," hexmask.long.word 0x14 0.--15. 1. "BC,Preload Byte Count register" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" bitfld.long 0x00 1. "INV," "0,1" bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x04 3. "SYSERR," "0,1" bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" group.long 0x80090++0x2F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" bitfld.long 0x00 1. "INV," "0,1" bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x04 3. "SYSERR," "0,1" bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" line.long 0x10 "EVE_WBUF_ED_CTL,WBUF error detection control" bitfld.long 0x10 1. "INV," "0,1" bitfld.long 0x10 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x14 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.word 0x14 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x14 3. "SYSERR," "0,1" bitfld.long 0x14 2. "DMAERR," "0,1" newline bitfld.long 0x14 1. "VERR," "0,1" bitfld.long 0x14 0. "ARP32ERR," "0,1" line.long 0x18 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x1C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" line.long 0x20 "EVE_IBUF_ED_CTL,IBUF error detection control" bitfld.long 0x20 1. "INV," "0,1" bitfld.long 0x20 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x24 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.word 0x24 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x24 3. "SYSERR," "0,1" bitfld.long 0x24 2. "DMAERR," "0,1" newline bitfld.long 0x24 1. "VERR," "0,1" bitfld.long 0x24 0. "ARP32ERR," "0,1" line.long 0x28 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x2C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x800F8++0x07 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" hexmask.long.word 0x00 0.--15. 1. "ENABLE,Disconnect Enable for Event #n" line.long 0x04 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" hexmask.long.word 0x04 0.--15. 1. "ENABLE,Disconnect Enable for Event #n" group.long 0x80110++0x1F line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" bitfld.long 0x04 0.--3. "EVENT,Clearable / enabled status for event #N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" bitfld.long 0x08 0.--3. "ENABLE,Enable for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" bitfld.long 0x0C 0.--3. "ENABLE,Enable for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" hexmask.long.word 0x10 0.--15. 1. "EVENT,settable raw status for event #n" line.long 0x14 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" hexmask.long.word 0x14 0.--15. 1. "EVENT,Clearable / enabled status for event #N" line.long 0x18 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" hexmask.long.word 0x18 0.--15. 1. "ENABLE,Enable for event #n" line.long 0x1C "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" hexmask.long.word 0x1C 0.--15. 1. "ENABLE,Enable for event #n" group.long 0x80200++0x0F line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," line.long 0x04 "ARP32_NMI_IRQSTATUS," line.long 0x08 "ARP32_NMI_IRQENABLE_SET," line.long 0x0C "ARP32_NMI_IRQENABLE_CLR," group.long 0x802FC++0x03 line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" hexmask.long.tbyte 0x00 0.--23. 1. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" group.long 0x80400++0x07 line.long 0x00 "MISR_CTL," bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "0,1,2,3,4,5,6,7" line.long 0x04 "MISR_CLEAR," bitfld.long 0x04 0.--2. "CLEAR,MISR Clear #N" "0,1,2,3,4,5,6,7" group.long 0x80410++0x0F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80510++0x0F line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," hexmask.long.word 0x00 0.--15. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "EVE_ED_OUT_IRQSTATUS," hexmask.long.word 0x04 0.--15. 1. "EVENT,Clearable / enabled status for event #N" line.long 0x08 "EVE_ED_OUT_IRQENABLE_SET," hexmask.long.word 0x08 0.--15. 1. "ENABLE,Enable for event #n" line.long 0x0C "EVE_ED_OUT_IRQENABLE_CLR," hexmask.long.word 0x0C 0.--15. 1. "ENABLE,Enable for event #n" rgroup.long 0x80680++0x1F line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," line.long 0x04 "ARP32_INT14_IRQSTATUS," line.long 0x08 "ARP32_INT14_IRQENABLE_SET," line.long 0x0C "ARP32_INT14_IRQENABLE_CLR," line.long 0x10 "ARP32_INT15_IRQSTATUS_RAW," line.long 0x14 "ARP32_INT15_IRQSTATUS," line.long 0x18 "ARP32_INT15_IRQENABLE_SET," line.long 0x1C "ARP32_INT15_IRQENABLE_CLR," group.long 0x80780++0x17 line.long 0x00 "EVE_CME_DONE_GPOUT," hexmask.long.byte 0x00 0.--7. 1. "EVENT,Internal CME Done Output #n" line.long 0x04 "EVE_CME_DONE_GPOUT_SET," hexmask.long.byte 0x04 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x08 "EVE_CME_DONE_GPOUT_CLR," hexmask.long.byte 0x08 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x0C "EVE_CME_DONE_GPOUT_PULSE," hexmask.long.byte 0x0C 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x10 "EVE_CME_DONE_SEL," bitfld.long 0x10 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "EVE_CME_DONE_EN," hexmask.long.byte 0x14 0.--7. 1. "EN,EVE CME Done EN #n" rgroup.long 0x80FE0++0x0B line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" line.long 0x08 "EVE_DBGOUT," hexmask.long.tbyte 0x08 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" bitfld.long 0x08 0.--3. "GROUP,Debug Group Output control : mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end repeat 4. (list 10. 11. 12. 13. ) tree "IRQ_Line_$1" group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," tree.end repeat.end repeat 2. (list 8. 9. ) tree "IRQ_Line_$1" group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," group.long 0x80320++0x03 line.long 0x00 "MMR_LOCKi_8,MMR Lock/Unlock register" tree.end repeat.end repeat 4. (list 4. 5. 6. 7. ) tree "IRQ_Line_$1" group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80310++0x03 line.long 0x00 "MMR_LOCKi_4,MMR Lock/Unlock register" tree.end repeat.end repeat 2. (list 2. 3. ) tree "IRQ_Line_$1" group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80428++0x03 line.long 0x00 "MISR2_Dk_2," group.long 0x80308++0x03 line.long 0x00 "MMR_LOCKi_2,MMR Lock/Unlock register" tree.end repeat.end repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80708++0x07 line.long 0x00 "EVE_GPOUTm_CLR_0," line.long 0x04 "EVE_GPOUTm_PULSE_0," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80520++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80420++0x03 line.long 0x00 "MISR2_Dk_0," group.long 0x80300++0x03 line.long 0x00 "MMR_LOCKi_0,MMR Lock/Unlock register" tree.end repeat.end tree.end tree "EVE2_DSP" base ad:0x2100000 rgroup.long 0x80000++0x2F line.long 0x00 "EVE_REVISION," line.long 0x04 "EVE_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_SYSCONFIG," bitfld.long 0x08 4.--5. "STANDBYMODE," "0,1,2,3" bitfld.long 0x08 2.--3. "IDLEMODE," "0,1,2,3" rbitfld.long 0x08 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x08 0. "SOFTRESET,Reserved" "0,1" line.long 0x0C "EVE_STAT," bitfld.long 0x0C 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,?,?" bitfld.long 0x0C 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,?,?" bitfld.long 0x0C 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x0C 7. "ARP_INTC_STAT,Interrupt Controller Status" "ARP_INTC_STAT_0,ARP_INTC_STAT_1" bitfld.long 0x0C 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" bitfld.long 0x0C 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" bitfld.long 0x0C 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" line.long 0x10 "EVE_DISC_CONFIG,Color 0 noise threshold" bitfld.long 0x10 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" bitfld.long 0x10 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" line.long 0x14 "EVE_BUS_CONFIG,Color 0 noise threshold" bitfld.long 0x14 12.--13. "TC1_DBS,TC1 default burst size" "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_DBS,TC0 default burst size" "0,1,2,3" bitfld.long 0x14 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x14 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EVE_VCOP_HALT_CONFIG," bitfld.long 0x18 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns" "?,FORCE_ABORT_1_w" bitfld.long 0x18 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" bitfld.long 0x18 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" line.long 0x1C "EVE_MMU_CONFIG," bitfld.long 0x1C 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" bitfld.long 0x1C 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" bitfld.long 0x1C 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline bitfld.long 0x1C 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" line.long 0x20 "EVE_MEMMAP," bitfld.long 0x20 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" bitfld.long 0x20 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" line.long 0x24 "EVE_MSW_CTL,Memory switch control register" bitfld.long 0x24 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" bitfld.long 0x24 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" bitfld.long 0x24 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline bitfld.long 0x24 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" bitfld.long 0x24 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x28 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.word 0x28 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x28 3. "SYSERR," "0,1" bitfld.long 0x28 2. "DMAERR," "0,1" newline bitfld.long 0x28 1. "VERR," "0,1" bitfld.long 0x28 0. "ARP32ERR," "0,1" line.long 0x2C "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" bitfld.long 0x00 0. "I,Invalidate all" "I_0_w,?" group.long 0x80050++0x17 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" line.long 0x08 "EVE_PC_ISAR,Invalidate single address register" line.long 0x0C "EVE_PC_ISAR_DONE,Invalidate single address done register" bitfld.long 0x0C 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x10 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x14 "EVE_PC_PBC," hexmask.long.word 0x14 0.--15. 1. "BC,Preload Byte Count register" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" bitfld.long 0x00 1. "INV," "0,1" bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x04 3. "SYSERR," "0,1" bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" group.long 0x80090++0x2F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" bitfld.long 0x00 1. "INV," "0,1" bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x04 3. "SYSERR," "0,1" bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" line.long 0x10 "EVE_WBUF_ED_CTL,WBUF error detection control" bitfld.long 0x10 1. "INV," "0,1" bitfld.long 0x10 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x14 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.word 0x14 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x14 3. "SYSERR," "0,1" bitfld.long 0x14 2. "DMAERR," "0,1" newline bitfld.long 0x14 1. "VERR," "0,1" bitfld.long 0x14 0. "ARP32ERR," "0,1" line.long 0x18 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x1C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" line.long 0x20 "EVE_IBUF_ED_CTL,IBUF error detection control" bitfld.long 0x20 1. "INV," "0,1" bitfld.long 0x20 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x24 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.word 0x24 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x24 3. "SYSERR," "0,1" bitfld.long 0x24 2. "DMAERR," "0,1" newline bitfld.long 0x24 1. "VERR," "0,1" bitfld.long 0x24 0. "ARP32ERR," "0,1" line.long 0x28 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x2C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x800F8++0x07 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" hexmask.long.word 0x00 0.--15. 1. "ENABLE,Disconnect Enable for Event #n" line.long 0x04 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" hexmask.long.word 0x04 0.--15. 1. "ENABLE,Disconnect Enable for Event #n" group.long 0x80110++0x1F line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" bitfld.long 0x04 0.--3. "EVENT,Clearable / enabled status for event #N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" bitfld.long 0x08 0.--3. "ENABLE,Enable for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" bitfld.long 0x0C 0.--3. "ENABLE,Enable for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" hexmask.long.word 0x10 0.--15. 1. "EVENT,settable raw status for event #n" line.long 0x14 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" hexmask.long.word 0x14 0.--15. 1. "EVENT,Clearable / enabled status for event #N" line.long 0x18 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" hexmask.long.word 0x18 0.--15. 1. "ENABLE,Enable for event #n" line.long 0x1C "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" hexmask.long.word 0x1C 0.--15. 1. "ENABLE,Enable for event #n" group.long 0x80200++0x0F line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," line.long 0x04 "ARP32_NMI_IRQSTATUS," line.long 0x08 "ARP32_NMI_IRQENABLE_SET," line.long 0x0C "ARP32_NMI_IRQENABLE_CLR," group.long 0x802FC++0x03 line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" hexmask.long.tbyte 0x00 0.--23. 1. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" group.long 0x80400++0x07 line.long 0x00 "MISR_CTL," bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "0,1,2,3,4,5,6,7" line.long 0x04 "MISR_CLEAR," bitfld.long 0x04 0.--2. "CLEAR,MISR Clear #N" "0,1,2,3,4,5,6,7" group.long 0x80410++0x0F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80510++0x0F line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," hexmask.long.word 0x00 0.--15. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "EVE_ED_OUT_IRQSTATUS," hexmask.long.word 0x04 0.--15. 1. "EVENT,Clearable / enabled status for event #N" line.long 0x08 "EVE_ED_OUT_IRQENABLE_SET," hexmask.long.word 0x08 0.--15. 1. "ENABLE,Enable for event #n" line.long 0x0C "EVE_ED_OUT_IRQENABLE_CLR," hexmask.long.word 0x0C 0.--15. 1. "ENABLE,Enable for event #n" rgroup.long 0x80680++0x1F line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," line.long 0x04 "ARP32_INT14_IRQSTATUS," line.long 0x08 "ARP32_INT14_IRQENABLE_SET," line.long 0x0C "ARP32_INT14_IRQENABLE_CLR," line.long 0x10 "ARP32_INT15_IRQSTATUS_RAW," line.long 0x14 "ARP32_INT15_IRQSTATUS," line.long 0x18 "ARP32_INT15_IRQENABLE_SET," line.long 0x1C "ARP32_INT15_IRQENABLE_CLR," group.long 0x80780++0x17 line.long 0x00 "EVE_CME_DONE_GPOUT," hexmask.long.byte 0x00 0.--7. 1. "EVENT,Internal CME Done Output #n" line.long 0x04 "EVE_CME_DONE_GPOUT_SET," hexmask.long.byte 0x04 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x08 "EVE_CME_DONE_GPOUT_CLR," hexmask.long.byte 0x08 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x0C "EVE_CME_DONE_GPOUT_PULSE," hexmask.long.byte 0x0C 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x10 "EVE_CME_DONE_SEL," bitfld.long 0x10 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "EVE_CME_DONE_EN," hexmask.long.byte 0x14 0.--7. 1. "EN,EVE CME Done EN #n" rgroup.long 0x80FE0++0x0B line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" line.long 0x08 "EVE_DBGOUT," hexmask.long.tbyte 0x08 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" bitfld.long 0x08 0.--3. "GROUP,Debug Group Output control : mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end repeat 4. (list 10. 11. 12. 13. ) tree "IRQ_Line_$1" group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," tree.end repeat.end repeat 2. (list 8. 9. ) tree "IRQ_Line_$1" group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," group.long 0x80320++0x03 line.long 0x00 "MMR_LOCKi_8,MMR Lock/Unlock register" tree.end repeat.end repeat 4. (list 4. 5. 6. 7. ) tree "IRQ_Line_$1" group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80310++0x03 line.long 0x00 "MMR_LOCKi_4,MMR Lock/Unlock register" tree.end repeat.end repeat 2. (list 2. 3. ) tree "IRQ_Line_$1" group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80428++0x03 line.long 0x00 "MISR2_Dk_2," group.long 0x80308++0x03 line.long 0x00 "MMR_LOCKi_2,MMR Lock/Unlock register" tree.end repeat.end repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80708++0x07 line.long 0x00 "EVE_GPOUTm_CLR_0," line.long 0x04 "EVE_GPOUTm_PULSE_0," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80520++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80420++0x03 line.long 0x00 "MISR2_Dk_0," group.long 0x80300++0x03 line.long 0x00 "MMR_LOCKi_0,MMR Lock/Unlock register" tree.end repeat.end tree.end tree "EVE1_L2_FNOC" base ad:0x208A000 repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x10++0x0B line.long 0x00 "ERRLOGGER_i_ERRCLR_0," bitfld.long 0x00 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x04 "ERRLOGGER_i_ERRLOG0_0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x04 31. "FORMAT,Format of ErrLog0 register" "0,1" hexmask.long.word 0x04 16.--25. 1. "LEN1,Header: Len1 value" bitfld.long 0x04 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x08 "ERRLOGGER_i_ERRLOG1_0," hexmask.long.word 0x08 0.--13. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x20++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG3_0," rgroup.long 0x28++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG5_0," hexmask.long.tbyte 0x00 0.--16. 1. "ERRLOG5,Header: User lsb value" rgroup.long 0x0C++0x03 line.long 0x00 "ERRLOGGER_i_ERRVLD_0," bitfld.long 0x00 0. "ERRVLD,Error logged Valid" "0,1" group.long 0x08++0x03 line.long 0x00 "ERRLOGGER_i_FAULTEN_0," bitfld.long 0x00 0. "FAULTEN,Enable Fault output" "0,1" rgroup.long 0x00++0x07 line.long 0x00 "ERRLOGGER_i_ID_COREID_0," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "ERRLOGGER_i_ID_REVISIONID_0," hexmask.long.tbyte 0x04 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x04 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" group.long 0x108++0x0F line.long 0x00 "FLAGMUX_i_FAULTEN_0," bitfld.long 0x00 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x04 "FLAGMUX_i_FAULTSTATUS_0," bitfld.long 0x04 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x08 "FLAGMUX_i_FLAGINEN0_0," bitfld.long 0x08 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x0C "FLAGMUX_i_FLAGINSTATUS0_0," bitfld.long 0x0C 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x100++0x07 line.long 0x00 "FLAGMUX_i_ID_COREID_0," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "FLAGMUX_i_ID_REVISIONID_0," hexmask.long.tbyte 0x04 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x04 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" tree.end repeat.end tree.end tree "EVE2_L2_FNOC" base ad:0x4218A000 repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x10++0x0B line.long 0x00 "ERRLOGGER_i_ERRCLR_0," bitfld.long 0x00 0. "ERRCLR,Clr ErrVld status" "0,1" line.long 0x04 "ERRLOGGER_i_ERRLOG0_0,Header: Lock. Opcode. Len1. ErrCode values" bitfld.long 0x04 31. "FORMAT,Format of ErrLog0 register" "0,1" hexmask.long.word 0x04 16.--25. 1. "LEN1,Header: Len1 value" bitfld.long 0x04 8.--10. "ERRCODE,Header: Error Code value" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--4. "OPC,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0. "LOCK,Header: Lock bit value" "0,1" line.long 0x08 "ERRLOGGER_i_ERRLOG1_0," hexmask.long.word 0x08 0.--13. 1. "ERRLOG1,Header: RouteId lsb value" rgroup.long 0x20++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG3_0," rgroup.long 0x28++0x03 line.long 0x00 "ERRLOGGER_i_ERRLOG5_0," hexmask.long.tbyte 0x00 0.--16. 1. "ERRLOG5,Header: User lsb value" rgroup.long 0x0C++0x03 line.long 0x00 "ERRLOGGER_i_ERRVLD_0," bitfld.long 0x00 0. "ERRVLD,Error logged Valid" "0,1" group.long 0x08++0x03 line.long 0x00 "ERRLOGGER_i_FAULTEN_0," bitfld.long 0x00 0. "FAULTEN,Enable Fault output" "0,1" rgroup.long 0x00++0x07 line.long 0x00 "ERRLOGGER_i_ID_COREID_0," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "ERRLOGGER_i_ID_REVISIONID_0," hexmask.long.tbyte 0x04 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x04 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" group.long 0x108++0x0F line.long 0x00 "FLAGMUX_i_FAULTEN_0," bitfld.long 0x00 0. "FAULTEN,Global Fault Enable register" "0,1" line.long 0x04 "FLAGMUX_i_FAULTSTATUS_0," bitfld.long 0x04 0. "FAULTSTATUS,Global Fault Status register" "0,1" line.long 0x08 "FLAGMUX_i_FLAGINEN0_0," bitfld.long 0x08 0. "FLAGINEN0,FlagIn Enable register #0" "0,1" line.long 0x0C "FLAGMUX_i_FLAGINSTATUS0_0," bitfld.long 0x0C 0. "FLAGINSTATUS0,FlagIn Status register #0" "0,1" rgroup.long 0x100++0x07 line.long 0x00 "FLAGMUX_i_ID_COREID_0," hexmask.long.tbyte 0x00 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP" hexmask.long.byte 0x00 0.--7. 1. "CORETYPEID,Field identifying the type of IP" line.long 0x04 "FLAGMUX_i_ID_REVISIONID_0," hexmask.long.tbyte 0x04 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code" hexmask.long.byte 0x04 0.--7. 1. "USERID,Field containing a user defined value not used anywhere inside the IP itself" tree.end repeat.end tree.end tree "EVE1_SCTM" base ad:0x42085000 group.long 0x00++0x03 line.long 0x00 "SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export through STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVID,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "0,1,2,3" bitfld.long 0x00 0. "ENBL,SCTM global enable - DISABLE" "ENBL_0,ENBL_1" group.long 0x20++0x0F line.long 0x00 "SCTM_CTSTMCNTL,This register contains the control and status settings for STM export" rbitfld.long 0x00 10. "XPORTACT,Indicates if a frame is currently being written to the STM" "0,1" bitfld.long 0x00 5.--9. "NUMXPORT,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "CCMXPORT,SW control of CCM message export" "0,1" rbitfld.long 0x00 3. "CCMVAIL,SCTM supports CCM export" "0,1" bitfld.long 0x00 2. "CSMXPORT,SW control of CSM message export" "0,1" bitfld.long 0x00 1. "SENDOVR,Send overflow data in CSM frame" "0,1" bitfld.long 0x00 0. "ENBL,STM global enable - DISABLE" "ENBL_0,ENBL_1" line.long 0x04 "SCTM_CTSTMMSTID," hexmask.long.byte 0x04 0.--6. 1. "MASTID,HW Master ID for this module" line.long 0x08 "SCTM_CTSTMINTVL," hexmask.long.word 0x08 0.--15. 1. "INTERVAL,Periodic export interval" line.long 0x0C "SCTM_CTSTMSEL,These registers mark the counters selected for export in the CSM" rgroup.long 0x7C++0x07 line.long 0x00 "SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" line.long 0x04 "SCTM_CTDBGEVT,Counter Timer Debug Event Register" hexmask.long.byte 0x04 0.--7. 1. "INPSEL,Index of event input signal on the module boundary" group.long 0xF0++0x03 line.long 0x00 "SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" repeat 2. (list 6. 7. ) tree "Channel_$1" rgroup.long 0x198++0x03 line.long 0x00 "SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the moduel" group.long 0x58++0x03 line.long 0x00 "SCTM_TINTVLR_i_6,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end repeat.end repeat 4. (list 2. 3. 4. 5. ) tree "Channel_$1" rgroup.long 0x188++0x03 line.long 0x00 "SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the moduel" group.long 0x110++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_2,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x48++0x03 line.long 0x00 "SCTM_TINTVLR_i_2,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end repeat.end repeat 2. (list 0. 1. ) tree "Channel_$1" rgroup.long 0x180++0x03 line.long 0x00 "SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the moduel" group.long 0x108++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x100++0x03 line.long 0x00 "SCTM_CTCR_WT_m_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x40++0x03 line.long 0x00 "SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end repeat.end tree.end tree "EVE2_SCTM" base ad:0x42185000 group.long 0x00++0x03 line.long 0x00 "SCTM_CTCNTL," rbitfld.long 0x00 26.--31. "NUMSTM,Number of timers that can export through STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 18.--25. 1. "NUMINPT,Number of event input signals" rbitfld.long 0x00 13.--17. "NUMTIMR,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 7.--12. "NUMCNTR,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 3.--6. "REVID,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. "IDLEMODE,Idle mode control" "0,1,2,3" bitfld.long 0x00 0. "ENBL,SCTM global enable - DISABLE" "ENBL_0,ENBL_1" group.long 0x20++0x0F line.long 0x00 "SCTM_CTSTMCNTL,This register contains the control and status settings for STM export" rbitfld.long 0x00 10. "XPORTACT,Indicates if a frame is currently being written to the STM" "0,1" bitfld.long 0x00 5.--9. "NUMXPORT,The total number of counters designated for export" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4. "CCMXPORT,SW control of CCM message export" "0,1" rbitfld.long 0x00 3. "CCMVAIL,SCTM supports CCM export" "0,1" bitfld.long 0x00 2. "CSMXPORT,SW control of CSM message export" "0,1" bitfld.long 0x00 1. "SENDOVR,Send overflow data in CSM frame" "0,1" bitfld.long 0x00 0. "ENBL,STM global enable - DISABLE" "ENBL_0,ENBL_1" line.long 0x04 "SCTM_CTSTMMSTID," hexmask.long.byte 0x04 0.--6. 1. "MASTID,HW Master ID for this module" line.long 0x08 "SCTM_CTSTMINTVL," hexmask.long.word 0x08 0.--15. 1. "INTERVAL,Periodic export interval" line.long 0x0C "SCTM_CTSTMSEL,These registers mark the counters selected for export in the CSM" rgroup.long 0x7C++0x07 line.long 0x00 "SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x00 0.--2. "NUMEVT,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" line.long 0x04 "SCTM_CTDBGEVT,Counter Timer Debug Event Register" hexmask.long.byte 0x04 0.--7. 1. "INPSEL,Index of event input signal on the module boundary" group.long 0xF0++0x03 line.long 0x00 "SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "ENABLE,The counter enable bit field" group.long 0xF8++0x03 line.long 0x00 "SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x00 0.--7. 1. "RESET,The counter reset bit field" repeat 2. (list 6. 7. ) tree "Channel_$1" rgroup.long 0x198++0x03 line.long 0x00 "SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the moduel" group.long 0x58++0x03 line.long 0x00 "SCTM_TINTVLR_i_6,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end repeat.end repeat 4. (list 2. 3. 4. 5. ) tree "Channel_$1" rgroup.long 0x188++0x03 line.long 0x00 "SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the moduel" group.long 0x110++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_2,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x48++0x03 line.long 0x00 "SCTM_TINTVLR_i_2,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end repeat.end repeat 2. (list 0. 1. ) tree "Channel_$1" rgroup.long 0x180++0x03 line.long 0x00 "SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the moduel" group.long 0x108++0x03 line.long 0x00 "SCTM_CTCR_WOT_n_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x100++0x03 line.long 0x00 "SCTM_CTCR_WT_m_0,These registers contain the control and status settings for a single counter in the module" bitfld.long 0x00 16.--20. "INPSEL,Counter Timer input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "RESTART,Restart the timer after an interval match" "0,1" bitfld.long 0x00 9. "DBG,Signal debug logic on interval match" "0,1" bitfld.long 0x00 8. "INT,Generate interrupt on interval match" "0,1" rbitfld.long 0x00 6. "OVRFLW,Counter has wrapped since it was last" "0,1" bitfld.long 0x00 5. "IDLE,Counter ignores processor IDLE state" "0,1" bitfld.long 0x00 4. "FREE,Counter ignores processor debug halt state" "0,1" bitfld.long 0x00 3. "DURMODE,Counter is in duration or occurrence mode" "0,1" bitfld.long 0x00 2. "CHAIN,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x00 1. "RESET,Counter reset control" "0,1" newline bitfld.long 0x00 0. "ENBL,Counter enable control" "0,1" group.long 0x40++0x03 line.long 0x00 "SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" tree.end repeat.end tree.end tree "EVE1_SMSET" base ad:0x42088000 tree "Channel_1" repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) group.long ($2+0x30)++0x03 line.long 0x00 "SMSET_SEDEN_i_$1,System Event Detection Enable register 1" bitfld.long 0x00 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x00 30. "EVENT31EN,Event 31 detection enable" "0,1" newline bitfld.long 0x00 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x00 28. "EVENT29EN,Event 29 detection enable" "0,1" newline bitfld.long 0x00 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x00 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x00 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x00 24. "EVENT25EN,Event 25 detection enable" "0,1" newline bitfld.long 0x00 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x00 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x00 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x00 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x00 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x00 18. "EVENT19EN,Event 19 detection enable" "0,1" newline bitfld.long 0x00 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x00 16. "EVENT17EN,Event 17 detection enable" "0,1" newline bitfld.long 0x00 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x00 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x00 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x00 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x00 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x00 10. "EVENT11EN,Event 11 detection enable" "0,1" newline bitfld.long 0x00 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x00 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x00 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x00 6. "EVENT7EN,Event 7 detection enable" "0,1" newline bitfld.long 0x00 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x00 4. "EVENT5EN,Event 5 detection enable" "0,1" newline bitfld.long 0x00 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x00 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x00 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x00 0. "EVENT1EN,Event 1 detection enable" "0,1" repeat.end tree.end group.long 0x24++0x03 line.long 0x00 "SMSET_CFG,SMSET Configuration register" bitfld.long 0x00 30.--31. "OWNERSHIP,Read to get current ownership status" "OWNERSHIP_0,OWNERSHIP_1,OWNERSHIP_2,OWNERSHIP_3" bitfld.long 0x00 29. "DEBUGGEROVERRIDE,Reading from the DebuggerOverride bit returns a 1" "DEBUGGEROVERRIDE_0,DEBUGGEROVERRIDE_1" rbitfld.long 0x00 28. "CURRENTOWNER,This value reflects the SMSET ownership when the register is in a non-Available state" "CURRENTOWNER_0,CURRENTOWNER_1" bitfld.long 0x00 7. "CAPTUREEN,When high the sytem event capture is enabled" "CAPTUREEN_0,CAPTUREEN_1" newline bitfld.long 0x00 4. "EVENTLEVEL,This applies to all selected events" "EVENTLEVEL_0,EVENTLEVEL_1" bitfld.long 0x00 3. "EVENTMSG,essage generated based on" "EVENTMSG_0,EVENTMSG_1" bitfld.long 0x00 2. "STOP,Stop capturing system events from external trigger detection [EMU1 HIGH to LOW]" "STOP_0,STOP_1" bitfld.long 0x00 1. "START,Start capturing system events from external trigger detection [EMU0 HIGH to LOW]" "START_0,START_1" rgroup.long 0x00++0x03 line.long 0x00 "SMSET_ID,SMSET identification register" group.long 0x10++0x03 line.long 0x00 "SMSET_SCFG,SMSET system configuration register" rbitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Triggers System Event Trace module reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x28++0x03 line.long 0x00 "SMSET_SESW,System Event Sampling Window register" hexmask.long.byte 0x00 0.--7. 1. "SAMPLINGWINDOWSIZE,System events sampling window size expressed as SMSET cycles" rgroup.long 0x14++0x03 line.long 0x00 "SMSET_SR,SMSET Status Register" bitfld.long 0x00 9. "SWFIFOEMPTY,SW message FIFO empty" "SWFIFOEMPTY_0,SWFIFOEMPTY_1" bitfld.long 0x00 8. "HWFIFOEMPTY,System event trace FIFO empty" "HWFIFOEMPTY_0,HWFIFOEMPTY_1" bitfld.long 0x00 0. "RESETDONE,Reset completed" "RESETDONE_0,RESETDONE_1" tree.end tree "EVE2_SMSET" base ad:0x42188000 tree "Channel_1" repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) group.long ($2+0x30)++0x03 line.long 0x00 "SMSET_SEDEN_i_$1,System Event Detection Enable register 1" bitfld.long 0x00 31. "EVENT32EN,Event 32 detection enable" "0,1" bitfld.long 0x00 30. "EVENT31EN,Event 31 detection enable" "0,1" newline bitfld.long 0x00 29. "EVENT30EN,Event 30 detection enable" "0,1" bitfld.long 0x00 28. "EVENT29EN,Event 29 detection enable" "0,1" newline bitfld.long 0x00 27. "EVENT28EN,Event 28 detection enable" "0,1" bitfld.long 0x00 26. "EVENT27EN,Event 27 detection enable" "0,1" newline bitfld.long 0x00 25. "EVENT26EN,Event 26 detection enable" "0,1" bitfld.long 0x00 24. "EVENT25EN,Event 25 detection enable" "0,1" newline bitfld.long 0x00 23. "EVENT24EN,Event 24 detection enable" "0,1" bitfld.long 0x00 22. "EVENT23EN,Event 23 detection enable" "0,1" newline bitfld.long 0x00 21. "EVENT22EN,Event 22 detection enable" "0,1" bitfld.long 0x00 20. "EVENT21EN,Event 21 detection enable" "0,1" newline bitfld.long 0x00 19. "EVENT20EN,Event 20 detection enable" "0,1" bitfld.long 0x00 18. "EVENT19EN,Event 19 detection enable" "0,1" newline bitfld.long 0x00 17. "EVENT18EN,Event 18 detection enable" "0,1" bitfld.long 0x00 16. "EVENT17EN,Event 17 detection enable" "0,1" newline bitfld.long 0x00 15. "EVENT16EN,Event 16 detection enable" "0,1" bitfld.long 0x00 14. "EVENT15EN,Event 15 detection enable" "0,1" newline bitfld.long 0x00 13. "EVENT14EN,Event 14 detection enable" "0,1" bitfld.long 0x00 12. "EVENT13EN,Event 13 detection enable" "0,1" newline bitfld.long 0x00 11. "EVENT12EN,Event 12 detection enable" "0,1" bitfld.long 0x00 10. "EVENT11EN,Event 11 detection enable" "0,1" newline bitfld.long 0x00 9. "EVENT10EN,Event 10 detection enable" "0,1" bitfld.long 0x00 8. "EVENT9EN,Event 9 detection enable" "0,1" newline bitfld.long 0x00 7. "EVENT8EN,Event 8 detection enable" "0,1" bitfld.long 0x00 6. "EVENT7EN,Event 7 detection enable" "0,1" newline bitfld.long 0x00 5. "EVENT6EN,Event 6 detection enable" "0,1" bitfld.long 0x00 4. "EVENT5EN,Event 5 detection enable" "0,1" newline bitfld.long 0x00 3. "EVENT4EN,Event 4 detection enable" "0,1" bitfld.long 0x00 2. "EVENT3EN,Event 3 detection enable" "0,1" newline bitfld.long 0x00 1. "EVENT2EN,Event 2 detection enable" "0,1" bitfld.long 0x00 0. "EVENT1EN,Event 1 detection enable" "0,1" repeat.end tree.end group.long 0x24++0x03 line.long 0x00 "SMSET_CFG,SMSET Configuration register" bitfld.long 0x00 30.--31. "OWNERSHIP,Read to get current ownership status" "OWNERSHIP_0,OWNERSHIP_1,OWNERSHIP_2,OWNERSHIP_3" bitfld.long 0x00 29. "DEBUGGEROVERRIDE,Reading from the DebuggerOverride bit returns a 1" "DEBUGGEROVERRIDE_0,DEBUGGEROVERRIDE_1" rbitfld.long 0x00 28. "CURRENTOWNER,This value reflects the SMSET ownership when the register is in a non-Available state" "CURRENTOWNER_0,CURRENTOWNER_1" bitfld.long 0x00 7. "CAPTUREEN,When high the sytem event capture is enabled" "CAPTUREEN_0,CAPTUREEN_1" newline bitfld.long 0x00 4. "EVENTLEVEL,This applies to all selected events" "EVENTLEVEL_0,EVENTLEVEL_1" bitfld.long 0x00 3. "EVENTMSG,essage generated based on" "EVENTMSG_0,EVENTMSG_1" bitfld.long 0x00 2. "STOP,Stop capturing system events from external trigger detection [EMU1 HIGH to LOW]" "STOP_0,STOP_1" bitfld.long 0x00 1. "START,Start capturing system events from external trigger detection [EMU0 HIGH to LOW]" "START_0,START_1" rgroup.long 0x00++0x03 line.long 0x00 "SMSET_ID,SMSET identification register" group.long 0x10++0x03 line.long 0x00 "SMSET_SCFG,SMSET system configuration register" rbitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Triggers System Event Trace module reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x28++0x03 line.long 0x00 "SMSET_SESW,System Event Sampling Window register" hexmask.long.byte 0x00 0.--7. 1. "SAMPLINGWINDOWSIZE,System events sampling window size expressed as SMSET cycles" rgroup.long 0x14++0x03 line.long 0x00 "SMSET_SR,SMSET Status Register" bitfld.long 0x00 9. "SWFIFOEMPTY,SW message FIFO empty" "SWFIFOEMPTY_0,SWFIFOEMPTY_1" bitfld.long 0x00 8. "HWFIFOEMPTY,System event trace FIFO empty" "HWFIFOEMPTY_0,HWFIFOEMPTY_1" bitfld.long 0x00 0. "RESETDONE,Reset completed" "RESETDONE_0,RESETDONE_1" tree.end tree "EVE2" base ad:0x42100000 rgroup.long 0x80000++0x2F line.long 0x00 "EVE_REVISION," line.long 0x04 "EVE_HWINFO," hexmask.long 0x04 4.--31. 1. "INFO," bitfld.long 0x04 0.--3. "EVENUM,EVE instance number set by eve_num inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_SYSCONFIG," bitfld.long 0x08 4.--5. "STANDBYMODE," "0,1,2,3" bitfld.long 0x08 2.--3. "IDLEMODE," "0,1,2,3" rbitfld.long 0x08 1. "FREEEMU,Resered" "0,1" newline rbitfld.long 0x08 0. "SOFTRESET,Reserved" "0,1" line.long 0x0C "EVE_STAT," bitfld.long 0x0C 20.--21. "OCPI_DISC_STAT,OCP Initiator(s) Disconnect status2" "OCPI_DISC_STAT_0,OCPI_DISC_STAT_1,?,?" bitfld.long 0x0C 16.--17. "ARP32_DISC_STATUS,ARP32 Program/Data Bus Disconnect Status" "ARP32_DISC_STATUS_0,ARP32_DISC_STATUS_1,?,?" bitfld.long 0x0C 8. "INT_OUT_STAT,Interrupt Output status" "INT_OUT_STAT_0,INT_OUT_STAT_1" newline bitfld.long 0x0C 7. "ARP_INTC_STAT,Interrupt Controller Status" "ARP_INTC_STAT_0,ARP_INTC_STAT_1" bitfld.long 0x0C 5. "TC1_STAT,Transfer Controller1 Status" "TC1_STAT_0,TC1_STAT_1" bitfld.long 0x0C 4. "TC0_STAT,Transfer Controller0 Status" "TC0_STAT_0,TC0_STAT_1" newline bitfld.long 0x0C 2. "PC_STAT,Program Cache Status" "PC_STAT_0,PC_STAT_1" bitfld.long 0x0C 1. "VCOP_STAT,VCOP Status" "VCOP_STAT_0,VCOP_STAT_1" bitfld.long 0x0C 0. "ARP32_STAT,Program Cache Status" "ARP32_STAT_0,ARP32_STAT_1" line.long 0x10 "EVE_DISC_CONFIG,Color 0 noise threshold" bitfld.long 0x10 4. "OCPI_DISC,OCP Initiator Disconnect request" "OCPI_DISC_0_r,OCPI_DISC_1_w" bitfld.long 0x10 0. "ARP32_DISC,ARP32 Initiator Disconnect request" "?,ARP32_DISC_1_r" line.long 0x14 "EVE_BUS_CONFIG,Color 0 noise threshold" bitfld.long 0x14 12.--13. "TC1_DBS,TC1 default burst size" "0,1,2,3" bitfld.long 0x14 8.--9. "TC0_DBS,TC0 default burst size" "0,1,2,3" bitfld.long 0x14 4. "DBP_ENABLE,Program Cache Demand Based Prefetch enable" "DBP_ENABLE_0,DBP_ENABLE_1" newline bitfld.long 0x14 0.--3. "MAX_IN_FLIGHT,Defines maximum number of OCP requests in flight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EVE_VCOP_HALT_CONFIG," bitfld.long 0x18 2. "FORCE_ABORT,VCOP Force Abort Write: Read always returns" "?,FORCE_ABORT_1_w" bitfld.long 0x18 1. "MSW_EN,VCOP Memory Seitch Error Halt Enable" "MSW_EN_0,MSW_EN_1" bitfld.long 0x18 0. "ED_EN,VCOP Parity Error Detect Halt Enable" "ED_EN_0,ED_EN_1" line.long 0x1C "EVE_MMU_CONFIG," bitfld.long 0x1C 12. "MMU1_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" bitfld.long 0x1C 8. "MMU0_ABORT,Causes the MMU to abort the current operation in case of lockup" "0,1" bitfld.long 0x1C 4. "MMU1_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" newline bitfld.long 0x1C 0. "MMU0_EN,Clearing this bit disables MMU table lookup and causes accesses to use the non-translated address" "0,1" line.long 0x20 "EVE_MEMMAP," bitfld.long 0x20 4. "LCL_EDMA_ALIAS," "?,LCL_EDMA_ALIAS_1" bitfld.long 0x20 0. "VCOP_ALIAS," "?,VCOP_ALIAS_1" line.long 0x24 "EVE_MSW_CTL,Memory switch control register" bitfld.long 0x24 16. "WBUF,Working buffer onwership" "WBUF_0,WBUF_1" bitfld.long 0x24 12. "IBUFHB,Image buffer high B ownership" "IBUFHB_0,IBUFHB_1" bitfld.long 0x24 8. "IBUFLB,Image buffer low B ownership" "IBUFLB_0,IBUFLB_1" newline bitfld.long 0x24 4. "IBUFHA,Image buffer high A ownership" "IBUFHA_0,IBUFHA_1" bitfld.long 0x24 0. "IBUFLA,Image buffer low A ownership" "IBUFLA_0,IBUFLA_1" line.long 0x28 "EVE_MSW_ERR,Memory Switch Error register" hexmask.long.word 0x28 16.--24. 1. "CONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x28 3. "SYSERR," "0,1" bitfld.long 0x28 2. "DMAERR," "0,1" newline bitfld.long 0x28 1. "VERR," "0,1" bitfld.long 0x28 0. "ARP32ERR," "0,1" line.long 0x2C "EVE_MSW_ERRADDR,Memory switch error address register" group.long 0x80040++0x03 line.long 0x00 "EVE_PC_INV,Invalidate all register" bitfld.long 0x00 0. "I,Invalidate all" "I_0_w,?" group.long 0x80050++0x17 line.long 0x00 "EVE_PC_IBAR,Invalidate Base Address register" line.long 0x04 "EVE_PC_IBC,Invalidate byte count register" hexmask.long.word 0x04 0.--15. 1. "BC,Invalidate Byte Count register" line.long 0x08 "EVE_PC_ISAR,Invalidate single address register" line.long 0x0C "EVE_PC_ISAR_DONE,Invalidate single address done register" bitfld.long 0x0C 0. "DONE,Reads return 0x1 when the invalidate operation is complete" "0,1" line.long 0x10 "EVE_PC_PBAR,Program cache preload base address register" line.long 0x14 "EVE_PC_PBC," hexmask.long.word 0x14 0.--15. 1. "BC,Preload Byte Count register" group.long 0x80080++0x0B line.long 0x00 "EVE_PMEM_ED_CTL,Program Memory Error Detection Control register" bitfld.long 0x00 1. "INV," "0,1" bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_PMEM_ED_STAT,Error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x04 3. "SYSERR," "0,1" bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_PMEM_EDADDR,Program memory error detection address" group.long 0x80090++0x2F line.long 0x00 "EVE_DMEM_ED_CTL,DMEM error detection control" bitfld.long 0x00 1. "INV," "0,1" bitfld.long 0x00 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x04 "EVE_DMEM_ED_STAT,DMEM error detection status register" hexmask.long.word 0x04 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x04 3. "SYSERR," "0,1" bitfld.long 0x04 2. "DMAERR," "0,1" newline bitfld.long 0x04 1. "VERR," "0,1" bitfld.long 0x04 0. "ARP32ERR," "0,1" line.long 0x08 "EVE_DMEM_EDADDR,DMEM error detection address register" line.long 0x0C "EVE_DMEM_EDADDR_BO,DMEM error detection address byte offset register" line.long 0x10 "EVE_WBUF_ED_CTL,WBUF error detection control" bitfld.long 0x10 1. "INV," "0,1" bitfld.long 0x10 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x14 "EVE_WBUF_ED_STAT,WBUF error detection status register" hexmask.long.word 0x14 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x14 3. "SYSERR," "0,1" bitfld.long 0x14 2. "DMAERR," "0,1" newline bitfld.long 0x14 1. "VERR," "0,1" bitfld.long 0x14 0. "ARP32ERR," "0,1" line.long 0x18 "EVE_WBUF_EDADDR,WBUF error detection address register" line.long 0x1C "EVE_WBUF_EDADDR_BO,WBUF error detection address byte offset register" line.long 0x20 "EVE_IBUF_ED_CTL,IBUF error detection control" bitfld.long 0x20 1. "INV," "0,1" bitfld.long 0x20 0. "EN,Error detection logic enable" "EN_0,EN_1" line.long 0x24 "EVE_IBUF_ED_STAT,IBUF error detection status register" hexmask.long.word 0x24 16.--24. 1. "SYSCONNID,Reads: OCP CONNID value for OCP request that results in buffer ownership error" bitfld.long 0x24 3. "SYSERR," "0,1" bitfld.long 0x24 2. "DMAERR," "0,1" newline bitfld.long 0x24 1. "VERR," "0,1" bitfld.long 0x24 0. "ARP32ERR," "0,1" line.long 0x28 "EVE_IBUF_EDADDR,IBUF error detection address register" line.long 0x2C "EVE_IBUF_EDADDR_BO,IBUF error detection address byte offset register" group.long 0x800F8++0x07 line.long 0x00 "EVE_ED_ARP32_DISC_EN,ARP32 disconnect enable register" hexmask.long.word 0x00 0.--15. 1. "ENABLE,Disconnect Enable for Event #n" line.long 0x04 "EVE_ED_OCPI_DISC_EN,OCP interface disconnect enable register" hexmask.long.word 0x04 0.--15. 1. "ENABLE,Disconnect Enable for Event #n" group.long 0x80110++0x1F line.long 0x00 "EVE_MSW_ERR_IRQSTATUS_RAW,Per event memory switch error interrupt status register" bitfld.long 0x00 0.--3. "EVENT,settable raw status for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EVE_MSW_ERR_IRQSTATUS,Memory switch error interrupt status register" bitfld.long 0x04 0.--3. "EVENT,Clearable / enabled status for event #N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_MSW_ERR_IRQENABLE_SET,Memory switch error interrupt enable register" bitfld.long 0x08 0.--3. "ENABLE,Enable for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EVE_MSW_ERR_IRQENABLE_CLR,Memory switch error interrupt clear register" bitfld.long 0x0C 0.--3. "ENABLE,Enable for event #n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EVE_ED_LCL_IRQSTATUS_RAW,Per event error detection local interrupt status register" hexmask.long.word 0x10 0.--15. 1. "EVENT,settable raw status for event #n" line.long 0x14 "EVE_ED_LCL_IRQSTATUS,Error detection local interrupt status register" hexmask.long.word 0x14 0.--15. 1. "EVENT,Clearable / enabled status for event #N" line.long 0x18 "EVE_ED_LCL_IRQENABLE_SET,Error detection local interrupt enable register" hexmask.long.word 0x18 0.--15. 1. "ENABLE,Enable for event #n" line.long 0x1C "EVE_ED_LCL_IRQENABLE_CLR,Error detection local interrupt clear register" hexmask.long.word 0x1C 0.--15. 1. "ENABLE,Enable for event #n" group.long 0x80200++0x0F line.long 0x00 "ARP32_NMI_IRQSTATUS_RAW," line.long 0x04 "ARP32_NMI_IRQSTATUS," line.long 0x08 "ARP32_NMI_IRQENABLE_SET," line.long 0x0C "ARP32_NMI_IRQENABLE_CLR," group.long 0x802FC++0x03 line.long 0x00 "ARP32_IRQWAKEEN,Wake enable register" hexmask.long.tbyte 0x00 0.--23. 1. "ENABLE,Wakeup Enable for event EVE_EVT_INT #n" group.long 0x80400++0x07 line.long 0x00 "MISR_CTL," bitfld.long 0x00 0.--2. "ENABLE,MISR Enable #N" "0,1,2,3,4,5,6,7" line.long 0x04 "MISR_CLEAR," bitfld.long 0x04 0.--2. "CLEAR,MISR Clear #N" "0,1,2,3,4,5,6,7" group.long 0x80410++0x0F line.long 0x00 "MISR0_A," line.long 0x04 "MISR0_D," line.long 0x08 "MISR1_A," line.long 0x0C "MISR1_D," group.long 0x80500++0x03 line.long 0x00 "EVE_IRQ_EOI," bitfld.long 0x00 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1,2,3,4,5,6,7" group.long 0x80510++0x0F line.long 0x00 "EVE_ED_OUT_IRQSTATUS_RAW," hexmask.long.word 0x00 0.--15. 1. "EVENT,Settable raw status for event #n" line.long 0x04 "EVE_ED_OUT_IRQSTATUS," hexmask.long.word 0x04 0.--15. 1. "EVENT,Clearable / enabled status for event #N" line.long 0x08 "EVE_ED_OUT_IRQENABLE_SET," hexmask.long.word 0x08 0.--15. 1. "ENABLE,Enable for event #n" line.long 0x0C "EVE_ED_OUT_IRQENABLE_CLR," hexmask.long.word 0x0C 0.--15. 1. "ENABLE,Enable for event #n" rgroup.long 0x80680++0x1F line.long 0x00 "ARP32_INT14_IRQSTATUS_RAW," line.long 0x04 "ARP32_INT14_IRQSTATUS," line.long 0x08 "ARP32_INT14_IRQENABLE_SET," line.long 0x0C "ARP32_INT14_IRQENABLE_CLR," line.long 0x10 "ARP32_INT15_IRQSTATUS_RAW," line.long 0x14 "ARP32_INT15_IRQSTATUS," line.long 0x18 "ARP32_INT15_IRQENABLE_SET," line.long 0x1C "ARP32_INT15_IRQENABLE_CLR," group.long 0x80780++0x07 line.long 0x00 "EVE_CME_DONE_GPOUT," hexmask.long.byte 0x00 0.--7. 1. "EVENT,Internal CME Done Output #n" line.long 0x04 "EVE_CME_DONE_GPOUT_SET," hexmask.long.byte 0x04 0.--7. 1. "EVENT,Internal CME Done #n" group.long 0x8078C++0x0B line.long 0x00 "EVE_CME_DONE_GPOUT_PULSE," hexmask.long.byte 0x00 0.--7. 1. "EVENT,Internal CME Done #n" line.long 0x04 "EVE_CME_DONE_SEL," bitfld.long 0x04 28.--31. "SEL7,CME Done Output select for Bit #7 (n=7)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. "SEL6,CME Done Output select for Bit #6 (n=6)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. "SEL5,CME Done Output select for Bit #5 (n=5)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 16.--19. "SEL4,CME Done Output select for Bit #4 (n=4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 12.--15. "SEL3,CME Done Output select for Bit #3 (n=3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. "SEL2,CME Done Output select for Bit #2 (n=2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. "SEL1,CME Done Output select for Bit #1 (n=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "SEL0,CME Done Output select for Bit #0 (n=0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EVE_CME_DONE_EN," hexmask.long.byte 0x08 0.--7. 1. "EN,EVE CME Done EN #n" rgroup.long 0x80FE0++0x0B line.long 0x00 "EVE_PM_STAT0," bitfld.long 0x00 28.--30. "OCPM1_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--25. "OCPM1_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 20.--22. "OCPM0_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--17. "OCPM0_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 12.--14. "OCPS_SCONNECT,Readable state of OCP Power management handshake" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--9. "OCPS_MCONNECT,Readable state of OCP Power management handshake" "0,1,2,3" newline bitfld.long 0x00 5. "MWAIT,Readable state of OCP Power management handshake" "0,1" bitfld.long 0x00 4. "MSTANDBY,Readable state of OCP Power management handshake" "0,1" bitfld.long 0x00 3. "SWAKEUP,Readable state of OCP Power management handshake" "0,1" newline bitfld.long 0x00 1.--2. "SIDLEACK,Readable state of OCP Power management handshake" "0,1,2,3" bitfld.long 0x00 0. "SIDLEREQ,Readable state of OCP Power management handshake" "0,1" line.long 0x04 "EVE_PM_STAT1," rbitfld.long 0x04 22.--23. "STBY_MDISCACK_OCPM1,Readable state of internal power management handshake" "0,1,2,3" rbitfld.long 0x04 20.--21. "STBY_MDISCACK_OCPM0,Readable state of internal power management handshake" "0,1,2,3" rbitfld.long 0x04 19. "STBY_MDISCREQ_OCPM1,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 18. "STBY_MDISCREQ_OCPM0,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 17. "IDLE_SDISCONNECT_ACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 16. "IDLE_SDISCONNECT_REQ,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 15. "EVE_IDLE_INTR_DISABLE,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 14. "TPTC1_MWAIT,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 13. "TPTC0_MWAIT,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 12. "EVE_PCACHE_OCP_BUSY,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 11. "EVE_CONTROL_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 10. "SMSET_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 9. "L2_EVE_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 8. "MMU1_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 7. "MMU1_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 6. "MMU0_CONFIG_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 5. "MMU0_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 4. "SCTM_SIDLEACK,Readable state of internal power management handshake" "0,1" newline rbitfld.long 0x04 3. "TPCC_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 2. "TPTC1_SIDLEACK,Readable state of internal power management handshake" "0,1" rbitfld.long 0x04 1. "TPTC0_SIDLEACK,Readable state of internal power management handshake" "0,1" newline bitfld.long 0x04 0. "SUBMODULE_IDLE_REQ," "0,1" line.long 0x08 "EVE_DBGOUT," hexmask.long.tbyte 0x08 8.--31. 1. "VALUE,Read returns state of eve_dbgout bus" bitfld.long 0x08 0.--3. "GROUP,Debug Group Output control : mux select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80FFC++0x03 line.long 0x00 "EVE_TEST," group.long 0x3DF780788++0x03 line.long 0x00 "EVE_CME_DONE_GPOUT_CLR," hexmask.long.byte 0x00 0.--7. 1. "EVENT,Internal CME Done #n" repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x80FF4)++0x03 line.long 0x00 "EVE_RSVD$1," repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0x80740)++0x03 line.long 0x00 "EVE_GPIN$1," repeat.end repeat 4. (list 10. 11. 12. 13. ) tree "IRQ_Line_$1" group.long 0x8062C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_10," group.long 0x80628++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_10," group.long 0x80624++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_10," rgroup.long 0x80620++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_10," tree.end repeat.end repeat 2. (list 8. 9. ) tree "IRQ_Line_$1" group.long 0x8060C++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_CLR_8," group.long 0x80608++0x03 line.long 0x00 "ARP32_INTj_IRQENABLE_SET_8," group.long 0x80604++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_8," rgroup.long 0x80600++0x03 line.long 0x00 "ARP32_INTj_IRQSTATUS_RAW_8," group.long 0x80320++0x03 line.long 0x00 "MMR_LOCKi_8,MMR Lock/Unlock register" tree.end repeat.end repeat 4. (list 4. 5. 6. 7. ) tree "IRQ_Line_$1" group.long 0x8021C++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_CLR_4," group.long 0x80218++0x03 line.long 0x00 "ARP32_INTn_IRQENABLE_SET_4," group.long 0x80214++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_4," group.long 0x80210++0x03 line.long 0x00 "ARP32_INTn_IRQSTATUS_RAW_4," group.long 0x80310++0x03 line.long 0x00 "MMR_LOCKi_4,MMR Lock/Unlock register" tree.end repeat.end repeat 2. (list 2. 3. ) tree "IRQ_Line_$1" group.long 0x8054C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_2," group.long 0x80548++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_2," group.long 0x80544++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_2," group.long 0x80540++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_2," group.long 0x80428++0x03 line.long 0x00 "MISR2_Dk_2," group.long 0x80308++0x03 line.long 0x00 "MMR_LOCKi_2,MMR Lock/Unlock register" tree.end repeat.end repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x80700++0x03 line.long 0x00 "EVE_GPOUTm_0," group.long 0x80708++0x07 line.long 0x00 "EVE_GPOUTm_CLR_0," line.long 0x04 "EVE_GPOUTm_PULSE_0," group.long 0x80704++0x03 line.long 0x00 "EVE_GPOUTm_SET_0," group.long 0x8052C++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_CLR_0," group.long 0x80528++0x03 line.long 0x00 "EVE_INTk_OUT_IRQENABLE_SET_0," group.long 0x80524++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_0," group.long 0x80520++0x03 line.long 0x00 "EVE_INTk_OUT_IRQSTATUS_RAW_0," group.long 0x80420++0x03 line.long 0x00 "MISR2_Dk_0," group.long 0x80300++0x03 line.long 0x00 "MMR_LOCKi_0,MMR Lock/Unlock register" tree.end repeat.end tree.end autoindent.off tree "EVE1_ARP32_DEBUG" base ad:0x42083000 width 10. base ad:0x42083000 tree "Control and Status Registers" rgroup.long 0x00++0x03 line.long 0x00 "DBG_CAP,Debug Capability Register" bitfld.long 0x00 29. " DBG_WP_DATA_SUP ,Specifies if data qualification is supported by the Watchpoint resources" "Not supported,Supported" bitfld.long 0x00 28. " DBG_OWN_SUP ,Specifies if Module Ownership is supported" "Not supported,Supported" bitfld.long 0x00 27. " DBG_INDIRECT_SUP ,Specifies if Indirect Memory access mechanism is supported" "Not supported,Supported" textline " " bitfld.long 0x00 26. " DBG_SWBP_SUP ,Specifies if Software Breakpoint is supported" "Not supported,Supported" bitfld.long 0x00 25. " DBG_RESET_SUP ,Specifies if debug initiated functional reset to CPU core is supported" "Not supported,Supported" bitfld.long 0x00 24. " SYS_EXE_REQ_SUP ,Specifies if Core Execution status change is supported" "Not supported,Supported" textline " " bitfld.long 0x00 23. " TRIG_OUTPUT_SUP ,Specifies if Trigger output is supported" "Not supported,Supported" bitfld.long 0x00 22. " TRIG_INPUT_SUP ,Specifies if Trigger input is supported" "Not supported,Supported" bitfld.long 0x00 20.--21. " NUM_TRIG_CHNS ,Specifies number of trigger channels supported" "0,1,2,3" textline " " bitfld.long 0x00 16.--19. " NUM_CNTRS ,Specifies number of counters supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " NUM_HWWPS ,Specifies number of Hardware Watchpoints supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NUM_HWBPS ,Specifies number of Hardware Breakpoints supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " REV_MAJ ,Specifies the major revision id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV_MIN ,Specifies the minor revision id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x04++0x03 line.long 0x00 "DBG_CNTL,Debug Control Register" bitfld.long 0x00 27. " DBG_HALT_FATAL ,This bit indicates that CPU is halted due to FATAL system error" "Executing,Halted" eventfld.long 0x00 26. " DBG_RESET_OCC ,This is a sticky bit indicating a functional reset has been seen/active at CPU core since it was cleared" "Not occurred,Occurred" bitfld.long 0x00 25. " DBG_RESET_REQ ,This bit is used to generate a debug initiated functional reset to CPU core and the external sub-system via CPU output port" "No reset,Reset" textline " " rbitfld.long 0x00 24. " DBG_CPU_IDLE_STATUS ,Indicates IDLE status of CPU" "Not idle,Idle" bitfld.long 0x00 20.--23. " DBG_EMU1_CNTL ,EMU1 pin/channel output control" "No output,Pulse on CPU halt,Pulse when any HWBP triggers,Pulse when any HWWP triggers,Drive pin HIGH,Drive pin LOW,?..." bitfld.long 0x00 16.--19. " DBG_EMU0_CNTL ,EMU0 pin/channel output control" "No output,Pulse on CPU halt,Pulse when any HWBP triggers,Pulse when any HWWP triggers,Drive pin HIGH,Drive pin LOW,?..." textline " " rbitfld.long 0x00 15. " DBG_STAT_EMU1 ,Status of EMU1 input pin" "0,1" rbitfld.long 0x00 14. " DBG_STAT_EMU0 ,Status of EMU0 input pin" "0,1" rbitfld.long 0x00 13. " DBG_HALT_EMU1 ,CPU halted due to input trigger on EMU1" "Executing,Halted" textline " " rbitfld.long 0x00 12. " DBG_HALT_EMU0 ,CPU halted due to input trigger on EMU0" "Executing,Halted" rbitfld.long 0x00 11. " DBG_HALT_USER ,CPU halted due to Manual Halt via DBG_CNTL register" "Executing,Halted" rbitfld.long 0x00 10. " DBG_HALT_STEP ,CPU halted due to single step completion" "Executing,Halted" textline " " rbitfld.long 0x00 9. " DBG_HALT_BPWP ,CPU halted due to trigger from HWBP/HWWP Unit" "Executing,Halted" rbitfld.long 0x00 8. " DBG_HALT_SWBP ,CPU halted due to SWBP (BKPT instruction)" "Executing,Halted" rbitfld.long 0x00 7. " DBG_EXE_STAT ,CPU execution state" "Executing,Halted" textline " " bitfld.long 0x00 6. " DBG_EMU1_EN ,Enable for CPU Halt via Input trigger on EMU1 pin" "Disabled,Enabled" bitfld.long 0x00 5. " DBG_EMU0_EN ,Enable for CPU Halt via Input trigger on EMU0 pin" "Disabled,Enabled" bitfld.long 0x00 4. " DBG_BPWP_EN ,Enable for CPU Halt via HWBP/HWWP unit trigger" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DBG_SWBP_EN ,Enable for CPU Halt via SWBP" "Disabled,Enabled" bitfld.long 0x00 2. " DBG_SINGLE_STEP_EN ,Enable for single Stepping" "Disabled,Enabled" bitfld.long 0x00 1. " DBG_RESTART_STAT ,Status bit showing CPU restarted" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DBG_HALT ,Global debug run control" "Executing,Halted" if (((d.l(ad:0x42083000+0x0C))&0x06)==0x00) group.long 0x0C++0x03 line.long 0x00 "DBG_OWN,Debug Ownership Register" bitfld.long 0x00 1.--2. " OWN ,This field shows the current ownership status" "NotOwned,DebugOwned,ApplicationOwned,Ownership not implemented" bitfld.long 0x00 0. " CLAIM ,This bit is used to obtain exclusive ownership of the debug module for either the debug initiator or the application initiator" "No effect,DebugOwned/ApplicationOwned" elif (((d.l(ad:0x42083000+0x0C))&0x06)==0x02)||(((d.l(ad:0x42083000+0x0C))&0x06)==0x04) group.long 0x0C++0x03 line.long 0x00 "DBG_OWN,Debug Ownership Register" bitfld.long 0x00 1.--2. " OWN ,This field shows the current ownership status" "NotOwned,DebugOwned,ApplicationOwned,Ownership not implemented" bitfld.long 0x00 0. " CLAIM ,This bit is used to obtain exclusive ownership of the debug module for either the debug initiator or the application initiator" "NotOwned,No effect" else group.long 0x0C++0x03 line.long 0x00 "DBG_OWN,Debug Ownership Register" bitfld.long 0x00 1.--2. " OWN ,This field shows the current ownership status" "NotOwned,DebugOwned,ApplicationOwned,Ownership not implemented" endif tree.end width 17. tree "Indirect Memory Access Control Registers" rgroup.long 0x14++0x03 line.long 0x00 "DBG_INDRCT_CAP,Debug Indirect Memory Access Capability register" bitfld.long 0x00 18.--19. " PAGE4_DATA_SIZE ,Indicates the max Data width of Page 4 is 32b" "32b,?..." bitfld.long 0x00 16.--17. " PAGE4_ADDR_SIZE ,Indicates the max Address width of Page 4 is 32b" ",32b,?..." textline " " bitfld.long 0x00 14.--15. " PAGE3_DATA_SIZE ,Indicates the max Data width of Page 3 is 32b" "32b,?..." bitfld.long 0x00 12.--13. " PAGE3_ADDR_SIZE ,Indicates the max Address width of Page 3 is 32b" ",32b,?..." textline " " bitfld.long 0x00 10.--11. " PAGE2_DATA_SIZE ,Indicates the max Data width of Page 2 is 32b" "32b,?..." bitfld.long 0x00 8.--9. " PAGE2_ADDR_SIZE ,Indicates the max Address width of Page 2 is 32b" ",32b,?..." textline " " bitfld.long 0x00 6.--7. " PAGE1_DATA_SIZE ,Indicates the max Data width of Page 1 is 32b" "32b,?..." bitfld.long 0x00 4.--5. " PAGE1_ADDR_SIZE ,Indicates the max Address width of Page 1 is 32b" ",32b,?..." textline " " bitfld.long 0x00 2.--3. " PAGE0_DATA_SIZE ,Indicates the max Data width of Page 0 is 32b" "32b,?..." bitfld.long 0x00 0.--1. " PAGE0_ADDR_SIZE ,Indicates the max Address width of Page 0 is 32b" ",32b,?..." group.long 0x18++0x07 line.long 0x00 "DBG_INDRCT_CNTL,Debug Indirect Memory Access Control Register" bitfld.long 0x00 30. " MEM_RESET_PORT ,This field causes the Indirect Memory Access Port to come back to the default/reset state" "No effect,State transition to reset" rbitfld.long 0x00 20.--23. " MEM_ERR_CODE ,This field indicates the Error codes for the last debug access" "No error,I/D mem page access error,CPU internal access error,?..." textline " " rbitfld.long 0x00 19. " MEM_BUS_STAT ,Indicates the ready status of CPU bus interface corresponding to the selected MEM_PAGE" "Not ready,Ready" rbitfld.long 0x00 18. " MEM_ERR_OVERRUN ,Indicates that a new access was requested before a previous access was completed" "No error,Overrun error" textline " " rbitfld.long 0x00 16.--17. " MEM_PORT_STAT ,Indicates the status of Indirect Memory Access Port" "Ready for next transaction,Busy doing a transaction,Transaction completed successfully,Transaction resulted in Error condition" bitfld.long 0x00 8.--10. " MEM_ACC_SIZE ,Indicates the access size of next debug access" ",8b,16b,,32b,?..." textline " " bitfld.long 0x00 4.--7. " MEM_PAGE ,Indicates the target page of next debug access" "Instruction Memory,Data Memory,CPU architectural register file,CPU control register file,CPU shadow register file,?..." bitfld.long 0x00 2. " MEM_PRIORITY ,Determines if debug access will be forced or wait" "Wait,Force" textline " " bitfld.long 0x00 1. " MEM_ADDR_INC ,Indicates Auto-incrementing Addressing mode" "No Auto-incrementing addressing,Post-Increment by access size" bitfld.long 0x00 0. " MEM_RW ,Indicates a read or write operation to be carried out via Indirect Memory Access port" "Read,Write" line.long 0x04 "DBG_INDRCT_ADDR,Debug Indirect Memory Access Address Register" group.long 0x24++0x03 line.long 0x00 "DBG_INDRCT_DATA,Debug Indirect Memory Access" tree.end width 18. tree "Hardware Breakpoint/Watchpoint Unit 0 Registers" group.long 0x40++0x07 line.long 0x00 "DBG_HWBP_0_CNTL,HWBP Unit Control Register" eventfld.long 0x00 2. " TRIGGERED ,Indicates that the HWBP Unit found a match as programmed and the designated instruction entered DEC phase of the pipeline" "No match,Match" bitfld.long 0x00 1. " HALT ,Specifies that the generated trigger should halt the CPU" "0,1" bitfld.long 0x00 0. " ENABLE ,Indicates that the HWBP Unit is enabled for operation" "Disabled,Enabled" line.long 0x04 "DBG_HWBP_0_ADDR,HWBP Unit Address Register" group.long 0x4C++0x03 line.long 0x00 "DBG_HWBP_0_AMASK,HWBP Unit Address Mask Register" group.long 0x54++0x07 line.long 0x00 "DBG_HWWP_0_CNTL,HWWP Unit Control Register" bitfld.long 0x00 12. " DATAMATCH ,Enables data value qualification in addition to addr match" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " BUSSEL ,Bussel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--7. " ACCSIZE ,Configures HWWP Unit to filter data access based on access size as follows" "Any access,Only 8bit access,Only 16b access,Only 32b access,Any access,Any access,Any access,Any access" textline " " bitfld.long 0x00 3.--4. " RDWR ,Configures HWWP Unit to filter data access based on access type as follows" "Read,Write,Read/Write,Read/Write" eventfld.long 0x00 2. " TRIGGERED ,Indicates that the HWWP Unit found a match as programmed" "No match,Match" bitfld.long 0x00 1. " HALT ,Specifies that the generated trigger should halt the CPU" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLE ,Indicates that the HWWP Unit is enabled for operation" "Disabled,Enabled" line.long 0x04 "DBG_HWWP_0_ADDR,HWWP Unit Address Register" group.long 0x60++0x03 line.long 0x00 "DBG_HWWP_0_AMASK,HWWP Unit Address Mask Register" group.long 0x68++0x03 line.long 0x00 "DBG_HWWP_0_DATA,HWWP Unit Data Register" tree.end width 18. tree "Hardware Breakpoint/Watchpoint Unit 1 Registers" group.long 0x80++0x07 line.long 0x00 "DBG_HWBP_1_CNTL,HWBP Unit Control Register" eventfld.long 0x00 2. " TRIGGERED ,Indicates that the HWBP Unit found a match as programmed and the designated instruction entered DEC phase of the pipeline" "No match,Match" bitfld.long 0x00 1. " HALT ,Specifies that the generated trigger should halt the CPU" "0,1" bitfld.long 0x00 0. " ENABLE ,Indicates that the HWBP Unit is enabled for operation" "Disabled,Enabled" line.long 0x04 "DBG_HWBP_0_ADDR,HWBP Unit Address Register" group.long 0x8C++0x03 line.long 0x00 "DBG_HWBP_0_AMASK,HWBP Unit Address Mask Register" group.long 0x94++0x07 line.long 0x00 "DBG_HWWP_1_CNTL,HWWP Unit Control Register" bitfld.long 0x00 12. " DATAMATCH ,Enables data value qualification in addition to addr match" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " BUSSEL ,Bussel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--7. " ACCSIZE ,Configures HWWP Unit to filter data access based on access size as follows" "Any access,Only 8bit access,Only 16b access,Only 32b access,Any access,Any access,Any access,Any access" textline " " bitfld.long 0x00 3.--4. " RDWR ,Configures HWWP Unit to filter data access based on access type as follows" "Read,Write,Read/Write,Read/Write" eventfld.long 0x00 2. " TRIGGERED ,Indicates that the HWWP Unit found a match as programmed" "No match,Match" bitfld.long 0x00 1. " HALT ,Specifies that the generated trigger should halt the CPU" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLE ,Indicates that the HWWP Unit is enabled for operation" "Disabled,Enabled" line.long 0x04 "DBG_HWWP_1_ADDR,HWWP Unit Address Register" group.long 0xA0++0x03 line.long 0x00 "DBG_HWWP_1_AMASK,HWWP Unit Address Mask Register" group.long 0xA8++0x03 line.long 0x00 "DBG_HWWP_1_DATA,HWWP Unit Data Register" tree.end width 0x0B tree.end tree "EVE2_ARP32_DEBUG" base ad:0x42183000 width 10. base ad:0x42183000 tree "Control and Status Registers" rgroup.long 0x00++0x03 line.long 0x00 "DBG_CAP,Debug Capability Register" bitfld.long 0x00 29. " DBG_WP_DATA_SUP ,Specifies if data qualification is supported by the Watchpoint resources" "Not supported,Supported" bitfld.long 0x00 28. " DBG_OWN_SUP ,Specifies if Module Ownership is supported" "Not supported,Supported" bitfld.long 0x00 27. " DBG_INDIRECT_SUP ,Specifies if Indirect Memory access mechanism is supported" "Not supported,Supported" textline " " bitfld.long 0x00 26. " DBG_SWBP_SUP ,Specifies if Software Breakpoint is supported" "Not supported,Supported" bitfld.long 0x00 25. " DBG_RESET_SUP ,Specifies if debug initiated functional reset to CPU core is supported" "Not supported,Supported" bitfld.long 0x00 24. " SYS_EXE_REQ_SUP ,Specifies if Core Execution status change is supported" "Not supported,Supported" textline " " bitfld.long 0x00 23. " TRIG_OUTPUT_SUP ,Specifies if Trigger output is supported" "Not supported,Supported" bitfld.long 0x00 22. " TRIG_INPUT_SUP ,Specifies if Trigger input is supported" "Not supported,Supported" bitfld.long 0x00 20.--21. " NUM_TRIG_CHNS ,Specifies number of trigger channels supported" "0,1,2,3" textline " " bitfld.long 0x00 16.--19. " NUM_CNTRS ,Specifies number of counters supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " NUM_HWWPS ,Specifies number of Hardware Watchpoints supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " NUM_HWBPS ,Specifies number of Hardware Breakpoints supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " REV_MAJ ,Specifies the major revision id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV_MIN ,Specifies the minor revision id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x04++0x03 line.long 0x00 "DBG_CNTL,Debug Control Register" bitfld.long 0x00 27. " DBG_HALT_FATAL ,This bit indicates that CPU is halted due to FATAL system error" "Executing,Halted" eventfld.long 0x00 26. " DBG_RESET_OCC ,This is a sticky bit indicating a functional reset has been seen/active at CPU core since it was cleared" "Not occurred,Occurred" bitfld.long 0x00 25. " DBG_RESET_REQ ,This bit is used to generate a debug initiated functional reset to CPU core and the external sub-system via CPU output port" "No reset,Reset" textline " " rbitfld.long 0x00 24. " DBG_CPU_IDLE_STATUS ,Indicates IDLE status of CPU" "Not idle,Idle" bitfld.long 0x00 20.--23. " DBG_EMU1_CNTL ,EMU1 pin/channel output control" "No output,Pulse on CPU halt,Pulse when any HWBP triggers,Pulse when any HWWP triggers,Drive pin HIGH,Drive pin LOW,?..." bitfld.long 0x00 16.--19. " DBG_EMU0_CNTL ,EMU0 pin/channel output control" "No output,Pulse on CPU halt,Pulse when any HWBP triggers,Pulse when any HWWP triggers,Drive pin HIGH,Drive pin LOW,?..." textline " " rbitfld.long 0x00 15. " DBG_STAT_EMU1 ,Status of EMU1 input pin" "0,1" rbitfld.long 0x00 14. " DBG_STAT_EMU0 ,Status of EMU0 input pin" "0,1" rbitfld.long 0x00 13. " DBG_HALT_EMU1 ,CPU halted due to input trigger on EMU1" "Executing,Halted" textline " " rbitfld.long 0x00 12. " DBG_HALT_EMU0 ,CPU halted due to input trigger on EMU0" "Executing,Halted" rbitfld.long 0x00 11. " DBG_HALT_USER ,CPU halted due to Manual Halt via DBG_CNTL register" "Executing,Halted" rbitfld.long 0x00 10. " DBG_HALT_STEP ,CPU halted due to single step completion" "Executing,Halted" textline " " rbitfld.long 0x00 9. " DBG_HALT_BPWP ,CPU halted due to trigger from HWBP/HWWP Unit" "Executing,Halted" rbitfld.long 0x00 8. " DBG_HALT_SWBP ,CPU halted due to SWBP (BKPT instruction)" "Executing,Halted" rbitfld.long 0x00 7. " DBG_EXE_STAT ,CPU execution state" "Executing,Halted" textline " " bitfld.long 0x00 6. " DBG_EMU1_EN ,Enable for CPU Halt via Input trigger on EMU1 pin" "Disabled,Enabled" bitfld.long 0x00 5. " DBG_EMU0_EN ,Enable for CPU Halt via Input trigger on EMU0 pin" "Disabled,Enabled" bitfld.long 0x00 4. " DBG_BPWP_EN ,Enable for CPU Halt via HWBP/HWWP unit trigger" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DBG_SWBP_EN ,Enable for CPU Halt via SWBP" "Disabled,Enabled" bitfld.long 0x00 2. " DBG_SINGLE_STEP_EN ,Enable for single Stepping" "Disabled,Enabled" bitfld.long 0x00 1. " DBG_RESTART_STAT ,Status bit showing CPU restarted" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DBG_HALT ,Global debug run control" "Executing,Halted" if (((d.l(ad:0x42183000+0x0C))&0x06)==0x00) group.long 0x0C++0x03 line.long 0x00 "DBG_OWN,Debug Ownership Register" bitfld.long 0x00 1.--2. " OWN ,This field shows the current ownership status" "NotOwned,DebugOwned,ApplicationOwned,Ownership not implemented" bitfld.long 0x00 0. " CLAIM ,This bit is used to obtain exclusive ownership of the debug module for either the debug initiator or the application initiator" "No effect,DebugOwned/ApplicationOwned" elif (((d.l(ad:0x42183000+0x0C))&0x06)==0x02)||(((d.l(ad:0x42183000+0x0C))&0x06)==0x04) group.long 0x0C++0x03 line.long 0x00 "DBG_OWN,Debug Ownership Register" bitfld.long 0x00 1.--2. " OWN ,This field shows the current ownership status" "NotOwned,DebugOwned,ApplicationOwned,Ownership not implemented" bitfld.long 0x00 0. " CLAIM ,This bit is used to obtain exclusive ownership of the debug module for either the debug initiator or the application initiator" "NotOwned,No effect" else group.long 0x0C++0x03 line.long 0x00 "DBG_OWN,Debug Ownership Register" bitfld.long 0x00 1.--2. " OWN ,This field shows the current ownership status" "NotOwned,DebugOwned,ApplicationOwned,Ownership not implemented" endif tree.end width 17. tree "Indirect Memory Access Control Registers" rgroup.long 0x14++0x03 line.long 0x00 "DBG_INDRCT_CAP,Debug Indirect Memory Access Capability register" bitfld.long 0x00 18.--19. " PAGE4_DATA_SIZE ,Indicates the max Data width of Page 4 is 32b" "32b,?..." bitfld.long 0x00 16.--17. " PAGE4_ADDR_SIZE ,Indicates the max Address width of Page 4 is 32b" ",32b,?..." textline " " bitfld.long 0x00 14.--15. " PAGE3_DATA_SIZE ,Indicates the max Data width of Page 3 is 32b" "32b,?..." bitfld.long 0x00 12.--13. " PAGE3_ADDR_SIZE ,Indicates the max Address width of Page 3 is 32b" ",32b,?..." textline " " bitfld.long 0x00 10.--11. " PAGE2_DATA_SIZE ,Indicates the max Data width of Page 2 is 32b" "32b,?..." bitfld.long 0x00 8.--9. " PAGE2_ADDR_SIZE ,Indicates the max Address width of Page 2 is 32b" ",32b,?..." textline " " bitfld.long 0x00 6.--7. " PAGE1_DATA_SIZE ,Indicates the max Data width of Page 1 is 32b" "32b,?..." bitfld.long 0x00 4.--5. " PAGE1_ADDR_SIZE ,Indicates the max Address width of Page 1 is 32b" ",32b,?..." textline " " bitfld.long 0x00 2.--3. " PAGE0_DATA_SIZE ,Indicates the max Data width of Page 0 is 32b" "32b,?..." bitfld.long 0x00 0.--1. " PAGE0_ADDR_SIZE ,Indicates the max Address width of Page 0 is 32b" ",32b,?..." group.long 0x18++0x07 line.long 0x00 "DBG_INDRCT_CNTL,Debug Indirect Memory Access Control Register" bitfld.long 0x00 30. " MEM_RESET_PORT ,This field causes the Indirect Memory Access Port to come back to the default/reset state" "No effect,State transition to reset" rbitfld.long 0x00 20.--23. " MEM_ERR_CODE ,This field indicates the Error codes for the last debug access" "No error,I/D mem page access error,CPU internal access error,?..." textline " " rbitfld.long 0x00 19. " MEM_BUS_STAT ,Indicates the ready status of CPU bus interface corresponding to the selected MEM_PAGE" "Not ready,Ready" rbitfld.long 0x00 18. " MEM_ERR_OVERRUN ,Indicates that a new access was requested before a previous access was completed" "No error,Overrun error" textline " " rbitfld.long 0x00 16.--17. " MEM_PORT_STAT ,Indicates the status of Indirect Memory Access Port" "Ready for next transaction,Busy doing a transaction,Transaction completed successfully,Transaction resulted in Error condition" bitfld.long 0x00 8.--10. " MEM_ACC_SIZE ,Indicates the access size of next debug access" ",8b,16b,,32b,?..." textline " " bitfld.long 0x00 4.--7. " MEM_PAGE ,Indicates the target page of next debug access" "Instruction Memory,Data Memory,CPU architectural register file,CPU control register file,CPU shadow register file,?..." bitfld.long 0x00 2. " MEM_PRIORITY ,Determines if debug access will be forced or wait" "Wait,Force" textline " " bitfld.long 0x00 1. " MEM_ADDR_INC ,Indicates Auto-incrementing Addressing mode" "No Auto-incrementing addressing,Post-Increment by access size" bitfld.long 0x00 0. " MEM_RW ,Indicates a read or write operation to be carried out via Indirect Memory Access port" "Read,Write" line.long 0x04 "DBG_INDRCT_ADDR,Debug Indirect Memory Access Address Register" group.long 0x24++0x03 line.long 0x00 "DBG_INDRCT_DATA,Debug Indirect Memory Access" tree.end width 18. tree "Hardware Breakpoint/Watchpoint Unit 0 Registers" group.long 0x40++0x07 line.long 0x00 "DBG_HWBP_0_CNTL,HWBP Unit Control Register" eventfld.long 0x00 2. " TRIGGERED ,Indicates that the HWBP Unit found a match as programmed and the designated instruction entered DEC phase of the pipeline" "No match,Match" bitfld.long 0x00 1. " HALT ,Specifies that the generated trigger should halt the CPU" "0,1" bitfld.long 0x00 0. " ENABLE ,Indicates that the HWBP Unit is enabled for operation" "Disabled,Enabled" line.long 0x04 "DBG_HWBP_0_ADDR,HWBP Unit Address Register" group.long 0x4C++0x03 line.long 0x00 "DBG_HWBP_0_AMASK,HWBP Unit Address Mask Register" group.long 0x54++0x07 line.long 0x00 "DBG_HWWP_0_CNTL,HWWP Unit Control Register" bitfld.long 0x00 12. " DATAMATCH ,Enables data value qualification in addition to addr match" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " BUSSEL ,Bussel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--7. " ACCSIZE ,Configures HWWP Unit to filter data access based on access size as follows" "Any access,Only 8bit access,Only 16b access,Only 32b access,Any access,Any access,Any access,Any access" textline " " bitfld.long 0x00 3.--4. " RDWR ,Configures HWWP Unit to filter data access based on access type as follows" "Read,Write,Read/Write,Read/Write" eventfld.long 0x00 2. " TRIGGERED ,Indicates that the HWWP Unit found a match as programmed" "No match,Match" bitfld.long 0x00 1. " HALT ,Specifies that the generated trigger should halt the CPU" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLE ,Indicates that the HWWP Unit is enabled for operation" "Disabled,Enabled" line.long 0x04 "DBG_HWWP_0_ADDR,HWWP Unit Address Register" group.long 0x60++0x03 line.long 0x00 "DBG_HWWP_0_AMASK,HWWP Unit Address Mask Register" group.long 0x68++0x03 line.long 0x00 "DBG_HWWP_0_DATA,HWWP Unit Data Register" tree.end width 18. tree "Hardware Breakpoint/Watchpoint Unit 1 Registers" group.long 0x80++0x07 line.long 0x00 "DBG_HWBP_1_CNTL,HWBP Unit Control Register" eventfld.long 0x00 2. " TRIGGERED ,Indicates that the HWBP Unit found a match as programmed and the designated instruction entered DEC phase of the pipeline" "No match,Match" bitfld.long 0x00 1. " HALT ,Specifies that the generated trigger should halt the CPU" "0,1" bitfld.long 0x00 0. " ENABLE ,Indicates that the HWBP Unit is enabled for operation" "Disabled,Enabled" line.long 0x04 "DBG_HWBP_0_ADDR,HWBP Unit Address Register" group.long 0x8C++0x03 line.long 0x00 "DBG_HWBP_0_AMASK,HWBP Unit Address Mask Register" group.long 0x94++0x07 line.long 0x00 "DBG_HWWP_1_CNTL,HWWP Unit Control Register" bitfld.long 0x00 12. " DATAMATCH ,Enables data value qualification in addition to addr match" "Disabled,Enabled" rbitfld.long 0x00 8.--10. " BUSSEL ,Bussel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--7. " ACCSIZE ,Configures HWWP Unit to filter data access based on access size as follows" "Any access,Only 8bit access,Only 16b access,Only 32b access,Any access,Any access,Any access,Any access" textline " " bitfld.long 0x00 3.--4. " RDWR ,Configures HWWP Unit to filter data access based on access type as follows" "Read,Write,Read/Write,Read/Write" eventfld.long 0x00 2. " TRIGGERED ,Indicates that the HWWP Unit found a match as programmed" "No match,Match" bitfld.long 0x00 1. " HALT ,Specifies that the generated trigger should halt the CPU" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLE ,Indicates that the HWWP Unit is enabled for operation" "Disabled,Enabled" line.long 0x04 "DBG_HWWP_1_ADDR,HWWP Unit Address Register" group.long 0xA0++0x03 line.long 0x00 "DBG_HWWP_1_AMASK,HWWP Unit Address Mask Register" group.long 0xA8++0x03 line.long 0x00 "DBG_HWWP_1_DATA,HWWP Unit Data Register" tree.end width 0x0B tree.end AUTOINDENT.ON center tree tree.end tree.open "EMIF_Controller" tree "EMIF1" base ad:0x4C000000 rgroup.long 0x00++0x2F line.long 0x00 "EMIF_REVISION,Revision number register" line.long 0x04 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x04 31. "BE,Big endian mode select for 8 and 16-bit devices set to 1 for big endian or 0 for little endian operation" "0,1" newline bitfld.long 0x04 30. "DUAL_CLK_MODE,Dual Clock mode" "0,1" newline bitfld.long 0x04 29. "FAST_INIT,Fast Init" "0,1" newline bitfld.long 0x04 6. "RDLVLGATETO,Read DQS Gate Training Timeout" "0,1" newline bitfld.long 0x04 5. "RDLVLTO,Read Data Eye Training Timeout" "0,1" newline bitfld.long 0x04 4. "WRLVLTO,Write Leveling Timeout" "0,1" newline bitfld.long 0x04 2. "PHY_DLL_READY,DDR PHY Ready" "0,1" line.long 0x08 "EMIF_SDRAM_CONFIG,SDRAM Config Register" bitfld.long 0x08 29.--31. "SDRAM_TYPE,SDRAM Type selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 27.--28. "IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x08 24.--26. "DDR_TERM,DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "DDR2_DDQS,DDR2 differential DDQS enable" "0,1" newline bitfld.long 0x08 21.--22. "DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x08 20. "DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x08 18.--19. "SDRAM_DRIVE,SDRAM drive strength.For DDR3 set to 0 for RZQ/6 and set to 1 for RZQ/7" "0,1,2,3" newline bitfld.long 0x08 16.--17. "CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x08 14.--15. "NARROW_MODE,SDRAM data bus width" "0,1,2,3" newline bitfld.long 0x08 10.--13. "CL,CAS Latency (referred to as read latency (RL) in some SDRAM specs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7.--9. "ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0.--2. "PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" line.long 0x0C "EMIF_SDRAM_CONFIG_2,SDRAM Config Register 2 CAUTION: This register is loaded with values by control module at device reset" bitfld.long 0x0C 27. "EBANK_POS,External bank position" "0,1" line.long 0x10 "EMIF_SDRAM_REFRESH_CONTROL,SDRAM Refresh Control Register" bitfld.long 0x10 31. "INITREF_DIS,Initialization and Refresh disable" "0,1" newline bitfld.long 0x10 29. "SRT,DDR3 Self Refresh temperature range" "0,1" newline bitfld.long 0x10 28. "ASR,DDR3 Auto Self Refresh enable" "0,1" newline bitfld.long 0x10 24.--26. "PASR,Partial Array Self Refresh" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--15. 1. "REFRESH_RATE,Refresh Rate" line.long 0x14 "EMIF_SDRAM_REFRESH_CONTROL_SHADOW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x14 0.--15. 1. "REFRESH_RATE_SHDW,Shadow field for REFRESH_RATE" line.long 0x18 "EMIF_SDRAM_TIMING_1,SDRAM Timing 1 Register" bitfld.long 0x18 29.--31. "T_RTW,Minimum number of DDR clock cycles between Read to Write data phases minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 25.--28. "T_RP,Minimum number of DDR clock cycles from Precharge to Activate or Refresh minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 21.--24. "T_RCD,Minimum number of DDR clock cycles from Activate to Read or Write minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 17.--20. "T_WR,Minimum number of DDR clock cycles from last Write transfer to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 12.--16. "T_RAS,Minimum number of DDR clock cycles from Activate to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--11. "T_RC,Minimum number of DDR clock cycles from Activate to Activate minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 3.--5. "T_RRD,Minimum number of DDR clock cycles from Activate to Activate for a different bank minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "T_WTR,Minimum number of DDR clock cycles from last Write to Read minus one" "0,1,2,3,4,5,6,7" line.long 0x1C "EMIF_SDRAM_TIMING_1_SHADOW,SDRAM Timing 1 Shadow Register" bitfld.long 0x1C 29.--31. "T_RTW_SHDW,Shadow field for T_RTW" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 25.--28. "T_RP_SHDW,Shadow field for T_RP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 21.--24. "T_RCD_SHDW,Shadow field for T_RCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 17.--20. "T_WR_SHDW,Shadow field for T_WR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 12.--16. "T_RAS_SHDW,Shadow field for T_RAS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--11. "T_RC_SHDW,Shadow field for T_RC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x1C 3.--5. "T_RRD_SHDW,Shadow field for T_RRD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0.--2. "T_WTR_SHDW,Shadow field for T_WTR" "0,1,2,3,4,5,6,7" line.long 0x20 "EMIF_SDRAM_TIMING_2,SDRAM Timing 2 Register" bitfld.long 0x20 28.--30. "T_XP,Minimum number of DDR clock cycles from power-down exit to any command other than a read command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 25.--27. "T_ODT,Minimum number of DDR clock cycles from ODT enable to write data driven for DDR3" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 16.--24. 1. "T_XSNR,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command minus one" newline hexmask.long.word 0x20 6.--15. 1. "T_XSRD,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command minus one" newline bitfld.long 0x20 3.--5. "T_RTP,Minimum number of DDR clock cycles for the last read command to a Precharge command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "T_CKE,Minimum number of DDR clock cycles between CKE pin changes minus one" "0,1,2,3,4,5,6,7" line.long 0x24 "EMIF_SDRAM_TIMING_2_SHADOW,SDRAM Timing 2 Shadow Register" bitfld.long 0x24 28.--30. "T_XP_SHDW,Shadow field for T_XP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 25.--27. "T_ODT_SHDW,Shadow field for T_ODT" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 16.--24. 1. "T_XSNR_SHDW,Shadow field for T_XSNR" newline hexmask.long.word 0x24 6.--15. 1. "T_XSRD_SHDW,Shadow field for T_XSRD" newline bitfld.long 0x24 3.--5. "T_RTP_SHDW,Shadow field for T_RTP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0.--2. "T_CKE_SHDW,Shadow field for T_CKE" "0,1,2,3,4,5,6,7" line.long 0x28 "EMIF_SDRAM_TIMING_3,SDRAM Timing 3 Register" bitfld.long 0x28 28.--31. "T_PDLL_UL,Minimum number of DDR clock cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 21.--23. "T_CKESR,Minimum number of DDR clock cycles for which SDRAM must remain in Self Refresh minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--20. "ZQ_ZQCS,Number of DDR clock cycles for a ZQCS command minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x28 4.--12. 1. "T_RFC,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate minus one" newline bitfld.long 0x28 0.--3. "T_RAS_MAX,Maximum number of REFRESH_RATE intervals from Activate to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "EMIF_SDRAM_TIMING_3_SHADOW,SDRAM Timing 3 Shadow Register" bitfld.long 0x2C 28.--31. "T_PDLL_UL_SHDW,Shadow field for T_PDLL_UL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 21.--23. "T_CKESR_SHDW,Shadow field for T_CKESR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 15.--20. "ZQ_ZQCS_SHDW,Shadow field for ZQ_ZQCS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x2C 4.--12. 1. "T_RFC_SHDW,Shadow field for T_RFC" newline bitfld.long 0x2C 0.--3. "T_RAS_MAX_SHDW,Shadow field for T_RAS_MAX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x07 line.long 0x00 "EMIF_POWER_MANAGEMENT_CONTROL,Power Management Control Register" bitfld.long 0x00 12.--15. "PD_TIM,Power Management timer for Power-Down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--10. "LP_MODE,Automatic Power Management enable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--7. "SR_TIM,Power Management timer for Self Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_POWER_MANAGEMENT_CONTROL_SHADOW,Power Management Control Shadow Register" bitfld.long 0x04 12.--15. "PD_TIM_SHDW,Shadow field for PD_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. "SR_TIM_SHDW,Shadow field for SR_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x0B line.long 0x00 "EMIF_OCP_CONFIG,OCP Config Register" bitfld.long 0x00 24.--27. "SYS_THRESH_MAX,System OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "MPU_THRESH_MAX,MPU Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_OCP_CONFIG_VALUE_1,OCP Config Value 1 Register" bitfld.long 0x04 30.--31. "SYS_BUS_WIDTH,System OCP data bus width" "0,1,2,3" newline hexmask.long.byte 0x04 8.--15. 1. "WR_FIFO_DEPTH,Write Data FIFO depth" newline hexmask.long.byte 0x04 0.--7. 1. "CMD_FIFO_DEPTH,Command FIFO depth" line.long 0x08 "EMIF_OCP_CONFIG_VALUE_2,OCP Config Value 2 Register" hexmask.long.byte 0x08 16.--23. 1. "RREG_FIFO_DEPTH,Register Read Data FIFO depth" newline hexmask.long.byte 0x08 8.--15. 1. "RSD_FIFO_DEPTH,SDRAM Read Data FIFO depth" newline hexmask.long.byte 0x08 0.--7. 1. "RCMD_FIFO_DEPTH,Read Command FIFO depth" rgroup.long 0x80++0x27 line.long 0x00 "EMIF_PERFORMANCE_COUNTER_1,Performance Counter 1 Register" line.long 0x04 "EMIF_PERFORMANCE_COUNTER_2,Performance Counter 2 Register" line.long 0x08 "EMIF_PERFORMANCE_COUNTER_CONFIG,Performance Counter Config Register" bitfld.long 0x08 31. "CNTR2_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline bitfld.long 0x08 30. "CNTR2_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline bitfld.long 0x08 16.--19. "CNTR2_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 15. "CNTR1_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline bitfld.long 0x08 14. "CNTR1_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline bitfld.long 0x08 0.--3. "CNTR1_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT,Performance Counter Master Region Select Register The values programmed into the MCONNIDx fields are those in Table ConnID Mapping (Debug View). in . On-Chip Debug Support. left-shifted by 2 bits" hexmask.long.byte 0x0C 24.--31. 1. "MCONNID2,MConnID forEMIF_PERFORMANCE_COUNTER_2 register" newline bitfld.long 0x0C 16.--17. "REGION_SEL2,MAddrSpace forEMIF_PERFORMANCE_COUNTER_2 register" "0,1,2,3" newline hexmask.long.byte 0x0C 8.--15. 1. "MCONNID1,MConnID forEMIF_PERFORMANCE_COUNTER_1 register" newline bitfld.long 0x0C 0.--1. "REGION_SEL1,MAddrSpace forEMIF_PERFORMANCE_COUNTER_1 register" "0,1,2,3" line.long 0x10 "EMIF_PERFORMANCE_COUNTER_TIME,Performance Counter Time Register" line.long 0x14 "EMIF_MISC_REG," bitfld.long 0x14 0. "DLL_CALIB_OS,Phy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse" "0,1" line.long 0x18 "EMIF_DLL_CALIB_CTRL,Control register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps" bitfld.long 0x18 16.--19. "ACK_WAIT,The ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x18 0.--8. 1. "DLL_CALIB_INTERVAL,This field determines the interval between phy_dll_calib generation" line.long 0x1C "EMIF_DLL_CALIB_CTRL_SHADOW,Read Idle Control Shadow Register" bitfld.long 0x1C 16.--19. "ACK_WAIT_SHDW,Shadow field for ACK_WAIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x1C 0.--8. 1. "DLL_CALIB_INTERVAL_SHDW,Shadow field for DLL_CALIB_INTERVAL" line.long 0x20 "EMIF_END_OF_INTERRUPT," bitfld.long 0x20 0. "EOI,Software End Of Interrupt (EOI) control" "0,1" line.long 0x24 "EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS,System OCP Interrupt Raw Status Register" bitfld.long 0x24 5. "ONEBIT_ECC_ERR_SYS,Raw status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x24 4. "TWOBIT_ECC_ERR_SYS,Raw status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x24 3. "WR_ECC_ERR_SYS,Raw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline bitfld.long 0x24 0. "ERR_SYS,Raw status of system OCP interrupt for command or address error" "0,1" group.long 0xAC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_STATUS,System OCP Interrupt Status Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline bitfld.long 0x00 0. "ERR_SYS,Enabled status of system OCP interrupt interrupt for command or address error" "0,1" group.long 0xB4++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET,System OCP Interrupt Enable Set Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of sysem ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable set for system OCP interrupt for command or address error" "0,1" group.long 0xBC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR,System OCP Interrupt Enable Clear Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable clear for system OCP interrupt for command or address error" "0,1" group.long 0xC8++0x03 line.long 0x00 "EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG,SDRAM Output Impedance Calibration Config Register" bitfld.long 0x00 30. "ZQ_CS0EN,Writing a 1 enables ZQ calibration for CS0" "0,1" newline bitfld.long 0x00 28. "ZQ_SFEXITEN,Writing a 1 enables the issuing of ZQCL on Self-Refresh Active Power-Down and Precharge Power-Down exit" "0,1" newline bitfld.long 0x00 16.--17. "ZQ_ZQCL_MULT,Indicates the number of ZQCS intervals that make up a ZQCL duration minus one" "0,1,2,3" newline hexmask.long.word 0x00 0.--15. 1. "ZQ_REFINTERVAL,Number of refresh periods between ZQCS commands" rgroup.long 0xD0++0x0F line.long 0x00 "EMIF_OCP_ERROR_LOG,OCP Error Log Register" bitfld.long 0x00 14.--15. "MADDRSPACE,Address space of the first errored transaction" "0,1,2,3" newline bitfld.long 0x00 11.--13. "MBURSTSEQ,Addressing mode of the first errored transaction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. "MCMD,Command type of the first errored transaction" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. "MCONNID,Connection ID of the first errored transaction" line.long 0x04 "EMIF_READ_WRITE_LEVELING_RAMP_WINDOW,Read/write leveling ramp window register" hexmask.long.word 0x04 0.--12. 1. "RDWRLVLINC_RMP_WIN,Incremental leveling ramp window in number of refresh periods" line.long 0x08 "EMIF_READ_WRITE_LEVELING_RAMP_CONTROL,Read/write leveling ramp control register" bitfld.long 0x08 31. "RDWRLVL_EN,Read-Write Leveling enable" "0,1" newline hexmask.long.byte 0x08 24.--30. 1. "RDWRLVLINC_RMP_PRE,Incremental leveling pre-scalar in number of refresh periods during ramp window" newline hexmask.long.byte 0x08 16.--23. 1. "RDLVLINC_RMP_INT,Incremental read data eye training interval during ramp window" newline hexmask.long.byte 0x08 8.--15. 1. "RDLVLGATEINC_RMP_INT,Incremental read DQS gate training interval during ramp window" newline hexmask.long.byte 0x08 0.--7. 1. "WRLVLINC_RMP_INT,Incremental write leveling interval during ramp window" line.long 0x0C "EMIF_READ_WRITE_LEVELING_CONTROL,Read/write leveling control register" bitfld.long 0x0C 31. "RDWRLVLFULL_START,Full leveling trigger" "0,1" newline hexmask.long.byte 0x0C 24.--30. 1. "RDWRLVLINC_PRE,Incremental leveling pre-scalar in number of refresh periods" newline hexmask.long.byte 0x0C 16.--23. 1. "RDLVLINC_INT,Incremental read data eye training interval" newline hexmask.long.byte 0x0C 8.--15. 1. "RDLVLGATEINC_INT,Incremental read DQS gate training interval" newline hexmask.long.byte 0x0C 0.--7. 1. "WRLVLINC_INT,Incremental write leveling interval" group.long 0xE4++0x07 line.long 0x00 "EMIF_DDR_PHY_CONTROL_1,PHY control register 1" bitfld.long 0x00 27. "RDLVL_MASK,Writing a 1 to this field will mask read data eye training during full leveling command plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 26. "RDLVLGATE_MASK,Writing a 1 to this field will mask dqs gate training during full leveling command plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 25. "WRLVL_MASK,Writing a 1 to this field will mask write leveling training during full leveling command plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 21. "PHY_HALF_DELAYS,Adjust slave delay line delays to support 2x mode" "0,1" newline bitfld.long 0x00 20. "PHY_CLK_STALL_LEVEL,Enable variable idle value for delay lines" "0,1" newline bitfld.long 0x00 19. "PHY_DIS_CALIB_RST,Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs" "0,1" newline bitfld.long 0x00 18. "PHY_INVERT_CLKOUT,Inverts the polarity of DRAM clock" "0,1" newline hexmask.long.byte 0x00 10.--17. 1. "PHY_DLL_LOCK_DIFF,The maximum number of delay line taps variation while maintaining the master DLL lock" newline bitfld.long 0x00 9. "PHY_FAST_DLL_LOCK,Controls master DLL to lock fast or average logic must be part of locking process" "0,1" newline bitfld.long 0x00 0.--4. "READ_LATENCY,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_DDR_PHY_CONTROL_1_SHADOW," bitfld.long 0x04 27. "RDLVL_MASK_SHDW,Shadow field for RDLVL_MASK" "0,1" newline bitfld.long 0x04 26. "RDLVLGATE_MASK_SHDW,Shadow field for RDLVLGATE_MASK" "0,1" newline bitfld.long 0x04 25. "WRLVL_MASK_SHDW,Shadow field for WRLVL_MASK" "0,1" newline bitfld.long 0x04 21. "PHY_HALF_DELAYS_SHDW,Shadow field for PHY_HALF_DELAYS" "0,1" newline bitfld.long 0x04 20. "PHY_CLK_STALL_LEVEL_SHDW,Shadow field for PHY_CLK_STALL_LEVEL" "0,1" newline bitfld.long 0x04 19. "PHY_DIS_CALIB_RST_SHDW,Shadow field for PHY_DIS_CALIB_RST" "0,1" newline bitfld.long 0x04 18. "PHY_INVERT_CLKOUT_SHDW,Shadow field for PHY_INVERT_CLKOUT" "0,1" newline hexmask.long.byte 0x04 10.--17. 1. "PHY_DLL_LOCK_DIFF_SHDW,Shadow field for PHY_DLL_LOCK_DIFF" newline bitfld.long 0x04 9. "PHY_FAST_DLL_SHDW,Shadow field for PHY_FAST_DLL" "0,1" newline bitfld.long 0x04 0.--4. "READ_LATENCY_SHDW,Shadow field for READ_LATENCY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x0B line.long 0x00 "EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING," bitfld.long 0x00 31. "PRI_COS_MAP_EN,Set 1 to enable priority to class of service mapping" "0,1" newline bitfld.long 0x00 14.--15. "PRI_7_COS,Class of service for commands with priority of 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. "PRI_6_COS,Class of service for commands with priority of 6" "0,1,2,3" newline bitfld.long 0x00 10.--11. "PRI_5_COS,Class of service for commands with priority of 5" "0,1,2,3" newline bitfld.long 0x00 8.--9. "PRI_4_COS,Class of service for commands with priority of 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. "PRI_3_COS,Class of service for commands with priority of 3" "0,1,2,3" newline bitfld.long 0x00 4.--5. "PRI_2_COS,Class of service for commands with priority of 2" "0,1,2,3" newline bitfld.long 0x00 2.--3. "PRI_1_COS,Class of service for commands with priority of 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. "PRI_0_COS,Class of service for commands with priority of 0" "0,1,2,3" line.long 0x04 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING," bitfld.long 0x04 31. "CONNID_COS_1_MAP_EN,Set 1 to enable Connection ID to class of service 1 mapping" "0,1" newline hexmask.long.byte 0x04 23.--30. 1. "CONNID_1_COS_1,Connection ID value 1 for class of service 1" newline bitfld.long 0x04 20.--22. "MSK_1_COS_1,Mask for Connection ID value 1 for class of service 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x04 12.--19. 1. "CONNID_2_COS_1,Connection ID value 2 for class of service 1" newline bitfld.long 0x04 10.--11. "MSK_2_COS_1,Mask for Connection ID value 2 for class of service 1" "0,1,2,3" newline hexmask.long.byte 0x04 2.--9. 1. "CONNID_3_COS_1,Connection ID value 3 for class of service 1" newline bitfld.long 0x04 0.--1. "MSK_3_COS_1,Mask for Connection ID value 3 for class of service 1" "0,1,2,3" line.long 0x08 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING," bitfld.long 0x08 31. "CONNID_COS_2_MAP_EN,Set 1 to enable Connection ID to class of service 2 mapping" "0,1" newline hexmask.long.byte 0x08 23.--30. 1. "CONNID_1_COS_2,Connection ID value 1 for class of service 2" newline bitfld.long 0x08 20.--22. "MSK_1_COS_2,Mask for Connection ID value 1 for class of service 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 12.--19. 1. "CONNID_2_COS_2,Connection ID value 2 for class of service 2" newline bitfld.long 0x08 10.--11. "MSK_2_COS_2,Mask for Connection ID value 2 for class of service 2" "0,1,2,3" newline hexmask.long.byte 0x08 2.--9. 1. "CONNID_3_COS_2,Connection ID value 3 for class of service 2" newline bitfld.long 0x08 0.--1. "MSK_3_COS_2,Mask for Connection ID value 3 for class of service 2" "0,1,2,3" group.long 0x110++0x03 line.long 0x00 "EMIF_ECC_CTRL_REG," bitfld.long 0x00 31. "REG_ECC_EN,Set 1 to enable ECC" "0,1" newline bitfld.long 0x00 30. "REG_ECC_ADDR_RGN_PROT,Setting this field to 1 and reg_ecc_en to a 1 will enable ECC calculation for accesses within the address ranges and disable ECC calculation for accesses outside the address ranges" "0,1" newline bitfld.long 0x00 1. "REG_ECC_ADDR_RGN_2_EN,Set 1 to enable ECC address range 2" "0,1" newline bitfld.long 0x00 0. "REG_ECC_ADDR_RGN_1_EN,Set 1 to enable ECC address range 1" "0,1" group.long 0x120++0x07 line.long 0x00 "EMIF_READ_WRITE_EXECUTION_THRESHOLD," bitfld.long 0x00 31. "MFLAG_OVERRIDE,Mflag override" "MFLAG_OVERRIDE_0,MFLAG_OVERRIDE_1" newline bitfld.long 0x00 30. "LL_BUBBLE_ENABLE,LL bubble enable" "LL_BUBBLE_ENABLE_0,LL_BUBBLE_ENABLE_1" newline bitfld.long 0x00 8.--12. "WR_THRSH,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0.--4. "RD_THRSH,Read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_COS_CONFIG,Priority Raise Counter Register" hexmask.long.byte 0x04 16.--23. 1. "COS_COUNT_1,Priority Raise Counter for class of service 1" newline hexmask.long.byte 0x04 8.--15. 1. "COS_COUNT_2,Priority Raise Counter for class of service 2" newline hexmask.long.byte 0x04 0.--7. 1. "PR_OLD_COUNT,Priority Raise Old Counter" group.long 0x130++0x17 line.long 0x00 "EMIF_1B_ECC_ERR_CNT," line.long 0x04 "EMIF_1B_ECC_ERR_THRSH," hexmask.long.byte 0x04 24.--31. 1. "REG_1B_ECC_ERR_THRSH,1-bit ECC error threshold" newline hexmask.long.word 0x04 0.--15. 1. "REG_1B_ECC_ERR_WIN,1-bit ECC error window in number of refresh periods" line.long 0x08 "EMIF_1B_ECC_ERR_DIST_1," line.long 0x0C "EMIF_1B_ECC_ERR_ADDR_LOG," line.long 0x10 "EMIF_2B_ECC_ERR_ADDR_LOG," line.long 0x14 "EMIF_PHY_STATUS_1," bitfld.long 0x14 5. "PHY_REG_STATUS_DLL_LOCK_3,Reflects lock status of DLL of data PHY 3" "0,1" newline bitfld.long 0x14 4. "PHY_REG_STATUS_DLL_LOCK_2,Reflects lock status of DLL of data PHY 2" "0,1" newline bitfld.long 0x14 3. "PHY_REG_STATUS_DLL_LOCK_1,Reflects lock status of DLL of data PHY 1" "0,1" newline bitfld.long 0x14 2. "PHY_REG_STATUS_DLL_LOCK_0,Reflects lock status of DLL of data PHY 0" "0,1" newline bitfld.long 0x14 1. "PHY_REG_STATUS_PHY_CTRL_DLL_LOCK_1,Reflects lock status of DLL 1 (command PHY 2)" "0,1" newline bitfld.long 0x14 0. "PHY_REG_STATUS_PHY_CTRL_DLL_LOCK_0,Reflects lock status of DLL 0 (command PHY 0 and 1)" "0,1" rgroup.long 0x18C++0x07 line.long 0x00 "EMIF_PHY_STATUS_20," bitfld.long 0x00 31. "PHY_REG_WRLVL_INC_FAIL_1,Incremental Write Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 30. "PHY_REG_WRLVL_INC_FAIL_0,Incremental Write Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 29. "PHY_REG_RDLVL_INC_FAIL_3,Incremental Read Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 28. "PHY_REG_RDLVL_INC_FAIL_2,Incremental Read Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 27. "PHY_REG_RDLVL_INC_FAIL_1,Incremental Read Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 26. "PHY_REG_RDLVL_INC_FAIL_0,Incremental Read Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 25. "PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_3,Data PHY 3" "0,1" newline bitfld.long 0x00 24. "PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_2,Data PHY 2" "0,1" newline bitfld.long 0x00 23. "PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_1,Data PHY 1" "0,1" newline bitfld.long 0x00 22. "PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_0,Data PHY 0" "0,1" newline bitfld.long 0x00 21. "PHY_REG_STATUS_PHY_CTRL_MDLL_UNLOCK_STICKY_1,Command DLL 1 (command PHY 2)" "0,1" newline bitfld.long 0x00 20. "PHY_REG_STATUS_PHY_CTRL_MDLL_UNLOCK_STICKY_0,Command DLL 0 (command PHYs 0 and 1)" "0,1" newline bitfld.long 0x00 19. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY_3,Data PHY 3" "0,1" newline bitfld.long 0x00 18. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY_2,Data PHY 2" "0,1" newline bitfld.long 0x00 17. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY_1,Data PHY 1" "0,1" newline bitfld.long 0x00 16. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY_0,Data PHY 0" "0,1" newline bitfld.long 0x00 12.--15. "PHY_REG_RDC_FIFO_RST_ERR_CNT_3,Counter for counting the number of times the pointers of read capture FIFO differ when they are reset by dll_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "PHY_REG_RDC_FIFO_RST_ERR_CNT_2,Counter for counting the number of times the pointers of read capture FIFO differ when they are reset by dll_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "PHY_REG_RDC_FIFO_RST_ERR_CNT_1,Counter for counting the number of times the pointers of read capture FIFO differ when they are reset by dll_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "PHY_REG_RDC_FIFO_RST_ERR_CNT_0,Counter for counting the number of times the pointers of read capture FIFO differ when they are reset by dll_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_PHY_STATUS_21," bitfld.long 0x04 5. "PHY_REG_GATELVL_INC_FAIL_3,Incremental Gate Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 4. "PHY_REG_GATELVL_INC_FAIL_2,Incremental Gate Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 3. "PHY_REG_GATELVL_INC_FAIL_1,Incremental Gate Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 2. "PHY_REG_GATELVL_INC_FAIL_0,Incremental Gate Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 1. "PHY_REG_WRLVL_INC_FAIL_3,Incremental Write Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 0. "PHY_REG_WRLVL_INC_FAIL_2,Incremental Write Leveling Fail Status Flag" "0,1" group.long 0x200++0x83 line.long 0x00 "EMIF_EXT_PHY_CONTROL_1,Programs command PHY slave DLL ratio" hexmask.long.word 0x00 20.--29. 1. "PHY_CTRL_SLAVE_RATIO_2,Slave DLL ratio for command PHY 2" newline hexmask.long.word 0x00 10.--19. 1. "PHY_CTRL_SLAVE_RATIO_1,Slave DLL ratio for command PHY 1" newline hexmask.long.word 0x00 0.--9. 1. "PHY_CTRL_SLAVE_RATIO_0,Slave DLL ratio for command PHY 0" line.long 0x04 "EMIF_EXT_PHY_CONTROL_1_SHADOW," hexmask.long.word 0x04 20.--29. 1. "PHY_CTRL_SLAVE_RATIO_2_SHDW,Shadow field for PHY_CTRL_SLAVE_RATIO_2" newline hexmask.long.word 0x04 10.--19. 1. "PHY_CTRL_SLAVE_RATIO_1_SHDW,Shadow field for PHY_CTRL_SLAVE_RATIO_1" newline hexmask.long.word 0x04 0.--9. 1. "PHY_CTRL_SLAVE_RATIO_0_SHDW,Shadow field for PHY_CTRL_SLAVE_RATIO_0" line.long 0x08 "EMIF_EXT_PHY_CONTROL_2,DQS gate opening delay" hexmask.long.word 0x08 22.--31. 1. "PHY_FIFO_WE_SLAVE_RATIO_1_0,DQS gate opening delay[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x08 11.--21. 1. "PHY_FIFO_WE_SLAVE_RATIO_0_1,DQS gate opening delay[10:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x08 0.--10. 1. "PHY_FIFO_WE_SLAVE_RATIO_0_0,DQS gate opening delay[10:0] for Data PHY 0 Rank 0" line.long 0x0C "EMIF_EXT_PHY_CONTROL_2_SHADOW," hexmask.long.word 0x0C 22.--31. 1. "PHY_FIFO_WE_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_1_0" newline hexmask.long.word 0x0C 11.--21. 1. "PHY_FIFO_WE_SLAVE_RATIO_0_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_0_1" newline hexmask.long.word 0x0C 0.--10. 1. "PHY_FIFO_WE_SLAVE_RATIO_0_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_0_0" line.long 0x10 "EMIF_EXT_PHY_CONTROL_3,DQS gate opening delay" hexmask.long.word 0x10 23.--31. 1. "PHY_FIFO_WE_SLAVE_RATIO_2_1,DQS gate opening delay[8:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x10 12.--22. 1. "PHY_FIFO_WE_SLAVE_RATIO_2_0,DQS gate opening delay[10:0] for Data PHY 2 Rank 0" newline hexmask.long.word 0x10 1.--11. 1. "PHY_FIFO_WE_SLAVE_RATIO_1_1,DQS gate opening delay[10:0] for Data PHY 1 Rank 1" newline bitfld.long 0x10 0. "PHY_FIFO_WE_SLAVE_RATIO_1_0,DQS gate opening delay[10] for Data PHY 1 Rank 0" "0,1" line.long 0x14 "EMIF_EXT_PHY_CONTROL_3_SHADOW," hexmask.long.word 0x14 23.--31. 1. "PHY_FIFO_WE_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_2_1" newline hexmask.long.word 0x14 12.--22. 1. "PHY_FIFO_WE_SLAVE_RATIO_2_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_2_0" newline hexmask.long.word 0x14 1.--11. 1. "PHY_FIFO_WE_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_1_1" newline bitfld.long 0x14 0. "PHY_FIFO_WE_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_1_0" "0,1" line.long 0x18 "EMIF_EXT_PHY_CONTROL_4,DQS gate opening delay" hexmask.long.word 0x18 13.--23. 1. "PHY_FIFO_WE_SLAVE_RATIO_3_1,DQS gate opening delay[10:0] for Data PHY 3 Rank 1" newline hexmask.long.word 0x18 2.--12. 1. "PHY_FIFO_WE_SLAVE_RATIO_3_0,DQS gate opening delay[10:0] for Data PHY 3 Rank 0" newline bitfld.long 0x18 0.--1. "PHY_FIFO_WE_SLAVE_RATIO_2_1,DQS gate opening delay[10:9] for Data PHY 2 Rank 1" "0,1,2,3" line.long 0x1C "EMIF_EXT_PHY_CONTROL_4_SHADOW," hexmask.long.word 0x1C 13.--23. 1. "PHY_FIFO_WE_SLAVE_RATIO_3_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_3_1" newline hexmask.long.word 0x1C 2.--12. 1. "PHY_FIFO_WE_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_3_0" newline bitfld.long 0x1C 0.--1. "PHY_FIFO_WE_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_2_1" "0,1,2,3" line.long 0x20 "EMIF_EXT_PHY_CONTROL_5,Ratio value for read DQS slave DLL" bitfld.long 0x20 30.--31. "PHY_RD_DQS_SLAVE_RATIO_1_1,Ratio value for read DQS slave DLL.[1:0] for Data PHY 1 Rank 1" "0,1,2,3" newline hexmask.long.word 0x20 20.--29. 1. "PHY_RD_DQS_SLAVE_RATIO_1_0,Ratio value for read DQS slave DLL.[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x20 10.--19. 1. "PHY_RD_DQS_SLAVE_RATIO_0_1,Ratio value for read DQS slave DLL.[9:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x20 0.--9. 1. "PHY_RD_DQS_SLAVE_RATIO_0_0,Ratio value for read DQS slave DLL.[9:0] for Data PHY 0 Rank 0" line.long 0x24 "EMIF_EXT_PHY_CONTROL_5_SHADOW," bitfld.long 0x24 30.--31. "PHY_RD_DQS_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_1_1" "0,1,2,3" newline hexmask.long.word 0x24 20.--29. 1. "PHY_RD_DQS_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_1_0" newline hexmask.long.word 0x24 10.--19. 1. "PHY_RD_DQS_SLAVE_RATIO_0_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_0_1" newline hexmask.long.word 0x24 0.--9. 1. "PHY_RD_DQS_SLAVE_RATIO_0_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_0_0" line.long 0x28 "EMIF_EXT_PHY_CONTROL_6,Ratio value for read DQS slave DLL" bitfld.long 0x28 28.--31. "PHY_RD_DQS_SLAVE_RATIO_3_0,Ratio value for read DQS slave DLL.[3:0] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x28 18.--27. 1. "PHY_RD_DQS_SLAVE_RATIO_2_1,Ratio value for read DQS slave DLL.[9:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x28 8.--17. 1. "PHY_RD_DQS_SLAVE_RATIO_2_0,Ratio value for read DQS slave DLL.[9:0] for Data PHY 2 Rank 0" newline hexmask.long.byte 0x28 0.--7. 1. "PHY_RD_DQS_SLAVE_RATIO_1_1,Ratio value for read DQS slave DLL.[9:2] for Data PHY 1 Rank 1" line.long 0x2C "EMIF_EXT_PHY_CONTROL_6_SHADOW," bitfld.long 0x2C 28.--31. "PHY_RD_DQS_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x2C 18.--27. 1. "PHY_RD_DQS_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_2_1" newline hexmask.long.word 0x2C 8.--17. 1. "PHY_RD_DQS_SLAVE_RATIO_2_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_2_0" newline hexmask.long.byte 0x2C 0.--7. 1. "PHY_RD_DQS_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_1_1" line.long 0x30 "EMIF_EXT_PHY_CONTROL_7,Ratio value for read DQS slave DLL" hexmask.long.word 0x30 6.--15. 1. "PHY_RD_DQS_SLAVE_RATIO_3_1,Ratio value for read DQS slave DLL.[9:0] for Data PHY 3 Rank 1" newline bitfld.long 0x30 0.--5. "PHY_RD_DQS_SLAVE_RATIO_3_0,Ratio value for read DQS slave DLL.[9:4] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EMIF_EXT_PHY_CONTROL_7_SHADOW," hexmask.long.word 0x34 6.--15. 1. "PHY_RD_DQS_SLAVE_RATIO_3_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_3_1" newline bitfld.long 0x34 0.--5. "PHY_RD_DQS_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EMIF_EXT_PHY_CONTROL_8,Ratio value for write data slave DLL" bitfld.long 0x38 30.--31. "PHY_WR_DATA_SLAVE_RATIO_1_1,Ratio value for write data slave DLL.[1:0] for Data PHY 1 Rank 1" "0,1,2,3" newline hexmask.long.word 0x38 20.--29. 1. "PHY_WR_DATA_SLAVE_RATIO_1_0,Ratio value for write data slave DLL.[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x38 10.--19. 1. "PHY_WR_DATA_SLAVE_RATIO_0_1,Ratio value for write data slave DLL.[9:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x38 0.--9. 1. "PHY_WR_DATA_SLAVE_RATIO_0_0,Ratio value for write data slave DLL.[9:0] for Data PHY 0 Rank 0" line.long 0x3C "EMIF_EXT_PHY_CONTROL_8_SHADOW," bitfld.long 0x3C 30.--31. "PHY_WR_DATA_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_1_1" "0,1,2,3" newline hexmask.long.word 0x3C 20.--29. 1. "PHY_WR_DATA_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_1_0" newline hexmask.long.word 0x3C 10.--19. 1. "PHY_WR_DATA_SLAVE_RATIO_0_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_0_1" newline hexmask.long.word 0x3C 0.--9. 1. "PHY_WR_DATA_SLAVE_RATIO_0_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_0_0" line.long 0x40 "EMIF_EXT_PHY_CONTROL_9,Ratio value for write data slave DLL" bitfld.long 0x40 28.--31. "PHY_WR_DATA_SLAVE_RATIO_3_0,Ratio value for write data slave DLL.[3:0] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x40 18.--27. 1. "PHY_WR_DATA_SLAVE_RATIO_2_1,Ratio value for write data slave DLL.[9:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x40 8.--17. 1. "PHY_WR_DATA_SLAVE_RATIO_2_0,Ratio value for write data slave DLL.[9:0] for Data PHY 2 Rank 0" newline hexmask.long.byte 0x40 0.--7. 1. "PHY_WR_DATA_SLAVE_RATIO_1_1,Ratio value for write data slave DLL.[9:2] for Data PHY 1 Rank 1" line.long 0x44 "EMIF_EXT_PHY_CONTROL_9_SHADOW," bitfld.long 0x44 28.--31. "PHY_WR_DATA_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x44 18.--27. 1. "PHY_WR_DATA_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_2_1" newline hexmask.long.word 0x44 8.--17. 1. "PHY_WR_DATA_SLAVE_RATIO_2_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_2_0" newline hexmask.long.byte 0x44 0.--7. 1. "PHY_WR_DATA_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_1_1" line.long 0x48 "EMIF_EXT_PHY_CONTROL_10,Ratio value for write data slave DLL" hexmask.long.word 0x48 6.--15. 1. "PHY_WR_DATA_SLAVE_RATIO_3_1,Ratio value for write data slave DLL.[9:0] for Data PHY 3 Rank 1" newline bitfld.long 0x48 0.--5. "PHY_WR_DATA_SLAVE_RATIO_3_0,Ratio value for write data slave DLL.[9:4] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EMIF_EXT_PHY_CONTROL_10_SHADOW," hexmask.long.word 0x4C 6.--15. 1. "PHY_WR_DATA_SLAVE_RATIO_3_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_3_1" newline bitfld.long 0x4C 0.--5. "PHY_WR_DATA_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EMIF_EXT_PHY_CONTROL_11,Ratio value for write DQS slave DLL" bitfld.long 0x50 30.--31. "PHY_WR_DQS_SLAVE_RATIO_1_1,Ratio value for write DQS slave DLL.[1:0] for Data PHY 1 Rank 1" "0,1,2,3" newline hexmask.long.word 0x50 20.--29. 1. "PHY_WR_DQS_SLAVE_RATIO_1_0,Ratio value for write DQS slave DLL.[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x50 10.--19. 1. "PHY_WR_DQS_SLAVE_RATIO_0_1,Ratio value for write DQS slave DLL.[9:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x50 0.--9. 1. "PHY_WR_DQS_SLAVE_RATIO_0_0,Ratio value for write DQS slave DLL.[9:0] for Data PHY 0 Rank 0" line.long 0x54 "EMIF_EXT_PHY_CONTROL_11_SHADOW," bitfld.long 0x54 30.--31. "PHY_WR_DQS_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_1_1" "0,1,2,3" newline hexmask.long.word 0x54 20.--29. 1. "PHY_WR_DQS_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_1_0" newline hexmask.long.word 0x54 10.--19. 1. "PHY_WR_DQS_SLAVE_RATIO_0_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_0_1" newline hexmask.long.word 0x54 0.--9. 1. "PHY_WR_DQS_SLAVE_RATIO_0_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_0_0" line.long 0x58 "EMIF_EXT_PHY_CONTROL_12,Ratio value for write DQS slave DLL" bitfld.long 0x58 28.--31. "PHY_WR_DQS_SLAVE_RATIO_3_0,Ratio value for write DQS slave DLL.[3:0] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x58 18.--27. 1. "PHY_WR_DQS_SLAVE_RATIO_2_1,Ratio value for write DQS slave DLL.[9:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x58 8.--17. 1. "PHY_WR_DQS_SLAVE_RATIO_2_0,Ratio value for write DQS slave DLL.[9:0] for Data PHY 2 Rank 0" newline hexmask.long.byte 0x58 0.--7. 1. "PHY_WR_DQS_SLAVE_RATIO_1_1,Ratio value for write DQS slave DLL.[9:2] for Data PHY 1 Rank 1" line.long 0x5C "EMIF_EXT_PHY_CONTROL_12_SHADOW," bitfld.long 0x5C 28.--31. "PHY_WR_DQS_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x5C 18.--27. 1. "PHY_WR_DQS_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_2_1" newline hexmask.long.word 0x5C 8.--17. 1. "PHY_WR_DQS_SLAVE_RATIO_2_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_2_0" newline hexmask.long.byte 0x5C 0.--7. 1. "PHY_WR_DQS_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_1_1" line.long 0x60 "EMIF_EXT_PHY_CONTROL_13,Ratio value for write DQS slave DLL" hexmask.long.word 0x60 6.--15. 1. "PHY_WR_DQS_SLAVE_RATIO_3_1,Ratio value for write DQS slave DLL.[9:0] for Data PHY 3 Rank 1" newline bitfld.long 0x60 0.--5. "PHY_WR_DQS_SLAVE_RATIO_3_0,Ratio value for write DQS slave DLL.[9:4] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EMIF_EXT_PHY_CONTROL_13_SHADOW," hexmask.long.word 0x64 6.--15. 1. "PHY_WR_DQS_SLAVE_RATIO_3_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_3_1" newline bitfld.long 0x64 0.--5. "PHY_WR_DQS_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EMIF_EXT_PHY_CONTROL_14,Only relevant when using the DLL in unlocked mode" hexmask.long.byte 0x68 24.--31. 1. "PHY_RD_DQS_SLAVE_DELAY,Replace delay/tap value for read DQS slave DLL with this value" newline hexmask.long.word 0x68 12.--20. 1. "PHY_FIFO_WE_IN_DELAY,Replace delay/tap value for slave DLL with this value" newline hexmask.long.word 0x68 0.--8. 1. "PHY_CTRL_SLAVE_DELAY,Replace delay/tap value for address/command timing slave DLL with this value" line.long 0x6C "EMIF_EXT_PHY_CONTROL_14_SHADOW," hexmask.long.byte 0x6C 24.--31. 1. "PHY_RD_DQS_SLAVE_DELAY_SHDW,Shadow field for PHY_RD_DQS_SLAVE_DELAY" newline hexmask.long.word 0x6C 12.--20. 1. "PHY_FIFO_WE_IN_DELAY_SHDW,Shadow field for PHY_FIFO_WE_IN_DELAY" newline hexmask.long.word 0x6C 0.--8. 1. "PHY_CTRL_SLAVE_DELAY_SHDW,Shadow field for PHY_CTRL_SLAVE_DELAY" line.long 0x70 "EMIF_EXT_PHY_CONTROL_15,Only relevant when using the DLL in unlocked mode" hexmask.long.word 0x70 16.--24. 1. "PHY_WR_DATA_SLAVE_DELAY,Replace delay/tap value for write data slave DLL with this value" newline hexmask.long.word 0x70 4.--12. 1. "PHY_WR_DQS_SLAVE_DELAY,Replace delay/tap value for write DQS slave DLL with this value" newline bitfld.long 0x70 0. "PHY_RD_DQS_SLAVE_DELAY,Replace delay/tap value for read DQS slave DLL with this value" "0,1" line.long 0x74 "EMIF_EXT_PHY_CONTROL_15_SHADOW," hexmask.long.word 0x74 16.--24. 1. "PHY_WR_DATA_SLAVE_DELAY_SHDW,Shadow field for PHY_WR_DATA_SLAVE_DELAY" newline hexmask.long.word 0x74 4.--12. 1. "PHY_WR_DQS_SLAVE_DELAY_SHDW,Shadow field for PHY_WR_DQS_SLAVE_DELAY" newline bitfld.long 0x74 0. "PHY_RD_DQS_SLAVE_DELAY_SHDW,Shadow field for PHY_RD_DQS_SLAVE_DELAY" "0,1" line.long 0x78 "EMIF_EXT_PHY_CONTROL_16,Offset value from write dqs to write dq during write leveling" hexmask.long.byte 0x78 21.--27. 1. "PHY_DQ_OFFSET_3,Offset value from write dqs to write dq during write leveling" newline hexmask.long.byte 0x78 14.--20. 1. "PHY_DQ_OFFSET_2,Offset value from write dqs to write dq during write leveling" newline hexmask.long.byte 0x78 7.--13. 1. "PHY_DQ_OFFSET_1,Offset value from write dqs to write dq during write leveling" newline hexmask.long.byte 0x78 0.--6. 1. "PHY_DQ_OFFSET_0,Offset value from write dqs to write dq during write leveling" line.long 0x7C "EMIF_EXT_PHY_CONTROL_16_SHADOW," hexmask.long.byte 0x7C 21.--27. 1. "PHY_DQ_OFFSET_3_SHDW,Shadow field for PHY_DQ_OFFSET_3" newline hexmask.long.byte 0x7C 14.--20. 1. "PHY_DQ_OFFSET_2_SHDW,Shadow field for PHY_DQ_OFFSET_2" newline hexmask.long.byte 0x7C 7.--13. 1. "PHY_DQ_OFFSET_1_SHDW,Shadow field for PHY_DQ_OFFSET_1" newline hexmask.long.byte 0x7C 0.--6. 1. "PHY_DQ_OFFSET_0_SHDW,Shadow field for PHY_DQ_OFFSET_0" line.long 0x80 "EMIF_EXT_PHY_CONTROL_17," bitfld.long 0x80 1. "PHY_GATELVL_INIT_MODE,The user programmable init ratio selection mode" "0,1" newline bitfld.long 0x80 0. "PHY_USE_RANK0_DELAYS,Delay selection" "0,1" hgroup.long 0x284++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_17_SHADOW," group.long 0x288++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_18,DQS gate training starting ratio" hexmask.long.word 0x00 22.--31. 1. "PHY_GATELVL_INIT_RATIO_1_0,DQS gate training starting ratio[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x00 11.--21. 1. "PHY_GATELVL_INIT_RATIO_0_1,DQS gate training starting ratio[10:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x00 0.--10. 1. "PHY_GATELVL_INIT_RATIO_0_0,DQS gate training starting ratio[10:0] for Data PHY 0 Rank 0" hgroup.long 0x28C++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_18_SHADOW," group.long 0x290++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_19,DQS gate training starting ratio" hexmask.long.word 0x00 23.--31. 1. "PHY_GATELVL_INIT_RATIO_2_1,DQS gate training starting ratio[8:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x00 12.--22. 1. "PHY_GATELVL_INIT_RATIO_2_0,DQS gate training starting ratio[10:0] for Data PHY 2 Rank 0" newline hexmask.long.word 0x00 1.--11. 1. "PHY_GATELVL_INIT_RATIO_1_1,DQS gate training starting ratio[10:0] for Data PHY 1 Rank 1" newline bitfld.long 0x00 0. "PHY_GATELVL_INIT_RATIO_1_0,DQS gate training starting ratio[10] for Data PHY 1 Rank 0" "0,1" hgroup.long 0x294++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_19_SHADOW," group.long 0x298++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_20,DQS gate training starting ratio" hexmask.long.word 0x00 13.--23. 1. "PHY_GATELVL_INIT_RATIO_3_1,DQS gate training starting ratio[10:0] for Data PHY 3 Rank 1" newline hexmask.long.word 0x00 2.--12. 1. "PHY_GATELVL_INIT_RATIO_3_0,DQS gate training starting ratio[10:0] for Data PHY 3 Rank 0" newline bitfld.long 0x00 0.--1. "PHY_GATELVL_INIT_RATIO_2_1,DQS gate training starting ratio[10:9] for Data PHY 2 Rank 1" "0,1,2,3" hgroup.long 0x29C++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_20_SHADOW," group.long 0x2A0++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_21,Write leveling starting ratio" bitfld.long 0x00 30.--31. "PHY_WRLVL_INIT_RATIO_1_1,Write leveling starting ratio[1:0] for Data PHY 1 Rank 1" "0,1,2,3" newline hexmask.long.word 0x00 20.--29. 1. "PHY_WRLVL_INIT_RATIO_1_0,Write leveling starting ratio[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x00 10.--19. 1. "PHY_WRLVL_INIT_RATIO_0_1,Write leveling starting ratio[9:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x00 0.--9. 1. "PHY_WRLVL_INIT_RATIO_0_0,Write leveling starting ratio[9:0] for Data PHY 0 Rank 0" hgroup.long 0x2A4++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_21_SHADOW," group.long 0x2A8++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_22,Write leveling starting ratio" bitfld.long 0x00 28.--31. "PHY_WRLVL_INIT_RATIO_3_0,Write leveling starting ratio[3:0] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 18.--27. 1. "PHY_WRLVL_INIT_RATIO_2_1,Write leveling starting ratio[9:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x00 8.--17. 1. "PHY_WRLVL_INIT_RATIO_2_0,Write leveling starting ratio[9:0] for Data PHY 2 Rank 0" newline hexmask.long.byte 0x00 0.--7. 1. "PHY_WRLVL_INIT_RATIO_1_1,Write leveling starting ratio[9:2] for Data PHY 1 Rank 1" hgroup.long 0x2AC++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_22_SHADOW," group.long 0x2B0++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_23,Write leveling starting ratio" hexmask.long.word 0x00 6.--15. 1. "PHY_WRLVL_INIT_RATIO_3_1,Write leveling starting ratio[9:0] for Data PHY 3 Rank 1" newline bitfld.long 0x00 0.--5. "PHY_WRLVL_INIT_RATIO_3_0,Write leveling starting ratio[9:4] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hgroup.long 0x2B4++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_23_SHADOW," group.long 0x2B8++0x07 line.long 0x00 "EMIF_EXT_PHY_CONTROL_24," bitfld.long 0x00 10. "PHY_RDC_FIFO_RST_ERR_CNT_CLR,Clear/reset theEMIF_PHY_STATUS_20[15:0] PHY_REG_RDC_FIFO_RST_ERR_CNT_0 EMIF_PHY_STATUS_5[11:0] PHY_REG_RDFIFO_RDPTR_* and EMIF_PHY_STATUS_5[27:16] PHY_REG_RDFIFO_WRPTR_* status fields and flags" "0,1" newline bitfld.long 0x00 9. "PHY_MDLL_UNLOCK_CLEAR,Clears theEMIF_PHY_STATUS_20[19:16] PHY_REG_STATUS_MDLL_UNLOCK_STICKY_* status flags" "0,1" newline bitfld.long 0x00 8. "PHY_FIFO_WE_IN_MISALIGNED_CLR,Clears the forEMIF_PHY_STATUS_20[25:20] PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_* status flags" "0,1" newline bitfld.long 0x00 4.--7. "PHY_WRLVL_NUM_OF_DQ0,This bit field determines the number of samples for dq0_in for each ratio increment by the write leveling FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "PHY_GATELVL_NUM_OF_DQ0,This bit field determines the number of samples for dq0_in for each ratio increment by the Gate Training FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_EXT_PHY_CONTROL_24_SHADOW," bitfld.long 0x04 0.--3. "PHY_GATELVL_NUM_OF_DQ0_SHDW,Shadow field for PHY_GATELVL_NUM_OF_DQ0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 2. (list 1. 2. )(list 0x00 0x04 ) group.long ($2+0x114)++0x03 line.long 0x00 "EMIF_ECC_ADDRESS_RANGE_$1," hexmask.long.word 0x00 16.--31. 1. "REG_ECC_END_ADDR_1,End caddress[32:17] for ECC address range 1" newline hexmask.long.word 0x00 0.--15. 1. "REG_ECC_STRT_ADDR_1,Start caddress[32:17] for ECC address range 1" repeat.end tree.end tree "EMIF2" base ad:0x4D000000 rgroup.long 0x00++0x2F line.long 0x00 "EMIF_REVISION,Revision number register" line.long 0x04 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x04 31. "BE,Big endian mode select for 8 and 16-bit devices set to 1 for big endian or 0 for little endian operation" "0,1" newline bitfld.long 0x04 30. "DUAL_CLK_MODE,Dual Clock mode" "0,1" newline bitfld.long 0x04 29. "FAST_INIT,Fast Init" "0,1" newline bitfld.long 0x04 6. "RDLVLGATETO,Read DQS Gate Training Timeout" "0,1" newline bitfld.long 0x04 5. "RDLVLTO,Read Data Eye Training Timeout" "0,1" newline bitfld.long 0x04 4. "WRLVLTO,Write Leveling Timeout" "0,1" newline bitfld.long 0x04 2. "PHY_DLL_READY,DDR PHY Ready" "0,1" line.long 0x08 "EMIF_SDRAM_CONFIG,SDRAM Config Register" bitfld.long 0x08 29.--31. "SDRAM_TYPE,SDRAM Type selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 27.--28. "IBANK_POS,Internal bank position" "0,1,2,3" newline bitfld.long 0x08 24.--26. "DDR_TERM,DDR3 termination resistor value" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 23. "DDR2_DDQS,DDR2 differential DDQS enable" "0,1" newline bitfld.long 0x08 21.--22. "DYN_ODT,DDR3 Dynamic ODT" "0,1,2,3" newline bitfld.long 0x08 20. "DDR_DISABLE_DLL,Disable DLL select" "0,1" newline bitfld.long 0x08 18.--19. "SDRAM_DRIVE,SDRAM drive strength.For DDR3 set to 0 for RZQ/6 and set to 1 for RZQ/7" "0,1,2,3" newline bitfld.long 0x08 16.--17. "CWL,DDR3 CAS Write latency" "0,1,2,3" newline bitfld.long 0x08 14.--15. "NARROW_MODE,SDRAM data bus width" "0,1,2,3" newline bitfld.long 0x08 10.--13. "CL,CAS Latency (referred to as read latency (RL) in some SDRAM specs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 7.--9. "ROWSIZE,Row Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 4.--6. "IBANK,Internal Bank setup" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0.--2. "PAGESIZE,Page Size" "0,1,2,3,4,5,6,7" line.long 0x0C "EMIF_SDRAM_CONFIG_2,SDRAM Config Register 2 CAUTION: This register is loaded with values by control module at device reset" bitfld.long 0x0C 27. "EBANK_POS,External bank position" "0,1" line.long 0x10 "EMIF_SDRAM_REFRESH_CONTROL,SDRAM Refresh Control Register" bitfld.long 0x10 31. "INITREF_DIS,Initialization and Refresh disable" "0,1" newline bitfld.long 0x10 29. "SRT,DDR3 Self Refresh temperature range" "0,1" newline bitfld.long 0x10 28. "ASR,DDR3 Auto Self Refresh enable" "0,1" newline bitfld.long 0x10 24.--26. "PASR,Partial Array Self Refresh" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 0.--15. 1. "REFRESH_RATE,Refresh Rate" line.long 0x14 "EMIF_SDRAM_REFRESH_CONTROL_SHADOW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x14 0.--15. 1. "REFRESH_RATE_SHDW,Shadow field for REFRESH_RATE" line.long 0x18 "EMIF_SDRAM_TIMING_1,SDRAM Timing 1 Register" bitfld.long 0x18 29.--31. "T_RTW,Minimum number of DDR clock cycles between Read to Write data phases minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 25.--28. "T_RP,Minimum number of DDR clock cycles from Precharge to Activate or Refresh minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 21.--24. "T_RCD,Minimum number of DDR clock cycles from Activate to Read or Write minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 17.--20. "T_WR,Minimum number of DDR clock cycles from last Write transfer to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x18 12.--16. "T_RAS,Minimum number of DDR clock cycles from Activate to Precharge minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x18 6.--11. "T_RC,Minimum number of DDR clock cycles from Activate to Activate minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x18 3.--5. "T_RRD,Minimum number of DDR clock cycles from Activate to Activate for a different bank minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "T_WTR,Minimum number of DDR clock cycles from last Write to Read minus one" "0,1,2,3,4,5,6,7" line.long 0x1C "EMIF_SDRAM_TIMING_1_SHADOW,SDRAM Timing 1 Shadow Register" bitfld.long 0x1C 29.--31. "T_RTW_SHDW,Shadow field for T_RTW" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 25.--28. "T_RP_SHDW,Shadow field for T_RP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 21.--24. "T_RCD_SHDW,Shadow field for T_RCD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 17.--20. "T_WR_SHDW,Shadow field for T_WR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x1C 12.--16. "T_RAS_SHDW,Shadow field for T_RAS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x1C 6.--11. "T_RC_SHDW,Shadow field for T_RC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x1C 3.--5. "T_RRD_SHDW,Shadow field for T_RRD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0.--2. "T_WTR_SHDW,Shadow field for T_WTR" "0,1,2,3,4,5,6,7" line.long 0x20 "EMIF_SDRAM_TIMING_2,SDRAM Timing 2 Register" bitfld.long 0x20 28.--30. "T_XP,Minimum number of DDR clock cycles from power-down exit to any command other than a read command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 25.--27. "T_ODT,Minimum number of DDR clock cycles from ODT enable to write data driven for DDR3" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 16.--24. 1. "T_XSNR,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command minus one" newline hexmask.long.word 0x20 6.--15. 1. "T_XSRD,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command minus one" newline bitfld.long 0x20 3.--5. "T_RTP,Minimum number of DDR clock cycles for the last read command to a Precharge command minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "T_CKE,Minimum number of DDR clock cycles between CKE pin changes minus one" "0,1,2,3,4,5,6,7" line.long 0x24 "EMIF_SDRAM_TIMING_2_SHADOW,SDRAM Timing 2 Shadow Register" bitfld.long 0x24 28.--30. "T_XP_SHDW,Shadow field for T_XP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 25.--27. "T_ODT_SHDW,Shadow field for T_ODT" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x24 16.--24. 1. "T_XSNR_SHDW,Shadow field for T_XSNR" newline hexmask.long.word 0x24 6.--15. 1. "T_XSRD_SHDW,Shadow field for T_XSRD" newline bitfld.long 0x24 3.--5. "T_RTP_SHDW,Shadow field for T_RTP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0.--2. "T_CKE_SHDW,Shadow field for T_CKE" "0,1,2,3,4,5,6,7" line.long 0x28 "EMIF_SDRAM_TIMING_3,SDRAM Timing 3 Register" bitfld.long 0x28 28.--31. "T_PDLL_UL,Minimum number of DDR clock cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x28 21.--23. "T_CKESR,Minimum number of DDR clock cycles for which SDRAM must remain in Self Refresh minus one" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 15.--20. "ZQ_ZQCS,Number of DDR clock cycles for a ZQCS command minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x28 4.--12. 1. "T_RFC,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate minus one" newline bitfld.long 0x28 0.--3. "T_RAS_MAX,Maximum number of REFRESH_RATE intervals from Activate to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "EMIF_SDRAM_TIMING_3_SHADOW,SDRAM Timing 3 Shadow Register" bitfld.long 0x2C 28.--31. "T_PDLL_UL_SHDW,Shadow field for T_PDLL_UL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x2C 21.--23. "T_CKESR_SHDW,Shadow field for T_CKESR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 15.--20. "ZQ_ZQCS_SHDW,Shadow field for ZQ_ZQCS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x2C 4.--12. 1. "T_RFC_SHDW,Shadow field for T_RFC" newline bitfld.long 0x2C 0.--3. "T_RAS_MAX_SHDW,Shadow field for T_RAS_MAX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x07 line.long 0x00 "EMIF_POWER_MANAGEMENT_CONTROL,Power Management Control Register" bitfld.long 0x00 12.--15. "PD_TIM,Power Management timer for Power-Down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--10. "LP_MODE,Automatic Power Management enable" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--7. "SR_TIM,Power Management timer for Self Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_POWER_MANAGEMENT_CONTROL_SHADOW,Power Management Control Shadow Register" bitfld.long 0x04 12.--15. "PD_TIM_SHDW,Shadow field for PD_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 4.--7. "SR_TIM_SHDW,Shadow field for SR_TIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x0B line.long 0x00 "EMIF_OCP_CONFIG,OCP Config Register" bitfld.long 0x00 24.--27. "SYS_THRESH_MAX,System OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 20.--23. "MPU_THRESH_MAX,MPU Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_OCP_CONFIG_VALUE_1,OCP Config Value 1 Register" bitfld.long 0x04 30.--31. "SYS_BUS_WIDTH,System OCP data bus width" "0,1,2,3" newline hexmask.long.byte 0x04 8.--15. 1. "WR_FIFO_DEPTH,Write Data FIFO depth" newline hexmask.long.byte 0x04 0.--7. 1. "CMD_FIFO_DEPTH,Command FIFO depth" line.long 0x08 "EMIF_OCP_CONFIG_VALUE_2,OCP Config Value 2 Register" hexmask.long.byte 0x08 16.--23. 1. "RREG_FIFO_DEPTH,Register Read Data FIFO depth" newline hexmask.long.byte 0x08 8.--15. 1. "RSD_FIFO_DEPTH,SDRAM Read Data FIFO depth" newline hexmask.long.byte 0x08 0.--7. 1. "RCMD_FIFO_DEPTH,Read Command FIFO depth" rgroup.long 0x80++0x27 line.long 0x00 "EMIF_PERFORMANCE_COUNTER_1,Performance Counter 1 Register" line.long 0x04 "EMIF_PERFORMANCE_COUNTER_2,Performance Counter 2 Register" line.long 0x08 "EMIF_PERFORMANCE_COUNTER_CONFIG,Performance Counter Config Register" bitfld.long 0x08 31. "CNTR2_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline bitfld.long 0x08 30. "CNTR2_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_2 register" "0,1" newline bitfld.long 0x08 16.--19. "CNTR2_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 15. "CNTR1_MCONNID_EN,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline bitfld.long 0x08 14. "CNTR1_REGION_EN,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_1 register" "0,1" newline bitfld.long 0x08 0.--3. "CNTR1_CFG,Filter configuration forEMIF_PERFORMANCE_COUNTER_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT,Performance Counter Master Region Select Register The values programmed into the MCONNIDx fields are those in Table ConnID Mapping (Debug View). in . On-Chip Debug Support. left-shifted by 2 bits" hexmask.long.byte 0x0C 24.--31. 1. "MCONNID2,MConnID forEMIF_PERFORMANCE_COUNTER_2 register" newline bitfld.long 0x0C 16.--17. "REGION_SEL2,MAddrSpace forEMIF_PERFORMANCE_COUNTER_2 register" "0,1,2,3" newline hexmask.long.byte 0x0C 8.--15. 1. "MCONNID1,MConnID forEMIF_PERFORMANCE_COUNTER_1 register" newline bitfld.long 0x0C 0.--1. "REGION_SEL1,MAddrSpace forEMIF_PERFORMANCE_COUNTER_1 register" "0,1,2,3" line.long 0x10 "EMIF_PERFORMANCE_COUNTER_TIME,Performance Counter Time Register" line.long 0x14 "EMIF_MISC_REG," bitfld.long 0x14 0. "DLL_CALIB_OS,Phy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse" "0,1" line.long 0x18 "EMIF_DLL_CALIB_CTRL,Control register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps" bitfld.long 0x18 16.--19. "ACK_WAIT,The ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x18 0.--8. 1. "DLL_CALIB_INTERVAL,This field determines the interval between phy_dll_calib generation" line.long 0x1C "EMIF_DLL_CALIB_CTRL_SHADOW,Read Idle Control Shadow Register" bitfld.long 0x1C 16.--19. "ACK_WAIT_SHDW,Shadow field for ACK_WAIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x1C 0.--8. 1. "DLL_CALIB_INTERVAL_SHDW,Shadow field for DLL_CALIB_INTERVAL" line.long 0x20 "EMIF_END_OF_INTERRUPT," bitfld.long 0x20 0. "EOI,Software End Of Interrupt (EOI) control" "0,1" line.long 0x24 "EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS,System OCP Interrupt Raw Status Register" bitfld.long 0x24 5. "ONEBIT_ECC_ERR_SYS,Raw status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x24 4. "TWOBIT_ECC_ERR_SYS,Raw status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x24 3. "WR_ECC_ERR_SYS,Raw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline bitfld.long 0x24 0. "ERR_SYS,Raw status of system OCP interrupt for command or address error" "0,1" group.long 0xAC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_STATUS,System OCP Interrupt Status Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline bitfld.long 0x00 0. "ERR_SYS,Enabled status of system OCP interrupt interrupt for command or address error" "0,1" group.long 0xB4++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET,System OCP Interrupt Enable Set Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of sysem ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable set for system OCP interrupt for command or address error" "0,1" group.long 0xBC++0x03 line.long 0x00 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR,System OCP Interrupt Enable Clear Register" bitfld.long 0x00 5. "ONEBIT_ECC_ERR_SYS,Enabled status of system ECC one bit error correction interrupt" "0,1" newline bitfld.long 0x00 4. "TWOBIT_ECC_ERR_SYS,Enabled status of system ECC two bit error detection interrupt" "0,1" newline bitfld.long 0x00 3. "WR_ECC_ERR_SYS,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location" "0,1" newline bitfld.long 0x00 0. "EN_ERR_SYS,Enable clear for system OCP interrupt for command or address error" "0,1" group.long 0xC8++0x03 line.long 0x00 "EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG,SDRAM Output Impedance Calibration Config Register" bitfld.long 0x00 30. "ZQ_CS0EN,Writing a 1 enables ZQ calibration for CS0" "0,1" newline bitfld.long 0x00 28. "ZQ_SFEXITEN,Writing a 1 enables the issuing of ZQCL on Self-Refresh Active Power-Down and Precharge Power-Down exit" "0,1" newline bitfld.long 0x00 16.--17. "ZQ_ZQCL_MULT,Indicates the number of ZQCS intervals that make up a ZQCL duration minus one" "0,1,2,3" newline hexmask.long.word 0x00 0.--15. 1. "ZQ_REFINTERVAL,Number of refresh periods between ZQCS commands" rgroup.long 0xD0++0x0F line.long 0x00 "EMIF_OCP_ERROR_LOG,OCP Error Log Register" bitfld.long 0x00 14.--15. "MADDRSPACE,Address space of the first errored transaction" "0,1,2,3" newline bitfld.long 0x00 11.--13. "MBURSTSEQ,Addressing mode of the first errored transaction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. "MCMD,Command type of the first errored transaction" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. "MCONNID,Connection ID of the first errored transaction" line.long 0x04 "EMIF_READ_WRITE_LEVELING_RAMP_WINDOW,Read/write leveling ramp window register" hexmask.long.word 0x04 0.--12. 1. "RDWRLVLINC_RMP_WIN,Incremental leveling ramp window in number of refresh periods" line.long 0x08 "EMIF_READ_WRITE_LEVELING_RAMP_CONTROL,Read/write leveling ramp control register" bitfld.long 0x08 31. "RDWRLVL_EN,Read-Write Leveling enable" "0,1" newline hexmask.long.byte 0x08 24.--30. 1. "RDWRLVLINC_RMP_PRE,Incremental leveling pre-scalar in number of refresh periods during ramp window" newline hexmask.long.byte 0x08 16.--23. 1. "RDLVLINC_RMP_INT,Incremental read data eye training interval during ramp window" newline hexmask.long.byte 0x08 8.--15. 1. "RDLVLGATEINC_RMP_INT,Incremental read DQS gate training interval during ramp window" newline hexmask.long.byte 0x08 0.--7. 1. "WRLVLINC_RMP_INT,Incremental write leveling interval during ramp window" line.long 0x0C "EMIF_READ_WRITE_LEVELING_CONTROL,Read/write leveling control register" bitfld.long 0x0C 31. "RDWRLVLFULL_START,Full leveling trigger" "0,1" newline hexmask.long.byte 0x0C 24.--30. 1. "RDWRLVLINC_PRE,Incremental leveling pre-scalar in number of refresh periods" newline hexmask.long.byte 0x0C 16.--23. 1. "RDLVLINC_INT,Incremental read data eye training interval" newline hexmask.long.byte 0x0C 8.--15. 1. "RDLVLGATEINC_INT,Incremental read DQS gate training interval" newline hexmask.long.byte 0x0C 0.--7. 1. "WRLVLINC_INT,Incremental write leveling interval" group.long 0xE4++0x07 line.long 0x00 "EMIF_DDR_PHY_CONTROL_1,PHY control register 1" bitfld.long 0x00 27. "RDLVL_MASK,Writing a 1 to this field will mask read data eye training during full leveling command plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 26. "RDLVLGATE_MASK,Writing a 1 to this field will mask dqs gate training during full leveling command plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 25. "WRLVL_MASK,Writing a 1 to this field will mask write leveling training during full leveling command plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values" "0,1" newline bitfld.long 0x00 21. "PHY_HALF_DELAYS,Adjust slave delay line delays to support 2x mode" "0,1" newline bitfld.long 0x00 20. "PHY_CLK_STALL_LEVEL,Enable variable idle value for delay lines" "0,1" newline bitfld.long 0x00 19. "PHY_DIS_CALIB_RST,Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs" "0,1" newline bitfld.long 0x00 18. "PHY_INVERT_CLKOUT,Inverts the polarity of DRAM clock" "0,1" newline hexmask.long.byte 0x00 10.--17. 1. "PHY_DLL_LOCK_DIFF,The maximum number of delay line taps variation while maintaining the master DLL lock" newline bitfld.long 0x00 9. "PHY_FAST_DLL_LOCK,Controls master DLL to lock fast or average logic must be part of locking process" "0,1" newline bitfld.long 0x00 0.--4. "READ_LATENCY,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_DDR_PHY_CONTROL_1_SHADOW," bitfld.long 0x04 27. "RDLVL_MASK_SHDW,Shadow field for RDLVL_MASK" "0,1" newline bitfld.long 0x04 26. "RDLVLGATE_MASK_SHDW,Shadow field for RDLVLGATE_MASK" "0,1" newline bitfld.long 0x04 25. "WRLVL_MASK_SHDW,Shadow field for WRLVL_MASK" "0,1" newline bitfld.long 0x04 21. "PHY_HALF_DELAYS_SHDW,Shadow field for PHY_HALF_DELAYS" "0,1" newline bitfld.long 0x04 20. "PHY_CLK_STALL_LEVEL_SHDW,Shadow field for PHY_CLK_STALL_LEVEL" "0,1" newline bitfld.long 0x04 19. "PHY_DIS_CALIB_RST_SHDW,Shadow field for PHY_DIS_CALIB_RST" "0,1" newline bitfld.long 0x04 18. "PHY_INVERT_CLKOUT_SHDW,Shadow field for PHY_INVERT_CLKOUT" "0,1" newline hexmask.long.byte 0x04 10.--17. 1. "PHY_DLL_LOCK_DIFF_SHDW,Shadow field for PHY_DLL_LOCK_DIFF" newline bitfld.long 0x04 9. "PHY_FAST_DLL_SHDW,Shadow field for PHY_FAST_DLL" "0,1" newline bitfld.long 0x04 0.--4. "READ_LATENCY_SHDW,Shadow field for READ_LATENCY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x0B line.long 0x00 "EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING," bitfld.long 0x00 31. "PRI_COS_MAP_EN,Set 1 to enable priority to class of service mapping" "0,1" newline bitfld.long 0x00 14.--15. "PRI_7_COS,Class of service for commands with priority of 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. "PRI_6_COS,Class of service for commands with priority of 6" "0,1,2,3" newline bitfld.long 0x00 10.--11. "PRI_5_COS,Class of service for commands with priority of 5" "0,1,2,3" newline bitfld.long 0x00 8.--9. "PRI_4_COS,Class of service for commands with priority of 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. "PRI_3_COS,Class of service for commands with priority of 3" "0,1,2,3" newline bitfld.long 0x00 4.--5. "PRI_2_COS,Class of service for commands with priority of 2" "0,1,2,3" newline bitfld.long 0x00 2.--3. "PRI_1_COS,Class of service for commands with priority of 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. "PRI_0_COS,Class of service for commands with priority of 0" "0,1,2,3" line.long 0x04 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING," bitfld.long 0x04 31. "CONNID_COS_1_MAP_EN,Set 1 to enable Connection ID to class of service 1 mapping" "0,1" newline hexmask.long.byte 0x04 23.--30. 1. "CONNID_1_COS_1,Connection ID value 1 for class of service 1" newline bitfld.long 0x04 20.--22. "MSK_1_COS_1,Mask for Connection ID value 1 for class of service 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x04 12.--19. 1. "CONNID_2_COS_1,Connection ID value 2 for class of service 1" newline bitfld.long 0x04 10.--11. "MSK_2_COS_1,Mask for Connection ID value 2 for class of service 1" "0,1,2,3" newline hexmask.long.byte 0x04 2.--9. 1. "CONNID_3_COS_1,Connection ID value 3 for class of service 1" newline bitfld.long 0x04 0.--1. "MSK_3_COS_1,Mask for Connection ID value 3 for class of service 1" "0,1,2,3" line.long 0x08 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING," bitfld.long 0x08 31. "CONNID_COS_2_MAP_EN,Set 1 to enable Connection ID to class of service 2 mapping" "0,1" newline hexmask.long.byte 0x08 23.--30. 1. "CONNID_1_COS_2,Connection ID value 1 for class of service 2" newline bitfld.long 0x08 20.--22. "MSK_1_COS_2,Mask for Connection ID value 1 for class of service 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 12.--19. 1. "CONNID_2_COS_2,Connection ID value 2 for class of service 2" newline bitfld.long 0x08 10.--11. "MSK_2_COS_2,Mask for Connection ID value 2 for class of service 2" "0,1,2,3" newline hexmask.long.byte 0x08 2.--9. 1. "CONNID_3_COS_2,Connection ID value 3 for class of service 2" newline bitfld.long 0x08 0.--1. "MSK_3_COS_2,Mask for Connection ID value 3 for class of service 2" "0,1,2,3" group.long 0x120++0x07 line.long 0x00 "EMIF_READ_WRITE_EXECUTION_THRESHOLD," bitfld.long 0x00 31. "MFLAG_OVERRIDE,Mflag override" "MFLAG_OVERRIDE_0,MFLAG_OVERRIDE_1" newline bitfld.long 0x00 30. "LL_BUBBLE_ENABLE,LL bubble enable" "LL_BUBBLE_ENABLE_0,LL_BUBBLE_ENABLE_1" newline bitfld.long 0x00 8.--12. "WR_THRSH,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0.--4. "RD_THRSH,Read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EMIF_COS_CONFIG,Priority Raise Counter Register" hexmask.long.byte 0x04 16.--23. 1. "COS_COUNT_1,Priority Raise Counter for class of service 1" newline hexmask.long.byte 0x04 8.--15. 1. "COS_COUNT_2,Priority Raise Counter for class of service 2" newline hexmask.long.byte 0x04 0.--7. 1. "PR_OLD_COUNT,Priority Raise Old Counter" rgroup.long 0x144++0x03 line.long 0x00 "EMIF_PHY_STATUS_1," bitfld.long 0x00 5. "PHY_REG_STATUS_DLL_LOCK_3,Reflects lock status of DLL of data PHY 3" "0,1" newline bitfld.long 0x00 4. "PHY_REG_STATUS_DLL_LOCK_2,Reflects lock status of DLL of data PHY 2" "0,1" newline bitfld.long 0x00 3. "PHY_REG_STATUS_DLL_LOCK_1,Reflects lock status of DLL of data PHY 1" "0,1" newline bitfld.long 0x00 2. "PHY_REG_STATUS_DLL_LOCK_0,Reflects lock status of DLL of data PHY 0" "0,1" newline bitfld.long 0x00 1. "PHY_REG_STATUS_PHY_CTRL_DLL_LOCK_1,Reflects lock status of DLL 1 (command PHY 2)" "0,1" newline bitfld.long 0x00 0. "PHY_REG_STATUS_PHY_CTRL_DLL_LOCK_0,Reflects lock status of DLL 0 (command PHY 0 and 1)" "0,1" rgroup.long 0x18C++0x07 line.long 0x00 "EMIF_PHY_STATUS_20," bitfld.long 0x00 31. "PHY_REG_WRLVL_INC_FAIL_1,Incremental Write Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 30. "PHY_REG_WRLVL_INC_FAIL_0,Incremental Write Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 29. "PHY_REG_RDLVL_INC_FAIL_3,Incremental Read Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 28. "PHY_REG_RDLVL_INC_FAIL_2,Incremental Read Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 27. "PHY_REG_RDLVL_INC_FAIL_1,Incremental Read Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 26. "PHY_REG_RDLVL_INC_FAIL_0,Incremental Read Leveling Fail Status Flag" "0,1" newline bitfld.long 0x00 25. "PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_3,Data PHY 3" "0,1" newline bitfld.long 0x00 24. "PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_2,Data PHY 2" "0,1" newline bitfld.long 0x00 23. "PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_1,Data PHY 1" "0,1" newline bitfld.long 0x00 22. "PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_0,Data PHY 0" "0,1" newline bitfld.long 0x00 21. "PHY_REG_STATUS_PHY_CTRL_MDLL_UNLOCK_STICKY_1,Command DLL 1 (command PHY 2)" "0,1" newline bitfld.long 0x00 20. "PHY_REG_STATUS_PHY_CTRL_MDLL_UNLOCK_STICKY_0,Command DLL 0 (command PHYs 0 and 1)" "0,1" newline bitfld.long 0x00 19. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY_3,Data PHY 3" "0,1" newline bitfld.long 0x00 18. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY_2,Data PHY 2" "0,1" newline bitfld.long 0x00 17. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY_1,Data PHY 1" "0,1" newline bitfld.long 0x00 16. "PHY_REG_STATUS_MDLL_UNLOCK_STICKY_0,Data PHY 0" "0,1" newline bitfld.long 0x00 12.--15. "PHY_REG_RDC_FIFO_RST_ERR_CNT_3,Counter for counting the number of times the pointers of read capture FIFO differ when they are reset by dll_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "PHY_REG_RDC_FIFO_RST_ERR_CNT_2,Counter for counting the number of times the pointers of read capture FIFO differ when they are reset by dll_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "PHY_REG_RDC_FIFO_RST_ERR_CNT_1,Counter for counting the number of times the pointers of read capture FIFO differ when they are reset by dll_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "PHY_REG_RDC_FIFO_RST_ERR_CNT_0,Counter for counting the number of times the pointers of read capture FIFO differ when they are reset by dll_calib" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_PHY_STATUS_21," bitfld.long 0x04 5. "PHY_REG_GATELVL_INC_FAIL_3,Incremental Gate Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 4. "PHY_REG_GATELVL_INC_FAIL_2,Incremental Gate Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 3. "PHY_REG_GATELVL_INC_FAIL_1,Incremental Gate Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 2. "PHY_REG_GATELVL_INC_FAIL_0,Incremental Gate Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 1. "PHY_REG_WRLVL_INC_FAIL_3,Incremental Write Leveling Fail Status Flag" "0,1" newline bitfld.long 0x04 0. "PHY_REG_WRLVL_INC_FAIL_2,Incremental Write Leveling Fail Status Flag" "0,1" group.long 0x200++0x83 line.long 0x00 "EMIF_EXT_PHY_CONTROL_1,Programs command PHY slave DLL ratio" hexmask.long.word 0x00 20.--29. 1. "PHY_CTRL_SLAVE_RATIO_2,Slave DLL ratio for command PHY 2" newline hexmask.long.word 0x00 10.--19. 1. "PHY_CTRL_SLAVE_RATIO_1,Slave DLL ratio for command PHY 1" newline hexmask.long.word 0x00 0.--9. 1. "PHY_CTRL_SLAVE_RATIO_0,Slave DLL ratio for command PHY 0" line.long 0x04 "EMIF_EXT_PHY_CONTROL_1_SHADOW," hexmask.long.word 0x04 20.--29. 1. "PHY_CTRL_SLAVE_RATIO_2_SHDW,Shadow field for PHY_CTRL_SLAVE_RATIO_2" newline hexmask.long.word 0x04 10.--19. 1. "PHY_CTRL_SLAVE_RATIO_1_SHDW,Shadow field for PHY_CTRL_SLAVE_RATIO_1" newline hexmask.long.word 0x04 0.--9. 1. "PHY_CTRL_SLAVE_RATIO_0_SHDW,Shadow field for PHY_CTRL_SLAVE_RATIO_0" line.long 0x08 "EMIF_EXT_PHY_CONTROL_2,DQS gate opening delay" hexmask.long.word 0x08 22.--31. 1. "PHY_FIFO_WE_SLAVE_RATIO_1_0,DQS gate opening delay[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x08 11.--21. 1. "PHY_FIFO_WE_SLAVE_RATIO_0_1,DQS gate opening delay[10:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x08 0.--10. 1. "PHY_FIFO_WE_SLAVE_RATIO_0_0,DQS gate opening delay[10:0] for Data PHY 0 Rank 0" line.long 0x0C "EMIF_EXT_PHY_CONTROL_2_SHADOW," hexmask.long.word 0x0C 22.--31. 1. "PHY_FIFO_WE_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_1_0" newline hexmask.long.word 0x0C 11.--21. 1. "PHY_FIFO_WE_SLAVE_RATIO_0_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_0_1" newline hexmask.long.word 0x0C 0.--10. 1. "PHY_FIFO_WE_SLAVE_RATIO_0_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_0_0" line.long 0x10 "EMIF_EXT_PHY_CONTROL_3,DQS gate opening delay" hexmask.long.word 0x10 23.--31. 1. "PHY_FIFO_WE_SLAVE_RATIO_2_1,DQS gate opening delay[8:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x10 12.--22. 1. "PHY_FIFO_WE_SLAVE_RATIO_2_0,DQS gate opening delay[10:0] for Data PHY 2 Rank 0" newline hexmask.long.word 0x10 1.--11. 1. "PHY_FIFO_WE_SLAVE_RATIO_1_1,DQS gate opening delay[10:0] for Data PHY 1 Rank 1" newline bitfld.long 0x10 0. "PHY_FIFO_WE_SLAVE_RATIO_1_0,DQS gate opening delay[10] for Data PHY 1 Rank 0" "0,1" line.long 0x14 "EMIF_EXT_PHY_CONTROL_3_SHADOW," hexmask.long.word 0x14 23.--31. 1. "PHY_FIFO_WE_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_2_1" newline hexmask.long.word 0x14 12.--22. 1. "PHY_FIFO_WE_SLAVE_RATIO_2_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_2_0" newline hexmask.long.word 0x14 1.--11. 1. "PHY_FIFO_WE_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_1_1" newline bitfld.long 0x14 0. "PHY_FIFO_WE_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_1_0" "0,1" line.long 0x18 "EMIF_EXT_PHY_CONTROL_4,DQS gate opening delay" hexmask.long.word 0x18 13.--23. 1. "PHY_FIFO_WE_SLAVE_RATIO_3_1,DQS gate opening delay[10:0] for Data PHY 3 Rank 1" newline hexmask.long.word 0x18 2.--12. 1. "PHY_FIFO_WE_SLAVE_RATIO_3_0,DQS gate opening delay[10:0] for Data PHY 3 Rank 0" newline bitfld.long 0x18 0.--1. "PHY_FIFO_WE_SLAVE_RATIO_2_1,DQS gate opening delay[10:9] for Data PHY 2 Rank 1" "0,1,2,3" line.long 0x1C "EMIF_EXT_PHY_CONTROL_4_SHADOW," hexmask.long.word 0x1C 13.--23. 1. "PHY_FIFO_WE_SLAVE_RATIO_3_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_3_1" newline hexmask.long.word 0x1C 2.--12. 1. "PHY_FIFO_WE_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_3_0" newline bitfld.long 0x1C 0.--1. "PHY_FIFO_WE_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_FIFO_WE_SLAVE_RATIO_2_1" "0,1,2,3" line.long 0x20 "EMIF_EXT_PHY_CONTROL_5,Ratio value for read DQS slave DLL" bitfld.long 0x20 30.--31. "PHY_RD_DQS_SLAVE_RATIO_1_1,Ratio value for read DQS slave DLL.[1:0] for Data PHY 1 Rank 1" "0,1,2,3" newline hexmask.long.word 0x20 20.--29. 1. "PHY_RD_DQS_SLAVE_RATIO_1_0,Ratio value for read DQS slave DLL.[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x20 10.--19. 1. "PHY_RD_DQS_SLAVE_RATIO_0_1,Ratio value for read DQS slave DLL.[9:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x20 0.--9. 1. "PHY_RD_DQS_SLAVE_RATIO_0_0,Ratio value for read DQS slave DLL.[9:0] for Data PHY 0 Rank 0" line.long 0x24 "EMIF_EXT_PHY_CONTROL_5_SHADOW," bitfld.long 0x24 30.--31. "PHY_RD_DQS_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_1_1" "0,1,2,3" newline hexmask.long.word 0x24 20.--29. 1. "PHY_RD_DQS_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_1_0" newline hexmask.long.word 0x24 10.--19. 1. "PHY_RD_DQS_SLAVE_RATIO_0_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_0_1" newline hexmask.long.word 0x24 0.--9. 1. "PHY_RD_DQS_SLAVE_RATIO_0_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_0_0" line.long 0x28 "EMIF_EXT_PHY_CONTROL_6,Ratio value for read DQS slave DLL" bitfld.long 0x28 28.--31. "PHY_RD_DQS_SLAVE_RATIO_3_0,Ratio value for read DQS slave DLL.[3:0] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x28 18.--27. 1. "PHY_RD_DQS_SLAVE_RATIO_2_1,Ratio value for read DQS slave DLL.[9:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x28 8.--17. 1. "PHY_RD_DQS_SLAVE_RATIO_2_0,Ratio value for read DQS slave DLL.[9:0] for Data PHY 2 Rank 0" newline hexmask.long.byte 0x28 0.--7. 1. "PHY_RD_DQS_SLAVE_RATIO_1_1,Ratio value for read DQS slave DLL.[9:2] for Data PHY 1 Rank 1" line.long 0x2C "EMIF_EXT_PHY_CONTROL_6_SHADOW," bitfld.long 0x2C 28.--31. "PHY_RD_DQS_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x2C 18.--27. 1. "PHY_RD_DQS_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_2_1" newline hexmask.long.word 0x2C 8.--17. 1. "PHY_RD_DQS_SLAVE_RATIO_2_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_2_0" newline hexmask.long.byte 0x2C 0.--7. 1. "PHY_RD_DQS_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_1_1" line.long 0x30 "EMIF_EXT_PHY_CONTROL_7,Ratio value for read DQS slave DLL" hexmask.long.word 0x30 6.--15. 1. "PHY_RD_DQS_SLAVE_RATIO_3_1,Ratio value for read DQS slave DLL.[9:0] for Data PHY 3 Rank 1" newline bitfld.long 0x30 0.--5. "PHY_RD_DQS_SLAVE_RATIO_3_0,Ratio value for read DQS slave DLL.[9:4] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x34 "EMIF_EXT_PHY_CONTROL_7_SHADOW," hexmask.long.word 0x34 6.--15. 1. "PHY_RD_DQS_SLAVE_RATIO_3_1_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_3_1" newline bitfld.long 0x34 0.--5. "PHY_RD_DQS_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_RD_DQS_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x38 "EMIF_EXT_PHY_CONTROL_8,Ratio value for write data slave DLL" bitfld.long 0x38 30.--31. "PHY_WR_DATA_SLAVE_RATIO_1_1,Ratio value for write data slave DLL.[1:0] for Data PHY 1 Rank 1" "0,1,2,3" newline hexmask.long.word 0x38 20.--29. 1. "PHY_WR_DATA_SLAVE_RATIO_1_0,Ratio value for write data slave DLL.[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x38 10.--19. 1. "PHY_WR_DATA_SLAVE_RATIO_0_1,Ratio value for write data slave DLL.[9:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x38 0.--9. 1. "PHY_WR_DATA_SLAVE_RATIO_0_0,Ratio value for write data slave DLL.[9:0] for Data PHY 0 Rank 0" line.long 0x3C "EMIF_EXT_PHY_CONTROL_8_SHADOW," bitfld.long 0x3C 30.--31. "PHY_WR_DATA_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_1_1" "0,1,2,3" newline hexmask.long.word 0x3C 20.--29. 1. "PHY_WR_DATA_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_1_0" newline hexmask.long.word 0x3C 10.--19. 1. "PHY_WR_DATA_SLAVE_RATIO_0_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_0_1" newline hexmask.long.word 0x3C 0.--9. 1. "PHY_WR_DATA_SLAVE_RATIO_0_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_0_0" line.long 0x40 "EMIF_EXT_PHY_CONTROL_9,Ratio value for write data slave DLL" bitfld.long 0x40 28.--31. "PHY_WR_DATA_SLAVE_RATIO_3_0,Ratio value for write data slave DLL.[3:0] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x40 18.--27. 1. "PHY_WR_DATA_SLAVE_RATIO_2_1,Ratio value for write data slave DLL.[9:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x40 8.--17. 1. "PHY_WR_DATA_SLAVE_RATIO_2_0,Ratio value for write data slave DLL.[9:0] for Data PHY 2 Rank 0" newline hexmask.long.byte 0x40 0.--7. 1. "PHY_WR_DATA_SLAVE_RATIO_1_1,Ratio value for write data slave DLL.[9:2] for Data PHY 1 Rank 1" line.long 0x44 "EMIF_EXT_PHY_CONTROL_9_SHADOW," bitfld.long 0x44 28.--31. "PHY_WR_DATA_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x44 18.--27. 1. "PHY_WR_DATA_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_2_1" newline hexmask.long.word 0x44 8.--17. 1. "PHY_WR_DATA_SLAVE_RATIO_2_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_2_0" newline hexmask.long.byte 0x44 0.--7. 1. "PHY_WR_DATA_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_1_1" line.long 0x48 "EMIF_EXT_PHY_CONTROL_10,Ratio value for write data slave DLL" hexmask.long.word 0x48 6.--15. 1. "PHY_WR_DATA_SLAVE_RATIO_3_1,Ratio value for write data slave DLL.[9:0] for Data PHY 3 Rank 1" newline bitfld.long 0x48 0.--5. "PHY_WR_DATA_SLAVE_RATIO_3_0,Ratio value for write data slave DLL.[9:4] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x4C "EMIF_EXT_PHY_CONTROL_10_SHADOW," hexmask.long.word 0x4C 6.--15. 1. "PHY_WR_DATA_SLAVE_RATIO_3_1_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_3_1" newline bitfld.long 0x4C 0.--5. "PHY_WR_DATA_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_WR_DATA_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x50 "EMIF_EXT_PHY_CONTROL_11,Ratio value for write DQS slave DLL" bitfld.long 0x50 30.--31. "PHY_WR_DQS_SLAVE_RATIO_1_1,Ratio value for write DQS slave DLL.[1:0] for Data PHY 1 Rank 1" "0,1,2,3" newline hexmask.long.word 0x50 20.--29. 1. "PHY_WR_DQS_SLAVE_RATIO_1_0,Ratio value for write DQS slave DLL.[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x50 10.--19. 1. "PHY_WR_DQS_SLAVE_RATIO_0_1,Ratio value for write DQS slave DLL.[9:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x50 0.--9. 1. "PHY_WR_DQS_SLAVE_RATIO_0_0,Ratio value for write DQS slave DLL.[9:0] for Data PHY 0 Rank 0" line.long 0x54 "EMIF_EXT_PHY_CONTROL_11_SHADOW," bitfld.long 0x54 30.--31. "PHY_WR_DQS_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_1_1" "0,1,2,3" newline hexmask.long.word 0x54 20.--29. 1. "PHY_WR_DQS_SLAVE_RATIO_1_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_1_0" newline hexmask.long.word 0x54 10.--19. 1. "PHY_WR_DQS_SLAVE_RATIO_0_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_0_1" newline hexmask.long.word 0x54 0.--9. 1. "PHY_WR_DQS_SLAVE_RATIO_0_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_0_0" line.long 0x58 "EMIF_EXT_PHY_CONTROL_12,Ratio value for write DQS slave DLL" bitfld.long 0x58 28.--31. "PHY_WR_DQS_SLAVE_RATIO_3_0,Ratio value for write DQS slave DLL.[3:0] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x58 18.--27. 1. "PHY_WR_DQS_SLAVE_RATIO_2_1,Ratio value for write DQS slave DLL.[9:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x58 8.--17. 1. "PHY_WR_DQS_SLAVE_RATIO_2_0,Ratio value for write DQS slave DLL.[9:0] for Data PHY 2 Rank 0" newline hexmask.long.byte 0x58 0.--7. 1. "PHY_WR_DQS_SLAVE_RATIO_1_1,Ratio value for write DQS slave DLL.[9:2] for Data PHY 1 Rank 1" line.long 0x5C "EMIF_EXT_PHY_CONTROL_12_SHADOW," bitfld.long 0x5C 28.--31. "PHY_WR_DQS_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x5C 18.--27. 1. "PHY_WR_DQS_SLAVE_RATIO_2_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_2_1" newline hexmask.long.word 0x5C 8.--17. 1. "PHY_WR_DQS_SLAVE_RATIO_2_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_2_0" newline hexmask.long.byte 0x5C 0.--7. 1. "PHY_WR_DQS_SLAVE_RATIO_1_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_1_1" line.long 0x60 "EMIF_EXT_PHY_CONTROL_13,Ratio value for write DQS slave DLL" hexmask.long.word 0x60 6.--15. 1. "PHY_WR_DQS_SLAVE_RATIO_3_1,Ratio value for write DQS slave DLL.[9:0] for Data PHY 3 Rank 1" newline bitfld.long 0x60 0.--5. "PHY_WR_DQS_SLAVE_RATIO_3_0,Ratio value for write DQS slave DLL.[9:4] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x64 "EMIF_EXT_PHY_CONTROL_13_SHADOW," hexmask.long.word 0x64 6.--15. 1. "PHY_WR_DQS_SLAVE_RATIO_3_1_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_3_1" newline bitfld.long 0x64 0.--5. "PHY_WR_DQS_SLAVE_RATIO_3_0_SHDW,Shadow field for PHY_WR_DQS_SLAVE_RATIO_3_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x68 "EMIF_EXT_PHY_CONTROL_14,Only relevant when using the DLL in unlocked mode" hexmask.long.byte 0x68 24.--31. 1. "PHY_RD_DQS_SLAVE_DELAY,Replace delay/tap value for read DQS slave DLL with this value" newline hexmask.long.word 0x68 12.--20. 1. "PHY_FIFO_WE_IN_DELAY,Replace delay/tap value for slave DLL with this value" newline hexmask.long.word 0x68 0.--8. 1. "PHY_CTRL_SLAVE_DELAY,Replace delay/tap value for address/command timing slave DLL with this value" line.long 0x6C "EMIF_EXT_PHY_CONTROL_14_SHADOW," hexmask.long.byte 0x6C 24.--31. 1. "PHY_RD_DQS_SLAVE_DELAY_SHDW,Shadow field for PHY_RD_DQS_SLAVE_DELAY" newline hexmask.long.word 0x6C 12.--20. 1. "PHY_FIFO_WE_IN_DELAY_SHDW,Shadow field for PHY_FIFO_WE_IN_DELAY" newline hexmask.long.word 0x6C 0.--8. 1. "PHY_CTRL_SLAVE_DELAY_SHDW,Shadow field for PHY_CTRL_SLAVE_DELAY" line.long 0x70 "EMIF_EXT_PHY_CONTROL_15,Only relevant when using the DLL in unlocked mode" hexmask.long.word 0x70 16.--24. 1. "PHY_WR_DATA_SLAVE_DELAY,Replace delay/tap value for write data slave DLL with this value" newline hexmask.long.word 0x70 4.--12. 1. "PHY_WR_DQS_SLAVE_DELAY,Replace delay/tap value for write DQS slave DLL with this value" newline bitfld.long 0x70 0. "PHY_RD_DQS_SLAVE_DELAY,Replace delay/tap value for read DQS slave DLL with this value" "0,1" line.long 0x74 "EMIF_EXT_PHY_CONTROL_15_SHADOW," hexmask.long.word 0x74 16.--24. 1. "PHY_WR_DATA_SLAVE_DELAY_SHDW,Shadow field for PHY_WR_DATA_SLAVE_DELAY" newline hexmask.long.word 0x74 4.--12. 1. "PHY_WR_DQS_SLAVE_DELAY_SHDW,Shadow field for PHY_WR_DQS_SLAVE_DELAY" newline bitfld.long 0x74 0. "PHY_RD_DQS_SLAVE_DELAY_SHDW,Shadow field for PHY_RD_DQS_SLAVE_DELAY" "0,1" line.long 0x78 "EMIF_EXT_PHY_CONTROL_16,Offset value from write dqs to write dq during write leveling" hexmask.long.byte 0x78 21.--27. 1. "PHY_DQ_OFFSET_3,Offset value from write dqs to write dq during write leveling" newline hexmask.long.byte 0x78 14.--20. 1. "PHY_DQ_OFFSET_2,Offset value from write dqs to write dq during write leveling" newline hexmask.long.byte 0x78 7.--13. 1. "PHY_DQ_OFFSET_1,Offset value from write dqs to write dq during write leveling" newline hexmask.long.byte 0x78 0.--6. 1. "PHY_DQ_OFFSET_0,Offset value from write dqs to write dq during write leveling" line.long 0x7C "EMIF_EXT_PHY_CONTROL_16_SHADOW," hexmask.long.byte 0x7C 21.--27. 1. "PHY_DQ_OFFSET_3_SHDW,Shadow field for PHY_DQ_OFFSET_3" newline hexmask.long.byte 0x7C 14.--20. 1. "PHY_DQ_OFFSET_2_SHDW,Shadow field for PHY_DQ_OFFSET_2" newline hexmask.long.byte 0x7C 7.--13. 1. "PHY_DQ_OFFSET_1_SHDW,Shadow field for PHY_DQ_OFFSET_1" newline hexmask.long.byte 0x7C 0.--6. 1. "PHY_DQ_OFFSET_0_SHDW,Shadow field for PHY_DQ_OFFSET_0" line.long 0x80 "EMIF_EXT_PHY_CONTROL_17," bitfld.long 0x80 1. "PHY_GATELVL_INIT_MODE,The user programmable init ratio selection mode" "0,1" newline bitfld.long 0x80 0. "PHY_USE_RANK0_DELAYS,Delay selection" "0,1" hgroup.long 0x284++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_17_SHADOW," group.long 0x288++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_18,DQS gate training starting ratio" hexmask.long.word 0x00 22.--31. 1. "PHY_GATELVL_INIT_RATIO_1_0,DQS gate training starting ratio[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x00 11.--21. 1. "PHY_GATELVL_INIT_RATIO_0_1,DQS gate training starting ratio[10:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x00 0.--10. 1. "PHY_GATELVL_INIT_RATIO_0_0,DQS gate training starting ratio[10:0] for Data PHY 0 Rank 0" hgroup.long 0x28C++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_18_SHADOW," group.long 0x290++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_19,DQS gate training starting ratio" hexmask.long.word 0x00 23.--31. 1. "PHY_GATELVL_INIT_RATIO_2_1,DQS gate training starting ratio[8:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x00 12.--22. 1. "PHY_GATELVL_INIT_RATIO_2_0,DQS gate training starting ratio[10:0] for Data PHY 2 Rank 0" newline hexmask.long.word 0x00 1.--11. 1. "PHY_GATELVL_INIT_RATIO_1_1,DQS gate training starting ratio[10:0] for Data PHY 1 Rank 1" newline bitfld.long 0x00 0. "PHY_GATELVL_INIT_RATIO_1_0,DQS gate training starting ratio[10] for Data PHY 1 Rank 0" "0,1" hgroup.long 0x294++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_19_SHADOW," group.long 0x298++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_20,DQS gate training starting ratio" hexmask.long.word 0x00 13.--23. 1. "PHY_GATELVL_INIT_RATIO_3_1,DQS gate training starting ratio[10:0] for Data PHY 3 Rank 1" newline hexmask.long.word 0x00 2.--12. 1. "PHY_GATELVL_INIT_RATIO_3_0,DQS gate training starting ratio[10:0] for Data PHY 3 Rank 0" newline bitfld.long 0x00 0.--1. "PHY_GATELVL_INIT_RATIO_2_1,DQS gate training starting ratio[10:9] for Data PHY 2 Rank 1" "0,1,2,3" hgroup.long 0x29C++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_20_SHADOW," group.long 0x2A0++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_21,Write leveling starting ratio" bitfld.long 0x00 30.--31. "PHY_WRLVL_INIT_RATIO_1_1,Write leveling starting ratio[1:0] for Data PHY 1 Rank 1" "0,1,2,3" newline hexmask.long.word 0x00 20.--29. 1. "PHY_WRLVL_INIT_RATIO_1_0,Write leveling starting ratio[9:0] for Data PHY 1 Rank 0" newline hexmask.long.word 0x00 10.--19. 1. "PHY_WRLVL_INIT_RATIO_0_1,Write leveling starting ratio[9:0] for Data PHY 0 Rank 1" newline hexmask.long.word 0x00 0.--9. 1. "PHY_WRLVL_INIT_RATIO_0_0,Write leveling starting ratio[9:0] for Data PHY 0 Rank 0" hgroup.long 0x2A4++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_21_SHADOW," group.long 0x2A8++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_22,Write leveling starting ratio" bitfld.long 0x00 28.--31. "PHY_WRLVL_INIT_RATIO_3_0,Write leveling starting ratio[3:0] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 18.--27. 1. "PHY_WRLVL_INIT_RATIO_2_1,Write leveling starting ratio[9:0] for Data PHY 2 Rank 1" newline hexmask.long.word 0x00 8.--17. 1. "PHY_WRLVL_INIT_RATIO_2_0,Write leveling starting ratio[9:0] for Data PHY 2 Rank 0" newline hexmask.long.byte 0x00 0.--7. 1. "PHY_WRLVL_INIT_RATIO_1_1,Write leveling starting ratio[9:2] for Data PHY 1 Rank 1" hgroup.long 0x2AC++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_22_SHADOW," group.long 0x2B0++0x03 line.long 0x00 "EMIF_EXT_PHY_CONTROL_23,Write leveling starting ratio" hexmask.long.word 0x00 6.--15. 1. "PHY_WRLVL_INIT_RATIO_3_1,Write leveling starting ratio[9:0] for Data PHY 3 Rank 1" newline bitfld.long 0x00 0.--5. "PHY_WRLVL_INIT_RATIO_3_0,Write leveling starting ratio[9:4] for Data PHY 3 Rank 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hgroup.long 0x2B4++0x03 hide.long 0x00 "EMIF_EXT_PHY_CONTROL_23_SHADOW," group.long 0x2B8++0x07 line.long 0x00 "EMIF_EXT_PHY_CONTROL_24," bitfld.long 0x00 10. "PHY_RDC_FIFO_RST_ERR_CNT_CLR,Clear/reset theEMIF_PHY_STATUS_20[15:0] PHY_REG_RDC_FIFO_RST_ERR_CNT_0 EMIF_PHY_STATUS_5[11:0] PHY_REG_RDFIFO_RDPTR_* and EMIF_PHY_STATUS_5[27:16] PHY_REG_RDFIFO_WRPTR_* status fields and flags" "0,1" newline bitfld.long 0x00 9. "PHY_MDLL_UNLOCK_CLEAR,Clears theEMIF_PHY_STATUS_20[19:16] PHY_REG_STATUS_MDLL_UNLOCK_STICKY_* status flags" "0,1" newline bitfld.long 0x00 8. "PHY_FIFO_WE_IN_MISALIGNED_CLR,Clears the forEMIF_PHY_STATUS_20[25:20] PHY_REG_FIFO_WE_IN_MISALIGNED_STICKY_* status flags" "0,1" newline bitfld.long 0x00 4.--7. "PHY_WRLVL_NUM_OF_DQ0,This bit field determines the number of samples for dq0_in for each ratio increment by the write leveling FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "PHY_GATELVL_NUM_OF_DQ0,This bit field determines the number of samples for dq0_in for each ratio increment by the Gate Training FSM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "EMIF_EXT_PHY_CONTROL_24_SHADOW," bitfld.long 0x04 0.--3. "PHY_GATELVL_NUM_OF_DQ0_SHDW,Shadow field for PHY_GATELVL_NUM_OF_DQ0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end tree.open "eMMC_SD_SDIO" repeat 2. (list 1. 2. )(list ad:0x4809C000 ad:0x480B4000 ) tree "MMC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "RETMODE_0_r,RETMODE_1_r" bitfld.long 0x04 2.--5. "MEM_SIZE,Memory size for FIFO buffer: - MEM_1024" "?,MEM_SIZE_1_r,MEM_SIZE_2_r,?,MEM_SIZE_4_r,?,?,?,MEM_SIZE_8_r,?,?,?,?,?,?,?" bitfld.long 0x04 1. "MERGE_MEM,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture" "MERGE_MEM_0_r,MERGE_MEM_1_r" newline bitfld.long 0x04 0. "MADMA_EN,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA" "MADMA_EN_0_r,MADMA_EN_1_r" group.long 0x10++0x03 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x110++0x07 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface" bitfld.long 0x00 12.--13. "STANDBYMODE,Master interface power Management standby/wait control" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,?" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 3.--4. "SIDLEMODE,Power management - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" newline bitfld.long 0x00 2. "ENAWAKEUP,Wakeup feature control - Disabled" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal Clock gating strategy - Off" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring Note: the debounce clock the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x124++0x13 line.long 0x00 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1. R1b for all cards and of R5. R5b and R6 response for cards types SD or SDIO" line.long 0x04 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification" rbitfld.long 0x04 16. "OBI,Out-Of-Band Interrupt (OBI) data value - HighLevel" "OBI_0_r,OBI_1_r" rbitfld.long 0x04 15. "SDCD,Card detect input signal (mmci_sdcd) data value - DrivenHigh" "SDCD_0_r,SDCD_1_r" rbitfld.long 0x04 14. "SDWP,Write protect input signal (mmci_sdwp) data value - DrivenHigh" "SDWP_0_r,SDWP_1_r" newline bitfld.long 0x04 13. "WAKD,Wake request output signal data value - DrivenLow_w" "WAKD_0_r,WAKD_1_r" bitfld.long 0x04 12. "SSB,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)" "SSB_0_r,SSB_1_r" bitfld.long 0x04 11. "D7D,DAT7 input/output signal data value - DriveLow_w" "D7D_0_r,D7D_1_r" newline bitfld.long 0x04 10. "D6D,DAT6 input/output signal data value - DriveLow_w" "D6D_0_r,D6D_1_r" bitfld.long 0x04 9. "D5D,DAT5 input/output signal data value - DriveLow_w" "D5D_0_r,D5D_1_r" bitfld.long 0x04 8. "D4D,DAT4 input/output signal data value - DriveLow_w" "D4D_0_r,D4D_1_r" newline bitfld.long 0x04 7. "D3D,DAT3 input/output signal data value - DriveLow_w" "D3D_0_r,D3D_1_r" bitfld.long 0x04 6. "D2D,DAT2 input/output signal data value - DriveLow_w" "D2D_0_r,D2D_1_r" bitfld.long 0x04 5. "D1D,DAT1 input/output signal data value - DriveLow_w" "D1D_0_r,D1D_1_r" newline bitfld.long 0x04 4. "D0D,DAT0 input/output signal data value - Zero_w" "D0D_0_r,D0D_1_r" bitfld.long 0x04 3. "DDIR,Control of the DAT[7:0] pins direction" "DDIR_0_r,DDIR_1_r" bitfld.long 0x04 2. "CDAT,CMD input/output signal data value - DriveLow_w" "CDAT_0_r,CDAT_1_r" newline bitfld.long 0x04 1. "CDIR,Control of the CMD pin direction" "CDIR_0_r,CDIR_1_r" bitfld.long 0x04 0. "MCKD,MMC clock output signal data value - DrivenLow_w" "MCKD_0_r,MCKD_1_r" line.long 0x08 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card" bitfld.long 0x08 21. "SDMA_LNE,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion request remains active until last allowed data written.." "SDMA_LNE_0,SDMA_LNE_1" bitfld.long 0x08 20. "DMA_MNS,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available.." "DMA_MNS_0,DMA_MNS_1" bitfld.long 0x08 19. "DDR,Dual Data Rate mode: When this register is set the controller uses both clock edge to emit or receive data" "DDR_0,DDR_1" newline bitfld.long 0x08 18. "BOOT_CF0,Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence" "BOOT_CF0_0_r,BOOT_CF0_1_r" bitfld.long 0x08 17. "BOOT_ACK,Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued" "BOOT_ACK_0,BOOT_ACK_1" bitfld.long 0x08 16. "CLKEXTFREE,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]" "CLKEXTFREE_0,CLKEXTFREE_1" newline bitfld.long 0x08 15. "PADEN,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power" "PADEN_0,PADEN_1" bitfld.long 0x08 14. "OBIE,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin" "OBIE_0,OBIE_1" bitfld.long 0x08 13. "OBIP,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards" "OBIP_0,OBIP_1" newline bitfld.long 0x08 12. "CEATA,CE-ATA control mode MMC cards compliant with CE-ATA:By default this bit is set to 0" "CEATA_0,CEATA_1" bitfld.long 0x08 11. "CTPL,Control Power for DAT[1] line MMC and SD cards: By default this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current" "CTPL_0,CTPL_1" bitfld.long 0x08 9.--10. "DVAL,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (mmci_sdcd)" "DVAL_0,DVAL_1,DVAL_2,DVAL_3" newline bitfld.long 0x08 8. "WPP,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (mmci_sdwp)" "WPP_0,WPP_1" bitfld.long 0x08 7. "CDP,Card detect polarity All cards This bit selects the active level of the card detect input signal (mmci_sdcd)" "CDP_0,CDP_1" bitfld.long 0x08 6. "MIT,MMC interrupt command Only for MMC cards" "MIT_0,MIT_1" newline bitfld.long 0x08 5. "DW8,8-bit mode MMC select For SD/SDIO cards this bit must be set to 0" "DW8_0,DW8_1" bitfld.long 0x08 4. "MODE,Mode select All cards This bit select between Functional mode and SYSTEST mode" "MODE_0,MODE_1" bitfld.long 0x08 3. "STR,Stream command Only for MMC cards" "STR_0,STR_1" newline bitfld.long 0x08 2. "HR,Broadcast host response Only for MMC cards" "HR_0,HR_1" bitfld.long 0x08 1. "INIT,Send initialization stream All cards" "INIT_0,INIT_1" bitfld.long 0x08 0. "OD,Card open drain mode" "OD_0,OD_1" line.long 0x0C "MMCHS_PWCNT,Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power. this value depends on PAD characteristics and voltage" hexmask.long.word 0x0C 0.--15. 1. "PWRCNT,Power counter register" line.long 0x10 "MMCHS_DLL,DLL control and status register This register is used for tuning procedure required for SDR104 speed mode" bitfld.long 0x10 31. "DLL_SOFT_RESET,Soft reset for DLL active HIGH" "DLL_SOFT_RESET_0_r,DLL_SOFT_RESET_1_r" bitfld.long 0x10 30. "LOCK_TIMER,Timer for the dll_lock signal to be asserted after reset" "LOCK_TIMER_0,LOCK_TIMER_1" hexmask.long.byte 0x10 22.--29. 1. "MAX_LOCK_DIFF,Maximum number of taps that the master DLL clock period measurement can deviate without resulting in the master DLL losing lock" newline bitfld.long 0x10 20.--21. "FORCE_SR_F,Forced fine delay value" "0,1,2,3" hexmask.long.byte 0x10 13.--19. 1. "FORCE_SR_C,Forced coarse delay value" bitfld.long 0x10 12. "FORCE_VALUE,Put forced values to slave DLL ignoring master DLL output and ratio value" "FORCE_VALUE_0,FORCE_VALUE_1" newline bitfld.long 0x10 6.--11. "SLAVE_RATIO,Fraction of a clock cycle for the shift to be implemented in units of 256ths of a clock cycle" "SLAVE_RATIO_0,?,SLAVE_RATIO_2,?,SLAVE_RATIO_4,?,SLAVE_RATIO_6,?,SLAVE_RATIO_8,?,SLAVE_RATIO_10,?,SLAVE_RATIO_12,?,SLAVE_RATIO_14,?,SLAVE_RATIO_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,SLAVE_RATIO_63" bitfld.long 0x10 3. "DLL_UNLOCK_CLEAR,Clears the phy_reg_status_mdll_unlock_sticky flags of the DLL" "DLL_UNLOCK_CLEAR_0,DLL_UNLOCK_CLEAR_1" rbitfld.long 0x10 2. "DLL_UNLOCK_STICKY,Asserted when any single period measurement exceeds MAX_LOCK_DIFF" "0,1" newline bitfld.long 0x10 1. "DLL_CALIB,Enables Slave DLL to update new delay values" "DLL_CALIB_0,DLL_CALIB_1" rbitfld.long 0x10 0. "DLL_LOCK,Master DLL lock status" "DLL_LOCK_0_r,DLL_LOCK_1_r" group.long 0x200++0x4B line.long 0x00 "MMCHS_SDMASA,SDMA System Address / Argument 2 Register" line.long 0x04 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register" hexmask.long.word 0x04 16.--31. 1. "NBLK,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers" hexmask.long.word 0x04 0.--11. 1. "BLEN,Transfer Block Size" line.long 0x08 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register)" line.long 0x0C "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode" bitfld.long 0x0C 24.--29. "INDX,Command index - Binary encoded value from 0 to 63 specifying the command number send to card" "INDX_0,INDX_1,INDX_2,INDX_3,INDX_4,INDX_5,INDX_6,INDX_7,INDX_8,INDX_9,INDX_10,INDX_11,INDX_12,INDX_13,INDX_14,INDX_15,INDX_16,INDX_17,INDX_18,INDX_19,INDX_20,INDX_21,INDX_22,INDX_23,INDX_24,INDX_25,INDX_26,INDX_27,INDX_28,INDX_29,INDX_30,INDX_31,INDX_32,INDX_33,INDX_34,INDX_35,INDX_36,INDX_37,INDX_38,INDX_39,INDX_40,INDX_41,INDX_42,INDX_43,INDX_44,INDX_45,INDX_46,INDX_47,INDX_48,INDX_49,INDX_50,INDX_51,INDX_52,INDX_53,INDX_54,INDX_55,INDX_56,INDX_57,INDX_58,INDX_59,INDX_60,INDX_61,INDX_62,INDX_63" bitfld.long 0x0C 22.--23. "CMD_TYPE,Command typeThis register specifies three types of special command: Suspend Resume and Abort" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3" bitfld.long 0x0C 21. "DP,Data present select - This register indicates that data is present and DAT line shall be used" "DP_0,DP_1" newline bitfld.long 0x0C 20. "CICE,Command Index check enable - This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command" "CICE_0,CICE_1" bitfld.long 0x0C 19. "CCCE,Command CRC check enable - This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus" "CCCE_0,CCCE_1" bitfld.long 0x0C 16.--17. "RSP_TYPE,Response type - This bits defines the response type of the command" "RSP_TYPE_0,RSP_TYPE_1,RSP_TYPE_2,RSP_TYPE_3" newline bitfld.long 0x0C 5. "MSBS,Multi/Single block select - This bit must be set to 1 for data transfer in case of multi block command" "MSBS_0,MSBS_1" bitfld.long 0x0C 4. "DDIR,Data transfer Direction Select - This bit defines either data transfer will be a read or a" "DDIR_0,DDIR_1" bitfld.long 0x0C 2.--3. "ACEN,Auto CMD Enable - SD card only" "ACEN_0,ACEN_1,ACEN_2,ACEN_3" newline bitfld.long 0x0C 1. "BCE,Block Count Enable - Multiple block transfers only" "BCE_0,BCE_1" bitfld.long 0x0C 0. "DE,DMA Enable - This bit is used to enable DMA mode for host data access" "DE_0,DE_1" line.long 0x10 "MMCHS_RSP10,Command Response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6/R7" hexmask.long.word 0x10 16.--31. 1. "RSP1,Command Response [31:16]" hexmask.long.word 0x10 0.--15. 1. "RSP0,Command Response [15:0]" line.long 0x14 "MMCHS_RSP32,Command Response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x14 16.--31. 1. "RSP3,Command Response [63:48]" hexmask.long.word 0x14 0.--15. 1. "RSP2,Command Response [47:32]" line.long 0x18 "MMCHS_RSP54,Command Response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x18 16.--31. 1. "RSP5,Command Response [95:80]" hexmask.long.word 0x18 0.--15. 1. "RSP4,Command Response [79:64]" line.long 0x1C "MMCHS_RSP76,Command Response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2" hexmask.long.word 0x1C 16.--31. 1. "RSP7,Command Response [127:112]" hexmask.long.word 0x1C 0.--15. 1. "RSP6,Command Response [111:96]" line.long 0x20 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers" line.long 0x24 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register" bitfld.long 0x24 24. "CLEV,CMD line signal level This status is used to check the CMD line level to recover from errors and for debugging" "CLEV_0_r,CLEV_1_r" bitfld.long 0x24 20.--23. "DLEV,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors and for debugging" "DLEV_0,DLEV_1,DLEV_2,DLEV_3,DLEV_4,DLEV_5,DLEV_6,DLEV_7,DLEV_8,DLEV_9,DLEV_10,DLEV_11,DLEV_12,DLEV_13,DLEV_14,DLEV_15" bitfld.long 0x24 19. "WP,Write protect switch pin level For SDIO cards only" "WP_0_r,WP_1_r" newline bitfld.long 0x24 18. "CDPL,Card detect pin level This bit reflects the inverse value of the card detect input pin (mmci_sdcd) debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTAE[CSS]) is set to 1" "CDPL_0_r,CDPL_1_r" bitfld.long 0x24 17. "CSS,Card State Stable This bit is used for testing" "CSS_0_r,CSS_1_r" bitfld.long 0x24 16. "CINS,Card inserted This bit is the debounced value of the card detect input pin (mmci_sdcd)" "CINS_0_r,CINS_1_r" newline bitfld.long 0x24 11. "BRE,Buffer read enable This bit is used for non-DMA read transfers" "BRE_0_r,BRE_1_r" bitfld.long 0x24 10. "BWE,Buffer Write enable This status is used for non-DMA write transfers" "BWE_0_r,BWE_1_r" bitfld.long 0x24 9. "RTA,Read transfer active This status is used for detecting completion of a read transfer" "RTA_0_r,RTA_1_r" newline bitfld.long 0x24 8. "WTA,Write transfer active This status indicates a write transfer active" "WTA_0_r,WTA_1_r" bitfld.long 0x24 3. "RTR,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data" "RTR_0_r,RTR_1_r" bitfld.long 0x24 2. "DLA,DAT line active This status bit indicates whether one of the DAT line is in use" "DLA_0_r,DLA_1_r" newline bitfld.long 0x24 1. "DATI,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued" "DATI_0_r,DATI_1_r" bitfld.long 0x24 0. "CMDI,Command inhibit(CMD) This status bit indicates that the CMD line is in use" "CMDI_0_r,CMDI_1_r" line.long 0x28 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power. wakeup and transfer parameters" bitfld.long 0x28 27. "OBWE,Wakeup event enable for 'Out-of-Band' Interrupt" "OBWE_0,OBWE_1" bitfld.long 0x28 26. "REM,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion" "REM_0,REM_1" bitfld.long 0x28 25. "INS,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion" "INS_0,INS_1" newline bitfld.long 0x28 24. "IWE,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion" "IWE_0,IWE_1" bitfld.long 0x28 19. "IBG,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer" "IBG_0,IBG_1" bitfld.long 0x28 18. "RWC,Read wait control The read wait function is optional only for SDIO cards" "RWC_0,RWC_1" newline bitfld.long 0x28 17. "CR,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR])" "CR_0,CR_1" bitfld.long 0x28 16. "SBGR,Stop at block gap request This bit is used to stop executing a transaction at the next block gap" "SBGR_0,SBGR_1" bitfld.long 0x28 9.--11. "SDVS,SD bus voltage select All cards" "?,?,?,?,?,SDVS_5,SDVS_6,SDVS_7" newline bitfld.long 0x28 8. "SDBP,SD bus power Before setting this bit the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS])" "SDBP_0,SDBP_1" bitfld.long 0x28 7. "CDSS,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in.." "CDSS_0,CDSS_1" bitfld.long 0x28 6. "CDTL,Card Detect Test Level: This bit is enabled while MMCHS_HCTL[7] CDSS is set to 1 and it indicates whether the card is inserted or not" "CDTL_0,CDTL_1" newline bitfld.long 0x28 3.--4. "DMAS,DMA Select Mode: One of supported DMA modes can be selected" "DMAS_0,DMAS_1,DMAS_2,DMAS_3" bitfld.long 0x28 2. "HSPE,High Speed Enable: Before setting this bit the Host Driver shall check the MMCHS_CAPA[21] HSS" "HSPE_0,HSPE_1" bitfld.long 0x28 1. "DTW,Data transfer width For MMC card this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument" "DTW_0,DTW_1" newline rbitfld.long 0x28 0. "LED,Reserved bit" "LED_0,LED_1" line.long 0x2C "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets. clock frequency management and data timeout" bitfld.long 0x2C 26. "SRD,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed" "SRD_0,SRD_1" bitfld.long 0x2C 25. "SRC,Software reset for CMD line For more information about SRC bit manipulation see" "SRC_0,SRC_1" bitfld.long 0x2C 24. "SRA,Software reset for all This bit is set to 1 for reset and released to 0 when completed" "SRA_0,SRA_1" newline bitfld.long 0x2C 16.--19. "DTO,Data timeout counter value and busy timeout" "DTO_0,DTO_1,?,?,?,?,?,?,?,?,?,?,?,?,DTO_14,DTO_15" hexmask.long.word 0x2C 6.--15. 1. "CLKD,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC SD or SDIO)" rbitfld.long 0x2C 5. "CGS,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit" "0,1" newline bitfld.long 0x2C 2. "CEN,Clock enable This bit controls if the clock is provided to the card or not" "CEN_0,CEN_1" rbitfld.long 0x2C 1. "ICS,Internal clock stable (status) This bit indicates either the internal clock is stable or not" "ICS_0_r,ICS_1_r" bitfld.long 0x2C 0. "ICE,Internal clock enable This register controls the internal clock activity" "ICE_0,ICE_1" line.long 0x30 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x30 29. "BADA,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit.." "BADA_0_r,BADA_1_r" bitfld.long 0x30 28. "CERR,Card error This bit is set automatically when there is at least one error in a response of type R1 R1b R6 R5 or R5b" "CERR_0_r,CERR_1_r" bitfld.long 0x30 26. "TE,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select)" "TE_0,TE_1" newline bitfld.long 0x30 25. "ADMAE,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer" "ADMAE_0_r,ADMAE_1_r" bitfld.long 0x30 24. "ACE,Auto CMD error Auto CMD12 and Auto CMD23 use this error status" "ACE_0_r,ACE_1_r" bitfld.long 0x30 22. "DEB,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode" "DEB_0_r,DEB_1_r" newline bitfld.long 0x30 21. "DCRC,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command" "DCRC_0_r,DCRC_1_r" bitfld.long 0x30 20. "DTO,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout - St_un_w" "DTO_0_r,DTO_1_r" bitfld.long 0x30 19. "CIE,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted" "CIE_0_r,CIE_1_r" newline bitfld.long 0x30 18. "CEB,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response" "CEB_0_r,CEB_1_r" bitfld.long 0x30 17. "CCRC,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register" "CCRC_0_r,CCRC_1_r" bitfld.long 0x30 16. "CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "CTO_0_r,CTO_1_r" newline rbitfld.long 0x30 15. "ERRI,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[24:15]) are set then this bit is set to 1" "ERRI_0_r,ERRI_1_r" bitfld.long 0x30 10. "BSR,Boot status received interrupt This bit is set automatically when MMCHS_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line" "BSR_0_r,BSR_1_r" bitfld.long 0x30 9. "OBI,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin" "OBI_0_r,OBI_1_r" newline rbitfld.long 0x30 8. "CIRQ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards" "CIRQ_0_r,CIRQ_1_r" bitfld.long 0x30 7. "CREM,Card removal This bit is set automatically when MMCHS_PSTATE[CINS] changes from 1 to 0" "CREM_0_r,CREM_1_r" bitfld.long 0x30 6. "CINS,Card insertion This bit is set automatically when MMCHS_PSTATE[CINS] changes from 0 to 1" "CINS_0_r,CINS_1_r" newline bitfld.long 0x30 5. "BRR,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer" "BRR_0_r,BRR_1_r" bitfld.long 0x30 4. "BWR,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]" "BWR_0_r,BWR_1_r" bitfld.long 0x30 3. "DMA,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion" "DMA_0_r,DMA_1_r" newline bitfld.long 0x30 2. "BGE,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]) this bit is automatically set when transaction is stopped at the block gap during a read or write operation" "BGE_0_r,BGE_1_r" bitfld.long 0x30 1. "TC,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR])" "TC_0_r,TC_1_r" bitfld.long 0x30 0. "CC,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected then the command complete interrupt is generated at the end of the command" "CC_0_r,CC_1_r" line.long 0x34 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits. on an event-by-event basis" bitfld.long 0x34 29. "BADA_ENABLE,Bad access to data space Status Enable - Masked" "BADA_ENABLE_0,BADA_ENABLE_1" bitfld.long 0x34 28. "CERR_ENABLE,Card Error Status Enable - Masked" "CERR_ENABLE_0,CERR_ENABLE_1" bitfld.long 0x34 26. "TE_ENABLE,Tuning Error Status Enable - Masked" "TE_ENABLE_0,TE_ENABLE_1" newline bitfld.long 0x34 25. "ADMAE_ENABLE,ADMA Error Status Enable - Masked" "ADMAE_ENABLE_0,ADMAE_ENABLE_1" bitfld.long 0x34 24. "ACE_ENABLE,Auto CMD Error Status Enable - Masked" "ACE_ENABLE_0,ACE_ENABLE_1" bitfld.long 0x34 22. "DEB_ENABLE,Data End Bit Error Status Enable - Masked" "DEB_ENABLE_0,DEB_ENABLE_1" newline bitfld.long 0x34 21. "DCRC_ENABLE,Data CRC Error Status Enable - Masked" "DCRC_ENABLE_0,DCRC_ENABLE_1" bitfld.long 0x34 20. "DTO_ENABLE,Data Timeout Error Status Enable - Masked" "DTO_ENABLE_0,DTO_ENABLE_1" bitfld.long 0x34 19. "CIE_ENABLE,Command Index Error Status Enable - Masked" "CIE_ENABLE_0,CIE_ENABLE_1" newline bitfld.long 0x34 18. "CEB_ENABLE,Command End Bit Error Status Enable - Masked" "CEB_ENABLE_0,CEB_ENABLE_1" bitfld.long 0x34 17. "CCRC_ENABLE,Command CRC Error Status Enable - Masked" "CCRC_ENABLE_0,CCRC_ENABLE_1" bitfld.long 0x34 16. "CTO_ENABLE,Command Timeout Error Status Enable - Masked" "CTO_ENABLE_0,CTO_ENABLE_1" newline rbitfld.long 0x34 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "NULL_0,NULL_1" bitfld.long 0x34 10. "BSR_ENABLE,Boot Status Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored" "BSR_ENABLE_0,BSR_ENABLE_1" bitfld.long 0x34 9. "OBI_ENABLE,Out-of-Band Status Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored" "OBI_ENABLE_0,OBI_ENABLE_1" newline bitfld.long 0x34 8. "CIRQ_ENABLE,Card Status Enable A clear of this bit also clears the corresponding status bit" "CIRQ_ENABLE_0,CIRQ_ENABLE_1" bitfld.long 0x34 7. "CREM_ENABLE,Card Removal Status Enable - Masked" "CREM_ENABLE_0,CREM_ENABLE_1" bitfld.long 0x34 6. "CINS_ENABLE,Card Insertion Status Enable - Masked" "CINS_ENABLE_0,CINS_ENABLE_1" newline bitfld.long 0x34 5. "BRR_ENABLE,Buffer Read Ready Status Enable - Masked" "BRR_ENABLE_0,BRR_ENABLE_1" bitfld.long 0x34 4. "BWR_ENABLE,Buffer Write Ready Status Enable - Masked" "BWR_ENABLE_0,BWR_ENABLE_1" bitfld.long 0x34 3. "DMA_ENABLE,DMA Status Enable - Masked" "DMA_ENABLE_0,DMA_ENABLE_1" newline bitfld.long 0x34 2. "BGE_ENABLE,Block Gap Event Status Enable - Masked" "BGE_ENABLE_0,BGE_ENABLE_1" bitfld.long 0x34 1. "TC_ENABLE,Transfer Complete Status Enable - Masked" "TC_ENABLE_0,TC_ENABLE_1" bitfld.long 0x34 0. "CC_ENABLE,Command Complete Status Enable - Masked" "CC_ENABLE_0,CC_ENABLE_1" line.long 0x38 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status. on an event-by-event basis" bitfld.long 0x38 29. "BADA_SIGEN,Bad access to data space Signal Enable - Masked" "BADA_SIGEN_0,BADA_SIGEN_1" bitfld.long 0x38 28. "CERR_SIGEN,Card Error Interrupt Signal Enable - Masked" "CERR_SIGEN_0,CERR_SIGEN_1" bitfld.long 0x38 26. "TE_SIGEN,Tuning Error Signal Enable - Masked" "TE_SIGEN_0,TE_SIGEN_1" newline bitfld.long 0x38 25. "ADMAE_SIGEN,ADMA Error Signal Enable - Masked" "ADMAE_SIGEN_0,ADMAE_SIGEN_1" bitfld.long 0x38 24. "ACE_SIGEN,Auto CMD Error Signal Enable - Masked" "ACE_SIGEN_0,ACE_SIGEN_1" bitfld.long 0x38 22. "DEB_SIGEN,Data End Bit Error Signal Enable - Masked" "DEB_SIGEN_0,DEB_SIGEN_1" newline bitfld.long 0x38 21. "DCRC_SIGEN,Data CRC Error Signal Enable - Masked" "DCRC_SIGEN_0,DCRC_SIGEN_1" bitfld.long 0x38 20. "DTO_SIGEN,Data Timeout Error Signal Enable - Masked" "DTO_SIGEN_0,DTO_SIGEN_1" bitfld.long 0x38 19. "CIE_SIGEN,Command Index Error Signal Enable - Masked" "CIE_SIGEN_0,CIE_SIGEN_1" newline bitfld.long 0x38 18. "CEB_SIGEN,Command End Bit Error Signal Enable - Masked" "CEB_SIGEN_0,CEB_SIGEN_1" bitfld.long 0x38 17. "CCRC_SIGEN,Command CRC Error Signal Enable - Masked" "CCRC_SIGEN_0,CCRC_SIGEN_1" bitfld.long 0x38 16. "CTO_SIGEN,Command timeout Error Signal Enable - Masked" "CTO_SIGEN_0,CTO_SIGEN_1" newline rbitfld.long 0x38 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "NULL_0,NULL_1" bitfld.long 0x38 10. "BSR_SIGEN,Boot Status Signal Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored" "BSR_SIGEN_0,BSR_SIGEN_1" bitfld.long 0x38 9. "OBI_SIGEN,Out-Of-Band Interrupt Signal Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored" "OBI_SIGEN_0,OBI_SIGEN_1" newline bitfld.long 0x38 8. "CIRQ_SIGEN,Card Interrupt Signal Enable - Masked" "CIRQ_SIGEN_0,CIRQ_SIGEN_1" bitfld.long 0x38 7. "CREM_SIGEN,Card Removal Signal Enable - Masked" "CREM_SIGEN_0,CREM_SIGEN_1" bitfld.long 0x38 6. "CINS_SIGEN,Card Insertion Signal Enable - Masked" "CINS_SIGEN_0,CINS_SIGEN_1" newline bitfld.long 0x38 5. "BRR_SIGEN,Buffer Read Ready Signal Enable - Masked" "BRR_SIGEN_0,BRR_SIGEN_1" bitfld.long 0x38 4. "BWR_SIGEN,Buffer Write Ready Signal Enable - Masked" "BWR_SIGEN_0,BWR_SIGEN_1" bitfld.long 0x38 3. "DMA_SIGEN,DMA Interrupt Signal Enable - Masked" "DMA_SIGEN_0,DMA_SIGEN_1" newline bitfld.long 0x38 2. "BGE_SIGEN,Black Gap Event Signal Enable - Masked" "BGE_SIGEN_0,BGE_SIGEN_1" bitfld.long 0x38 1. "TC_SIGEN,Transfer Completed Status Enable - Masked" "TC_SIGEN_0,TC_SIGEN_1" bitfld.long 0x38 0. "CC_SIGEN,Command Complete Status Enable - Masked" "CC_SIGEN_0,CC_SIGEN_1" line.long 0x3C "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23" bitfld.long 0x3C 31. "PV_ENABLE,Preset Value Enable Host Controller Version 3.00 supports this bit" "PV_ENABLE_0,PV_ENABLE_1" bitfld.long 0x3C 30. "AI_ENABLE,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1" "AI_ENABLE_0,AI_ENABLE_1" bitfld.long 0x3C 23. "SCLK_SEL,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT" "SCLK_SEL_0,SCLK_SEL_1" newline bitfld.long 0x3C 22. "ET,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed" "ET_0,ET_1" bitfld.long 0x3C 20.--21. "DS_SEL,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit" "DS_SEL_0,DS_SEL_1,DS_SEL_2,DS_SEL_3" bitfld.long 0x3C 19. "V1V8_SIGEN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell" "V1V8_SIGEN_0,V1V8_SIGEN_1" newline bitfld.long 0x3C 16.--18. "UHSMS,UHS Mode Select This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1" "UHSMS_0,UHSMS_1,UHSMS_2,UHSMS_3,UHSMS_4,UHSMS_5,UHSMS_6,UHSMS_7" rbitfld.long 0x3C 7. "CNI,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register" "CNI_0_r,CNI_1_r" rbitfld.long 0x3C 4. "ACIE,Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command" "ACIE_0_r,ACIE_1_r" newline rbitfld.long 0x3C 3. "ACEB,Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0" "ACEB_0_r,ACEB_1_r" rbitfld.long 0x3C 2. "ACCE,Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response" "ACCE_0_r,ACCE_1_r" rbitfld.long 0x3C 1. "ACTO,Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command" "ACTO_0_r,ACTO_1_r" newline rbitfld.long 0x3C 0. "ACNE,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "ACNE_0_r,ACNE_1_r" line.long 0x40 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller" rbitfld.long 0x40 29. "AIS,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "AIS_0_r,AIS_1_r" rbitfld.long 0x40 28. "BIT64,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus" "BIT64_0_r,BIT64_1_r" bitfld.long 0x40 26. "VS18,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS18_0_r,VS18_1_r" newline bitfld.long 0x40 25. "VS30,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS30_0_r,VS30_1_r" bitfld.long 0x40 24. "VS33,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS33_0_r,VS33_1_r" rbitfld.long 0x40 23. "SRS,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality" "SRS_0_r,SRS_1_r" newline rbitfld.long 0x40 22. "DS,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly" "DS_0_r,DS_1_r" rbitfld.long 0x40 21. "HSS,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency" "HSS_0_r,HSS_1_r" rbitfld.long 0x40 19. "AD2S,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2" "AD2S_0_r,AD2S_1_r" newline rbitfld.long 0x40 16.--17. "MBL,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller" "MBL_0_r,MBL_1_r,MBL_2_r,?" hexmask.long.byte 0x40 8.--15. 1. "BCF,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock" rbitfld.long 0x40 7. "TCU,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCU_0_r,TCU_1_r" newline rbitfld.long 0x40 0.--5. "TCF,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCF_0_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation" hexmask.long.byte 0x44 16.--23. 1. "CM,Clock Multiplier This field indicates clock multiplier value of programmable clock generator" bitfld.long 0x44 14.--15. "RTM,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length" "RTM_0_r,RTM_1_r,RTM_2_r,RTM_3_r" bitfld.long 0x44 13. "TSDR50,Use Tuning for SDR50 If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "TSDR50_0_r,TSDR50_1_r" newline bitfld.long 0x44 8.--11. "TCRT,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "TCRT_0_r,TCRT_1_r,TCRT_2_r,TCRT_3_r,TCRT_4_r,TCRT_5_r,TCRT_6_r,TCRT_7_r,TCRT_8_r,TCRT_9_r,TCRT_10_r,TCRT_11_r,TCRT_12_r,TCRT_13_r,TCRT_14_r,TCRT_15_r" bitfld.long 0x44 6. "DTD,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling" "DTD_0_r,DTD_1_r" bitfld.long 0x44 5. "DTC,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling" "DTC_0_r,DTC_1_r" newline bitfld.long 0x44 4. "DTA,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling" "DTA_0_r,DTA_1_r" bitfld.long 0x44 2. "DDR50,DDR50 Support - Supported" "DDR50_0_r,DDR50_1_r" bitfld.long 0x44 1. "SDR104,SDR104 Support SDR104 requires tuning" "SDR104_0_r,SDR104_1_r" newline bitfld.long 0x44 0. "SDR50,SDR50 Support If SDR104 is supported this bit shall be set to 1" "SDR50_0_r,SDR50_1_r" line.long 0x48 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage" hexmask.long.byte 0x48 16.--23. 1. "CUR_1V8,Maximum current for" hexmask.long.byte 0x48 8.--15. 1. "CUR_3V0,Maximum current for" hexmask.long.byte 0x48 0.--7. 1. "CUR_3V3,Maximum current for" group.long 0x250++0x0B line.long 0x00 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register" bitfld.long 0x00 29. "FE_BADA,Force Event Bad access to data space" "FE_BADA_0_w,FE_BADA_1_w" bitfld.long 0x00 28. "FE_CERR,Force Event Card error" "FE_CERR_0_w,FE_CERR_1_w" bitfld.long 0x00 25. "FE_ADMAE,Force Event ADMA Error" "FE_ADMAE_0_w,FE_ADMAE_1_w" newline bitfld.long 0x00 24. "FE_ACE,Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23 - NoAction" "FE_ACE_0_w,FE_ACE_1_w" bitfld.long 0x00 22. "FE_DEB,Force Event Data End Bit error" "FE_DEB_0_w,FE_DEB_1_w" bitfld.long 0x00 21. "FE_DCRC,Force Event Data CRC Error" "FE_DCRC_0_w,FE_DCRC_1_w" newline bitfld.long 0x00 20. "FE_DTO,Force Event Data Timeout Error" "FE_DTO_0_w,FE_DTO_1_w" bitfld.long 0x00 19. "FE_CIE,Force Event Command Index Error" "FE_CIE_0_w,FE_CIE_1_w" bitfld.long 0x00 18. "FE_CEB,Force Event Command End Bit Error" "FE_CEB_0_w,FE_CEB_1_w" newline bitfld.long 0x00 17. "FE_CCRC,Force Event Command CRC Error" "FE_CCRC_0_w,FE_CCRC_1_w" bitfld.long 0x00 16. "FE_CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "FE_CTO_0_w,FE_CTO_1_w" bitfld.long 0x00 7. "FE_CNI,Force Event Command not issue by Auto CMD12 error - NoAction" "FE_CNI_0_w,FE_CNI_1_w" newline bitfld.long 0x00 4. "FE_ACIE,Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23 - NoAction" "FE_ACIE_0_w,FE_ACIE_1_w" bitfld.long 0x00 3. "FE_ACEB,Force Event Auto CMD End Bit Error - NoAction" "FE_ACEB_0_w,FE_ACEB_1_w" bitfld.long 0x00 2. "FE_ACCE,Force Event Auto CMD CRC Error - NoAction" "FE_ACCE_0_w,FE_ACCE_1_w" newline bitfld.long 0x00 1. "FE_ACTO,Force Event Auto CMD Timeout Error - NoAction" "FE_ACTO_0_w,FE_ACTO_1_w" bitfld.long 0x00 0. "FE_ACNE,Force Event Auto CMD12 Not Executed - NoAction" "FE_ACNE_0_w,FE_ACNE_1_w" line.long 0x04 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred. the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor" bitfld.long 0x04 2. "LME,ADMA Length Mismatch Error: (1) While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length" "LME_0,LME_1" bitfld.long 0x04 0.--1. "AES,ADMA Error State his field indicates the state of ADMA when error is occurred during ADMA data transfer" "AES_0,AES_1,AES_2,AES_3" line.long 0x08 "MMCHS_ADMASAL,ADMA System address Low bits" rgroup.long 0x260++0x0F line.long 0x00 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" bitfld.long 0x00 30.--31. "DSDS_SEL,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "DSDS_SEL_0_r,DSDS_SEL_1_r,DSDS_SEL_2_r,DSDS_SEL_3_r" bitfld.long 0x00 26. "DSCLKGEN_SEL,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator" "DSCLKGEN_SEL_0_r,DSCLKGEN_SEL_1_r" hexmask.long.word 0x00 16.--25. 1. "DSSDCLK_SEL,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" newline bitfld.long 0x00 14.--15. "INITDS_SEL,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes" "INITDS_SEL_0_r,INITDS_SEL_1_r,INITDS_SEL_2_r,INITDS_SEL_3_r" bitfld.long 0x00 10. "INITCLKGEN_SEL,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator" "INITCLKGEN_SEL_0_r,INITCLKGEN_SEL_1_r" hexmask.long.word 0x00 0.--9. 1. "INITSDCLK_SEL,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x04 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" bitfld.long 0x04 30.--31. "SDR12DS_SEL,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR12DS_SEL_0_r,SDR12DS_SEL_1_r,SDR12DS_SEL_2_r,SDR12DS_SEL_3_r" bitfld.long 0x04 26. "SDR12CLKGEN_SEL,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator" "SDR12CLKGEN_SEL_0_r,SDR12CLKGEN_SEL_1_r" hexmask.long.word 0x04 16.--25. 1. "SDR12SDCLK_SEL,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" newline bitfld.long 0x04 14.--15. "HSDS_SEL,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "HSDS_SEL_0_r,HSDS_SEL_1_r,HSDS_SEL_2_r,HSDS_SEL_3_r" bitfld.long 0x04 10. "HSCLKGEN_SEL,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator" "HSCLKGEN_SEL_0_r,HSCLKGEN_SEL_1_r" hexmask.long.word 0x04 0.--9. 1. "HSSDCLK_SEL,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x08 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 and SDR50 speed modes" bitfld.long 0x08 30.--31. "SDR50DS_SEL,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR50DS_SEL_0_r,SDR50DS_SEL_1_r,SDR50DS_SEL_2_r,SDR50DS_SEL_3_r" bitfld.long 0x08 26. "SDR50CLKGEN_SEL,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator" "SDR50CLKGEN_SEL_0_r,SDR50CLKGEN_SEL_1_r" hexmask.long.word 0x08 16.--25. 1. "SDR50SDCLK_SEL,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" newline bitfld.long 0x08 14.--15. "SDR25DS_SEL,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR25DS_SEL_0_r,SDR25DS_SEL_1_r,SDR25DS_SEL_2_r,SDR25DS_SEL_3_r" bitfld.long 0x08 10. "SDR25CLKGEN_SEL,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator" "SDR25CLKGEN_SEL_0_r,SDR25CLKGEN_SEL_1_r" hexmask.long.word 0x08 0.--9. 1. "SDR25SDCLK_SEL,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x0C "MMCHS_PVSDR104DDR50,Preset Value for SDR104 and DDR50 speed modes" bitfld.long 0x0C 30.--31. "DDR50DS_SEL,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes" "DDR50DS_SEL_0_r,DDR50DS_SEL_1_r,DDR50DS_SEL_2_r,DDR50DS_SEL_3_r" bitfld.long 0x0C 26. "DDR50CLKGEN_SEL,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator" "DDR50CLKGEN_SEL_0_r,DDR50CLKGEN_SEL_1_r" hexmask.long.word 0x0C 16.--25. 1. "DDR50SDCLK_SEL,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" newline bitfld.long 0x0C 14.--15. "SDR104DS_SEL,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR104DS_SEL_0_r,SDR104DS_SEL_1_r,SDR104DS_SEL_2_r,SDR104DS_SEL_3_r" bitfld.long 0x0C 10. "SDR104CLKGEN_SEL,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator" "SDR104CLKGEN_SEL_0_r,SDR104CLKGEN_SEL_1_r" hexmask.long.word 0x0C 0.--9. 1. "SDR104SDCLK_SEL,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" rgroup.long 0x2FC++0x03 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number. the version number of SD specification compliancy and a slot status bit" hexmask.long.byte 0x00 24.--31. 1. "VREV,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. "SREV,Specification Version Number This status indicates the Host Controller Spec" bitfld.long 0x00 0. "SIS,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module" "SIS_0,SIS_1" tree.end repeat.end repeat 2. (list 3. 4. )(list ad:0x480AD000 ad:0x480D1000 ) tree "MMC$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "RETMODE_0_r,RETMODE_1_r" bitfld.long 0x04 2.--5. "MEM_SIZE,Memory size for FIFO buffer: - MEM_1024" "?,MEM_SIZE_1_r,MEM_SIZE_2_r,?,MEM_SIZE_4_r,?,?,?,MEM_SIZE_8_r,?,?,?,?,?,?,?" bitfld.long 0x04 1. "MERGE_MEM,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture" "MERGE_MEM_0_r,MERGE_MEM_1_r" newline bitfld.long 0x04 0. "MADMA_EN,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA" "MADMA_EN_0_r,MADMA_EN_1_r" group.long 0x10++0x03 line.long 0x00 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" group.long 0x110++0x07 line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface" bitfld.long 0x00 12.--13. "STANDBYMODE,Master interface power Management standby/wait control" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,?" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 3.--4. "SIDLEMODE,Power management - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" newline bitfld.long 0x00 2. "ENAWAKEUP,Wakeup feature control - Disabled" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal Clock gating strategy - Off" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring Note: the debounce clock the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x124++0x0F line.long 0x00 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1. R1b for all cards and of R5. R5b and R6 response for cards types SD or SDIO" line.long 0x04 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification" rbitfld.long 0x04 16. "OBI,Out-Of-Band Interrupt (OBI) data value - HighLevel" "OBI_0_r,OBI_1_r" rbitfld.long 0x04 15. "SDCD,Card detect input signal (mmci_sdcd) data value - DrivenHigh" "SDCD_0_r,SDCD_1_r" rbitfld.long 0x04 14. "SDWP,Write protect input signal (mmci_sdwp) data value - DrivenHigh" "SDWP_0_r,SDWP_1_r" newline bitfld.long 0x04 13. "WAKD,Wake request output signal data value - DrivenLow_w" "WAKD_0_r,WAKD_1_r" bitfld.long 0x04 12. "SSB,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)" "SSB_0_r,SSB_1_r" bitfld.long 0x04 11. "D7D,DAT7 input/output signal data value - DriveLow_w" "D7D_0_r,D7D_1_r" newline bitfld.long 0x04 10. "D6D,DAT6 input/output signal data value - DriveLow_w" "D6D_0_r,D6D_1_r" bitfld.long 0x04 9. "D5D,DAT5 input/output signal data value - DriveLow_w" "D5D_0_r,D5D_1_r" bitfld.long 0x04 8. "D4D,DAT4 input/output signal data value - DriveLow_w" "D4D_0_r,D4D_1_r" newline bitfld.long 0x04 7. "D3D,DAT3 input/output signal data value - DriveLow_w" "D3D_0_r,D3D_1_r" bitfld.long 0x04 6. "D2D,DAT2 input/output signal data value - DriveLow_w" "D2D_0_r,D2D_1_r" bitfld.long 0x04 5. "D1D,DAT1 input/output signal data value - DriveLow_w" "D1D_0_r,D1D_1_r" newline bitfld.long 0x04 4. "D0D,DAT0 input/output signal data value - Zero_w" "D0D_0_r,D0D_1_r" bitfld.long 0x04 3. "DDIR,Control of the DAT[7:0] pins direction" "DDIR_0_r,DDIR_1_r" bitfld.long 0x04 2. "CDAT,CMD input/output signal data value - DriveLow_w" "CDAT_0_r,CDAT_1_r" newline bitfld.long 0x04 1. "CDIR,Control of the CMD pin direction" "CDIR_0_r,CDIR_1_r" bitfld.long 0x04 0. "MCKD,MMC clock output signal data value - DrivenLow_w" "MCKD_0_r,MCKD_1_r" line.long 0x08 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card" bitfld.long 0x08 21. "SDMA_LNE,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion request remains active until last allowed data written.." "SDMA_LNE_0,SDMA_LNE_1" bitfld.long 0x08 20. "DMA_MNS,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available.." "DMA_MNS_0,DMA_MNS_1" bitfld.long 0x08 19. "DDR,Dual Data Rate mode: When this register is set the controller uses both clock edge to emit or receive data" "DDR_0,DDR_1" newline bitfld.long 0x08 18. "BOOT_CF0,Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence" "BOOT_CF0_0_r,BOOT_CF0_1_r" bitfld.long 0x08 17. "BOOT_ACK,Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued" "BOOT_ACK_0,BOOT_ACK_1" bitfld.long 0x08 16. "CLKEXTFREE,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]" "CLKEXTFREE_0,CLKEXTFREE_1" newline bitfld.long 0x08 15. "PADEN,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power" "PADEN_0,PADEN_1" bitfld.long 0x08 14. "OBIE,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin" "OBIE_0,OBIE_1" bitfld.long 0x08 13. "OBIP,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards" "OBIP_0,OBIP_1" newline bitfld.long 0x08 12. "CEATA,CE-ATA control mode MMC cards compliant with CE-ATA:By default this bit is set to 0" "CEATA_0,CEATA_1" bitfld.long 0x08 11. "CTPL,Control Power for DAT[1] line MMC and SD cards: By default this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current" "CTPL_0,CTPL_1" bitfld.long 0x08 9.--10. "DVAL,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (mmci_sdcd)" "DVAL_0,DVAL_1,DVAL_2,DVAL_3" newline bitfld.long 0x08 8. "WPP,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (mmci_sdwp)" "WPP_0,WPP_1" bitfld.long 0x08 7. "CDP,Card detect polarity All cards This bit selects the active level of the card detect input signal (mmci_sdcd)" "CDP_0,CDP_1" bitfld.long 0x08 6. "MIT,MMC interrupt command Only for MMC cards" "MIT_0,MIT_1" newline bitfld.long 0x08 5. "DW8,8-bit mode MMC select For SD/SDIO cards this bit must be set to 0" "DW8_0,DW8_1" bitfld.long 0x08 4. "MODE,Mode select All cards This bit select between Functional mode and SYSTEST mode" "MODE_0,MODE_1" bitfld.long 0x08 3. "STR,Stream command Only for MMC cards" "STR_0,STR_1" newline bitfld.long 0x08 2. "HR,Broadcast host response Only for MMC cards" "HR_0,HR_1" bitfld.long 0x08 1. "INIT,Send initialization stream All cards" "INIT_0,INIT_1" bitfld.long 0x08 0. "OD,Card open drain mode" "OD_0,OD_1" line.long 0x0C "MMCHS_PWCNT,Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power. this value depends on PAD characteristics and voltage" hexmask.long.word 0x0C 0.--15. 1. "PWRCNT,Power counter register" group.long 0x200++0x4B line.long 0x00 "MMCHS_SDMASA,SDMA System Address / Argument 2 Register" line.long 0x04 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register" hexmask.long.word 0x04 16.--31. 1. "NBLK,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers" hexmask.long.word 0x04 0.--11. 1. "BLEN,Transfer Block Size" line.long 0x08 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register)" line.long 0x0C "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode" bitfld.long 0x0C 24.--29. "INDX,Command index - Binary encoded value from 0 to 63 specifying the command number send to card" "INDX_0,INDX_1,INDX_2,INDX_3,INDX_4,INDX_5,INDX_6,INDX_7,INDX_8,INDX_9,INDX_10,INDX_11,INDX_12,INDX_13,INDX_14,INDX_15,INDX_16,INDX_17,INDX_18,INDX_19,INDX_20,INDX_21,INDX_22,INDX_23,INDX_24,INDX_25,INDX_26,INDX_27,INDX_28,INDX_29,INDX_30,INDX_31,INDX_32,INDX_33,INDX_34,INDX_35,INDX_36,INDX_37,INDX_38,INDX_39,INDX_40,INDX_41,INDX_42,INDX_43,INDX_44,INDX_45,INDX_46,INDX_47,INDX_48,INDX_49,INDX_50,INDX_51,INDX_52,INDX_53,INDX_54,INDX_55,INDX_56,INDX_57,INDX_58,INDX_59,INDX_60,INDX_61,INDX_62,INDX_63" bitfld.long 0x0C 22.--23. "CMD_TYPE,Command typeThis register specifies three types of special command: Suspend Resume and Abort" "CMD_TYPE_0,CMD_TYPE_1,CMD_TYPE_2,CMD_TYPE_3" bitfld.long 0x0C 21. "DP,Data present select - This register indicates that data is present and DAT line shall be used" "DP_0,DP_1" newline bitfld.long 0x0C 20. "CICE,Command Index check enable - This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command" "CICE_0,CICE_1" bitfld.long 0x0C 19. "CCCE,Command CRC check enable - This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus" "CCCE_0,CCCE_1" bitfld.long 0x0C 16.--17. "RSP_TYPE,Response type - This bits defines the response type of the command" "RSP_TYPE_0,RSP_TYPE_1,RSP_TYPE_2,RSP_TYPE_3" newline bitfld.long 0x0C 5. "MSBS,Multi/Single block select - This bit must be set to 1 for data transfer in case of multi block command" "MSBS_0,MSBS_1" bitfld.long 0x0C 4. "DDIR,Data transfer Direction Select - This bit defines either data transfer will be a read or a" "DDIR_0,DDIR_1" bitfld.long 0x0C 2.--3. "ACEN,Auto CMD Enable - SD card only" "ACEN_0,ACEN_1,ACEN_2,ACEN_3" newline bitfld.long 0x0C 1. "BCE,Block Count Enable - Multiple block transfers only" "BCE_0,BCE_1" bitfld.long 0x0C 0. "DE,DMA Enable - This bit is used to enable DMA mode for host data access" "DE_0,DE_1" line.long 0x10 "MMCHS_RSP10,Command Response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6/R7" hexmask.long.word 0x10 16.--31. 1. "RSP1,Command Response [31:16]" hexmask.long.word 0x10 0.--15. 1. "RSP0,Command Response [15:0]" line.long 0x14 "MMCHS_RSP32,Command Response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x14 16.--31. 1. "RSP3,Command Response [63:48]" hexmask.long.word 0x14 0.--15. 1. "RSP2,Command Response [47:32]" line.long 0x18 "MMCHS_RSP54,Command Response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x18 16.--31. 1. "RSP5,Command Response [95:80]" hexmask.long.word 0x18 0.--15. 1. "RSP4,Command Response [79:64]" line.long 0x1C "MMCHS_RSP76,Command Response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2" hexmask.long.word 0x1C 16.--31. 1. "RSP7,Command Response [127:112]" hexmask.long.word 0x1C 0.--15. 1. "RSP6,Command Response [111:96]" line.long 0x20 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers" line.long 0x24 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register" bitfld.long 0x24 24. "CLEV,CMD line signal level This status is used to check the CMD line level to recover from errors and for debugging" "CLEV_0_r,CLEV_1_r" bitfld.long 0x24 20.--23. "DLEV,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors and for debugging" "DLEV_0,DLEV_1,DLEV_2,DLEV_3,DLEV_4,DLEV_5,DLEV_6,DLEV_7,DLEV_8,DLEV_9,DLEV_10,DLEV_11,DLEV_12,DLEV_13,DLEV_14,DLEV_15" bitfld.long 0x24 19. "WP,Write protect switch pin level For SDIO cards only" "WP_0_r,WP_1_r" newline bitfld.long 0x24 18. "CDPL,Card detect pin level This bit reflects the inverse value of the card detect input pin (mmci_sdcd) debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTAE[CSS]) is set to 1" "CDPL_0_r,CDPL_1_r" bitfld.long 0x24 17. "CSS,Card State Stable This bit is used for testing" "CSS_0_r,CSS_1_r" bitfld.long 0x24 16. "CINS,Card inserted This bit is the debounced value of the card detect input pin (mmci_sdcd)" "CINS_0_r,CINS_1_r" newline bitfld.long 0x24 11. "BRE,Buffer read enable This bit is used for non-DMA read transfers" "BRE_0_r,BRE_1_r" bitfld.long 0x24 10. "BWE,Buffer Write enable This status is used for non-DMA write transfers" "BWE_0_r,BWE_1_r" bitfld.long 0x24 9. "RTA,Read transfer active This status is used for detecting completion of a read transfer" "RTA_0_r,RTA_1_r" newline bitfld.long 0x24 8. "WTA,Write transfer active This status indicates a write transfer active" "WTA_0_r,WTA_1_r" bitfld.long 0x24 3. "RTR,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data" "RTR_0_r,RTR_1_r" bitfld.long 0x24 2. "DLA,DAT line active This status bit indicates whether one of the DAT line is in use" "DLA_0_r,DLA_1_r" newline bitfld.long 0x24 1. "DATI,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued" "DATI_0_r,DATI_1_r" bitfld.long 0x24 0. "CMDI,Command inhibit(CMD) This status bit indicates that the CMD line is in use" "CMDI_0_r,CMDI_1_r" line.long 0x28 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power. wakeup and transfer parameters" bitfld.long 0x28 27. "OBWE,Wakeup event enable for 'Out-of-Band' Interrupt" "OBWE_0,OBWE_1" bitfld.long 0x28 26. "REM,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion" "REM_0,REM_1" bitfld.long 0x28 25. "INS,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion" "INS_0,INS_1" newline bitfld.long 0x28 24. "IWE,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion" "IWE_0,IWE_1" bitfld.long 0x28 19. "IBG,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer" "IBG_0,IBG_1" bitfld.long 0x28 18. "RWC,Read wait control The read wait function is optional only for SDIO cards" "RWC_0,RWC_1" newline bitfld.long 0x28 17. "CR,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR])" "CR_0,CR_1" bitfld.long 0x28 16. "SBGR,Stop at block gap request This bit is used to stop executing a transaction at the next block gap" "SBGR_0,SBGR_1" bitfld.long 0x28 9.--11. "SDVS,SD bus voltage select All cards" "?,?,?,?,?,SDVS_5,SDVS_6,SDVS_7" newline bitfld.long 0x28 8. "SDBP,SD bus power Before setting this bit the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS])" "SDBP_0,SDBP_1" bitfld.long 0x28 7. "CDSS,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in.." "CDSS_0,CDSS_1" bitfld.long 0x28 6. "CDTL,Card Detect Test Level: This bit is enabled while MMCHS_HCTL[7] CDSS is set to 1 and it indicates whether the card is inserted or not" "CDTL_0,CDTL_1" newline bitfld.long 0x28 3.--4. "DMAS,DMA Select Mode: One of supported DMA modes can be selected" "DMAS_0,DMAS_1,DMAS_2,DMAS_3" bitfld.long 0x28 2. "HSPE,High Speed Enable: Before setting this bit the Host Driver shall check the MMCHS_CAPA[21] HSS" "HSPE_0,HSPE_1" bitfld.long 0x28 1. "DTW,Data transfer width For MMC card this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument" "DTW_0,DTW_1" newline rbitfld.long 0x28 0. "LED,Reserved bit" "LED_0,LED_1" line.long 0x2C "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets. clock frequency management and data timeout" bitfld.long 0x2C 26. "SRD,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed" "SRD_0,SRD_1" bitfld.long 0x2C 25. "SRC,Software reset for CMD line For more information about SRC bit manipulation see" "SRC_0,SRC_1" bitfld.long 0x2C 24. "SRA,Software reset for all This bit is set to 1 for reset and released to 0 when completed" "SRA_0,SRA_1" newline bitfld.long 0x2C 16.--19. "DTO,Data timeout counter value and busy timeout" "DTO_0,DTO_1,?,?,?,?,?,?,?,?,?,?,?,?,DTO_14,DTO_15" hexmask.long.word 0x2C 6.--15. 1. "CLKD,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC SD or SDIO)" rbitfld.long 0x2C 5. "CGS,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit" "0,1" newline bitfld.long 0x2C 2. "CEN,Clock enable This bit controls if the clock is provided to the card or not" "CEN_0,CEN_1" rbitfld.long 0x2C 1. "ICS,Internal clock stable (status) This bit indicates either the internal clock is stable or not" "ICS_0_r,ICS_1_r" bitfld.long 0x2C 0. "ICE,Internal clock enable This register controls the internal clock activity" "ICE_0,ICE_1" line.long 0x30 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x30 29. "BADA,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit.." "BADA_0_r,BADA_1_r" bitfld.long 0x30 28. "CERR,Card error This bit is set automatically when there is at least one error in a response of type R1 R1b R6 R5 or R5b" "CERR_0_r,CERR_1_r" bitfld.long 0x30 26. "TE,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select)" "TE_0,TE_1" newline bitfld.long 0x30 25. "ADMAE,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer" "ADMAE_0_r,ADMAE_1_r" bitfld.long 0x30 24. "ACE,Auto CMD error Auto CMD12 and Auto CMD23 use this error status" "ACE_0_r,ACE_1_r" bitfld.long 0x30 22. "DEB,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode" "DEB_0_r,DEB_1_r" newline bitfld.long 0x30 21. "DCRC,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command" "DCRC_0_r,DCRC_1_r" bitfld.long 0x30 20. "DTO,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout - St_un_w" "DTO_0_r,DTO_1_r" bitfld.long 0x30 19. "CIE,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted" "CIE_0_r,CIE_1_r" newline bitfld.long 0x30 18. "CEB,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response" "CEB_0_r,CEB_1_r" bitfld.long 0x30 17. "CCRC,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register" "CCRC_0_r,CCRC_1_r" bitfld.long 0x30 16. "CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "CTO_0_r,CTO_1_r" newline rbitfld.long 0x30 15. "ERRI,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[24:15]) are set then this bit is set to 1" "ERRI_0_r,ERRI_1_r" bitfld.long 0x30 10. "BSR,Boot status received interrupt This bit is set automatically when MMCHS_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line" "BSR_0_r,BSR_1_r" bitfld.long 0x30 9. "OBI,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin" "OBI_0_r,OBI_1_r" newline rbitfld.long 0x30 8. "CIRQ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards" "CIRQ_0_r,CIRQ_1_r" bitfld.long 0x30 7. "CREM,Card removal This bit is set automatically when MMCHS_PSTATE[CINS] changes from 1 to 0" "CREM_0_r,CREM_1_r" bitfld.long 0x30 6. "CINS,Card insertion This bit is set automatically when MMCHS_PSTATE[CINS] changes from 0 to 1" "CINS_0_r,CINS_1_r" newline bitfld.long 0x30 5. "BRR,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer" "BRR_0_r,BRR_1_r" bitfld.long 0x30 4. "BWR,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]" "BWR_0_r,BWR_1_r" bitfld.long 0x30 3. "DMA,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion" "DMA_0_r,DMA_1_r" newline bitfld.long 0x30 2. "BGE,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]) this bit is automatically set when transaction is stopped at the block gap during a read or write operation" "BGE_0_r,BGE_1_r" bitfld.long 0x30 1. "TC,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR])" "TC_0_r,TC_1_r" bitfld.long 0x30 0. "CC,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected then the command complete interrupt is generated at the end of the command" "CC_0_r,CC_1_r" line.long 0x34 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits. on an event-by-event basis" bitfld.long 0x34 29. "BADA_ENABLE,Bad access to data space Status Enable - Masked" "BADA_ENABLE_0,BADA_ENABLE_1" bitfld.long 0x34 28. "CERR_ENABLE,Card Error Status Enable - Masked" "CERR_ENABLE_0,CERR_ENABLE_1" bitfld.long 0x34 26. "TE_ENABLE,Tuning Error Status Enable - Masked" "TE_ENABLE_0,TE_ENABLE_1" newline bitfld.long 0x34 25. "ADMAE_ENABLE,ADMA Error Status Enable - Masked" "ADMAE_ENABLE_0,ADMAE_ENABLE_1" bitfld.long 0x34 24. "ACE_ENABLE,Auto CMD Error Status Enable - Masked" "ACE_ENABLE_0,ACE_ENABLE_1" bitfld.long 0x34 22. "DEB_ENABLE,Data End Bit Error Status Enable - Masked" "DEB_ENABLE_0,DEB_ENABLE_1" newline bitfld.long 0x34 21. "DCRC_ENABLE,Data CRC Error Status Enable - Masked" "DCRC_ENABLE_0,DCRC_ENABLE_1" bitfld.long 0x34 20. "DTO_ENABLE,Data Timeout Error Status Enable - Masked" "DTO_ENABLE_0,DTO_ENABLE_1" bitfld.long 0x34 19. "CIE_ENABLE,Command Index Error Status Enable - Masked" "CIE_ENABLE_0,CIE_ENABLE_1" newline bitfld.long 0x34 18. "CEB_ENABLE,Command End Bit Error Status Enable - Masked" "CEB_ENABLE_0,CEB_ENABLE_1" bitfld.long 0x34 17. "CCRC_ENABLE,Command CRC Error Status Enable - Masked" "CCRC_ENABLE_0,CCRC_ENABLE_1" bitfld.long 0x34 16. "CTO_ENABLE,Command Timeout Error Status Enable - Masked" "CTO_ENABLE_0,CTO_ENABLE_1" newline rbitfld.long 0x34 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "NULL_0,NULL_1" bitfld.long 0x34 10. "BSR_ENABLE,Boot Status Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored" "BSR_ENABLE_0,BSR_ENABLE_1" bitfld.long 0x34 9. "OBI_ENABLE,Out-of-Band Status Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored" "OBI_ENABLE_0,OBI_ENABLE_1" newline bitfld.long 0x34 8. "CIRQ_ENABLE,Card Status Enable A clear of this bit also clears the corresponding status bit" "CIRQ_ENABLE_0,CIRQ_ENABLE_1" bitfld.long 0x34 7. "CREM_ENABLE,Card Removal Status Enable - Masked" "CREM_ENABLE_0,CREM_ENABLE_1" bitfld.long 0x34 6. "CINS_ENABLE,Card Insertion Status Enable - Masked" "CINS_ENABLE_0,CINS_ENABLE_1" newline bitfld.long 0x34 5. "BRR_ENABLE,Buffer Read Ready Status Enable - Masked" "BRR_ENABLE_0,BRR_ENABLE_1" bitfld.long 0x34 4. "BWR_ENABLE,Buffer Write Ready Status Enable - Masked" "BWR_ENABLE_0,BWR_ENABLE_1" bitfld.long 0x34 3. "DMA_ENABLE,DMA Status Enable - Masked" "DMA_ENABLE_0,DMA_ENABLE_1" newline bitfld.long 0x34 2. "BGE_ENABLE,Block Gap Event Status Enable - Masked" "BGE_ENABLE_0,BGE_ENABLE_1" bitfld.long 0x34 1. "TC_ENABLE,Transfer Complete Status Enable - Masked" "TC_ENABLE_0,TC_ENABLE_1" bitfld.long 0x34 0. "CC_ENABLE,Command Complete Status Enable - Masked" "CC_ENABLE_0,CC_ENABLE_1" line.long 0x38 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status. on an event-by-event basis" bitfld.long 0x38 29. "BADA_SIGEN,Bad access to data space Signal Enable - Masked" "BADA_SIGEN_0,BADA_SIGEN_1" bitfld.long 0x38 28. "CERR_SIGEN,Card Error Interrupt Signal Enable - Masked" "CERR_SIGEN_0,CERR_SIGEN_1" bitfld.long 0x38 26. "TE_SIGEN,Tuning Error Signal Enable - Masked" "TE_SIGEN_0,TE_SIGEN_1" newline bitfld.long 0x38 25. "ADMAE_SIGEN,ADMA Error Signal Enable - Masked" "ADMAE_SIGEN_0,ADMAE_SIGEN_1" bitfld.long 0x38 24. "ACE_SIGEN,Auto CMD Error Signal Enable - Masked" "ACE_SIGEN_0,ACE_SIGEN_1" bitfld.long 0x38 22. "DEB_SIGEN,Data End Bit Error Signal Enable - Masked" "DEB_SIGEN_0,DEB_SIGEN_1" newline bitfld.long 0x38 21. "DCRC_SIGEN,Data CRC Error Signal Enable - Masked" "DCRC_SIGEN_0,DCRC_SIGEN_1" bitfld.long 0x38 20. "DTO_SIGEN,Data Timeout Error Signal Enable - Masked" "DTO_SIGEN_0,DTO_SIGEN_1" bitfld.long 0x38 19. "CIE_SIGEN,Command Index Error Signal Enable - Masked" "CIE_SIGEN_0,CIE_SIGEN_1" newline bitfld.long 0x38 18. "CEB_SIGEN,Command End Bit Error Signal Enable - Masked" "CEB_SIGEN_0,CEB_SIGEN_1" bitfld.long 0x38 17. "CCRC_SIGEN,Command CRC Error Signal Enable - Masked" "CCRC_SIGEN_0,CCRC_SIGEN_1" bitfld.long 0x38 16. "CTO_SIGEN,Command timeout Error Signal Enable - Masked" "CTO_SIGEN_0,CTO_SIGEN_1" newline rbitfld.long 0x38 15. "NULL,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "NULL_0,NULL_1" bitfld.long 0x38 10. "BSR_SIGEN,Boot Status Signal Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored" "BSR_SIGEN_0,BSR_SIGEN_1" bitfld.long 0x38 9. "OBI_SIGEN,Out-Of-Band Interrupt Signal Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored" "OBI_SIGEN_0,OBI_SIGEN_1" newline bitfld.long 0x38 8. "CIRQ_SIGEN,Card Interrupt Signal Enable - Masked" "CIRQ_SIGEN_0,CIRQ_SIGEN_1" bitfld.long 0x38 7. "CREM_SIGEN,Card Removal Signal Enable - Masked" "CREM_SIGEN_0,CREM_SIGEN_1" bitfld.long 0x38 6. "CINS_SIGEN,Card Insertion Signal Enable - Masked" "CINS_SIGEN_0,CINS_SIGEN_1" newline bitfld.long 0x38 5. "BRR_SIGEN,Buffer Read Ready Signal Enable - Masked" "BRR_SIGEN_0,BRR_SIGEN_1" bitfld.long 0x38 4. "BWR_SIGEN,Buffer Write Ready Signal Enable - Masked" "BWR_SIGEN_0,BWR_SIGEN_1" bitfld.long 0x38 3. "DMA_SIGEN,DMA Interrupt Signal Enable - Masked" "DMA_SIGEN_0,DMA_SIGEN_1" newline bitfld.long 0x38 2. "BGE_SIGEN,Black Gap Event Signal Enable - Masked" "BGE_SIGEN_0,BGE_SIGEN_1" bitfld.long 0x38 1. "TC_SIGEN,Transfer Completed Status Enable - Masked" "TC_SIGEN_0,TC_SIGEN_1" bitfld.long 0x38 0. "CC_SIGEN,Command Complete Status Enable - Masked" "CC_SIGEN_0,CC_SIGEN_1" line.long 0x3C "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23" bitfld.long 0x3C 31. "PV_ENABLE,Preset Value Enable Host Controller Version 3.00 supports this bit" "PV_ENABLE_0,PV_ENABLE_1" bitfld.long 0x3C 30. "AI_ENABLE,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1" "AI_ENABLE_0,AI_ENABLE_1" bitfld.long 0x3C 23. "SCLK_SEL,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT" "SCLK_SEL_0,SCLK_SEL_1" newline bitfld.long 0x3C 22. "ET,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed" "ET_0,ET_1" bitfld.long 0x3C 20.--21. "DS_SEL,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit" "DS_SEL_0,DS_SEL_1,DS_SEL_2,DS_SEL_3" bitfld.long 0x3C 19. "V1V8_SIGEN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell" "V1V8_SIGEN_0,V1V8_SIGEN_1" newline bitfld.long 0x3C 16.--18. "UHSMS,UHS Mode Select This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1" "UHSMS_0,UHSMS_1,UHSMS_2,UHSMS_3,UHSMS_4,UHSMS_5,UHSMS_6,UHSMS_7" rbitfld.long 0x3C 7. "CNI,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register" "CNI_0_r,CNI_1_r" rbitfld.long 0x3C 4. "ACIE,Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command" "ACIE_0_r,ACIE_1_r" newline rbitfld.long 0x3C 3. "ACEB,Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0" "ACEB_0_r,ACEB_1_r" rbitfld.long 0x3C 2. "ACCE,Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response" "ACCE_0_r,ACCE_1_r" rbitfld.long 0x3C 1. "ACTO,Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command" "ACTO_0_r,ACTO_1_r" newline rbitfld.long 0x3C 0. "ACNE,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "ACNE_0_r,ACNE_1_r" line.long 0x40 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller" rbitfld.long 0x40 29. "AIS,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "AIS_0_r,AIS_1_r" rbitfld.long 0x40 28. "BIT64,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus" "BIT64_0_r,BIT64_1_r" bitfld.long 0x40 26. "VS18,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS18_0_r,VS18_1_r" newline bitfld.long 0x40 25. "VS30,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS30_0_r,VS30_1_r" bitfld.long 0x40 24. "VS33,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities" "VS33_0_r,VS33_1_r" rbitfld.long 0x40 23. "SRS,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality" "SRS_0_r,SRS_1_r" newline rbitfld.long 0x40 22. "DS,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly" "DS_0_r,DS_1_r" rbitfld.long 0x40 21. "HSS,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency" "HSS_0_r,HSS_1_r" rbitfld.long 0x40 19. "AD2S,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2" "AD2S_0_r,AD2S_1_r" newline rbitfld.long 0x40 16.--17. "MBL,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller" "MBL_0_r,MBL_1_r,MBL_2_r,?" hexmask.long.byte 0x40 8.--15. 1. "BCF,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock" rbitfld.long 0x40 7. "TCU,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCU_0_r,TCU_1_r" newline rbitfld.long 0x40 0.--5. "TCF,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])" "TCF_0_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x44 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation" hexmask.long.byte 0x44 16.--23. 1. "CM,Clock Multiplier This field indicates clock multiplier value of programmable clock generator" bitfld.long 0x44 14.--15. "RTM,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length" "RTM_0_r,RTM_1_r,RTM_2_r,RTM_3_r" bitfld.long 0x44 13. "TSDR50,Use Tuning for SDR50 If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "TSDR50_0_r,TSDR50_1_r" newline bitfld.long 0x44 8.--11. "TCRT,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "TCRT_0_r,TCRT_1_r,TCRT_2_r,TCRT_3_r,TCRT_4_r,TCRT_5_r,TCRT_6_r,TCRT_7_r,TCRT_8_r,TCRT_9_r,TCRT_10_r,TCRT_11_r,TCRT_12_r,TCRT_13_r,TCRT_14_r,TCRT_15_r" bitfld.long 0x44 6. "DTD,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling" "DTD_0_r,DTD_1_r" bitfld.long 0x44 5. "DTC,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling" "DTC_0_r,DTC_1_r" newline bitfld.long 0x44 4. "DTA,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling" "DTA_0_r,DTA_1_r" bitfld.long 0x44 2. "DDR50,DDR50 Support - Supported" "DDR50_0_r,DDR50_1_r" bitfld.long 0x44 1. "SDR104,SDR104 Support SDR104 requires tuning" "SDR104_0_r,SDR104_1_r" newline bitfld.long 0x44 0. "SDR50,SDR50 Support If SDR104 is supported this bit shall be set to 1" "SDR50_0_r,SDR50_1_r" line.long 0x48 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage" hexmask.long.byte 0x48 16.--23. 1. "CUR_1V8,Maximum current for" hexmask.long.byte 0x48 8.--15. 1. "CUR_3V0,Maximum current for" hexmask.long.byte 0x48 0.--7. 1. "CUR_3V3,Maximum current for" group.long 0x250++0x0B line.long 0x00 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register" bitfld.long 0x00 29. "FE_BADA,Force Event Bad access to data space" "FE_BADA_0_w,FE_BADA_1_w" bitfld.long 0x00 28. "FE_CERR,Force Event Card error" "FE_CERR_0_w,FE_CERR_1_w" bitfld.long 0x00 25. "FE_ADMAE,Force Event ADMA Error" "FE_ADMAE_0_w,FE_ADMAE_1_w" newline bitfld.long 0x00 24. "FE_ACE,Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23 - NoAction" "FE_ACE_0_w,FE_ACE_1_w" bitfld.long 0x00 22. "FE_DEB,Force Event Data End Bit error" "FE_DEB_0_w,FE_DEB_1_w" bitfld.long 0x00 21. "FE_DCRC,Force Event Data CRC Error" "FE_DCRC_0_w,FE_DCRC_1_w" newline bitfld.long 0x00 20. "FE_DTO,Force Event Data Timeout Error" "FE_DTO_0_w,FE_DTO_1_w" bitfld.long 0x00 19. "FE_CIE,Force Event Command Index Error" "FE_CIE_0_w,FE_CIE_1_w" bitfld.long 0x00 18. "FE_CEB,Force Event Command End Bit Error" "FE_CEB_0_w,FE_CEB_1_w" newline bitfld.long 0x00 17. "FE_CCRC,Force Event Command CRC Error" "FE_CCRC_0_w,FE_CCRC_1_w" bitfld.long 0x00 16. "FE_CTO,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command" "FE_CTO_0_w,FE_CTO_1_w" bitfld.long 0x00 7. "FE_CNI,Force Event Command not issue by Auto CMD12 error - NoAction" "FE_CNI_0_w,FE_CNI_1_w" newline bitfld.long 0x00 4. "FE_ACIE,Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23 - NoAction" "FE_ACIE_0_w,FE_ACIE_1_w" bitfld.long 0x00 3. "FE_ACEB,Force Event Auto CMD End Bit Error - NoAction" "FE_ACEB_0_w,FE_ACEB_1_w" bitfld.long 0x00 2. "FE_ACCE,Force Event Auto CMD CRC Error - NoAction" "FE_ACCE_0_w,FE_ACCE_1_w" newline bitfld.long 0x00 1. "FE_ACTO,Force Event Auto CMD Timeout Error - NoAction" "FE_ACTO_0_w,FE_ACTO_1_w" bitfld.long 0x00 0. "FE_ACNE,Force Event Auto CMD12 Not Executed - NoAction" "FE_ACNE_0_w,FE_ACNE_1_w" line.long 0x04 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred. the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor" bitfld.long 0x04 2. "LME,ADMA Length Mismatch Error: (1) While Block Count Enable being set the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length" "LME_0,LME_1" bitfld.long 0x04 0.--1. "AES,ADMA Error State his field indicates the state of ADMA when error is occurred during ADMA data transfer" "AES_0,AES_1,AES_2,AES_3" line.long 0x08 "MMCHS_ADMASAL,ADMA System address Low bits" rgroup.long 0x260++0x0F line.long 0x00 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" bitfld.long 0x00 30.--31. "DSDS_SEL,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "DSDS_SEL_0_r,DSDS_SEL_1_r,DSDS_SEL_2_r,DSDS_SEL_3_r" bitfld.long 0x00 26. "DSCLKGEN_SEL,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator" "DSCLKGEN_SEL_0_r,DSCLKGEN_SEL_1_r" hexmask.long.word 0x00 16.--25. 1. "DSSDCLK_SEL,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" newline bitfld.long 0x00 14.--15. "INITDS_SEL,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes" "INITDS_SEL_0_r,INITDS_SEL_1_r,INITDS_SEL_2_r,INITDS_SEL_3_r" bitfld.long 0x00 10. "INITCLKGEN_SEL,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator" "INITCLKGEN_SEL_0_r,INITCLKGEN_SEL_1_r" hexmask.long.word 0x00 0.--9. 1. "INITSDCLK_SEL,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x04 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" bitfld.long 0x04 30.--31. "SDR12DS_SEL,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR12DS_SEL_0_r,SDR12DS_SEL_1_r,SDR12DS_SEL_2_r,SDR12DS_SEL_3_r" bitfld.long 0x04 26. "SDR12CLKGEN_SEL,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator" "SDR12CLKGEN_SEL_0_r,SDR12CLKGEN_SEL_1_r" hexmask.long.word 0x04 16.--25. 1. "SDR12SDCLK_SEL,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" newline bitfld.long 0x04 14.--15. "HSDS_SEL,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes" "HSDS_SEL_0_r,HSDS_SEL_1_r,HSDS_SEL_2_r,HSDS_SEL_3_r" bitfld.long 0x04 10. "HSCLKGEN_SEL,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator" "HSCLKGEN_SEL_0_r,HSCLKGEN_SEL_1_r" hexmask.long.word 0x04 0.--9. 1. "HSSDCLK_SEL,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x08 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 and SDR50 speed modes" bitfld.long 0x08 30.--31. "SDR50DS_SEL,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR50DS_SEL_0_r,SDR50DS_SEL_1_r,SDR50DS_SEL_2_r,SDR50DS_SEL_3_r" bitfld.long 0x08 26. "SDR50CLKGEN_SEL,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator" "SDR50CLKGEN_SEL_0_r,SDR50CLKGEN_SEL_1_r" hexmask.long.word 0x08 16.--25. 1. "SDR50SDCLK_SEL,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" newline bitfld.long 0x08 14.--15. "SDR25DS_SEL,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR25DS_SEL_0_r,SDR25DS_SEL_1_r,SDR25DS_SEL_2_r,SDR25DS_SEL_3_r" bitfld.long 0x08 10. "SDR25CLKGEN_SEL,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator" "SDR25CLKGEN_SEL_0_r,SDR25CLKGEN_SEL_1_r" hexmask.long.word 0x08 0.--9. 1. "SDR25SDCLK_SEL,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" line.long 0x0C "MMCHS_PVSDR104DDR50,Preset Value for SDR104 and DDR50 speed modes" bitfld.long 0x0C 30.--31. "DDR50DS_SEL,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes" "DDR50DS_SEL_0_r,DDR50DS_SEL_1_r,DDR50DS_SEL_2_r,DDR50DS_SEL_3_r" bitfld.long 0x0C 26. "DDR50CLKGEN_SEL,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator" "DDR50CLKGEN_SEL_0_r,DDR50CLKGEN_SEL_1_r" hexmask.long.word 0x0C 16.--25. 1. "DDR50SDCLK_SEL,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" newline bitfld.long 0x0C 14.--15. "SDR104DS_SEL,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes" "SDR104DS_SEL_0_r,SDR104DS_SEL_1_r,SDR104DS_SEL_2_r,SDR104DS_SEL_3_r" bitfld.long 0x0C 10. "SDR104CLKGEN_SEL,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator" "SDR104CLKGEN_SEL_0_r,SDR104CLKGEN_SEL_1_r" hexmask.long.word 0x0C 0.--9. 1. "SDR104SDCLK_SEL,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system" rgroup.long 0x2FC++0x03 line.long 0x00 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number. the version number of SD specification compliancy and a slot status bit" hexmask.long.byte 0x00 24.--31. 1. "VREV,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" hexmask.long.byte 0x00 16.--23. 1. "SREV,Specification Version Number This status indicates the Host Controller Spec" bitfld.long 0x00 0. "SIS,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module" "SIS_0,SIS_1" tree.end repeat.end tree.end tree.open "Enhanced_DMA" tree "EDMA_TPCC_L3_MAINInterconnect" base ad:0x43300000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x03 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" group.long 0x260++0x03 line.long 0x00 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" newline bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" newline bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" newline bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" newline bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" newline bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" newline bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" newline bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" newline bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error" "TCERR_0,TCERR_1" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7" "QTHRXCD7_0,QTHRXCD7_1" bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5" "QTHRXCD5_0,QTHRXCD5_1" bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4" "QTHRXCD4_0,QTHRXCD4_1" newline bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3" "QTHRXCD3_0,QTHRXCD3_1" bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1" "QTHRXCD1_0,QTHRXCD1_1" bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR" "0,1" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7 - Write 0x0 have no affect" "0,1" bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6 - Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5 - Write 0x0 have no affect" "0,1" bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4: - Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3 - Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2 - Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1 - Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0 - Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x20 1. "SET,Error Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "QUEACTV2_0,QUEACTV2_1" bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" bitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "TRACTV_0,TRACTV_1" bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" bitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x08 0. "CLR,AET Clear command - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x0F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" bitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" bitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" bitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" newline bitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" bitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0C 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x0C 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x0C 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" newline bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" newline bitfld.long 0x04 26. "E58,Event #58" "0,1" bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" bitfld.long 0x04 7. "E39,Event #39" "0,1" newline bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" bitfld.long 0x08 27. "E27,Event #27" "0,1" newline bitfld.long 0x08 26. "E26,Event #26" "0,1" bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" bitfld.long 0x08 17. "E17,Event #17" "0,1" newline bitfld.long 0x08 16. "E16,Event #16" "0,1" bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" bitfld.long 0x0C 27. "E59,Event #59" "0,1" newline bitfld.long 0x0C 26. "E58,Event #58" "0,1" bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" bitfld.long 0x0C 17. "E49,Event #49" "0,1" newline bitfld.long 0x0C 16. "E48,Event #48" "0,1" bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" bitfld.long 0x0C 7. "E39,Event #39" "0,1" newline bitfld.long 0x0C 6. "E38,Event #38" "0,1" bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" bitfld.long 0x10 27. "E27,Event #27" "0,1" newline bitfld.long 0x10 26. "E26,Event #26" "0,1" bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" bitfld.long 0x10 17. "E17,Event #17" "0,1" newline bitfld.long 0x10 16. "E16,Event #16" "0,1" bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" bitfld.long 0x10 7. "E7,Event #7" "0,1" newline bitfld.long 0x10 6. "E6,Event #6" "0,1" bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" bitfld.long 0x14 27. "E59,Event #59" "0,1" newline bitfld.long 0x14 26. "E58,Event #58" "0,1" bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" bitfld.long 0x14 17. "E49,Event #49" "0,1" newline bitfld.long 0x14 16. "E48,Event #48" "0,1" bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" bitfld.long 0x14 7. "E39,Event #39" "0,1" newline bitfld.long 0x14 6. "E38,Event #38" "0,1" bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" bitfld.long 0x18 27. "E27,Event #27" "0,1" newline bitfld.long 0x18 26. "E26,Event #26" "0,1" bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" bitfld.long 0x18 17. "E17,Event #17" "0,1" newline bitfld.long 0x18 16. "E16,Event #16" "0,1" bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" bitfld.long 0x18 7. "E7,Event #7" "0,1" newline bitfld.long 0x18 6. "E6,Event #6" "0,1" bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" bitfld.long 0x1C 27. "E59,Event #59" "0,1" newline bitfld.long 0x1C 26. "E58,Event #58" "0,1" bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" bitfld.long 0x1C 17. "E49,Event #49" "0,1" newline bitfld.long 0x1C 16. "E48,Event #48" "0,1" bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" bitfld.long 0x1C 7. "E39,Event #39" "0,1" newline bitfld.long 0x1C 6. "E38,Event #38" "0,1" bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" bitfld.long 0x20 27. "E27,Event #27" "0,1" newline bitfld.long 0x20 26. "E26,Event #26" "0,1" bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" bitfld.long 0x20 17. "E17,Event #17" "0,1" newline bitfld.long 0x20 16. "E16,Event #16" "0,1" bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" bitfld.long 0x20 7. "E7,Event #7" "0,1" newline bitfld.long 0x20 6. "E6,Event #6" "0,1" bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" bitfld.long 0x24 27. "E59,Event #59" "0,1" newline bitfld.long 0x24 26. "E58,Event #58" "0,1" bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" bitfld.long 0x24 17. "E49,Event #49" "0,1" newline bitfld.long 0x24 16. "E48,Event #48" "0,1" bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" bitfld.long 0x24 7. "E39,Event #39" "0,1" newline bitfld.long 0x24 6. "E38,Event #38" "0,1" bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" bitfld.long 0x28 27. "E27,Event #27" "0,1" newline bitfld.long 0x28 26. "E26,Event #26" "0,1" bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" bitfld.long 0x28 17. "E17,Event #17" "0,1" newline bitfld.long 0x28 16. "E16,Event #16" "0,1" bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" bitfld.long 0x28 7. "E7,Event #7" "0,1" newline bitfld.long 0x28 6. "E6,Event #6" "0,1" bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" bitfld.long 0x2C 27. "E59,Event #59" "0,1" newline bitfld.long 0x2C 26. "E58,Event #58" "0,1" bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" bitfld.long 0x2C 17. "E49,Event #49" "0,1" newline bitfld.long 0x2C 16. "E48,Event #48" "0,1" bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" bitfld.long 0x2C 7. "E39,Event #39" "0,1" newline bitfld.long 0x2C 6. "E38,Event #38" "0,1" bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" bitfld.long 0x30 27. "E27,Event #27" "0,1" newline bitfld.long 0x30 26. "E26,Event #26" "0,1" bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" bitfld.long 0x30 17. "E17,Event #17" "0,1" newline bitfld.long 0x30 16. "E16,Event #16" "0,1" bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" bitfld.long 0x30 7. "E7,Event #7" "0,1" newline bitfld.long 0x30 6. "E6,Event #6" "0,1" bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" bitfld.long 0x34 27. "E59,Event #59" "0,1" newline bitfld.long 0x34 26. "E58,Event #58" "0,1" bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" bitfld.long 0x34 17. "E49,Event #49" "0,1" newline bitfld.long 0x34 16. "E48,Event #48" "0,1" bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" bitfld.long 0x34 7. "E39,Event #39" "0,1" newline bitfld.long 0x34 6. "E38,Event #38" "0,1" bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" bitfld.long 0x38 27. "E27,Event #27" "0,1" newline bitfld.long 0x38 26. "E26,Event #26" "0,1" bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" bitfld.long 0x38 17. "E17,Event #17" "0,1" newline bitfld.long 0x38 16. "E16,Event #16" "0,1" bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" bitfld.long 0x38 7. "E7,Event #7" "0,1" newline bitfld.long 0x38 6. "E6,Event #6" "0,1" bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" bitfld.long 0x3C 27. "E59,Event #59" "0,1" newline bitfld.long 0x3C 26. "E58,Event #58" "0,1" bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" bitfld.long 0x3C 17. "E49,Event #49" "0,1" newline bitfld.long 0x3C 16. "E48,Event #48" "0,1" bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" bitfld.long 0x3C 7. "E39,Event #39" "0,1" newline bitfld.long 0x3C 6. "E38,Event #38" "0,1" bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" bitfld.long 0x40 27. "E27,Event #27" "0,1" newline bitfld.long 0x40 26. "E26,Event #26" "0,1" bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" bitfld.long 0x40 17. "E17,Event #17" "0,1" newline bitfld.long 0x40 16. "E16,Event #16" "0,1" bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" bitfld.long 0x40 7. "E7,Event #7" "0,1" newline bitfld.long 0x40 6. "E6,Event #6" "0,1" bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" bitfld.long 0x44 27. "E59,Event #59" "0,1" newline bitfld.long 0x44 26. "E58,Event #58" "0,1" bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" bitfld.long 0x44 17. "E49,Event #49" "0,1" newline bitfld.long 0x44 16. "E48,Event #48" "0,1" bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" bitfld.long 0x44 7. "E39,Event #39" "0,1" newline bitfld.long 0x44 6. "E38,Event #38" "0,1" bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x04 7. "E7,Event #7" "0,1" bitfld.long 0x04 6. "E6,Event #6" "0,1" bitfld.long 0x04 5. "E5,Event #5" "0,1" bitfld.long 0x04 4. "E4,Event #4" "0,1" bitfld.long 0x04 3. "E3,Event #3" "0,1" newline bitfld.long 0x04 2. "E2,Event #2" "0,1" bitfld.long 0x04 1. "E1,Event #1" "0,1" bitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x0C 7. "E7,Event #7" "0,1" bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" bitfld.long 0x10 3. "E3,Event #3" "0,1" newline bitfld.long 0x10 2. "E2,Event #2" "0,1" bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" bitfld.long 0x14 7. "E7,Event #7" "0,1" bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" bitfld.long 0x14 0. "E0,Event #0" "0,1" repeat 16. (list 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. ) tree "DMA_Channel_$1" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_112,Source Address" tree.end repeat.end repeat 16. (list 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. ) tree "DMA_Channel_$1" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_100,Source Address" tree.end repeat.end repeat 16. (list 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. ) tree "DMA_Channel_$1" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_80,Source Address" tree.end repeat.end repeat 16. (list 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. ) tree "DMA_Channel_$1" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_64,Source Address" tree.end repeat.end repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. ) tree "DMA_Channel_$1" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x1C0++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_48,Source Address" tree.end repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. ) tree "DMA_Channel_$1" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x180++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_32,Source Address" tree.end repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. ) tree "DMA_Channel_$1" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x140++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_16,Source Address" tree.end repeat.end repeat 8. (list 8. 9. 10. 11. 12. 13. 14. 15. ) tree "DMA_Channel_$1" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x128++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4140++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x428++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x468++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4144++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_10,Source Address" tree.end repeat.end repeat 4. (list 4. 5. 6. 7. ) tree "DMA_Channel_$1" group.long 0x4088++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4090++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_4," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x409C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x281C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2818++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4098++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x110++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x250++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x364++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x360++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x408C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_4,Destination Address" group.long 0x280C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2808++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x282C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2828++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2824++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2820++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2834++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2830++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2804++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2800++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2814++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2810++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2874++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2870++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x285C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2858++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2854++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2850++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2864++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2860++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2878++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x286C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2868++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4094++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x820++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4080++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_4,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x410++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x450++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2888++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2884++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x288C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2880++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x390++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2894++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2890++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2844++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2840++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x283C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2838++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4084++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_4,Source Address" tree.end repeat.end repeat 2. (list 2. 3. ) tree "DMA_Channel_$1" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x108++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x248++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x354++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x350++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x818++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x408++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x448++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x208++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x388++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" tree.end repeat.end repeat 2. (list 0. 1. ) tree "DMA_Channel_$1" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x100++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x240++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x344++0x03 line.long 0x00 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x00 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" bitfld.long 0x00 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x00 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" bitfld.long 0x00 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x00 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x00 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x00 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" bitfld.long 0x00 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x00 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" bitfld.long 0x00 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x00 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x00 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x00 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" bitfld.long 0x00 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x00 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" bitfld.long 0x00 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x00 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x00 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x00 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" bitfld.long 0x00 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x00 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" bitfld.long 0x00 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x00 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x00 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x00 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" bitfld.long 0x00 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x00 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" bitfld.long 0x00 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x00 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x00 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x00 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x340++0x03 line.long 0x00 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x810++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" rgroup.long 0x400++0x03 line.long 0x00 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x440++0x03 line.long 0x00 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue" bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3" bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x380++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x600++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" tree.end repeat.end tree.end repeat 2. (list 1. 2. )(list ad:0x420A0000 ad:0x421A0000 ) tree "EDMA_TPCC_EVE$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPCC_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence" "MPEXIST_0,MPEXIST_1" bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence" "CHMAPEXIST_0,CHMAPEXIST_1" bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0xFC++0x03 line.long 0x00 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x00 0. "CLKGDIS,Auto Clock Gate Disable" "0,1" group.long 0x260++0x03 line.long 0x00 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel" bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x07 line.long 0x00 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7" line.long 0x04 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x23 line.long 0x00 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x00 31. "E31,Event Missed #31" "0,1" bitfld.long 0x00 30. "E30,Event Missed #30" "0,1" bitfld.long 0x00 29. "E29,Event Missed #29" "0,1" bitfld.long 0x00 28. "E28,Event Missed #28" "0,1" bitfld.long 0x00 27. "E27,Event Missed #27" "0,1" newline bitfld.long 0x00 26. "E26,Event Missed #26" "0,1" bitfld.long 0x00 25. "E25,Event Missed #25" "0,1" bitfld.long 0x00 24. "E24,Event Missed #24" "0,1" bitfld.long 0x00 23. "E23,Event Missed #23" "0,1" bitfld.long 0x00 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x00 21. "E21,Event Missed #21" "0,1" bitfld.long 0x00 20. "E20,Event Missed #20" "0,1" bitfld.long 0x00 19. "E19,Event Missed #19" "0,1" bitfld.long 0x00 18. "E18,Event Missed #18" "0,1" bitfld.long 0x00 17. "E17,Event Missed #17" "0,1" newline bitfld.long 0x00 16. "E16,Event Missed #16" "0,1" bitfld.long 0x00 15. "E15,Event Missed #15" "0,1" bitfld.long 0x00 14. "E14,Event Missed #14" "0,1" bitfld.long 0x00 13. "E13,Event Missed #13" "0,1" bitfld.long 0x00 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x00 11. "E11,Event Missed #11" "0,1" bitfld.long 0x00 10. "E10,Event Missed #10" "0,1" bitfld.long 0x00 9. "E9,Event Missed #9" "0,1" bitfld.long 0x00 8. "E8,Event Missed #8" "0,1" bitfld.long 0x00 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x00 6. "E6,Event Missed #6" "0,1" bitfld.long 0x00 5. "E5,Event Missed #5" "0,1" bitfld.long 0x00 4. "E4,Event Missed #4" "0,1" bitfld.long 0x00 3. "E3,Event Missed #3" "0,1" bitfld.long 0x00 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x00 1. "E1,Event Missed #1" "0,1" bitfld.long 0x00 0. "E0,Event Missed #0" "0,1" line.long 0x04 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced" bitfld.long 0x04 31. "E63,Event Missed #63" "0,1" bitfld.long 0x04 30. "E62,Event Missed #62" "0,1" bitfld.long 0x04 29. "E61,Event Missed #61" "0,1" bitfld.long 0x04 28. "E60,Event Missed #60" "0,1" bitfld.long 0x04 27. "E59,Event Missed #59" "0,1" newline bitfld.long 0x04 26. "E58,Event Missed #58" "0,1" bitfld.long 0x04 25. "E57,Event Missed #57" "0,1" bitfld.long 0x04 24. "E56,Event Missed #56" "0,1" bitfld.long 0x04 23. "E55,Event Missed #55" "0,1" bitfld.long 0x04 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x04 21. "E53,Event Missed #53" "0,1" bitfld.long 0x04 20. "E52,Event Missed #52" "0,1" bitfld.long 0x04 19. "E51,Event Missed #51" "0,1" bitfld.long 0x04 18. "E50,Event Missed #50" "0,1" bitfld.long 0x04 17. "E49,Event Missed #49" "0,1" newline bitfld.long 0x04 16. "E48,Event Missed #48" "0,1" bitfld.long 0x04 15. "E47,Event Missed #47" "0,1" bitfld.long 0x04 14. "E46,Event Missed #46" "0,1" bitfld.long 0x04 13. "E45,Event Missed #45" "0,1" bitfld.long 0x04 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x04 11. "E43,Event Missed #43" "0,1" bitfld.long 0x04 10. "E42,Event Missed #42" "0,1" bitfld.long 0x04 9. "E41,Event Missed #41" "0,1" bitfld.long 0x04 8. "E40,Event Missed #40" "0,1" bitfld.long 0x04 7. "E39,Event Missed #39" "0,1" newline bitfld.long 0x04 6. "E38,Event Missed #38" "0,1" bitfld.long 0x04 5. "E37,Event Missed #37" "0,1" bitfld.long 0x04 4. "E36,Event Missed #36" "0,1" bitfld.long 0x04 3. "E35,Event Missed #35" "0,1" bitfld.long 0x04 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x04 1. "E33,Event Missed #33" "0,1" bitfld.long 0x04 0. "E32,Event Missed #32" "0,1" line.long 0x08 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1" bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1" bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1" newline bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1" bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1" bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1" bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1" bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1" newline bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1" bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1" bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1" bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1" bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1" line.long 0x0C "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1" bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1" bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1" newline bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1" bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1" bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1" bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1" bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1" newline bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1" bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1" bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1" bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1" bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1" newline bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1" bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1" bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1" line.long 0x10 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced" bitfld.long 0x10 7. "E7,Event Missed #7" "0,1" bitfld.long 0x10 6. "E6,Event Missed #6" "0,1" bitfld.long 0x10 5. "E5,Event Missed #5" "0,1" bitfld.long 0x10 4. "E4,Event Missed #4" "0,1" bitfld.long 0x10 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x10 2. "E2,Event Missed #2" "0,1" bitfld.long 0x10 1. "E1,Event Missed #1" "0,1" bitfld.long 0x10 0. "E0,Event Missed #0" "0,1" line.long 0x14 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared" bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1" line.long 0x18 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error" "TCERR_0,TCERR_1" bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7" "QTHRXCD7_0,QTHRXCD7_1" bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6" "QTHRXCD6_0,QTHRXCD6_1" bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5" "QTHRXCD5_0,QTHRXCD5_1" bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4" "QTHRXCD4_0,QTHRXCD4_1" newline bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3" "QTHRXCD3_0,QTHRXCD3_1" bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2" "QTHRXCD2_0,QTHRXCD2_1" bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1" "QTHRXCD1_0,QTHRXCD1_1" bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0" "QTHRXCD0_0,QTHRXCD0_1" line.long 0x1C "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x1C 16. "TCERR,Clear Error forEDMA_TPCC_CCERR[16] TR" "0,1" bitfld.long 0x1C 7. "QTHRXCD7,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7 - Write 0x0 have no affect" "0,1" bitfld.long 0x1C 6. "QTHRXCD6,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6 - Write 0x0 have no affect" "0,1" bitfld.long 0x1C 5. "QTHRXCD5,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5 - Write 0x0 have no affect" "0,1" bitfld.long 0x1C 4. "QTHRXCD4,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4: - Write 0x0 have no affect" "0,1" newline bitfld.long 0x1C 3. "QTHRXCD3,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3 - Write 0x1 to clear the values of QSTAT3.WM QSTAT3.THRXCD [3] QTHRXCD3" "0,1" bitfld.long 0x1C 2. "QTHRXCD2,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2 - Write 0x0 have no affect" "0,1" bitfld.long 0x1C 1. "QTHRXCD1,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1 - Write 0x1 to clear the values of QSTAT1.WM QSTAT1.THRXCD [1] QTHRXCD1" "0,1" bitfld.long 0x1C 0. "QTHRXCD0,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0 - Write 0x0 have no affect" "0,1" line.long 0x20 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x20 1. "SET,Error Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" group.long 0x620++0x07 line.long 0x00 "EDMA_TPCC_QWMTHRA,Queue Threshold A. for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn" bitfld.long 0x00 24.--28. "Q3,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "Q2,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "EDMA_TPCC_QWMTHRB,Queue Threshold B. for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn" bitfld.long 0x04 24.--28. "Q7,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "Q6,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "Q5,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. "Q4,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x640++0x03 line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active" "QUEACTV7_0,QUEACTV7_1" bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active" "QUEACTV6_0,QUEACTV6_1" bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active" "QUEACTV5_0,QUEACTV5_1" bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active" "QUEACTV4_0,QUEACTV4_1" bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active" "QUEACTV3_0,QUEACTV3_1" newline bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "QUEACTV2_0,QUEACTV2_1" bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active" "QUEACTV1_0,QUEACTV1_1" bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active" "QUEACTV0_0,QUEACTV0_1" bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "COMPACTV_0,COMPACTV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,COMPACTV_63" bitfld.long 0x00 4. "ACTV,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals" "ACTV_0,ACTV_1" newline bitfld.long 0x00 2. "TRACTV,Transfer Request Active TRACTV =" "TRACTV_0,TRACTV_1" bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active" "QEVTACTV_0,QEVTACTV_1" bitfld.long 0x00 0. "EVTACTV,DMA Event Active" "EVTACTV_0,EVTACTV_1" group.long 0x700++0x0B line.long 0x00 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x00 31. "EN,AET Enable" "EN_0,EN_1" bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6. "TYPE,AET Event Type" "TYPE_0,TYPE_1" bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x04 0. "STAT,AET Status" "STAT_0,STAT_1" line.long 0x08 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x08 0. "CLR,AET Clear command - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x800++0x0F line.long 0x00 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" line.long 0x04 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x04 9.--12. "FID,Faulted ID: FID register contains valid info if any of the MP error bits (UXE UWE URE SXE SWE SRE) are non-zero (i.e. if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5. "SRE,Supervisor Read Error" "SRE_0,SRE_1" bitfld.long 0x04 4. "SWE,Supervisor Write Error" "SWE_0,SWE_1" bitfld.long 0x04 3. "SXE,Supervisor Execute Error" "SXE_0,SXE_1" bitfld.long 0x04 2. "URE,User Read Error" "URE_0,URE_1" newline bitfld.long 0x04 1. "UWE,User Write Error" "UWE_0,UWE_1" bitfld.long 0x04 0. "UXE,User Execute Error" "UXE_0,UXE_1" line.long 0x08 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x08 0. "MPFCLR,Fault Clear register" "MPFCLR_0_w,MPFCLR_1_w" line.long 0x0C "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0C 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x0C 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x0C 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x0C 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x0C 11. "AID1,Allowed ID" "AID1_0,AID1_1" newline bitfld.long 0x0C 10. "AID0,Allowed ID" "AID0_0,AID0_1" bitfld.long 0x0C 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x0C 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x0C 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x0C 3. "SX,Supervisor Execute permission" "SX_0,SX_1" newline bitfld.long 0x0C 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x0C 1. "UW,User Write permission" "UW_0,UW_1" bitfld.long 0x0C 0. "UX,User Execute permission" "UX_0,UX_1" rgroup.long 0x1000++0x47 line.long 0x00 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" newline bitfld.long 0x00 26. "E26,Event #26" "0,1" bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" newline bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" newline bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" newline bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" bitfld.long 0x00 7. "E7,Event #7" "0,1" newline bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x04 31. "E63,Event #63" "0,1" bitfld.long 0x04 30. "E62,Event #62" "0,1" bitfld.long 0x04 29. "E61,Event #61" "0,1" bitfld.long 0x04 28. "E60,Event #60" "0,1" bitfld.long 0x04 27. "E59,Event #59" "0,1" newline bitfld.long 0x04 26. "E58,Event #58" "0,1" bitfld.long 0x04 25. "E57,Event #57" "0,1" bitfld.long 0x04 24. "E56,Event #56" "0,1" bitfld.long 0x04 23. "E55,Event #55" "0,1" bitfld.long 0x04 22. "E54,Event #54" "0,1" newline bitfld.long 0x04 21. "E53,Event #53" "0,1" bitfld.long 0x04 20. "E52,Event #52" "0,1" bitfld.long 0x04 19. "E51,Event #51" "0,1" bitfld.long 0x04 18. "E50,Event #50" "0,1" bitfld.long 0x04 17. "E49,Event #49" "0,1" newline bitfld.long 0x04 16. "E48,Event #48" "0,1" bitfld.long 0x04 15. "E47,Event #47" "0,1" bitfld.long 0x04 14. "E46,Event #46" "0,1" bitfld.long 0x04 13. "E45,Event #45" "0,1" bitfld.long 0x04 12. "E44,Event #44" "0,1" newline bitfld.long 0x04 11. "E43,Event #43" "0,1" bitfld.long 0x04 10. "E42,Event #42" "0,1" bitfld.long 0x04 9. "E41,Event #41" "0,1" bitfld.long 0x04 8. "E40,Event #40" "0,1" bitfld.long 0x04 7. "E39,Event #39" "0,1" newline bitfld.long 0x04 6. "E38,Event #38" "0,1" bitfld.long 0x04 5. "E37,Event #37" "0,1" bitfld.long 0x04 4. "E36,Event #36" "0,1" bitfld.long 0x04 3. "E35,Event #35" "0,1" bitfld.long 0x04 2. "E34,Event #34" "0,1" newline bitfld.long 0x04 1. "E33,Event #33" "0,1" bitfld.long 0x04 0. "E32,Event #32" "0,1" line.long 0x08 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 31. "E31,Event #31" "0,1" bitfld.long 0x08 30. "E30,Event #30" "0,1" bitfld.long 0x08 29. "E29,Event #29" "0,1" bitfld.long 0x08 28. "E28,Event #28" "0,1" bitfld.long 0x08 27. "E27,Event #27" "0,1" newline bitfld.long 0x08 26. "E26,Event #26" "0,1" bitfld.long 0x08 25. "E25,Event #25" "0,1" bitfld.long 0x08 24. "E24,Event #24" "0,1" bitfld.long 0x08 23. "E23,Event #23" "0,1" bitfld.long 0x08 22. "E22,Event #22" "0,1" newline bitfld.long 0x08 21. "E21,Event #21" "0,1" bitfld.long 0x08 20. "E20,Event #20" "0,1" bitfld.long 0x08 19. "E19,Event #19" "0,1" bitfld.long 0x08 18. "E18,Event #18" "0,1" bitfld.long 0x08 17. "E17,Event #17" "0,1" newline bitfld.long 0x08 16. "E16,Event #16" "0,1" bitfld.long 0x08 15. "E15,Event #15" "0,1" bitfld.long 0x08 14. "E14,Event #14" "0,1" bitfld.long 0x08 13. "E13,Event #13" "0,1" bitfld.long 0x08 12. "E12,Event #12" "0,1" newline bitfld.long 0x08 11. "E11,Event #11" "0,1" bitfld.long 0x08 10. "E10,Event #10" "0,1" bitfld.long 0x08 9. "E9,Event #9" "0,1" bitfld.long 0x08 8. "E8,Event #8" "0,1" bitfld.long 0x08 7. "E7,Event #7" "0,1" newline bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" bitfld.long 0x08 2. "E2,Event #2" "0,1" newline bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x0C 31. "E63,Event #63" "0,1" bitfld.long 0x0C 30. "E62,Event #62" "0,1" bitfld.long 0x0C 29. "E61,Event #61" "0,1" bitfld.long 0x0C 28. "E60,Event #60" "0,1" bitfld.long 0x0C 27. "E59,Event #59" "0,1" newline bitfld.long 0x0C 26. "E58,Event #58" "0,1" bitfld.long 0x0C 25. "E57,Event #57" "0,1" bitfld.long 0x0C 24. "E56,Event #56" "0,1" bitfld.long 0x0C 23. "E55,Event #55" "0,1" bitfld.long 0x0C 22. "E54,Event #54" "0,1" newline bitfld.long 0x0C 21. "E53,Event #53" "0,1" bitfld.long 0x0C 20. "E52,Event #52" "0,1" bitfld.long 0x0C 19. "E51,Event #51" "0,1" bitfld.long 0x0C 18. "E50,Event #50" "0,1" bitfld.long 0x0C 17. "E49,Event #49" "0,1" newline bitfld.long 0x0C 16. "E48,Event #48" "0,1" bitfld.long 0x0C 15. "E47,Event #47" "0,1" bitfld.long 0x0C 14. "E46,Event #46" "0,1" bitfld.long 0x0C 13. "E45,Event #45" "0,1" bitfld.long 0x0C 12. "E44,Event #44" "0,1" newline bitfld.long 0x0C 11. "E43,Event #43" "0,1" bitfld.long 0x0C 10. "E42,Event #42" "0,1" bitfld.long 0x0C 9. "E41,Event #41" "0,1" bitfld.long 0x0C 8. "E40,Event #40" "0,1" bitfld.long 0x0C 7. "E39,Event #39" "0,1" newline bitfld.long 0x0C 6. "E38,Event #38" "0,1" bitfld.long 0x0C 5. "E37,Event #37" "0,1" bitfld.long 0x0C 4. "E36,Event #36" "0,1" bitfld.long 0x0C 3. "E35,Event #35" "0,1" bitfld.long 0x0C 2. "E34,Event #34" "0,1" newline bitfld.long 0x0C 1. "E33,Event #33" "0,1" bitfld.long 0x0C 0. "E32,Event #32" "0,1" line.long 0x10 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x10 31. "E31,Event #31" "0,1" bitfld.long 0x10 30. "E30,Event #30" "0,1" bitfld.long 0x10 29. "E29,Event #29" "0,1" bitfld.long 0x10 28. "E28,Event #28" "0,1" bitfld.long 0x10 27. "E27,Event #27" "0,1" newline bitfld.long 0x10 26. "E26,Event #26" "0,1" bitfld.long 0x10 25. "E25,Event #25" "0,1" bitfld.long 0x10 24. "E24,Event #24" "0,1" bitfld.long 0x10 23. "E23,Event #23" "0,1" bitfld.long 0x10 22. "E22,Event #22" "0,1" newline bitfld.long 0x10 21. "E21,Event #21" "0,1" bitfld.long 0x10 20. "E20,Event #20" "0,1" bitfld.long 0x10 19. "E19,Event #19" "0,1" bitfld.long 0x10 18. "E18,Event #18" "0,1" bitfld.long 0x10 17. "E17,Event #17" "0,1" newline bitfld.long 0x10 16. "E16,Event #16" "0,1" bitfld.long 0x10 15. "E15,Event #15" "0,1" bitfld.long 0x10 14. "E14,Event #14" "0,1" bitfld.long 0x10 13. "E13,Event #13" "0,1" bitfld.long 0x10 12. "E12,Event #12" "0,1" newline bitfld.long 0x10 11. "E11,Event #11" "0,1" bitfld.long 0x10 10. "E10,Event #10" "0,1" bitfld.long 0x10 9. "E9,Event #9" "0,1" bitfld.long 0x10 8. "E8,Event #8" "0,1" bitfld.long 0x10 7. "E7,Event #7" "0,1" newline bitfld.long 0x10 6. "E6,Event #6" "0,1" bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" bitfld.long 0x10 3. "E3,Event #3" "0,1" bitfld.long 0x10 2. "E2,Event #2" "0,1" newline bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x14 31. "E63,Event #63" "0,1" bitfld.long 0x14 30. "E62,Event #62" "0,1" bitfld.long 0x14 29. "E61,Event #61" "0,1" bitfld.long 0x14 28. "E60,Event #60" "0,1" bitfld.long 0x14 27. "E59,Event #59" "0,1" newline bitfld.long 0x14 26. "E58,Event #58" "0,1" bitfld.long 0x14 25. "E57,Event #57" "0,1" bitfld.long 0x14 24. "E56,Event #56" "0,1" bitfld.long 0x14 23. "E55,Event #55" "0,1" bitfld.long 0x14 22. "E54,Event #54" "0,1" newline bitfld.long 0x14 21. "E53,Event #53" "0,1" bitfld.long 0x14 20. "E52,Event #52" "0,1" bitfld.long 0x14 19. "E51,Event #51" "0,1" bitfld.long 0x14 18. "E50,Event #50" "0,1" bitfld.long 0x14 17. "E49,Event #49" "0,1" newline bitfld.long 0x14 16. "E48,Event #48" "0,1" bitfld.long 0x14 15. "E47,Event #47" "0,1" bitfld.long 0x14 14. "E46,Event #46" "0,1" bitfld.long 0x14 13. "E45,Event #45" "0,1" bitfld.long 0x14 12. "E44,Event #44" "0,1" newline bitfld.long 0x14 11. "E43,Event #43" "0,1" bitfld.long 0x14 10. "E42,Event #42" "0,1" bitfld.long 0x14 9. "E41,Event #41" "0,1" bitfld.long 0x14 8. "E40,Event #40" "0,1" bitfld.long 0x14 7. "E39,Event #39" "0,1" newline bitfld.long 0x14 6. "E38,Event #38" "0,1" bitfld.long 0x14 5. "E37,Event #37" "0,1" bitfld.long 0x14 4. "E36,Event #36" "0,1" bitfld.long 0x14 3. "E35,Event #35" "0,1" bitfld.long 0x14 2. "E34,Event #34" "0,1" newline bitfld.long 0x14 1. "E33,Event #33" "0,1" bitfld.long 0x14 0. "E32,Event #32" "0,1" line.long 0x18 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x18 31. "E31,Event #31" "0,1" bitfld.long 0x18 30. "E30,Event #30" "0,1" bitfld.long 0x18 29. "E29,Event #29" "0,1" bitfld.long 0x18 28. "E28,Event #28" "0,1" bitfld.long 0x18 27. "E27,Event #27" "0,1" newline bitfld.long 0x18 26. "E26,Event #26" "0,1" bitfld.long 0x18 25. "E25,Event #25" "0,1" bitfld.long 0x18 24. "E24,Event #24" "0,1" bitfld.long 0x18 23. "E23,Event #23" "0,1" bitfld.long 0x18 22. "E22,Event #22" "0,1" newline bitfld.long 0x18 21. "E21,Event #21" "0,1" bitfld.long 0x18 20. "E20,Event #20" "0,1" bitfld.long 0x18 19. "E19,Event #19" "0,1" bitfld.long 0x18 18. "E18,Event #18" "0,1" bitfld.long 0x18 17. "E17,Event #17" "0,1" newline bitfld.long 0x18 16. "E16,Event #16" "0,1" bitfld.long 0x18 15. "E15,Event #15" "0,1" bitfld.long 0x18 14. "E14,Event #14" "0,1" bitfld.long 0x18 13. "E13,Event #13" "0,1" bitfld.long 0x18 12. "E12,Event #12" "0,1" newline bitfld.long 0x18 11. "E11,Event #11" "0,1" bitfld.long 0x18 10. "E10,Event #10" "0,1" bitfld.long 0x18 9. "E9,Event #9" "0,1" bitfld.long 0x18 8. "E8,Event #8" "0,1" bitfld.long 0x18 7. "E7,Event #7" "0,1" newline bitfld.long 0x18 6. "E6,Event #6" "0,1" bitfld.long 0x18 5. "E5,Event #5" "0,1" bitfld.long 0x18 4. "E4,Event #4" "0,1" bitfld.long 0x18 3. "E3,Event #3" "0,1" bitfld.long 0x18 2. "E2,Event #2" "0,1" newline bitfld.long 0x18 1. "E1,Event #1" "0,1" bitfld.long 0x18 0. "E0,Event #0" "0,1" line.long 0x1C "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x1C 31. "E63,Event #63" "0,1" bitfld.long 0x1C 30. "E62,Event #62" "0,1" bitfld.long 0x1C 29. "E61,Event #61" "0,1" bitfld.long 0x1C 28. "E60,Event #60" "0,1" bitfld.long 0x1C 27. "E59,Event #59" "0,1" newline bitfld.long 0x1C 26. "E58,Event #58" "0,1" bitfld.long 0x1C 25. "E57,Event #57" "0,1" bitfld.long 0x1C 24. "E56,Event #56" "0,1" bitfld.long 0x1C 23. "E55,Event #55" "0,1" bitfld.long 0x1C 22. "E54,Event #54" "0,1" newline bitfld.long 0x1C 21. "E53,Event #53" "0,1" bitfld.long 0x1C 20. "E52,Event #52" "0,1" bitfld.long 0x1C 19. "E51,Event #51" "0,1" bitfld.long 0x1C 18. "E50,Event #50" "0,1" bitfld.long 0x1C 17. "E49,Event #49" "0,1" newline bitfld.long 0x1C 16. "E48,Event #48" "0,1" bitfld.long 0x1C 15. "E47,Event #47" "0,1" bitfld.long 0x1C 14. "E46,Event #46" "0,1" bitfld.long 0x1C 13. "E45,Event #45" "0,1" bitfld.long 0x1C 12. "E44,Event #44" "0,1" newline bitfld.long 0x1C 11. "E43,Event #43" "0,1" bitfld.long 0x1C 10. "E42,Event #42" "0,1" bitfld.long 0x1C 9. "E41,Event #41" "0,1" bitfld.long 0x1C 8. "E40,Event #40" "0,1" bitfld.long 0x1C 7. "E39,Event #39" "0,1" newline bitfld.long 0x1C 6. "E38,Event #38" "0,1" bitfld.long 0x1C 5. "E37,Event #37" "0,1" bitfld.long 0x1C 4. "E36,Event #36" "0,1" bitfld.long 0x1C 3. "E35,Event #35" "0,1" bitfld.long 0x1C 2. "E34,Event #34" "0,1" newline bitfld.long 0x1C 1. "E33,Event #33" "0,1" bitfld.long 0x1C 0. "E32,Event #32" "0,1" line.long 0x20 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events" bitfld.long 0x20 31. "E31,Event #31" "0,1" bitfld.long 0x20 30. "E30,Event #30" "0,1" bitfld.long 0x20 29. "E29,Event #29" "0,1" bitfld.long 0x20 28. "E28,Event #28" "0,1" bitfld.long 0x20 27. "E27,Event #27" "0,1" newline bitfld.long 0x20 26. "E26,Event #26" "0,1" bitfld.long 0x20 25. "E25,Event #25" "0,1" bitfld.long 0x20 24. "E24,Event #24" "0,1" bitfld.long 0x20 23. "E23,Event #23" "0,1" bitfld.long 0x20 22. "E22,Event #22" "0,1" newline bitfld.long 0x20 21. "E21,Event #21" "0,1" bitfld.long 0x20 20. "E20,Event #20" "0,1" bitfld.long 0x20 19. "E19,Event #19" "0,1" bitfld.long 0x20 18. "E18,Event #18" "0,1" bitfld.long 0x20 17. "E17,Event #17" "0,1" newline bitfld.long 0x20 16. "E16,Event #16" "0,1" bitfld.long 0x20 15. "E15,Event #15" "0,1" bitfld.long 0x20 14. "E14,Event #14" "0,1" bitfld.long 0x20 13. "E13,Event #13" "0,1" bitfld.long 0x20 12. "E12,Event #12" "0,1" newline bitfld.long 0x20 11. "E11,Event #11" "0,1" bitfld.long 0x20 10. "E10,Event #10" "0,1" bitfld.long 0x20 9. "E9,Event #9" "0,1" bitfld.long 0x20 8. "E8,Event #8" "0,1" bitfld.long 0x20 7. "E7,Event #7" "0,1" newline bitfld.long 0x20 6. "E6,Event #6" "0,1" bitfld.long 0x20 5. "E5,Event #5" "0,1" bitfld.long 0x20 4. "E4,Event #4" "0,1" bitfld.long 0x20 3. "E3,Event #3" "0,1" bitfld.long 0x20 2. "E2,Event #2" "0,1" newline bitfld.long 0x20 1. "E1,Event #1" "0,1" bitfld.long 0x20 0. "E0,Event #0" "0,1" line.long 0x24 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events" bitfld.long 0x24 31. "E63,Event #63" "0,1" bitfld.long 0x24 30. "E62,Event #62" "0,1" bitfld.long 0x24 29. "E61,Event #61" "0,1" bitfld.long 0x24 28. "E60,Event #60" "0,1" bitfld.long 0x24 27. "E59,Event #59" "0,1" newline bitfld.long 0x24 26. "E58,Event #58" "0,1" bitfld.long 0x24 25. "E57,Event #57" "0,1" bitfld.long 0x24 24. "E56,Event #56" "0,1" bitfld.long 0x24 23. "E55,Event #55" "0,1" bitfld.long 0x24 22. "E54,Event #54" "0,1" newline bitfld.long 0x24 21. "E53,Event #53" "0,1" bitfld.long 0x24 20. "E52,Event #52" "0,1" bitfld.long 0x24 19. "E51,Event #51" "0,1" bitfld.long 0x24 18. "E50,Event #50" "0,1" bitfld.long 0x24 17. "E49,Event #49" "0,1" newline bitfld.long 0x24 16. "E48,Event #48" "0,1" bitfld.long 0x24 15. "E47,Event #47" "0,1" bitfld.long 0x24 14. "E46,Event #46" "0,1" bitfld.long 0x24 13. "E45,Event #45" "0,1" bitfld.long 0x24 12. "E44,Event #44" "0,1" newline bitfld.long 0x24 11. "E43,Event #43" "0,1" bitfld.long 0x24 10. "E42,Event #42" "0,1" bitfld.long 0x24 9. "E41,Event #41" "0,1" bitfld.long 0x24 8. "E40,Event #40" "0,1" bitfld.long 0x24 7. "E39,Event #39" "0,1" newline bitfld.long 0x24 6. "E38,Event #38" "0,1" bitfld.long 0x24 5. "E37,Event #37" "0,1" bitfld.long 0x24 4. "E36,Event #36" "0,1" bitfld.long 0x24 3. "E35,Event #35" "0,1" bitfld.long 0x24 2. "E34,Event #34" "0,1" newline bitfld.long 0x24 1. "E33,Event #33" "0,1" bitfld.long 0x24 0. "E32,Event #32" "0,1" line.long 0x28 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x28 31. "E31,Event #31" "0,1" bitfld.long 0x28 30. "E30,Event #30" "0,1" bitfld.long 0x28 29. "E29,Event #29" "0,1" bitfld.long 0x28 28. "E28,Event #28" "0,1" bitfld.long 0x28 27. "E27,Event #27" "0,1" newline bitfld.long 0x28 26. "E26,Event #26" "0,1" bitfld.long 0x28 25. "E25,Event #25" "0,1" bitfld.long 0x28 24. "E24,Event #24" "0,1" bitfld.long 0x28 23. "E23,Event #23" "0,1" bitfld.long 0x28 22. "E22,Event #22" "0,1" newline bitfld.long 0x28 21. "E21,Event #21" "0,1" bitfld.long 0x28 20. "E20,Event #20" "0,1" bitfld.long 0x28 19. "E19,Event #19" "0,1" bitfld.long 0x28 18. "E18,Event #18" "0,1" bitfld.long 0x28 17. "E17,Event #17" "0,1" newline bitfld.long 0x28 16. "E16,Event #16" "0,1" bitfld.long 0x28 15. "E15,Event #15" "0,1" bitfld.long 0x28 14. "E14,Event #14" "0,1" bitfld.long 0x28 13. "E13,Event #13" "0,1" bitfld.long 0x28 12. "E12,Event #12" "0,1" newline bitfld.long 0x28 11. "E11,Event #11" "0,1" bitfld.long 0x28 10. "E10,Event #10" "0,1" bitfld.long 0x28 9. "E9,Event #9" "0,1" bitfld.long 0x28 8. "E8,Event #8" "0,1" bitfld.long 0x28 7. "E7,Event #7" "0,1" newline bitfld.long 0x28 6. "E6,Event #6" "0,1" bitfld.long 0x28 5. "E5,Event #5" "0,1" bitfld.long 0x28 4. "E4,Event #4" "0,1" bitfld.long 0x28 3. "E3,Event #3" "0,1" bitfld.long 0x28 2. "E2,Event #2" "0,1" newline bitfld.long 0x28 1. "E1,Event #1" "0,1" bitfld.long 0x28 0. "E0,Event #0" "0,1" line.long 0x2C "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared" bitfld.long 0x2C 31. "E63,Event #63" "0,1" bitfld.long 0x2C 30. "E62,Event #62" "0,1" bitfld.long 0x2C 29. "E61,Event #61" "0,1" bitfld.long 0x2C 28. "E60,Event #60" "0,1" bitfld.long 0x2C 27. "E59,Event #59" "0,1" newline bitfld.long 0x2C 26. "E58,Event #58" "0,1" bitfld.long 0x2C 25. "E57,Event #57" "0,1" bitfld.long 0x2C 24. "E56,Event #56" "0,1" bitfld.long 0x2C 23. "E55,Event #55" "0,1" bitfld.long 0x2C 22. "E54,Event #54" "0,1" newline bitfld.long 0x2C 21. "E53,Event #53" "0,1" bitfld.long 0x2C 20. "E52,Event #52" "0,1" bitfld.long 0x2C 19. "E51,Event #51" "0,1" bitfld.long 0x2C 18. "E50,Event #50" "0,1" bitfld.long 0x2C 17. "E49,Event #49" "0,1" newline bitfld.long 0x2C 16. "E48,Event #48" "0,1" bitfld.long 0x2C 15. "E47,Event #47" "0,1" bitfld.long 0x2C 14. "E46,Event #46" "0,1" bitfld.long 0x2C 13. "E45,Event #45" "0,1" bitfld.long 0x2C 12. "E44,Event #44" "0,1" newline bitfld.long 0x2C 11. "E43,Event #43" "0,1" bitfld.long 0x2C 10. "E42,Event #42" "0,1" bitfld.long 0x2C 9. "E41,Event #41" "0,1" bitfld.long 0x2C 8. "E40,Event #40" "0,1" bitfld.long 0x2C 7. "E39,Event #39" "0,1" newline bitfld.long 0x2C 6. "E38,Event #38" "0,1" bitfld.long 0x2C 5. "E37,Event #37" "0,1" bitfld.long 0x2C 4. "E36,Event #36" "0,1" bitfld.long 0x2C 3. "E35,Event #35" "0,1" bitfld.long 0x2C 2. "E34,Event #34" "0,1" newline bitfld.long 0x2C 1. "E33,Event #33" "0,1" bitfld.long 0x2C 0. "E32,Event #32" "0,1" line.long 0x30 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x30 31. "E31,Event #31" "0,1" bitfld.long 0x30 30. "E30,Event #30" "0,1" bitfld.long 0x30 29. "E29,Event #29" "0,1" bitfld.long 0x30 28. "E28,Event #28" "0,1" bitfld.long 0x30 27. "E27,Event #27" "0,1" newline bitfld.long 0x30 26. "E26,Event #26" "0,1" bitfld.long 0x30 25. "E25,Event #25" "0,1" bitfld.long 0x30 24. "E24,Event #24" "0,1" bitfld.long 0x30 23. "E23,Event #23" "0,1" bitfld.long 0x30 22. "E22,Event #22" "0,1" newline bitfld.long 0x30 21. "E21,Event #21" "0,1" bitfld.long 0x30 20. "E20,Event #20" "0,1" bitfld.long 0x30 19. "E19,Event #19" "0,1" bitfld.long 0x30 18. "E18,Event #18" "0,1" bitfld.long 0x30 17. "E17,Event #17" "0,1" newline bitfld.long 0x30 16. "E16,Event #16" "0,1" bitfld.long 0x30 15. "E15,Event #15" "0,1" bitfld.long 0x30 14. "E14,Event #14" "0,1" bitfld.long 0x30 13. "E13,Event #13" "0,1" bitfld.long 0x30 12. "E12,Event #12" "0,1" newline bitfld.long 0x30 11. "E11,Event #11" "0,1" bitfld.long 0x30 10. "E10,Event #10" "0,1" bitfld.long 0x30 9. "E9,Event #9" "0,1" bitfld.long 0x30 8. "E8,Event #8" "0,1" bitfld.long 0x30 7. "E7,Event #7" "0,1" newline bitfld.long 0x30 6. "E6,Event #6" "0,1" bitfld.long 0x30 5. "E5,Event #5" "0,1" bitfld.long 0x30 4. "E4,Event #4" "0,1" bitfld.long 0x30 3. "E3,Event #3" "0,1" bitfld.long 0x30 2. "E2,Event #2" "0,1" newline bitfld.long 0x30 1. "E1,Event #1" "0,1" bitfld.long 0x30 0. "E0,Event #0" "0,1" line.long 0x34 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x34 31. "E63,Event #63" "0,1" bitfld.long 0x34 30. "E62,Event #62" "0,1" bitfld.long 0x34 29. "E61,Event #61" "0,1" bitfld.long 0x34 28. "E60,Event #60" "0,1" bitfld.long 0x34 27. "E59,Event #59" "0,1" newline bitfld.long 0x34 26. "E58,Event #58" "0,1" bitfld.long 0x34 25. "E57,Event #57" "0,1" bitfld.long 0x34 24. "E56,Event #56" "0,1" bitfld.long 0x34 23. "E55,Event #55" "0,1" bitfld.long 0x34 22. "E54,Event #54" "0,1" newline bitfld.long 0x34 21. "E53,Event #53" "0,1" bitfld.long 0x34 20. "E52,Event #52" "0,1" bitfld.long 0x34 19. "E51,Event #51" "0,1" bitfld.long 0x34 18. "E50,Event #50" "0,1" bitfld.long 0x34 17. "E49,Event #49" "0,1" newline bitfld.long 0x34 16. "E48,Event #48" "0,1" bitfld.long 0x34 15. "E47,Event #47" "0,1" bitfld.long 0x34 14. "E46,Event #46" "0,1" bitfld.long 0x34 13. "E45,Event #45" "0,1" bitfld.long 0x34 12. "E44,Event #44" "0,1" newline bitfld.long 0x34 11. "E43,Event #43" "0,1" bitfld.long 0x34 10. "E42,Event #42" "0,1" bitfld.long 0x34 9. "E41,Event #41" "0,1" bitfld.long 0x34 8. "E40,Event #40" "0,1" bitfld.long 0x34 7. "E39,Event #39" "0,1" newline bitfld.long 0x34 6. "E38,Event #38" "0,1" bitfld.long 0x34 5. "E37,Event #37" "0,1" bitfld.long 0x34 4. "E36,Event #36" "0,1" bitfld.long 0x34 3. "E35,Event #35" "0,1" bitfld.long 0x34 2. "E34,Event #34" "0,1" newline bitfld.long 0x34 1. "E33,Event #33" "0,1" bitfld.long 0x34 0. "E32,Event #32" "0,1" line.long 0x38 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x38 31. "E31,Event #31" "0,1" bitfld.long 0x38 30. "E30,Event #30" "0,1" bitfld.long 0x38 29. "E29,Event #29" "0,1" bitfld.long 0x38 28. "E28,Event #28" "0,1" bitfld.long 0x38 27. "E27,Event #27" "0,1" newline bitfld.long 0x38 26. "E26,Event #26" "0,1" bitfld.long 0x38 25. "E25,Event #25" "0,1" bitfld.long 0x38 24. "E24,Event #24" "0,1" bitfld.long 0x38 23. "E23,Event #23" "0,1" bitfld.long 0x38 22. "E22,Event #22" "0,1" newline bitfld.long 0x38 21. "E21,Event #21" "0,1" bitfld.long 0x38 20. "E20,Event #20" "0,1" bitfld.long 0x38 19. "E19,Event #19" "0,1" bitfld.long 0x38 18. "E18,Event #18" "0,1" bitfld.long 0x38 17. "E17,Event #17" "0,1" newline bitfld.long 0x38 16. "E16,Event #16" "0,1" bitfld.long 0x38 15. "E15,Event #15" "0,1" bitfld.long 0x38 14. "E14,Event #14" "0,1" bitfld.long 0x38 13. "E13,Event #13" "0,1" bitfld.long 0x38 12. "E12,Event #12" "0,1" newline bitfld.long 0x38 11. "E11,Event #11" "0,1" bitfld.long 0x38 10. "E10,Event #10" "0,1" bitfld.long 0x38 9. "E9,Event #9" "0,1" bitfld.long 0x38 8. "E8,Event #8" "0,1" bitfld.long 0x38 7. "E7,Event #7" "0,1" newline bitfld.long 0x38 6. "E6,Event #6" "0,1" bitfld.long 0x38 5. "E5,Event #5" "0,1" bitfld.long 0x38 4. "E4,Event #4" "0,1" bitfld.long 0x38 3. "E3,Event #3" "0,1" bitfld.long 0x38 2. "E2,Event #2" "0,1" newline bitfld.long 0x38 1. "E1,Event #1" "0,1" bitfld.long 0x38 0. "E0,Event #0" "0,1" line.long 0x3C "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x3C 31. "E63,Event #63" "0,1" bitfld.long 0x3C 30. "E62,Event #62" "0,1" bitfld.long 0x3C 29. "E61,Event #61" "0,1" bitfld.long 0x3C 28. "E60,Event #60" "0,1" bitfld.long 0x3C 27. "E59,Event #59" "0,1" newline bitfld.long 0x3C 26. "E58,Event #58" "0,1" bitfld.long 0x3C 25. "E57,Event #57" "0,1" bitfld.long 0x3C 24. "E56,Event #56" "0,1" bitfld.long 0x3C 23. "E55,Event #55" "0,1" bitfld.long 0x3C 22. "E54,Event #54" "0,1" newline bitfld.long 0x3C 21. "E53,Event #53" "0,1" bitfld.long 0x3C 20. "E52,Event #52" "0,1" bitfld.long 0x3C 19. "E51,Event #51" "0,1" bitfld.long 0x3C 18. "E50,Event #50" "0,1" bitfld.long 0x3C 17. "E49,Event #49" "0,1" newline bitfld.long 0x3C 16. "E48,Event #48" "0,1" bitfld.long 0x3C 15. "E47,Event #47" "0,1" bitfld.long 0x3C 14. "E46,Event #46" "0,1" bitfld.long 0x3C 13. "E45,Event #45" "0,1" bitfld.long 0x3C 12. "E44,Event #44" "0,1" newline bitfld.long 0x3C 11. "E43,Event #43" "0,1" bitfld.long 0x3C 10. "E42,Event #42" "0,1" bitfld.long 0x3C 9. "E41,Event #41" "0,1" bitfld.long 0x3C 8. "E40,Event #40" "0,1" bitfld.long 0x3C 7. "E39,Event #39" "0,1" newline bitfld.long 0x3C 6. "E38,Event #38" "0,1" bitfld.long 0x3C 5. "E37,Event #37" "0,1" bitfld.long 0x3C 4. "E36,Event #36" "0,1" bitfld.long 0x3C 3. "E35,Event #35" "0,1" bitfld.long 0x3C 2. "E34,Event #34" "0,1" newline bitfld.long 0x3C 1. "E33,Event #33" "0,1" bitfld.long 0x3C 0. "E32,Event #32" "0,1" line.long 0x40 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x40 31. "E31,Event #31" "0,1" bitfld.long 0x40 30. "E30,Event #30" "0,1" bitfld.long 0x40 29. "E29,Event #29" "0,1" bitfld.long 0x40 28. "E28,Event #28" "0,1" bitfld.long 0x40 27. "E27,Event #27" "0,1" newline bitfld.long 0x40 26. "E26,Event #26" "0,1" bitfld.long 0x40 25. "E25,Event #25" "0,1" bitfld.long 0x40 24. "E24,Event #24" "0,1" bitfld.long 0x40 23. "E23,Event #23" "0,1" bitfld.long 0x40 22. "E22,Event #22" "0,1" newline bitfld.long 0x40 21. "E21,Event #21" "0,1" bitfld.long 0x40 20. "E20,Event #20" "0,1" bitfld.long 0x40 19. "E19,Event #19" "0,1" bitfld.long 0x40 18. "E18,Event #18" "0,1" bitfld.long 0x40 17. "E17,Event #17" "0,1" newline bitfld.long 0x40 16. "E16,Event #16" "0,1" bitfld.long 0x40 15. "E15,Event #15" "0,1" bitfld.long 0x40 14. "E14,Event #14" "0,1" bitfld.long 0x40 13. "E13,Event #13" "0,1" bitfld.long 0x40 12. "E12,Event #12" "0,1" newline bitfld.long 0x40 11. "E11,Event #11" "0,1" bitfld.long 0x40 10. "E10,Event #10" "0,1" bitfld.long 0x40 9. "E9,Event #9" "0,1" bitfld.long 0x40 8. "E8,Event #8" "0,1" bitfld.long 0x40 7. "E7,Event #7" "0,1" newline bitfld.long 0x40 6. "E6,Event #6" "0,1" bitfld.long 0x40 5. "E5,Event #5" "0,1" bitfld.long 0x40 4. "E4,Event #4" "0,1" bitfld.long 0x40 3. "E3,Event #3" "0,1" bitfld.long 0x40 2. "E2,Event #2" "0,1" newline bitfld.long 0x40 1. "E1,Event #1" "0,1" bitfld.long 0x40 0. "E0,Event #0" "0,1" line.long 0x44 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x44 31. "E63,Event #63" "0,1" bitfld.long 0x44 30. "E62,Event #62" "0,1" bitfld.long 0x44 29. "E61,Event #61" "0,1" bitfld.long 0x44 28. "E60,Event #60" "0,1" bitfld.long 0x44 27. "E59,Event #59" "0,1" newline bitfld.long 0x44 26. "E58,Event #58" "0,1" bitfld.long 0x44 25. "E57,Event #57" "0,1" bitfld.long 0x44 24. "E56,Event #56" "0,1" bitfld.long 0x44 23. "E55,Event #55" "0,1" bitfld.long 0x44 22. "E54,Event #54" "0,1" newline bitfld.long 0x44 21. "E53,Event #53" "0,1" bitfld.long 0x44 20. "E52,Event #52" "0,1" bitfld.long 0x44 19. "E51,Event #51" "0,1" bitfld.long 0x44 18. "E50,Event #50" "0,1" bitfld.long 0x44 17. "E49,Event #49" "0,1" newline bitfld.long 0x44 16. "E48,Event #48" "0,1" bitfld.long 0x44 15. "E47,Event #47" "0,1" bitfld.long 0x44 14. "E46,Event #46" "0,1" bitfld.long 0x44 13. "E45,Event #45" "0,1" bitfld.long 0x44 12. "E44,Event #44" "0,1" newline bitfld.long 0x44 11. "E43,Event #43" "0,1" bitfld.long 0x44 10. "E42,Event #42" "0,1" bitfld.long 0x44 9. "E41,Event #41" "0,1" bitfld.long 0x44 8. "E40,Event #40" "0,1" bitfld.long 0x44 7. "E39,Event #39" "0,1" newline bitfld.long 0x44 6. "E38,Event #38" "0,1" bitfld.long 0x44 5. "E37,Event #37" "0,1" bitfld.long 0x44 4. "E36,Event #36" "0,1" bitfld.long 0x44 3. "E35,Event #35" "0,1" bitfld.long 0x44 2. "E34,Event #34" "0,1" newline bitfld.long 0x44 1. "E33,Event #33" "0,1" bitfld.long 0x44 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x2B line.long 0x00 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x04 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x08 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x0C "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x10 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x14 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set" bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x18 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x1C "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x20 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1" newline bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1" bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1" bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1" newline bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1" bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1" bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1" newline bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x24 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared" bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1" newline bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1" bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1" bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1" newline bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1" bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1" bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1" newline bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x28 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn)" "0,1" bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn)" "0,1" rgroup.long 0x1080++0x17 line.long 0x00 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" newline bitfld.long 0x00 2. "E2,Event #2" "0,1" bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" line.long 0x04 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x04 7. "E7,Event #7" "0,1" bitfld.long 0x04 6. "E6,Event #6" "0,1" bitfld.long 0x04 5. "E5,Event #5" "0,1" bitfld.long 0x04 4. "E4,Event #4" "0,1" bitfld.long 0x04 3. "E3,Event #3" "0,1" newline bitfld.long 0x04 2. "E2,Event #2" "0,1" bitfld.long 0x04 1. "E1,Event #1" "0,1" bitfld.long 0x04 0. "E0,Event #0" "0,1" line.long 0x08 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x08 7. "E7,Event #7" "0,1" bitfld.long 0x08 6. "E6,Event #6" "0,1" bitfld.long 0x08 5. "E5,Event #5" "0,1" bitfld.long 0x08 4. "E4,Event #4" "0,1" bitfld.long 0x08 3. "E3,Event #3" "0,1" newline bitfld.long 0x08 2. "E2,Event #2" "0,1" bitfld.long 0x08 1. "E1,Event #1" "0,1" bitfld.long 0x08 0. "E0,Event #0" "0,1" line.long 0x0C "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x0C 7. "E7,Event #7" "0,1" bitfld.long 0x0C 6. "E6,Event #6" "0,1" bitfld.long 0x0C 5. "E5,Event #5" "0,1" bitfld.long 0x0C 4. "E4,Event #4" "0,1" bitfld.long 0x0C 3. "E3,Event #3" "0,1" newline bitfld.long 0x0C 2. "E2,Event #2" "0,1" bitfld.long 0x0C 1. "E1,Event #1" "0,1" bitfld.long 0x0C 0. "E0,Event #0" "0,1" line.long 0x10 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x10 7. "E7,Event #7" "0,1" bitfld.long 0x10 6. "E6,Event #6" "0,1" bitfld.long 0x10 5. "E5,Event #5" "0,1" bitfld.long 0x10 4. "E4,Event #4" "0,1" bitfld.long 0x10 3. "E3,Event #3" "0,1" newline bitfld.long 0x10 2. "E2,Event #2" "0,1" bitfld.long 0x10 1. "E1,Event #1" "0,1" bitfld.long 0x10 0. "E0,Event #0" "0,1" line.long 0x14 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation. which does not clear the .En register)" bitfld.long 0x14 7. "E7,Event #7" "0,1" bitfld.long 0x14 6. "E6,Event #6" "0,1" bitfld.long 0x14 5. "E5,Event #5" "0,1" bitfld.long 0x14 4. "E4,Event #4" "0,1" bitfld.long 0x14 3. "E3,Event #3" "0,1" newline bitfld.long 0x14 2. "E2,Event #2" "0,1" bitfld.long 0x14 1. "E1,Event #1" "0,1" bitfld.long 0x14 0. "E0,Event #0" "0,1" repeat 16. (list 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. ) tree "DMA_Channel_$1" group.long 0x4E08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4E10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_112," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4E1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4E18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4E0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_112,Destination Address" group.long 0x4E14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4E00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_112,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_112,Source Address" tree.end repeat.end repeat 16. (list 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. ) tree "DMA_Channel_$1" group.long 0x4C88++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4C90++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_100," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4C9C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4C98++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4C8C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_100,Destination Address" group.long 0x4C94++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4C80++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_100,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_100,Source Address" tree.end repeat.end repeat 16. (list 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. ) tree "DMA_Channel_$1" group.long 0x4A08++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4A10++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_80," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x4A1C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4A18++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x4A0C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_80,Destination Address" group.long 0x4A14++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4A00++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_80,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_80,Source Address" tree.end repeat.end repeat 16. (list 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. ) tree "DMA_Channel_$1" group.long 0x4808++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4810++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_64," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x481C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4818++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x480C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_64,Destination Address" group.long 0x4814++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4800++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_64,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_64,Source Address" tree.end repeat.end repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. ) tree "DMA_Channel_$1" group.long 0x4608++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4610++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_48," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x461C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4618++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x460C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_48,Destination Address" group.long 0x4614++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4600++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_48,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_48,Source Address" tree.end repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. ) tree "DMA_Channel_$1" group.long 0x4408++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4410++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_32," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x441C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4418++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x440C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_32,Destination Address" group.long 0x4414++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4400++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_32,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_32,Source Address" tree.end repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. ) tree "DMA_Channel_$1" group.long 0x4208++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4210++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_16," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x421C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4218++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x420C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_16,Destination Address" group.long 0x4214++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4200++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_16,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_16,Source Address" tree.end repeat.end repeat 8. (list 8. 9. 10. 11. 12. 13. 14. 15. ) tree "DMA_Channel_$1" group.long 0x4148++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4150++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_10," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x415C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" group.long 0x4158++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x128++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x414C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_10,Destination Address" group.long 0x4154++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x4140++0x07 line.long 0x00 "EDMA_TPCC_OPT_n_10,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPCC_SRC_n_10,Source Address" tree.end repeat.end repeat 6. (list 2. 3. 4. 5. 6. 7. ) tree "DMA_Channel_$1" group.long 0x4048++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4050++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_2," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x405C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x241C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2418++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4058++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x108++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x248++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x404C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_2,Destination Address" group.long 0x240C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2408++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x242C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2428++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2424++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2420++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2434++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2430++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2404++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2400++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2414++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2410++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2474++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2470++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x245C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2458++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2454++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2450++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2464++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2460++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2478++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x246C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2468++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4054++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x818++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4040++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_2,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x208++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2488++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2484++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x248C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2480++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x388++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2494++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2490++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2444++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2440++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x243C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2438++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4044++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_2,Source Address" tree.end repeat.end repeat 2. (list 0. 1. ) tree "DMA_Channel_$1" group.long 0x4008++0x03 line.long 0x00 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x00 16.--31. 1. "BCNT,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT" hexmask.long.word 0x00 0.--15. 1. "ACNT,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer" group.long 0x4010++0x03 line.long 0x00 "EDMA_TPCC_BIDX_n_0," hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension" group.long 0x401C++0x03 line.long 0x00 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x00 0.--15. 1. "CCNT,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block" rgroup.long 0x201C++0x03 line.long 0x00 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0x03 line.long 0x00 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En). then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4018++0x03 line.long 0x00 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x00 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension" hexmask.long.word 0x00 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension" group.long 0x100++0x03 line.long 0x00 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for DMA Channel N" group.long 0x240++0x03 line.long 0x00 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel" bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x400C++0x03 line.long 0x00 "EDMA_TPCC_DST_n_0,Destination Address" group.long 0x200C++0x03 line.long 0x00 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2008++0x03 line.long 0x00 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x202C++0x03 line.long 0x00 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2028++0x03 line.long 0x00 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2024++0x03 line.long 0x00 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2020++0x03 line.long 0x00 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2034++0x03 line.long 0x00 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2030++0x03 line.long 0x00 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2004++0x03 line.long 0x00 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2000++0x03 line.long 0x00 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set. then the corresponding DMA channel is prioritized vs" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2014++0x03 line.long 0x00 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2010++0x03 line.long 0x00 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x2074++0x03 line.long 0x00 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2070++0x03 line.long 0x00 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x205C++0x03 line.long 0x00 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2058++0x03 line.long 0x00 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" rgroup.long 0x2054++0x03 line.long 0x00 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2050++0x03 line.long 0x00 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2064++0x03 line.long 0x00 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2060++0x03 line.long 0x00 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x2078++0x03 line.long 0x00 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x00 1. "SET,Interrupt Set - CPU writes 0x0 has no effect" "0,1" bitfld.long 0x00 0. "EVAL,Interrupt Evaluate - CPU writes 0x0 has no effect" "0,1" rgroup.long 0x206C++0x03 line.long 0x00 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x00 30. "I62,Interrupt associated with TCC #62" "0,1" bitfld.long 0x00 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x00 28. "I60,Interrupt associated with TCC #60" "0,1" bitfld.long 0x00 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x00 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x00 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x00 24. "I56,Interrupt associated with TCC #56" "0,1" bitfld.long 0x00 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x00 22. "I54,Interrupt associated with TCC #54" "0,1" bitfld.long 0x00 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x00 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x00 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x00 18. "I50,Interrupt associated with TCC #50" "0,1" bitfld.long 0x00 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x00 16. "I48,Interrupt associated with TCC #48" "0,1" bitfld.long 0x00 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x00 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x00 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x00 12. "I44,Interrupt associated with TCC #44" "0,1" bitfld.long 0x00 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x00 10. "I42,Interrupt associated with TCC #42" "0,1" bitfld.long 0x00 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x00 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x00 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x00 6. "I38,Interrupt associated with TCC #38" "0,1" bitfld.long 0x00 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x00 4. "I36,Interrupt associated with TCC #36" "0,1" bitfld.long 0x00 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x00 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x00 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x00 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x03 line.long 0x00 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected" bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1" bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1" bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1" bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1" bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1" bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1" bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1" bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1" bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1" bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1" bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1" group.long 0x4014++0x03 line.long 0x00 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x00 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred" hexmask.long.word 0x00 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry" group.long 0x810++0x03 line.long 0x00 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x00 15. "AID5,Allowed ID" "AID5_0,AID5_1" bitfld.long 0x00 14. "AID4,Allowed ID" "AID4_0,AID4_1" bitfld.long 0x00 13. "AID3,Allowed ID" "AID3_0,AID3_1" bitfld.long 0x00 12. "AID2,Allowed ID" "AID2_0,AID2_1" bitfld.long 0x00 11. "AID1,Allowed ID" "AID1_0,AID1_1" bitfld.long 0x00 10. "AID0,Allowed ID" "AID0_0,AID0_1" newline bitfld.long 0x00 9. "EXT,External Allowed ID" "EXT_0,EXT_1" bitfld.long 0x00 5. "SR,Supervisor Read permission" "SR_0,SR_1" bitfld.long 0x00 4. "SW,Supervisor Write permission" "SW_0,SW_1" bitfld.long 0x00 3. "SX,Supervisor Execute permission" "SX_0,SX_1" bitfld.long 0x00 2. "UR,User Read permission" "UR_0,UR_1" bitfld.long 0x00 1. "UW,User Write permission" "UW_0,UW_1" newline bitfld.long 0x00 0. "UX,User Execute permission" "UX_0,?" group.long 0x4000++0x03 line.long 0x00 "EDMA_TPCC_OPT_n_0,Options Parameter" rbitfld.long 0x00 31. "PRIV,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry" "PRIV_0,PRIV_1" rbitfld.long 0x00 24.--27. "PRIVID,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. "ITCCHEN,Intermediate transfer completion chaining enable" "ITCCHEN_0,ITCCHEN_1" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 21. "ITCINTEN,Intermediate transfer completion interrupt enable" "ITCINTEN_0,ITCINTEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" newline bitfld.long 0x00 19. "WIMODE,Backward compatibility mode" "WIMODE_0,WIMODE_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed" "TCCMODE_0,TCCMODE_1" bitfld.long 0x00 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STATIC,Static Entry" "STATIC_0,STATIC_1" bitfld.long 0x00 2. "SYNCDIM,Transfer Synchronization Dimension" "SYNCDIM_0,SYNCDIM_1" newline bitfld.long 0x00 1. "DAM,Destination Address Mode: Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode: Source Address Mode within an array" "SAM_0,SAM_1" group.long 0x200++0x03 line.long 0x00 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N" bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x2088++0x03 line.long 0x00 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2084++0x03 line.long 0x00 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x208C++0x03 line.long 0x00 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2080++0x03 line.long 0x00 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set. then the corresponding QDMA channel is prioritized vs" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x380++0x03 line.long 0x00 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En =" bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" group.long 0x2094++0x03 line.long 0x00 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x03 line.long 0x00 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event" bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x600++0x03 line.long 0x00 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x00 24. "THRXCD,Threshold Exceeded" "THRXCD_0,THRXCD_1" bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "WM_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,WM_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "NUMVAL_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NUMVAL_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of *entries*" "STRTPTR_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,STRTPTR_15" group.long 0x2044++0x03 line.long 0x00 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" group.long 0x2040++0x03 line.long 0x00 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E63,Event #63" "0,1" bitfld.long 0x00 30. "E62,Event #62" "0,1" bitfld.long 0x00 29. "E61,Event #61" "0,1" bitfld.long 0x00 28. "E60,Event #60" "0,1" bitfld.long 0x00 27. "E59,Event #59" "0,1" bitfld.long 0x00 26. "E58,Event #58" "0,1" newline bitfld.long 0x00 25. "E57,Event #57" "0,1" bitfld.long 0x00 24. "E56,Event #56" "0,1" bitfld.long 0x00 23. "E55,Event #55" "0,1" bitfld.long 0x00 22. "E54,Event #54" "0,1" bitfld.long 0x00 21. "E53,Event #53" "0,1" bitfld.long 0x00 20. "E52,Event #52" "0,1" newline bitfld.long 0x00 19. "E51,Event #51" "0,1" bitfld.long 0x00 18. "E50,Event #50" "0,1" bitfld.long 0x00 17. "E49,Event #49" "0,1" bitfld.long 0x00 16. "E48,Event #48" "0,1" bitfld.long 0x00 15. "E47,Event #47" "0,1" bitfld.long 0x00 14. "E46,Event #46" "0,1" newline bitfld.long 0x00 13. "E45,Event #45" "0,1" bitfld.long 0x00 12. "E44,Event #44" "0,1" bitfld.long 0x00 11. "E43,Event #43" "0,1" bitfld.long 0x00 10. "E42,Event #42" "0,1" bitfld.long 0x00 9. "E41,Event #41" "0,1" bitfld.long 0x00 8. "E40,Event #40" "0,1" newline bitfld.long 0x00 7. "E39,Event #39" "0,1" bitfld.long 0x00 6. "E38,Event #38" "0,1" bitfld.long 0x00 5. "E37,Event #37" "0,1" bitfld.long 0x00 4. "E36,Event #36" "0,1" bitfld.long 0x00 3. "E35,Event #35" "0,1" bitfld.long 0x00 2. "E34,Event #34" "0,1" newline bitfld.long 0x00 1. "E33,Event #33" "0,1" bitfld.long 0x00 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event" bitfld.long 0x00 31. "E31,Event #31" "0,1" bitfld.long 0x00 30. "E30,Event #30" "0,1" bitfld.long 0x00 29. "E29,Event #29" "0,1" bitfld.long 0x00 28. "E28,Event #28" "0,1" bitfld.long 0x00 27. "E27,Event #27" "0,1" bitfld.long 0x00 26. "E26,Event #26" "0,1" newline bitfld.long 0x00 25. "E25,Event #25" "0,1" bitfld.long 0x00 24. "E24,Event #24" "0,1" bitfld.long 0x00 23. "E23,Event #23" "0,1" bitfld.long 0x00 22. "E22,Event #22" "0,1" bitfld.long 0x00 21. "E21,Event #21" "0,1" bitfld.long 0x00 20. "E20,Event #20" "0,1" newline bitfld.long 0x00 19. "E19,Event #19" "0,1" bitfld.long 0x00 18. "E18,Event #18" "0,1" bitfld.long 0x00 17. "E17,Event #17" "0,1" bitfld.long 0x00 16. "E16,Event #16" "0,1" bitfld.long 0x00 15. "E15,Event #15" "0,1" bitfld.long 0x00 14. "E14,Event #14" "0,1" newline bitfld.long 0x00 13. "E13,Event #13" "0,1" bitfld.long 0x00 12. "E12,Event #12" "0,1" bitfld.long 0x00 11. "E11,Event #11" "0,1" bitfld.long 0x00 10. "E10,Event #10" "0,1" bitfld.long 0x00 9. "E9,Event #9" "0,1" bitfld.long 0x00 8. "E8,Event #8" "0,1" newline bitfld.long 0x00 7. "E7,Event #7" "0,1" bitfld.long 0x00 6. "E6,Event #6" "0,1" bitfld.long 0x00 5. "E5,Event #5" "0,1" bitfld.long 0x00 4. "E4,Event #4" "0,1" bitfld.long 0x00 3. "E3,Event #3" "0,1" bitfld.long 0x00 2. "E2,Event #2" "0,1" newline bitfld.long 0x00 1. "E1,Event #1" "0,1" bitfld.long 0x00 0. "E0,Event #0" "0,1" group.long 0x4004++0x03 line.long 0x00 "EDMA_TPCC_SRC_n_0,Source Address" tree.end repeat.end tree.end repeat.end tree "EDMA_TPTC0_L3_MAINInterconnect" base ad:0x43400000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" rgroup.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" rgroup.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" repeat 2. (list 0. 1. ) tree "DMA_Channel_$1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end repeat.end tree.end tree "EDMA_TPTC1_L3_MAINInterconnect" base ad:0x43500000 rgroup.long 0x00++0x07 line.long 0x00 "EDMA_TPTCn_PID,Peripheral ID Register" line.long 0x04 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x04 8.--9. "DREGDEPTH,Destination Register FIFO Depth Parameterization" "0,1,2,3" bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" rgroup.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" rgroup.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x23 line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" line.long 0x0C "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved. return 0x0 w/o AERROR" line.long 0x10 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x14 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x1C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x20 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x280++0x0B line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" line.long 0x08 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" repeat 2. (list 0. 1. ) tree "DMA_Channel_$1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end repeat.end tree.end repeat 2. (list 1. 2. )(list ad:0x42087000 ad:0x42187000 ) tree "EDMA_TPTC1_EVE$1" base $2 rgroup.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" rgroup.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x0B line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x250++0x13 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x04 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x04 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x04 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x08 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x0C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x10 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x280++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" repeat 2. (list 0. 1. ) tree "DMA_Channel_$1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end repeat.end tree.end repeat.end repeat 2. (list 1. 2. )(list ad:0x42086000 ad:0x42186000 ) tree "EDMA_TPTC0_EVE$1" base $2 rgroup.long 0x100++0x13 line.long 0x00 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of *entries*" "0,1,2,3" bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals" "ACTV_0,ACTV_1" bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "WSACTV,Write Status Active" "WSACTV_0,WSACTV_1" bitfld.long 0x00 1. "SRCACTV,Source Active State" "SRCACTV_0,SRCACTV_1" newline bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy" "PROGBUSY_0,PROGBUSY_1" line.long 0x04 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x04 1. "TRDONE,TR Done Event Status" "TRDONE_0,TRDONE_1" bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x08 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x08 1. "TRDONE,TR Done Event Enable" "TRDONE_0,TRDONE_1" bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable" "PROGEMPTY_0,PROGEMPTY_1" line.long 0x0C "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear" "TRDONE_0_w,TRDONE_1_w" bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear" "PROGEMPTY_0_w,PROGEMPTY_1_w" line.long 0x10 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x10 1. "SET,Set TPTC interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt" "EVAL_0_w,EVAL_1" rgroup.long 0x120++0x13 line.long 0x00 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x00 3. "MMRAERR,MR Address Error" "MMRAERR_0,MMRAERR_1" bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0" "0,1" bitfld.long 0x00 0. "BUSERR,Bus Error Event" "BUSERR_0,BUSERR_1" line.long 0x04 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x04 3. "MMRAERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0,MMRAERR_1" bitfld.long 0x04 2. "TRERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0,TRERR_1" bitfld.long 0x04 0. "BUSERR,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0,BUSERR_1" line.long 0x08 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x08 3. "MMRAERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "MMRAERR_0_w,MMRAERR_1_w" bitfld.long 0x08 2. "TRERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "TRERR_0_w,TRERR_1_w" bitfld.long 0x08 0. "BUSERR,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "BUSERR_0_w,BUSERR_1_w" line.long 0x0C "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0C 17. "TCCHEN,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 16. "TCINTEN,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1" bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x10 1. "SET,Set TPTC error interrupt" "SET_0_w,SET_1_w" bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1'" "EVAL_0_w,EVAL_1_w" group.long 0x140++0x03 line.long 0x00 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7" group.long 0x200++0x17 line.long 0x00 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_PSRC,Program Set Source Address" line.long 0x08 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count" line.long 0x0C "EDMA_TPTCn_PDST,Program Set Destination Address" line.long 0x10 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements)" hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements)" line.long 0x14 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x14 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x240++0x0B line.long 0x00 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" newline bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_SASRC,Source Active Set Source Address" line.long 0x08 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count: Number of bytes to be transferred in first dimension" rgroup.long 0x250++0x13 line.long 0x00 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Destination B-Idx for Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set" line.long 0x04 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x04 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x04 0.--3. "PRIVID,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x08 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set" line.long 0x0C "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" line.long 0x10 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved. return 0x0 w/o AERROR" rgroup.long 0x280++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set" line.long 0x04 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved. return 0x0 w/o AERROR" repeat 2. (list 0. 1. ) tree "DMA_Channel_$1" rgroup.long 0x310++0x03 line.long 0x00 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x00 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. "SBIDX,Dest B-Idx for Dest FIFO Register Set" rgroup.long 0x308++0x07 line.long 0x00 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x00 16.--31. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length" hexmask.long.word 0x00 0.--15. 1. "ACNT,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension" line.long 0x04 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" rgroup.long 0x314++0x03 line.long 0x00 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x00 8. "PRIV,Privilege Level" "PRIV_0,PRIV_1" bitfld.long 0x00 0.--3. "PRIVID,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x300++0x07 line.long 0x00 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable" "TCCHEN_0,TCCHEN_1" bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable" "TCINTEN_0,TCINTEN_1" bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--10. "FWID,FIFO width control Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI,Transfer Priority" "PRI_0,PRI_1,?,?,?,?,?,PRI_7" bitfld.long 0x00 1. "DAM,Destination Address Mode within an array" "DAM_0,DAM_1" bitfld.long 0x00 0. "SAM,Source Address Mode within an array" "SAM_0,SAM_1" line.long 0x04 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved. return 0x0 w/o AERROR" tree.end repeat.end tree.end repeat.end tree.end tree.open "Error_Location_Module" tree "ELM" base ad:0x48078000 rgroup.long 0x00++0x03 line.long 0x00 "ELM_REVISION,This register contains the IP revision code" group.long 0x10++0x13 line.long 0x00 "ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8. "CLOCKACTIVITYOCP,OCP clock activity when module is in IDLE mode (during wake-up mode period) - OCP_OFF" "CLOCKACTIVITYOCP_0,CLOCKACTIVITYOCP_1" bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE req/ack control) - FORCE_IDLE" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Module software reset This bit is automatically reset by hardware (during reads it always returns 0)" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOGATING,Internal OCP clock gating strategy (no module visible effect other than saving power) - OCP_FREE" "AUTOGATING_0,AUTOGATING_1" line.long 0x04 "ELM_SYSSTATUS,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective. the reset state is 0" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective the reset state is 0" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "ELM_IRQSTATUS,Interrupt status" bitfld.long 0x08 8. "PAGE_VALID,Error-location status for a full page based on the mask definition Read" "PAGE_VALID_0,PAGE_VALID_1" bitfld.long 0x08 7. "LOC_VALID_7,Error-location status for syndrome polynomial 7" "LOC_VALID_7_0,LOC_VALID_7_1" bitfld.long 0x08 6. "LOC_VALID_6,Error-location status for syndrome polynomial 6" "LOC_VALID_6_0,LOC_VALID_6_1" newline bitfld.long 0x08 5. "LOC_VALID_5,Error-location status for syndrome polynomial 5" "LOC_VALID_5_0,LOC_VALID_5_1" bitfld.long 0x08 4. "LOC_VALID_4,Error-location status for syndrome polynomial 4" "LOC_VALID_4_0,LOC_VALID_4_1" bitfld.long 0x08 3. "LOC_VALID_3,Error-location status for syndrome polynomial 3" "LOC_VALID_3_0,LOC_VALID_3_1" newline bitfld.long 0x08 2. "LOC_VALID_2,Error-location status for syndrome polynomial 2" "LOC_VALID_2_0,LOC_VALID_2_1" bitfld.long 0x08 1. "LOC_VALID_1,Error-location status for syndrome polynomial 1" "LOC_VALID_1_0,LOC_VALID_1_1" bitfld.long 0x08 0. "LOC_VALID_0,Error-location status for syndrome polynomial 0" "LOC_VALID_0_0,LOC_VALID_0_1" line.long 0x0C "ELM_IRQENABLE,Interrupt enable" bitfld.long 0x0C 8. "PAGE_MASK,Page interrupt mask bit" "PAGE_MASK_0,PAGE_MASK_1" bitfld.long 0x0C 7. "LOCATION_MASK_7,Error-location interrupt mask bit for syndrome polynomial 7" "LOCATION_MASK_7_0,LOCATION_MASK_7_1" bitfld.long 0x0C 6. "LOCATION_MASK_6,Error-location interrupt mask bit for syndrome polynomial 6" "LOCATION_MASK_6_0,LOCATION_MASK_6_1" newline bitfld.long 0x0C 5. "LOCATION_MASK_5,Error-location interrupt mask bit for syndrome polynomial 5" "LOCATION_MASK_5_0,LOCATION_MASK_5_1" bitfld.long 0x0C 4. "LOCATION_MASK_4,Error-location interrupt mask bit for syndrome polynomial 4" "LOCATION_MASK_4_0,LOCATION_MASK_4_1" bitfld.long 0x0C 3. "LOCATION_MASK_3,Error-location interrupt mask bit for syndrome polynomial 3" "LOCATION_MASK_3_0,LOCATION_MASK_3_1" newline bitfld.long 0x0C 2. "LOCATION_MASK_2,Error-location interrupt mask bit for syndrome polynomial 2" "LOCATION_MASK_2_0,LOCATION_MASK_2_1" bitfld.long 0x0C 1. "LOCATION_MASK_1,Error-location interrupt mask bit for syndrome polynomial 1" "LOCATION_MASK_1_0,LOCATION_MASK_1_1" bitfld.long 0x0C 0. "LOCATION_MASK_0,Error-location interrupt mask bit for syndrome polynomial 0" "LOCATION_MASK_0_0,LOCATION_MASK_0_1" line.long 0x10 "ELM_LOCATION_CONFIG,ECC algorithm parameters" hexmask.long.word 0x10 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error-location engine is used in number of nibbles (4-bit entities)" bitfld.long 0x10 0.--1. "ECC_BCH_LEVEL,Error correction level" "ECC_BCH_LEVEL_0,ECC_BCH_LEVEL_1,ECC_BCH_LEVEL_2,ECC_BCH_LEVEL_3" group.long 0x80++0x03 line.long 0x00 "ELM_PAGE_CTRL,Page definition" bitfld.long 0x00 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode" "SECTOR_7_0,SECTOR_7_1" bitfld.long 0x00 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode" "SECTOR_6_0,SECTOR_6_1" bitfld.long 0x00 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode" "SECTOR_5_0,SECTOR_5_1" newline bitfld.long 0x00 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode" "SECTOR_4_0,SECTOR_4_1" bitfld.long 0x00 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode" "SECTOR_3_0,SECTOR_3_1" bitfld.long 0x00 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode" "SECTOR_2_0,SECTOR_2_1" newline bitfld.long 0x00 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode" "SECTOR_1_0,SECTOR_1_1" bitfld.long 0x00 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode" "SECTOR_0_0,SECTOR_0_1" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x880++0x03 line.long 0x00 "ELM_ERROR_LOCATION_0_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x8A8++0x17 line.long 0x00 "ELM_ERROR_LOCATION_10_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_11_i_0,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_12_i_0,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_13_i_0,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_14_i_0,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_15_i_0,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x884++0x23 line.long 0x00 "ELM_ERROR_LOCATION_1_i_0,Error-location register" hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x04 "ELM_ERROR_LOCATION_2_i_0,Error-location register" hexmask.long.word 0x04 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x08 "ELM_ERROR_LOCATION_3_i_0,Error-location register" hexmask.long.word 0x08 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x0C "ELM_ERROR_LOCATION_4_i_0,Error-location register" hexmask.long.word 0x0C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x10 "ELM_ERROR_LOCATION_5_i_0,Error-location register" hexmask.long.word 0x10 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x14 "ELM_ERROR_LOCATION_6_i_0,Error-location register" hexmask.long.word 0x14 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x18 "ELM_ERROR_LOCATION_7_i_0,Error-location register" hexmask.long.word 0x18 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x1C "ELM_ERROR_LOCATION_8_i_0,Error-location register" hexmask.long.word 0x1C 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" line.long 0x20 "ELM_ERROR_LOCATION_9_i_0,Error-location register" hexmask.long.word 0x20 0.--12. 1. "ECC_ERROR_LOCATION,Error-location bit address" rgroup.long 0x800++0x03 line.long 0x00 "ELM_LOCATION_STATUS_i_0,Exit status for the syndrome polynomial processing" bitfld.long 0x00 8. "ECC_CORRECTABLE,Error-location process exit status" "0,1" bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x400++0x1B line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_i_0,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_i_0,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_i_0,Input syndrome polynomial bits 64 to 95" line.long 0x0C "ELM_SYNDROME_FRAGMENT_3_i_0,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_i_0,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_i_0,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_i_0,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "0,1" hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207" tree.end repeat.end tree.end tree.end tree.open "General_Purpose_Interface" repeat 8. (list 7. 8. 2. 3. 4. 5. 6. 1. )(list ad:0x48051000 ad:0x48053000 ad:0x48055000 ad:0x48057000 ad:0x48059000 ad:0x4805B000 ad:0x4805D000 ad:0x4AE10000 ) tree "GPIO$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "GPIO_REVISION,IP revision identifier (X.Y.R)" group.long 0x10++0x03 line.long 0x00 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x00 3.--4. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up control" "ENAWAKEUP_0,ENAWAKEUP_1" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,OCP clock gating control" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x20++0x2B line.long 0x00 "GPIO_EOI,Software end of interrupt" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1" line.long 0x04 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector (corresponding to first line of interrupt)" line.long 0x08 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector (corresponding to second line of interrupt)" line.long 0x0C "GPIO_IRQSTATUS_0,Per-event interrupt status vector (enabled) (corresponding to first line of interrupt)" line.long 0x10 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector (corresponding to second line of interrupt)" line.long 0x14 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" line.long 0x18 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" line.long 0x1C "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" line.long 0x20 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" line.long 0x24 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" line.long 0x28 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. "RESETDONE,- InProgress" "RESETDONE_0_r,RESETDONE_1_r" group.long 0x130++0x27 line.long 0x00 "GPIO_CTRL,GPIO control register" bitfld.long 0x00 1.--2. "GATINGRATIO,Clock gating ratio for event detection - N_1" "GATINGRATIO_0,GATINGRATIO_1,GATINGRATIO_2,GATINGRATIO_3" bitfld.long 0x00 0. "DISABLEMODULE,- Enabled" "DISABLEMODULE_0,DISABLEMODULE_1" line.long 0x04 "GPIO_OE,Output enable register" line.long 0x08 "GPIO_DATAIN,Data input register (with sampled input data)" line.long 0x0C "GPIO_DATAOUT,Data-output register (data to set on output pins)" line.long 0x10 "GPIO_LEVELDETECT0,Detect low-level register" line.long 0x14 "GPIO_LEVELDETECT1,Detect high-level register" line.long 0x18 "GPIO_RISINGDETECT,Detect rising edge register" line.long 0x1C "GPIO_FALLINGDETECT,Detect falling edge register" line.long 0x20 "GPIO_DEBOUNCENABLE,Debouncing enable register" line.long 0x24 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x24 0.--7. 1. "DEBOUNCETIME,8-bit values specifying the debouncing time" group.long 0x190++0x07 line.long 0x00 "GPIO_CLEARDATAOUT,Clear data-output register" line.long 0x04 "GPIO_SETDATAOUT,Set data-output register" tree.end repeat.end tree.end tree.open "General_Purpose_Memory_Controller" tree "GPMC" base ad:0x50000000 repeat 7. (list 0. 1. 2. 3. 4. 5. 6. ) tree "Channel_$1" group.long 0x240++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_0,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_0,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_0,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_0,BCH ECC result (bits 96 to 127)" group.long 0x300++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_0,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_0,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_0,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x60++0x1B line.long 0x00 "GPMC_CONFIG1_i_0,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_0,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "GPMC_CONFIG3_i_0,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "GPMC_CONFIG4_i_0,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "GPMC_CONFIG5_i_0,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "GPMC_CONFIG6_i_0,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "GPMC_CONFIG7_i_0,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x200++0x03 line.long 0x00 "GPMC_ECCj_RESULT_0,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" group.long 0x80++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_0,This register is not a true register. only an address location" group.long 0x7C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_0,This register is not a true register. only an address location" group.long 0x84++0x03 line.long 0x00 "GPMC_NAND_DATA_i_0,This register is not a true register.only an address location" tree.end repeat.end tree "Channel_7" group.long 0x2B0++0x0F line.long 0x00 "GPMC_BCH_RESULT0_i_7,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_i_7,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_i_7,BCH ECC result (bits 64 to 95)" line.long 0x0C "GPMC_BCH_RESULT3_i_7,BCH ECC result (bits 96 to 127)" group.long 0x370++0x0B line.long 0x00 "GPMC_BCH_RESULT4_i_7,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_i_7,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_i_7,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result (bits 192 to 207)" group.long 0x1B0++0x1B line.long 0x00 "GPMC_CONFIG1_i_7,The configuration register 1 sets signal control parameters per chip-select" bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "WRAPBURST_0,WRAPBURST_1" bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "READMULTIPLE_0,READMULTIPLE_1" newline bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "READTYPE_0,READTYPE_1" bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "WRITEMULTIPLE_0,WRITEMULTIPLE_1" newline bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "WRITETYPE_0,WRITETYPE_1" bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC_CLK activation time" "CLKACTIVATIONTIME_0,CLKACTIVATIONTIME_1,CLKACTIVATIONTIME_2,CLKACTIVATIONTIME_3" newline bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page (burst) length" "ATTACHEDDEVICEPAGELENGTH_0,ATTACHEDDEVICEPAGELENGTH_1,ATTACHEDDEVICEPAGELENGTH_2,ATTACHEDDEVICEPAGELENGTH_3" bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses (Reset value is input pin sampled at device reset)" "WAITREADMONITORING_0,WAITREADMONITORING_1" newline bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "WAITWRITEMONITORING_0,WAITWRITEMONITORING_1" bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "WAITMONITORINGTIME_0,WAITMONITORINGTIME_1,WAITMONITORINGTIME_2,WAITMONITORINGTIME_3" newline bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)" "WAITPINSELECT_0,WAITPINSELECT_1,?,?" bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached (Reset value is input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "DEVICESIZE_0,DEVICESIZE_1,DEVICESIZE_2,DEVICESIZE_3" newline bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "DEVICETYPE_0,DEVICETYPE_1,DEVICETYPE_2,DEVICETYPE_3" bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the address and data multiplexed protocol (Reset value is input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "MUXADDDATA_0,MUXADDDATA_1,MUXADDDATA_2,MUXADDDATA_3" newline bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor (RD/WRCYCLETIME RD/WRACCESSTIME PAGEBURSTACCESSTIME CSONTIME CSRD/WROFFTIME ADVONTIME ADVRD/WROFFTIME OEONTIME OEOFFTIME WEONTIME WEOFFTIME CYCLE2CYCLEDELAY BUSTURNAROUND TIMEOUTSTARTVALUE.." "TIMEPARAGRANULARITY_0,TIMEPARAGRANULARITY_1" bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC_FCLK clock" "GPMCFCLKDIVIDER_0,GPMCFCLKDIVIDER_1,GPMCFCLKDIVIDER_2,GPMCFCLKDIVIDER_3" line.long 0x04 "GPMC_CONFIG2_i_7,CS signal timing parameter configuration" bitfld.long 0x04 16.--20. "CSWROFFTIME,CS i deassertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS i de-assertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 7. "CSEXTRADELAY,CS i Add extra half-GPMC_FCLK cycle" "CSEXTRADELAY_0,CSEXTRADELAY_1" bitfld.long 0x04 0.--3. "CSONTIME,CS i assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "GPMC_CONFIG3_i_7,nADV signal timing parameter configuration" bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,nADV deassertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 16.--20. "ADVWROFFTIME,nADV deassertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 8.--12. "ADVRDOFFTIME,nADV deassertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x08 7. "ADVEXTRADELAY,nADV add extra half-GPMC_FCLK cycle" "ADVEXTRADELAY_0,ADVEXTRADELAY_1" bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,nADV assertion for first address phase when using the AAD-multiplexed protocol" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0.--3. "ADVONTIME,nADV assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "GPMC_CONFIG4_i_7,nWE and nOE signals timing parameter configuration" bitfld.long 0x0C 24.--28. "WEOFFTIME,nWE deassertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 23. "WEEXTRADELAY,nWE add extra half-GPMC_FCLK cycle" "WEEXTRADELAY_0,WEEXTRADELAY_1" newline bitfld.long 0x0C 16.--19. "WEONTIME,nWE assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 13.--15. "OEAADMUX OFFTIME,nOE deassertion time for the first address phase in an AAD-multiplexed access" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 8.--12. "OEOFFTIME,nOE deassertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 7. "OEEXTRADELAY,nOE add extra half-GPMC_FCLK cycle" "OEEXTRADELAY_0,OEEXTRADELAY_1" newline bitfld.long 0x0C 4.--6. "OEAADMUX ONTIME,nOE assertion time for the first address phase in an AAD-mux access" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. "OEONTIME,nOE assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "GPMC_CONFIG5_i_7,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "GPMC_CONFIG6_i_7,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC_FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip-select high pulse delay between successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "CYCLE2CYCLESAMECSEN_0,CYCLE2CYCLESAMECSEN_1" newline bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "CYCLE2CYCLEDIFFCSEN_0,CYCLE2CYCLEDIFFCSEN_1" bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "GPMC_CONFIG7_i_7,CS address mapping configuration" bitfld.long 0x18 8.--11. "MASKADDRESS,CS mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 6. "CSVALID,CS enable" "CSVALID_0,CSVALID_1" newline bitfld.long 0x18 0.--5. "BASEADDRESS,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29 A28 A27 A26 A25 and A24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1D0++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_i_7,This register is not a true register. only an address location" group.long 0x1CC++0x03 line.long 0x00 "GPMC_NAND_COMMAND_i_7,This register is not a true register. only an address location" group.long 0x1D4++0x03 line.long 0x00 "GPMC_NAND_DATA_i_7,This register is not a true register.only an address location" repeat 2. (list 7. 8. )(list 0x00 0x04 ) rgroup.long ($2+0x21C)++0x03 line.long 0x00 "GPMC_ECCj_RESULT_$1,ECC result register" bitfld.long 0x00 27. "P2048O,Odd row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 26. "P1024O,Odd row parity bit 1024" "0,1" newline bitfld.long 0x00 25. "P512O,Odd row parity bit 512" "0,1" bitfld.long 0x00 24. "P256O,Odd row parity bit 256" "0,1" newline bitfld.long 0x00 23. "P128O,Odd row parity bit 128" "0,1" bitfld.long 0x00 22. "P64O,Odd row parity bit 64" "0,1" newline bitfld.long 0x00 21. "P32O,Odd row parity bit 32" "0,1" bitfld.long 0x00 20. "P16O,Odd row parity bit 16" "0,1" newline bitfld.long 0x00 19. "P8O,Odd row parity bit 8" "0,1" bitfld.long 0x00 18. "P4O,Odd Column Parity bit 4" "0,1" newline bitfld.long 0x00 17. "P2O,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. "P1O,Odd Column Parity bit 1" "0,1" newline bitfld.long 0x00 11. "P2048E,Even row parity bit 2048 only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x00 10. "P1024E,Even row parity bit 1024" "0,1" newline bitfld.long 0x00 9. "P512E,Even row parity bit 512" "0,1" bitfld.long 0x00 8. "P256E,Even row parity bit 256" "0,1" newline bitfld.long 0x00 7. "P128E,Even row parity bit 128" "0,1" bitfld.long 0x00 6. "P64E,Even row parity bit 64" "0,1" newline bitfld.long 0x00 5. "P32E,Even row parity bit 32" "0,1" bitfld.long 0x00 4. "P16E,Even row parity bit 16" "0,1" newline bitfld.long 0x00 3. "P8E,Even row parity bit 8" "0,1" bitfld.long 0x00 2. "P4E,Even column parity bit 4" "0,1" newline bitfld.long 0x00 1. "P2E,Even column parity bit 2" "0,1" bitfld.long 0x00 0. "P1E,Even column parity bit 1" "0,1" repeat.end tree.end group.long 0x2D0++0x03 line.long 0x00 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface" hexmask.long.word 0x00 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation Only bits 0 to 7 are considered if the calculator is configured to use 8-bit data (GPMC_ECC_CONFIG[7] ECC16B = 0)" group.long 0x50++0x03 line.long 0x00 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC" bitfld.long 0x00 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1 - W1ActiveL" "WAIT1PINPOLARITY_0,WAIT1PINPOLARITY_1" bitfld.long 0x00 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0 - W0ActiveL" "WAIT0PINPOLARITY_0,WAIT0PINPOLARITY_1" newline bitfld.long 0x00 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location - NoForcePWr" "NANDFORCEPOSTEDWRITE_0,NANDFORCEPOSTEDWRITE_1" group.long 0x1F4++0x0B line.long 0x00 "GPMC_ECC_CONFIG,ECC configuration" bitfld.long 0x00 16. "ECCALGORITHM,ECC algorithm used" "ECCALGORITHM_0,ECCALGORITHM_1" bitfld.long 0x00 12.--13. "ECCBCHTSEL,Error correction capability used for BCH" "ECCBCHTSEL_0,ECCBCHTSEL_1,ECCBCHTSEL_2,ECCBCHTSEL_3" newline bitfld.long 0x00 8.--11. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm" "ECCWRAPMODE_0,ECCWRAPMODE_1,ECCWRAPMODE_2,ECCWRAPMODE_3,ECCWRAPMODE_4,ECCWRAPMODE_5,ECCWRAPMODE_6,ECCWRAPMODE_7,ECCWRAPMODE_8,ECCWRAPMODE_9,ECCWRAPMODE_10,ECCWRAPMODE_11,ECCWRAPMODE_12,ECCWRAPMODE_13,ECCWRAPMODE_14,ECCWRAPMODE_15" bitfld.long 0x00 7. "ECC16B,Selects an ECC calculated on 16 columns - EightCol" "ECC16B_0,ECC16B_1" newline bitfld.long 0x00 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm" "ECCTOPSECTOR_0,ECCTOPSECTOR_1,ECCTOPSECTOR_2,ECCTOPSECTOR_3,ECCTOPSECTOR_4,ECCTOPSECTOR_5,ECCTOPSECTOR_6,ECCTOPSECTOR_7" bitfld.long 0x00 1.--3. "ECCCS,Selects the CS where ECC is computed - CS0" "ECCCS_0,ECCCS_1,ECCCS_2,ECCCS_3,?,?,?,?" newline bitfld.long 0x00 0. "ECCENABLE,Enables the ECC feature - ECCDisabled" "ECCENABLE_0,ECCENABLE_1" line.long 0x04 "GPMC_ECC_CONTROL,ECC control" bitfld.long 0x04 8. "ECCCLEAR,Clear all ECC result registers Reads return 0" "ECCCLEAR_0,ECCCLEAR_1" bitfld.long 0x04 0.--3. "ECCPOINTER,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Other enums: writing other values disables.." "ECCPOINTER_0,ECCPOINTER_1,ECCPOINTER_2,ECCPOINTER_3,ECCPOINTER_4,ECCPOINTER_5,ECCPOINTER_6,ECCPOINTER_7,ECCPOINTER_8,ECCPOINTER_9,?,?,?,?,?,?" line.long 0x08 "GPMC_ECC_SIZE_CONFIG,ECC size" hexmask.long.byte 0x08 22.--29. 1. "ECCSIZE1,Defines Hamming code ECC size 1 in bytes" hexmask.long.byte 0x08 12.--19. 1. "ECCSIZE0,Defines Hamming code ECC size 0 in bytes" newline bitfld.long 0x08 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register - Size0Sel" "ECC9RESULTSIZE_0,ECC9RESULTSIZE_1" bitfld.long 0x08 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register - Size0Sel" "ECC8RESULTSIZE_0,ECC8RESULTSIZE_1" newline bitfld.long 0x08 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register - Size0Sel" "ECC7RESULTSIZE_0,ECC7RESULTSIZE_1" bitfld.long 0x08 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register - Size0Sel" "ECC6RESULTSIZE_0,ECC6RESULTSIZE_1" newline bitfld.long 0x08 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register - Size0Sel" "ECC5RESULTSIZE_0,ECC5RESULTSIZE_1" bitfld.long 0x08 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register - Size0Sel" "ECC4RESULTSIZE_0,ECC4RESULTSIZE_1" newline bitfld.long 0x08 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register - Size0Sel" "ECC3RESULTSIZE_0,ECC3RESULTSIZE_1" bitfld.long 0x08 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register - Size0Sel" "ECC2RESULTSIZE_0,ECC2RESULTSIZE_1" newline bitfld.long 0x08 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register - Size0Sel" "ECC1RESULTSIZE_0,ECC1RESULTSIZE_1" rgroup.long 0x44++0x07 line.long 0x00 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs" hexmask.long 0x00 0.--30. 1. "ILLEGALADD,Address of illegal access A30: 0 for memory region 1 for GPMC register region A29-A0: 1 GiB maximum" line.long 0x04 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs" rbitfld.long 0x04 8.--10. "ILLEGALMCMD,System command of the transaction that caused the error" "ILLEGALMCMD_0,ILLEGALMCMD_1,ILLEGALMCMD_2,ILLEGALMCMD_3,ILLEGALMCMD_4,ILLEGALMCMD_5,ILLEGALMCMD_6,ILLEGALMCMD_7" rbitfld.long 0x04 4. "ERRORNOTSUPPADD,Not supported address error - NoErr" "ERRORNOTSUPPADD_0,ERRORNOTSUPPADD_1" newline rbitfld.long 0x04 3. "ERRORNOTSUPPMCMD,Not supported command error - NoErr" "ERRORNOTSUPPMCMD_0,ERRORNOTSUPPMCMD_1" rbitfld.long 0x04 2. "ERRORTIMEOUT,Time-out error - NoErr" "ERRORTIMEOUT_0,ERRORTIMEOUT_1" newline bitfld.long 0x04 0. "ERRORVALID,Error validity status - Must be explicitly cleared with a write 1 transaction - NotValid" "ERRORVALID_0,ERRORVALID_1" group.long 0x1C++0x03 line.long 0x00 "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x00 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt - W1Masked" "WAIT1EDGEDETECTIONENABLE_0,WAIT1EDGEDETECTIONENABLE_1" bitfld.long 0x00 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt - W0Masked" "WAIT0EDGEDETECTIONENABLE_0,WAIT0EDGEDETECTIONENABLE_1" newline bitfld.long 0x00 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode - TCMasked" "TERMINALCOUNTEVENTENABLE_0,TERMINALCOUNTEVENTENABLE_1" bitfld.long 0x00 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt - FIFOMasked" "FIFOEVENTENABLE_0,FIFOEVENTENABLE_1" group.long 0x18++0x03 line.long 0x00 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x00 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt - W1Det0_R" "WAIT1EDGEDETECTIONSTATUS_0_w,WAIT1EDGEDETECTIONSTATUS_1_w" bitfld.long 0x00 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt - W0Det0_R" "WAIT0EDGEDETECTIONSTATUS_0_w,WAIT0EDGEDETECTIONSTATUS_1_w" newline bitfld.long 0x00 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt - TCStat0_R" "TERMINALCOUNTSTATUS_0_w,TERMINALCOUNTSTATUS_1_w" bitfld.long 0x00 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt - FIFOStat0_R" "FIFOEVENTSTATUS_0_w,FIFOEVENTSTATUS_1_w" group.long 0x1E0++0x07 line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1" bitfld.long 0x00 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME WRCYCLETIME RDACCESSTIME CSRDOFFTIME CSWROFFTIME ADVRDOFFTIME ADVWROFFTIME OEOFFTIME WEOFFTIME" "CYCLEOPTIMIZATION_0,CYCLEOPTIMIZATION_1,CYCLEOPTIMIZATION_2,CYCLEOPTIMIZATION_3,CYCLEOPTIMIZATION_4,CYCLEOPTIMIZATION_5,CYCLEOPTIMIZATION_6,CYCLEOPTIMIZATION_7" bitfld.long 0x00 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization - OptDisabled" "ENABLEOPTIMIZEDACCESS_0,ENABLEOPTIMIZEDACCESS_1" newline bitfld.long 0x00 24.--26. "ENGINECSSELECTOR,Selects the chip-select where Prefetch Postwrite engine is active" "ENGINECSSELECTOR_0,ENGINECSSELECTOR_1,ENGINECSSELECTOR_2,ENGINECSSELECTOR_3,ENGINECSSELECTOR_4,ENGINECSSELECTOR_5,ENGINECSSELECTOR_6,ENGINECSSELECTOR_7" bitfld.long 0x00 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration - RRDisabled" "PFPWENROUNDROBIN_0,PFPWENROUNDROBIN_1" newline bitfld.long 0x00 16.--19. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a DMA and a PFPW engine access the DMA is always serviced" "PFPWWEIGHTEDPRIO_0,PFPWWEIGHTEDPRIO_1,PFPWWEIGHTEDPRIO_2,PFPWWEIGHTEDPRIO_3,PFPWWEIGHTEDPRIO_4,PFPWWEIGHTEDPRIO_5,PFPWWEIGHTEDPRIO_6,PFPWWEIGHTEDPRIO_7,PFPWWEIGHTEDPRIO_8,PFPWWEIGHTEDPRIO_9,PFPWWEIGHTEDPRIO_10,PFPWWEIGHTEDPRIO_11,PFPWWEIGHTEDPRIO_12,PFPWWEIGHTEDPRIO_13,PFPWWEIGHTEDPRIO_14,PFPWWEIGHTEDPRIO_15" hexmask.long.byte 0x00 8.--14. 1. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request" newline bitfld.long 0x00 7. "ENABLEENGINE,Enables the Prefetch Postwite engine - PPDisabled" "ENABLEENGINE_0,ENABLEENGINE_1" bitfld.long 0x00 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode - W0" "WAITPINSELECTOR_0,WAITPINSELECTOR_1,?,?" newline bitfld.long 0x00 3. "SYNCHROMODE,Selects when the engine starts the access to" "SYNCHROMODE_0,SYNCHROMODE_1" bitfld.long 0x00 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization - InterruptSync" "DMAMODE_0,DMAMODE_1" newline bitfld.long 0x00 0. "ACCESSMODE,Selects prefetch read or write-posting accesses - PrefetchRead" "ACCESSMODE_0,ACCESSMODE_1" line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" hexmask.long.word 0x04 0.--13. 1. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected chip-select" group.long 0x1EC++0x07 line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch engine control" bitfld.long 0x00 0. "STARTENGINE,Resets the FIFO pointer and starts the engine - Stop" "STARTENGINE_0_w,STARTENGINE_1_w" line.long 0x04 "GPMC_PREFETCH_STATUS,Prefetch engine status" hexmask.long.byte 0x04 24.--30. 1. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written" bitfld.long 0x04 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value - SmallerThanThres" "FIFOTHRESHOLDSTATUS_0,FIFOTHRESHOLDSTATUS_1" newline hexmask.long.word 0x04 0.--13. 1. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value" rgroup.long 0x00++0x03 line.long 0x00 "GPMC_REVISION,This register contains the IP revision code" rgroup.long 0x54++0x03 line.long 0x00 "GPMC_STATUS,The status register provides global status bits of the GPMC" bitfld.long 0x00 9. "WAIT1STATUS,Is a copy of input pin WAIT1" "WAIT1STATUS_0,WAIT1STATUS_1" bitfld.long 0x00 8. "WAIT0STATUS,Is a copy of input pin WAIT0" "WAIT0STATUS_0,WAIT0STATUS_1" newline bitfld.long 0x00 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer - b0" "EMPTYWRITEBUFFERSTATUS_0,EMPTYWRITEBUFFERSTATUS_1" group.long 0x10++0x07 line.long 0x00 "GPMC_SYSCONFIG,This register controls the various parameters of the interconnect" bitfld.long 0x00 3.--4. "IDLEMODE," "?,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x00 0. "AUTOIDLE,Internal interface clock-gating strategy - FreeRun" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RstOnGoing" "RESETDONE_0,RESETDONE_1" group.long 0x40++0x03 line.long 0x00 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter" hexmask.long.word 0x00 4.--12. 1. "TIMEOUTSTARTVALUE,Start value of the time-out counter" bitfld.long 0x00 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature - TODisabled" "TIMEOUTENABLE_0,TIMEOUTENABLE_1" tree.end tree.end tree.open "General_Purpose_Timers" tree "TIMER10_L4_PER1Interconnect" base ad:0x48086000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x4F line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQSTATUS_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQSTATUS_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" line.long 0x3C "TPIR,This register is used for 1-ms tick generation" line.long 0x40 "TNIR,This register is used for 1-ms tick generation" line.long 0x44 "TCVR,This register is used for 1-ms tick generation" line.long 0x48 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x4C "TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER1_L4_WKUPInterconnect" base ad:0x4AE18000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x4F line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQSTATUS_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQSTATUS_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" line.long 0x3C "TPIR,This register is used for 1-ms tick generation" line.long 0x40 "TNIR,This register is used for 1-ms tick generation" line.long 0x44 "TCVR,This register is used for 1-ms tick generation" line.long 0x48 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x4C "TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER2_L4_PER1Interconnect" base ad:0x48032000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x4F line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQSTATUS_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQSTATUS_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" newline bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" newline bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" newline bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" newline bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" newline bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" newline bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" line.long 0x3C "TPIR,This register is used for 1-ms tick generation" line.long 0x40 "TNIR,This register is used for 1-ms tick generation" line.long 0x44 "TCVR,This register is used for 1-ms tick generation" line.long 0x48 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,Number of overflow events" line.long 0x4C "TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,Number of masked interrupts" tree.end tree "TIMER11_L4_PER1Interconnect" base ad:0x48088000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER12_L4_WKUPInterconnect" base ad:0x4AE20000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER13_L4_PER3Interconnect" base ad:0x48828000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER14_L4_PER3Interconnect" base ad:0x4882A000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER15_L4_PER3Interconnect" base ad:0x4882C000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER16_L4_PER3Interconnect" base ad:0x4882E000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER3_L4_PER1Interconnect" base ad:0x48034000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER4_L4_PER1Interconnect" base ad:0x48036000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER5_L4_PER3Interconnect" base ad:0x48820000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER6_L4_PER3Interconnect" base ad:0x48822000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER7_L4_PER3Interconnect" base ad:0x48824000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER8_L4_PER3Interconnect" base ad:0x48826000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree "TIMER9_L4_PER1Interconnect" base ad:0x4803E000 rgroup.long 0x00++0x03 line.long 0x00 "TIDR,This read-only register contains the revision number of the module" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,This register controls the various parameters of the L4 interface" bitfld.long 0x00 2.--3. "IDLEMODE,Power management req/ack control - Idle_Mode_0x0" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "EMUFREE,Emulation mode - timer_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 0. "SOFTRESET,Software reset - SoftReset_Value_0" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x3B line.long 0x00 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Write the number of the interrupt line to apply a SW EOI to it" "0,1" line.long 0x04 "IRQSTATUS_RAW,Component interrupt-request status" bitfld.long 0x04 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x04 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x04 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x08 "IRQSTATUS,Component interrupt-request status" bitfld.long 0x08 2. "TCAR_IT_FLAG,IRQ status for capture" "0,1" bitfld.long 0x08 1. "OVF_IT_FLAG,IRQ status for overflow" "0,1" bitfld.long 0x08 0. "MAT_IT_FLAG,IRQ status for match" "0,1" line.long 0x0C "IRQENABLE_SET,Component interrupt-request enable" bitfld.long 0x0C 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x0C 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x0C 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x10 "IRQENABLE_CLR,Component interrupt-request enable" bitfld.long 0x10 2. "TCAR_EN_FLAG,IRQ enable for compare Read" "0,1" bitfld.long 0x10 1. "OVF_EN_FLAG,IRQ enable for overflow" "0,1" bitfld.long 0x10 0. "MAT_EN_FLAG,IRQ enable for match" "0,1" line.long 0x14 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up" bitfld.long 0x14 2. "TCAR_WUP_ENA,Wake-up generation for compare - TCAR_WUP_ENA_Value_0" "TCAR_WUP_ENA_0,TCAR_WUP_ENA_1" bitfld.long 0x14 1. "OVF_WUP_ENA,Wake-up generation for overflow - OVF_WUP_ENA_Value_0" "OVF_WUP_ENA_0,OVF_WUP_ENA_1" bitfld.long 0x14 0. "MAT_WUP_ENA,Wake-up generation for match - MAT_WUP_ENA_VALUE_0" "MAT_WUP_ENA_0,MAT_WUP_ENA_1" line.long 0x18 "TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x18 14. "GPO_CFG,General-purpose output - this register directly drives the PO_GPOCFG output pin" "GPO_CFG_0,GPO_CFG_1" bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit (first/second) - First_capt" "CAPT_MODE_0,CAPT_MODE_1" bitfld.long 0x18 12. "PT,Pulse or toggle mode on TIMERi_PWM_out output pin - pulse" "PT_0,PT_1" bitfld.long 0x18 10.--11. "TRG,Trigger output mode on TIMERi_PWM_out output pin - no_trg" "TRG_0,TRG_1,TRG_2,TRG_3" newline bitfld.long 0x18 8.--9. "TCM,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination the TCAR_IT_FLAG and the edge detection logic are cleared.) - no_edge" "TCM_0,TCM_1,TCM_2,TCM_3" bitfld.long 0x18 7. "SCPWM,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off" "SCPWM_0,SCPWM_1" bitfld.long 0x18 6. "CE,Compare enable - dsb_cmp" "CE_0,CE_1" bitfld.long 0x18 5. "PRE,Prescaler enable - no_prescal" "PRE_0,PRE_1" newline bitfld.long 0x18 2.--4. "PTV,Prescale clock timer value The timer counter is prescaled with the value 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x18 1. "AR,Autoreload mode - one_shot" "AR_0,AR_1" bitfld.long 0x18 0. "ST,Start/stop timer control - cnt_stop" "ST_0,ST_1" line.long 0x1C "TCRR,This register holds the value of the internal counter" line.long 0x20 "TLDR,This register holds the timer load value" line.long 0x24 "TTGR,The read value of this register is always 0xFFFF FFFF" line.long 0x28 "TWPS,This register contains the write posting bits for all writable functional registers" bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for theTOWR register" "W_PEND_TOWR_0_r,W_PEND_TOWR_1_r" bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for theTOCR register" "W_PEND_TOCR_0_r,W_PEND_TOCR_1_r" bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for theTCVR register" "W_PEND_TCVR_0_r,W_PEND_TCVR_1_r" bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for theTNIR register" "W_PEND_TNIR_0_r,W_PEND_TNIR_1_r" newline bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for theTPIR register" "W_PEND_TPIR_0_r,W_PEND_TPIR_1_r" bitfld.long 0x28 4. "W_PEND_TMAR,When equal to 1 a write is pending to theTMAR register" "W_PEND_TMAR_0,W_PEND_TMAR_1" bitfld.long 0x28 3. "W_PEND_TTGR,When equal to 1 a write is pending to theTTGR register" "W_PEND_TTGR_0,W_PEND_TTGR_1" bitfld.long 0x28 2. "W_PEND_TLDR,When equal to 1 a write is pending to theTLDR register" "W_PEND_TLDR_0,W_PEND_TLDR_1" newline bitfld.long 0x28 1. "W_PEND_TCRR,When equal to 1 a write is pending to theTCRR register" "W_PEND_TCRR_0,W_PEND_TCRR_1" bitfld.long 0x28 0. "W_PEND_TCLR,When equal to 1 a write is pending to theTCLR register" "W_PEND_TCLR_0,W_PEND_TCLR_1" line.long 0x2C "TMAR,The compare logic consists of a 32-bit-wide. read/write data register and logic to compare counter" line.long 0x30 "TCAR1,This register holds the first captured value of the counter register" line.long 0x34 "TSICR,Timer synchronous interface control register" bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "READ_MODE_0,READ_MODE_1" bitfld.long 0x34 2. "POSTED,Posted mode selection - POSTED_Value_0" "POSTED_0,POSTED_1" bitfld.long 0x34 1. "SFT,This bit resets all the functional part of the module" "SFT_0,SFT_1" line.long 0x38 "TCAR2,This register holds the second captured value of the counter register" tree.end tree.end tree.open "Gigabit_Ethernet_Switch__GMAC_SW" tree "ALE" base ad:0x48484D00 rgroup.long 0x00++0x03 line.long 0x00 "ALE_IDVER,ADDRESS LOOKUP ENGINE revision register" group.long 0x08++0x03 line.long 0x00 "ALE_CONTROL,Address lookup engine control register" bitfld.long 0x00 31. "ENABLE_ALE,Enable ALE" "0,1" bitfld.long 0x00 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero" "0,1" bitfld.long 0x00 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit" "0,1" newline bitfld.long 0x00 8. "EN_P0_UNI_FLOOD,Enable Port 0 (Host Port) unicast flood" "0,1" bitfld.long 0x00 7. "LEARN_NO_VID,Learn No VID" "0,1" bitfld.long 0x00 6. "EN_VID0_MODE,Enable VLAN ID = 0 Mode" "0,1" newline bitfld.long 0x00 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set this bit indicates that a packet with a non OUI table entry matching source address will be dropped to the host unless the destination address matches a multicast table entry with the super bit set" "0,1" bitfld.long 0x00 4. "BYPASS,ALE Bypass - When set all packets received on ports 0 and 1 are sent to the host (only to the host)" "0,1" bitfld.long 0x00 3. "RATE_LIMIT_TX,Rate Limit Transmit mode" "0,1" newline bitfld.long 0x00 2. "VLAN_AWARE,ALE VLAN Aware - Determines what is done if VLAN not found" "0,1" bitfld.long 0x00 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software" "0,1" bitfld.long 0x00 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit" "0,1" group.long 0x10++0x03 line.long 0x00 "ALE_PRESCALE,Address lookup engine prescale register" hexmask.long.tbyte 0x00 0.--19. 1. "PRESCALE,ALE Prescale Register - The input clock is divided by this value for use in the multicast/broadcast rate limiters" group.long 0x18++0x03 line.long 0x00 "ALE_UNKNOWN_VLAN,Address lookup engine unknown vlan register" bitfld.long 0x00 24.--29. "UNKNOWN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. "UNKNOWN_REG_MCAST_FLOOD_MASK,Unknown VLAN Registered Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. "UNKNOWN_MCAST_FLOOD_MASK,Unknown VLAN Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. "UNKNOWN_VLAN_MEMBER_LIST,Unknown VLAN Member List" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x20++0x03 line.long 0x00 "ALE_TBLCTL,Address lookup engine table control" bitfld.long 0x00 31. "WRITE_RDZ,Write Bit - This bit is always read as zero" "0,1" hexmask.long.word 0x00 0.--9. 1. "ENTRY_POINTER,Table Entry Pointer - The entry_pointer contains the table entry value that will be read/written with accesses to the table word registers" group.long 0x34++0x23 line.long 0x00 "ALE_TBLW2,Address lookup engine table word 2 register" hexmask.long.byte 0x00 0.--7. 1. "ENTRY71_64,Table entry bits 71:64" line.long 0x04 "ALE_TBLW1,Address lookup engine table word 1 register" line.long 0x08 "ALE_TBLW0,Address lookup engine table word 0 register" line.long 0x0C "ALE_PORTCTL0,Address lookup engine port 0 control register" hexmask.long.byte 0x0C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" hexmask.long.byte 0x0C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" bitfld.long 0x0C 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x0C 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" bitfld.long 0x0C 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" bitfld.long 0x0C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x0C 0.--1. "PORT_STATE,Port State" "0,1,2,3" line.long 0x10 "ALE_PORTCTL1,Address lookup engine port 1 control register" hexmask.long.byte 0x10 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" hexmask.long.byte 0x10 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" bitfld.long 0x10 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x10 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" bitfld.long 0x10 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" bitfld.long 0x10 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x10 0.--1. "PORT_STATE,Port State" "0,1,2,3" line.long 0x14 "ALE_PORTCTL2,Address lookup engine port 2 control register" hexmask.long.byte 0x14 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" hexmask.long.byte 0x14 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" bitfld.long 0x14 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x14 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" bitfld.long 0x14 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" bitfld.long 0x14 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x14 0.--1. "PORT_STATE,Port State" "0,1,2,3" line.long 0x18 "ALE_PORTCTL3,Address lookup engine port 3 control register" hexmask.long.byte 0x18 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" hexmask.long.byte 0x18 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" bitfld.long 0x18 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x18 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" bitfld.long 0x18 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" bitfld.long 0x18 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x18 0.--1. "PORT_STATE,Port State" "0,1,2,3" line.long 0x1C "ALE_PORTCTL4,Address lookup engine port 4 control register" hexmask.long.byte 0x1C 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" hexmask.long.byte 0x1C 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" bitfld.long 0x1C 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x1C 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" bitfld.long 0x1C 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" bitfld.long 0x1C 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x1C 0.--1. "PORT_STATE,Port State" "0,1,2,3" line.long 0x20 "ALE_PORTCTL5,Address lookup engine port 5 control register" hexmask.long.byte 0x20 24.--31. 1. "BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter" hexmask.long.byte 0x20 16.--23. 1. "MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter" bitfld.long 0x20 5. "NO_SA_UPDATE,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry" "0,1" newline bitfld.long 0x20 4. "NO_LEARN,No Learn Mode - When set the port is disabled from learning an address" "0,1" bitfld.long 0x20 3. "VID_INGRESS_CHECK,VLAN ID Ingress" "0,1" bitfld.long 0x20 2. "DROP_UNTAGGED,Drop Untagged Packets - Drop non-VLAN tagged ingress packets" "0,1" newline bitfld.long 0x20 0.--1. "PORT_STATE,Port State" "0,1,2,3" tree.end tree "CPDMA" base ad:0x48484800 rgroup.long 0x00++0x0B line.long 0x00 "CPDMA_TX_IDVER,CPDMA_REGS TX revision register" line.long 0x04 "CPDMA_TX_CONTROL,CPDMA_REGS TX control register" bitfld.long 0x04 0. "TX_EN,TX Enable" "0,1" line.long 0x08 "CPDMA_TX_TEARDOWN,CPDMA_REGS TX teardown register" rbitfld.long 0x08 31. "TX_TDN_RDY,Tx Teardown Ready - read as zero but is always assumed to be one (unused)" "0,1" bitfld.long 0x08 0.--2. "TX_TDN_CH,Tx Teardown" "0,1,2,3,4,5,6,7" rgroup.long 0x10++0x3F line.long 0x00 "CPDMA_RX_IDVER,CPDMA_REGS RX revision register" line.long 0x04 "CPDMA_RX_CONTROL,CPDMA_REGS RX control register" bitfld.long 0x04 0. "RX_EN,RX DMA Enable" "0,1" line.long 0x08 "CPDMA_RX_TEARDOWN,CPDMA_REGS RX teardown register" rbitfld.long 0x08 31. "RX_TDN_RDY,Teardown Ready - read as zero but is always assumed to be one (unused)" "0,1" bitfld.long 0x08 0.--2. "RX_TDN_CH,Rx Teardown Channel -Receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down" "0,1,2,3,4,5,6,7" line.long 0x0C "CPDMA_SOFT_RESET,CPDMA_REGS soft reset register" bitfld.long 0x0C 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPDMA logic to be reset" "0,1" line.long 0x10 "CPDMA_DMACONTROL,CPDMA_REGS CPDMA control register" hexmask.long.byte 0x10 8.--15. 1. "TX_RLIM,Transmit Rate Limit Channel Bus" bitfld.long 0x10 4. "RX_CEF,RX Copy Error Frames Enable - Enables DMA overrun frames to be transferred to memory (up to the point of overrun)" "0,1" bitfld.long 0x10 3. "CMD_IDLE,Command Idle" "0,1" bitfld.long 0x10 2. "RX_OFFLEN_BLOCK,Receive Offset/Length word write block" "0,1" newline bitfld.long 0x10 1. "RX_OWNERSHIP,Receive Ownership Write Bit Value" "0,1" bitfld.long 0x10 0. "TX_PTYPE,Transmit Queue Priority Type" "0,1" line.long 0x14 "CPDMA_DMASTATUS,CPDMA_REGS CPDMA status register" bitfld.long 0x14 31. "IDLE,Idle Status Bit - Indicates when set that the CPDMA is not transferring a packet on transmit or receive" "0,1" bitfld.long 0x14 20.--23. "TX_HOST_ERR_CODE,TX Host Error Code - This field is set to indicate CPDMA detected TX DMA related host errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 16.--18. "TX_ERR_CH,TX Host Error" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--15. "RX_HOST_ERR_CODE,RX Host Error Code - This field is set to indicate CPDMA detected RX DMA related host errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x14 8.--10. "RX_ERR_CH,RX Host Error" "0,1,2,3,4,5,6,7" line.long 0x18 "CPDMA_RX_BUFFER_OFFSET,CPDMA_REGS receive buffer offset" hexmask.long.word 0x18 0.--15. 1. "RX_BUFFER_OFFSET,Receive Buffer Offset Value - The RX_BUFFER_OFFSET will be written by the port into each frame SOP buffer descriptor buffer_offset field" line.long 0x1C "CPDMA_EMCONTROL,CPDMA_REGS emulation control" bitfld.long 0x1C 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x1C 0. "FREE,Emulation Free Bit" "0,1" line.long 0x20 "CPDMA_TX_PRI0_RATE,CPDMA_REGS transmit (ingress) priority 0 rate" hexmask.long.word 0x20 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" hexmask.long.word 0x20 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x24 "CPDMA_TX_PRI1_RATE,CPDMA_REGS transmit (ingress) priority 1 rate" hexmask.long.word 0x24 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" hexmask.long.word 0x24 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x28 "CPDMA_TX_PRI2_RATE,CPDMA_REGS transmit (ingress) priority 2 rate" hexmask.long.word 0x28 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" hexmask.long.word 0x28 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x2C "CPDMA_TX_PRI3_RATE,CPDMA_REGS transmit (ingress) priority 3 rate" hexmask.long.word 0x2C 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" hexmask.long.word 0x2C 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x30 "CPDMA_TX_PRI4_RATE,CPDMA_REGS transmit (ingress) priority 4 rate" hexmask.long.word 0x30 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" hexmask.long.word 0x30 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x34 "CPDMA_TX_PRI5_RATE,CPDMA_REGS transmit (ingress) priority 5 rate" hexmask.long.word 0x34 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" hexmask.long.word 0x34 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x38 "CPDMA_TX_PRI6_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 6 RATE" hexmask.long.word 0x38 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" hexmask.long.word 0x38 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" line.long 0x3C "CPDMA_TX_PRI7_RATE,CPDMA_REGS transmit (ingress) priority 7 rate" hexmask.long.word 0x3C 16.--29. 1. "PRIN_IDLE_CNT,Priority ( 7:0) idle count" hexmask.long.word 0x3C 0.--13. 1. "PRIN_SEND_CNT,Priority ( 7:0) send count" rgroup.long 0x80++0x17 line.long 0x00 "CPDMA_TX_INTSTAT_RAW,CPDMA_INT TX interrupt status register (raw value)" bitfld.long 0x00 7. "TX7_PEND,TX7_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 6. "TX6_PEND,TX6_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 5. "TX5_PEND,TX5_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 4. "TX4_PEND,TX4_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 3. "TX3_PEND,TX3_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 2. "TX2_PEND,TX2_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 1. "TX1_PEND,TX1_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 0. "TX0_PEND,TX0_PEND raw int read (before mask)" "0,1" line.long 0x04 "CPDMA_TX_INTSTAT_MASKED,CPDMA_INT TX interrupt status register (masked value)" bitfld.long 0x04 7. "TX7_PEND,TX7_PEND masked interrupt" "0,1" bitfld.long 0x04 6. "TX6_PEND,TX6_PEND masked interrupt" "0,1" bitfld.long 0x04 5. "TX5_PEND,TX5_PEND masked interrupt" "0,1" bitfld.long 0x04 4. "TX4_PEND,TX4_PEND masked interrupt" "0,1" newline bitfld.long 0x04 3. "TX3_PEND,TX3_PEND masked interrupt" "0,1" bitfld.long 0x04 2. "TX2_PEND,TX2_PEND masked interrupt" "0,1" bitfld.long 0x04 1. "TX1_PEND,TX1_PEND masked interrupt" "0,1" bitfld.long 0x04 0. "TX0_PEND,TX0_PEND masked interrupt" "0,1" line.long 0x08 "CPDMA_TX_INTMASK_SET,CPDMA_INT TX interrupt mask set register" bitfld.long 0x08 7. "TX7_MASK,TX Channel 7 Mask - Write one to enable interrupt" "0,1" bitfld.long 0x08 6. "TX6_MASK,TX Channel 6 Mask - Write one to enable interrupt" "0,1" bitfld.long 0x08 5. "TX5_MASK,TX Channel 5 Mask - Write one to enable interrupt" "0,1" bitfld.long 0x08 4. "TX4_MASK,TX Channel 4 Mask - Write one to enable interrupt" "0,1" newline bitfld.long 0x08 3. "TX3_MASK,TX Channel 3 Mask - Write one to enable interrupt" "0,1" bitfld.long 0x08 2. "TX2_MASK,TX Channel 2 Mask - Write one to enable interrupt" "0,1" bitfld.long 0x08 1. "TX1_MASK,TX Channel 1 Mask - Write one to enable interrupt" "0,1" bitfld.long 0x08 0. "TX0_MASK,TX Channel 0 Mask - Write one to enable interrupt" "0,1" line.long 0x0C "CPDMA_TX_INTMASK_CLEAR,CPDMA_INT TX Interrupt mask clear register" bitfld.long 0x0C 7. "TX7_MASK,TX Channel 7 Mask - Write one to disable interrupt" "0,1" bitfld.long 0x0C 6. "TX6_MASK,TX Channel 6 Mask - Write one to disable interrupt" "0,1" bitfld.long 0x0C 5. "TX5_MASK,TX Channel 5 Mask - Write one to disable interrupt" "0,1" bitfld.long 0x0C 4. "TX4_MASK,TX Channel 4 Mask - Write one to disable interrupt" "0,1" newline bitfld.long 0x0C 3. "TX3_MASK,TX Channel 3 Mask - Write one to disable interrupt" "0,1" bitfld.long 0x0C 2. "TX2_MASK,TX Channel 2 Mask - Write one to disable interrupt" "0,1" bitfld.long 0x0C 1. "TX1_MASK,TX Channel 1 Mask - Write one to disable interrupt" "0,1" bitfld.long 0x0C 0. "TX0_MASK,TX Channel 0 Mask - Write one to disable interrupt" "0,1" line.long 0x10 "CPDMA_IN_VECTOR,CPDMA_INT input vector (read only)" line.long 0x14 "CPDMA_EOI_VECTOR,CPDMA_INT end of interrupt vector" bitfld.long 0x14 0.--4. "DMA_EOI_VECTOR,DMA End of Interrupt Vector - The EOI_VECTOR( 4:0) pins reflect the value written to this location one MAIN_CLK cycle after a write to this location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA0++0x5F line.long 0x00 "CPDMA_RX_INTSTAT_RAW,CPDMA_INT RX Interrupt status register (raw value)" bitfld.long 0x00 15. "RX7_THRESH_PEND,RX7_THRESH_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 14. "RX6_THRESH_PEND,RX6_THRESH_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 13. "RX5_THRESH_PEND,RX5_THRESH_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 12. "RX4_THRESH_PEND,RX4_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 11. "RX3_THRESH_PEND,RX3_THRESH_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 10. "RX2_THRESH_PEND,RX2_THRESH_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 9. "RX1_THRESH_PEND,RX1_THRESH_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 8. "RX0_THRESH_PEND,RX0_THRESH_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 7. "RX7_PEND,RX7_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 6. "RX6_PEND,RX6_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 5. "RX5_PEND,RX5_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 4. "RX4_PEND,RX4_PEND raw int read (before mask)" "0,1" newline bitfld.long 0x00 3. "RX3_PEND,RX3_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 2. "RX2_PEND,RX2_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 1. "RX1_PEND,RX1_PEND raw int read (before mask)" "0,1" bitfld.long 0x00 0. "RX0_PEND,RX0_PEND raw int read (before mask)" "0,1" line.long 0x04 "CPDMA_RX_INTSTAT_MASKED,CPDMA_INT RX interrupt status register (masked value)" bitfld.long 0x04 15. "RX7_THRESH_PEND,RX7_THRESH_PEND masked int" "0,1" bitfld.long 0x04 14. "RX6_THRESH_PEND,RX6_THRESH_PEND masked int" "0,1" bitfld.long 0x04 13. "RX5_THRESH_PEND,RX5_THRESH_PEND masked int" "0,1" bitfld.long 0x04 12. "RX4_THRESH_PEND,RX4_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 11. "RX3_THRESH_PEND,RX3_THRESH_PEND masked int" "0,1" bitfld.long 0x04 10. "RX2_THRESH_PEND,RX2_THRESH_PEND masked int" "0,1" bitfld.long 0x04 9. "RX1_THRESH_PEND,RX1_THRESH_PEND masked int" "0,1" bitfld.long 0x04 8. "RX0_THRESH_PEND,RX0_THRESH_PEND masked int" "0,1" newline bitfld.long 0x04 7. "RX7_PEND,RX7_PEND masked int" "0,1" bitfld.long 0x04 6. "RX6_PEND,RX6_PEND masked int" "0,1" bitfld.long 0x04 5. "RX5_PEND,RX5_PEND masked int" "0,1" bitfld.long 0x04 4. "RX4_PEND,RX4_PEND masked int" "0,1" newline bitfld.long 0x04 3. "RX3_PEND,RX3_PEND masked int" "0,1" bitfld.long 0x04 2. "RX2_PEND,RX2_PEND masked int" "0,1" bitfld.long 0x04 1. "RX1_PEND,RX1_PEND masked int" "0,1" bitfld.long 0x04 0. "RX0_PEND,RX0_PEND masked int" "0,1" line.long 0x08 "CPDMA_RX_INTMASK_SET,CPDMA_INT RX interrupt mask set register" bitfld.long 0x08 15. "RX7_THRESH_PEND_MASK,RX Channel 7 Threshold Pending Int" "0,1" bitfld.long 0x08 14. "RX6_THRESH_PEND_MASK,RX Channel 6 Threshold Pending Int" "0,1" bitfld.long 0x08 13. "RX5_THRESH_PEND_MASK,RX Channel 5 Threshold Pending Int" "0,1" bitfld.long 0x08 12. "RX4_THRESH_PEND_MASK,RX Channel 4 Threshold Pending Int" "0,1" newline bitfld.long 0x08 11. "RX3_THRESH_PEND_MASK,RX Channel 3 Threshold Pending Int" "0,1" bitfld.long 0x08 10. "RX2_THRESH_PEND_MASK,RX Channel 2 Threshold Pending Int" "0,1" bitfld.long 0x08 9. "RX1_THRESH_PEND_MASK,RX Channel 1 Threshold Pending Int" "0,1" bitfld.long 0x08 8. "RX0_THRESH_PEND_MASK,RX Channel 0 Threshold Pending Int" "0,1" newline bitfld.long 0x08 7. "RX7_PEND_MASK,RX Channel 7 Pending Int" "0,1" bitfld.long 0x08 6. "RX6_PEND_MASK,RX Channel 6 Pending Int" "0,1" bitfld.long 0x08 5. "RX5_PEND_MASK,RX Channel 5 Pending Int" "0,1" bitfld.long 0x08 4. "RX4_PEND_MASK,RX Channel 4 Pending Int" "0,1" newline bitfld.long 0x08 3. "RX3_PEND_MASK,RX Channel 3 Pending Int" "0,1" bitfld.long 0x08 2. "RX2_PEND_MASK,RX Channel 2 Pending Int" "0,1" bitfld.long 0x08 1. "RX1_PEND_MASK,RX Channel 1 Pending Int" "0,1" bitfld.long 0x08 0. "RX0_PEND_MASK,RX Channel 0 Pending Int" "0,1" line.long 0x0C "CPDMA_RX_INTMASK_CLEAR,CPDMA_INT RX interrupt mask clear register" bitfld.long 0x0C 15. "RX7_THRESH_PEND_MASK,RX Channel 7 Threshold Pending Int" "0,1" bitfld.long 0x0C 14. "RX6_THRESH_PEND_MASK,RX Channel 6 Threshold Pending Int" "0,1" bitfld.long 0x0C 13. "RX5_THRESH_PEND_MASK,RX Channel 5 Threshold Pending Int" "0,1" bitfld.long 0x0C 12. "RX4_THRESH_PEND_MASK,RX Channel 4 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 11. "RX3_THRESH_PEND_MASK,RX Channel 3 Threshold Pending Int" "0,1" bitfld.long 0x0C 10. "RX2_THRESH_PEND_MASK,RX Channel 2 Threshold Pending Int" "0,1" bitfld.long 0x0C 9. "RX1_THRESH_PEND_MASK,RX Channel 1 Threshold Pending Int" "0,1" bitfld.long 0x0C 8. "RX0_THRESH_PEND_MASK,RX Channel 0 Threshold Pending Int" "0,1" newline bitfld.long 0x0C 7. "RX7_PEND_MASK,RX Channel 7 Pending Int" "0,1" bitfld.long 0x0C 6. "RX6_PEND_MASK,RX Channel 6 Pending Int" "0,1" bitfld.long 0x0C 5. "RX5_PEND_MASK,RX Channel 5 Pending Int" "0,1" bitfld.long 0x0C 4. "RX4_PEND_MASK,RX Channel 4 Pending Int" "0,1" newline bitfld.long 0x0C 3. "RX3_PEND_MASK,RX Channel 3 Pending Int" "0,1" bitfld.long 0x0C 2. "RX2_PEND_MASK,RX Channel 2 Pending Int" "0,1" bitfld.long 0x0C 1. "RX1_PEND_MASK,RX Channel 1 Pending Int" "0,1" bitfld.long 0x0C 0. "RX0_PEND_MASK,RX Channel 0 Pending Int" "0,1" line.long 0x10 "CPDMA_DMA_INTSTAT_RAW,CPDMA_INT DMA interrupt status register (raw value)" bitfld.long 0x10 1. "HOST_PEND,Host Pending Interrupt - raw int read (before mask)" "0,1" bitfld.long 0x10 0. "STAT_PEND,Statistics Pending Interrupt - raw int read (before mask)" "0,1" line.long 0x14 "CPDMA_DMA_INTSTAT_MASKED,CPDMA_INT DMA interrupt status register (masked value)" bitfld.long 0x14 1. "HOST_PEND,Host Pending Interrupt - masked interrupt" "0,1" bitfld.long 0x14 0. "STAT_PEND,Statistics Pending Interrupt - masked interrupt" "0,1" line.long 0x18 "CPDMA_DMA_INTMASK_SET,CPDMA_INT DMA interrupt mask set register" bitfld.long 0x18 1. "HOST_ERR_INT_MASK,Host Error Interrupt Mask - Write one to enable interrupt" "0,1" rbitfld.long 0x18 0. "STAT_INT_MASK,Statistics Interrupt Mask - Write one to enable interrupt" "0,1" line.long 0x1C "CPDMA_DMA_INTMASK_CLEAR,CPDMA_INT DMA interrupt mask clear register" bitfld.long 0x1C 1. "HOST_ERR_INT_MASK,Host Error Interrupt Mask - Write one to disable interrupt" "0,1" bitfld.long 0x1C 0. "STAT_INT_MASK,Statistics Interrupt Mask - Write one to disable interrupt" "0,1" line.long 0x20 "CPDMA_RX0_PENDTHRESH,CPDMA_INT receive threshold pending register channel 0" hexmask.long.byte 0x20 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x24 "CPDMA_RX1_PENDTHRESH,CPDMA_INT receive threshold pending register channel 1" hexmask.long.byte 0x24 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x28 "CPDMA_RX2_PENDTHRESH,CPDMA_INT receive threshold pending register channel 2" hexmask.long.byte 0x28 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x2C "CPDMA_RX3_PENDTHRESH,CPDMA_INT receive threshold pending register channel 3" hexmask.long.byte 0x2C 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x30 "CPDMA_RX4_PENDTHRESH,CPDMA_INT receive threshold pending register channel 4" hexmask.long.byte 0x30 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x34 "CPDMA_RX5_PENDTHRESH,CPDMA_INT receive threshold pending register channel 5" hexmask.long.byte 0x34 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x38 "CPDMA_RX6_PENDTHRESH,CPDMA_INT receive threshold pending register channel 6" hexmask.long.byte 0x38 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x3C "CPDMA_RX7_PENDTHRESH,CPDMA_INT receive threshold pending register channel 7" hexmask.long.byte 0x3C 0.--7. 1. "RX_PENDTHRESH,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)" line.long 0x40 "CPDMA_RX0_FREEBUFFER,CPDMA_INT receive free buffer register channel 0" hexmask.long.word 0x40 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x44 "CPDMA_RX1_FREEBUFFER,CPDMA_INT receive free buffer register channel 1" hexmask.long.word 0x44 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x48 "CPDMA_RX2_FREEBUFFER,CPDMA_INT receive free buffer register channel 2" hexmask.long.word 0x48 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x4C "CPDMA_RX3_FREEBUFFER,CPDMA_INT receive free buffer register channel 3" hexmask.long.word 0x4C 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x50 "CPDMA_RX4_FREEBUFFER,CPDMA_INT receive free buffer register channel 4" hexmask.long.word 0x50 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x54 "CPDMA_RX5_FREEBUFFER,CPDMA_INT receive free buffer register channel 5" hexmask.long.word 0x54 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x58 "CPDMA_RX6_FREEBUFFER,CPDMA_INT receive free buffer register channel 6" hexmask.long.word 0x58 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" line.long 0x5C "CPDMA_RX7_FREEBUFFER,CPDMA_INT receive free buffer register channel 7" hexmask.long.word 0x5C 0.--15. 1. "RX_FREEBUFFER,Rx Free Buffer Count - This field contains the count of free buffers available" tree.end tree "CPTS" base ad:0x48484C00 rgroup.long 0x00++0x07 line.long 0x00 "CPTS_IDVER,CPTS revision" line.long 0x04 "CPTS_CONTROL,Time sync control register" bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1" bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1" bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1" bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1" bitfld.long 0x04 1. "INT_TEST,Interrupt Test - When set this bit allows the raw interrupt to be written to facilitate interrupt test" "0,1" bitfld.long 0x04 0. "CPTS_EN,Time Sync Enable - When disabled (cleared to zero) the RCLK domain is held in reset" "0,1" group.long 0x0C++0x0B line.long 0x00 "CPTS_TS_PUSH,Time stamp event push register" bitfld.long 0x00 0. "TS_PUSH,Time stamp event push - When a logic high is written to this bit a time stamp event is pushed onto the event FIFO" "0,1" line.long 0x04 "CPTS_TS_LOAD_VAL,Time stamp load value register" line.long 0x08 "CPTS_TS_LOAD_EN,Time stamp load enable register" bitfld.long 0x08 0. "TS_LOAD_EN,Time Stamp Load - Writing a one to this bit enables the time stamp value to be written via theCPTS_TS_LOAD_VAL register" "0,1" group.long 0x20++0x0B line.long 0x00 "CPTS_INTSTAT_RAW,Time sync interrupt status raw register" bitfld.long 0x00 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1" line.long 0x04 "CPTS_INTSTAT_MASKED,Time sync interrupt status masked register" bitfld.long 0x04 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1" line.long 0x08 "CPTS_INT_ENABLE,Time sync interrupt enable register" bitfld.long 0x08 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1" group.long 0x30++0x0B line.long 0x00 "CPTS_EVENT_POP,Event interrupt pop register" bitfld.long 0x00 0. "EVENT_POP,Event Pop - When a logic high is written to this bit an event is popped off the event FIFO" "0,1" line.long 0x04 "CPTS_EVENT_LOW,Lower 32-bits of the event value" line.long 0x08 "CPTS_EVENT_HIGH,Upper 32-bits of the event value" bitfld.long 0x08 24.--28. "PORT_NUMBER,Port Number - indicates the port number of an ethernet event or the hardware push pin number (1 to 4)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20.--23. "EVENT_TYPE,Time Sync Event Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--19. "MESSAGE_TYPE,Message type - The message type value that was contained in an ethernet transmit or receive time sync packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--15. 1. "SEQUENCE_ID,Sequence ID - The 16-bit sequence id is the value that was contained in an ethernet transmit or receivetime sync packet" tree.end tree "MDIO" base ad:0x48485000 group.long 0x00++0x17 line.long 0x00 "MDIO_VER,MDIO Revision" line.long 0x04 "MDIO_CONTROL,MDIO Control register" rbitfld.long 0x04 31. "IDLE,MDIO state machine IDLE" "0,1" bitfld.long 0x04 30. "ENABLE,Enable control" "0,1" rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1" bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1" newline bitfld.long 0x04 18. "FAULTENB,Fault detect enable" "0,1" bitfld.long 0x04 17. "INTTESTENB,Interrupt test enable" "0,1" hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider" line.long 0x08 "MDIO_ALIVE,PHY Alive Status Register" line.long 0x0C "MDIO_LINK,PHY Link Status" line.long 0x10 "MDIO_LINKINTRAW," bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3" line.long 0x14 "MDIO_LINKINTMASKED,MDIO Link Status Change Interrupt Register" bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3" group.long 0x20++0x0F line.long 0x00 "MDIO_USERINTRAW,MDIO User Command Complete Interrupt" bitfld.long 0x00 0.--1. "USERINTRAW,Raw value of MDIO user command complete event for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register respectively" "0,1,2,3" line.long 0x04 "MDIO_USERINTMASKED,MDIO User Command Complete Interrupt" bitfld.long 0x04 0.--1. "USERINTMASKED,Masked value of MDIO user command complete interrupt for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register respectively" "0,1,2,3" line.long 0x08 "MDIO_USERINTMASKSET,MDIO User Command Complete Interrupt Mask Set" bitfld.long 0x08 0.--1. "USERINTMASKSET,MDIO user interrupt mask set for USERINTMASKED[1:0] respectively" "0,1,2,3" line.long 0x0C "MDIO_USERINTMASKCLR,MDIO User Command Complete Interrupt Mask Clear" bitfld.long 0x0C 0.--1. "USERINTMASKCLEAR,MDIO user command complete interrupt mask clear for USERINTMASKED[1:0] respectively" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "MDIO_USERACCESS0,MDIO_User_Access" bitfld.long 0x00 31. "GO,Go" "0,1" bitfld.long 0x00 30. "WRITE,Write enable" "0,1" bitfld.long 0x00 29. "ACK,Acknowledge" "0,1" bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--15. 1. "DATA,User data" group.long 0x88++0x03 line.long 0x00 "MDIO_USERACCESS1,MDIO User Access" bitfld.long 0x00 31. "GO,Go" "0,1" bitfld.long 0x00 30. "WRITE,Write enable" "0,1" bitfld.long 0x00 29. "ACK,Acknowledge" "0,1" bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.word 0x00 0.--15. 1. "DATA,User data" repeat 2. (list 0. 1. )(list 0x00 0x08 ) group.long ($2+0x84)++0x03 line.long 0x00 "MDIO_USERPHYSEL$1,MDIO User PHY Select" bitfld.long 0x00 7. "LINKSEL,Link status determination select" "0,1" bitfld.long 0x00 6. "LINKINTENB,Link change interrupt enable" "0,1" newline bitfld.long 0x00 0.--4. "PHYADDRMON,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat.end tree.end tree "PORT" base ad:0x48484100 group.long 0x00++0x03 line.long 0x00 "P0_CONTROL,CPSW PORT 0 control register" bitfld.long 0x00 28.--30. "P0_DLR_CPDMA_CH,Port 0 DLR CPDMA Channel This field indicates the CPDMA channel that DLR packets will be received on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1" bitfld.long 0x00 21. "P0_VLAN_LTYPE2_EN,Port 0 VLAN LTYPE 2 enable" "0,1" bitfld.long 0x00 20. "P0_VLAN_LTYPE1_EN,Port 0 VLAN LTYPE 1 enable" "0,1" newline bitfld.long 0x00 16. "P0_DSCP_PRI_EN,Port 0 DSCP Priority Enable" "0,1" group.long 0x08++0x1B line.long 0x00 "P0_MAX_BLKS,CPSW PORT 0 maximum FIFO blocks register" bitfld.long 0x00 4.--8. "P0_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. "P0_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P0_BLK_CNT,CPSW PORT 0 FIFO block usage count (read only)" bitfld.long 0x04 4.--8. "P0_TX_BLK_CNT,Port 0 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--3. "P0_RX_BLK_CNT,Port 0 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P0_TX_IN_CTL,CPSW PORT 0 transmit FIFO control" bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "0,1,2,3" bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P0_PORT_VLAN,CPSW PORT 0 VLAN register" bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P0_TX_PRI_MAP,CPSW PORT 0 TX header priority to switch priority mapping register" bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P0_CPDMA_TX_PRI_MAP,CPSW CPDMA TX (PORT 0 RX) packet priority to header priority" bitfld.long 0x14 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P0_CPDMA_RX_CH_MAP,CPSW CPDMA RX (PORT 0 TX) switch priority to DMA channel" bitfld.long 0x18 28.--30. "P2_PRI3,Port 2 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "P2_PRI2,Port 2 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "P2_PRI1,Port 2 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "P2_PRI0,Port 2 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "P1_PRI3,Port 1 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "P1_PRI2,Port 1 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "P1_PRI1,Port 1 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "P1_PRI0,Port 1 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" group.long 0x30++0x27 line.long 0x00 "P0_RX_DSCP_PRI_MAP0,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P0_RX_DSCP_PRI_MAP1,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P0_RX_DSCP_PRI_MAP2,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P0_RX_DSCP_PRI_MAP3,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P0_RX_DSCP_PRI_MAP4,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P0_RX_DSCP_PRI_MAP5,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P0_RX_DSCP_PRI_MAP6,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P0_RX_DSCP_PRI_MAP7,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P0_IDLE2LPI,Port 0 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x20 0.--19. 1. "P0_IDLE2LPI,Port 0 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 0 idle to LPI counter on each clock that the port 0 transmit is not idle" line.long 0x24 "P0_LPI2WAKE,Port 0 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x24 0.--19. 1. "P0_LPI2WAKE,Port 0 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 0 LPI to wake counter" group.long 0x100++0x03 line.long 0x00 "P1_CONTROL,CPSW PORT 1 control register" bitfld.long 0x00 24. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1" bitfld.long 0x00 21. "P1_VLAN_LTYPE2_EN,Port 1 VLAN LTYPE 2 enable" "0,1" bitfld.long 0x00 20. "P1_VLAN_LTYPE1_EN,Port 1 VLAN LTYPE 1 enable" "0,1" bitfld.long 0x00 16. "P1_DSCP_PRI_EN,Port 1 DSCP Priority Enable" "0,1" newline bitfld.long 0x00 14. "P1_TS_320,Port 1 Time Sync Destination Port Number 320 enable" "0,1" bitfld.long 0x00 13. "P1_TS_319,Port 1 Time Sync Destination Port Number 319 enable" "0,1" bitfld.long 0x00 12. "P1_TS_132,Port 1 Time Sync Destination IP Address 132 enable" "0,1" bitfld.long 0x00 11. "P1_TS_131,Port 1 Time Sync Destination IP Address 131 enable" "0,1" newline bitfld.long 0x00 10. "P1_TS_130,Port 1 Time Sync Destination IP Address 130 enable" "0,1" bitfld.long 0x00 9. "P1_TS_129,Port 1 Time Sync Destination IP Address 129 enable" "0,1" bitfld.long 0x00 8. "P1_TS_TTL_NONZERO,Port 1 Time Sync Time To Live Non-zero enable" "0,1" bitfld.long 0x00 4. "P1_TS_ANNEX_D_EN,Port 1 Time Sync Annex D enable" "0,1" newline bitfld.long 0x00 3. "P1_TS_LTYPE2_EN,Port 1 Time Sync LTYPE 2 enable" "0,1" bitfld.long 0x00 2. "P1_TS_LTYPE1_EN,Port 1 Time Sync LTYPE 1 enable" "0,1" bitfld.long 0x00 1. "P1_TS_TX_EN,Port 1 Time Sync Transmit Enable" "0,1" bitfld.long 0x00 0. "P1_TS_RX_EN,Port 1 Time Sync Receive Enable" "0,1" group.long 0x108++0x23 line.long 0x00 "P1_MAX_BLKS,CPSW PORT 1 maximum FIFO blocks register" bitfld.long 0x00 4.--8. "P1_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. "P1_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P1_BLK_CNT,CPSW PORT 1 FIFO block usage count (read only)" bitfld.long 0x04 4.--8. "P1_TX_BLK_CNT,Port 1 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--3. "P1_RX_BLK_CNT,Port 1 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P1_TX_IN_CTL,CPSW PORT 1 transmit FIFO control" bitfld.long 0x08 24.--27. "HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "0,1,2,3" bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input Blocks to subtract in dual mac mode and blocks to subtract on non rate-limited traffic in rate-limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P1_PORT_VLAN,CPSW PORT 1 VLAN register" bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P1_TX_PRI_MAP,CPSW PORT 1 TX header priority to switch priority mapping register" bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P1_TS_SEQ_MTYPE,CPSW PORT 1 time sync sequence ID offset and message type" bitfld.long 0x14 16.--21. "P1_TS_SEQ_ID_OFFSET,Port 1 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x14 0.--15. 1. "P1_TS_MSG_TYPE_EN,Port 1 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" line.long 0x18 "P1_SA_LO,CPSW CPGMAC_SL1 source address low register" hexmask.long.byte 0x18 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" hexmask.long.byte 0x18 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)" line.long 0x1C "P1_SA_HI,CPSW CPGMAC_SL1 source address high register" hexmask.long.byte 0x1C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)" hexmask.long.byte 0x1C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24 (byte 3)" hexmask.long.byte 0x1C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)" hexmask.long.byte 0x1C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)" line.long 0x20 "P1_SEND_PERCENT,CPSW PORT 1 transmit queue send percentages" hexmask.long.byte 0x20 16.--22. 1. "PRI3_SEND_PERCENT,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) whenCPSW_PTYPE[18] P1_PRI3_SHAPE_EN is set (queue shaping enabled)" hexmask.long.byte 0x20 8.--14. 1. "PRI2_SEND_PERCENT,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) whenCPSW_PTYPE[17] P1_PRI2_SHAPE_EN is set (queue shaping enabled)" hexmask.long.byte 0x20 0.--6. 1. "PRI1_SEND_PERCENT,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[16] P1_PRI1_SHAPE_EN is set (queue shaping enabled)" group.long 0x130++0x27 line.long 0x00 "P1_RX_DSCP_PRI_MAP0,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P1_RX_DSCP_PRI_MAP1,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P1_RX_DSCP_PRI_MAP2,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P1_RX_DSCP_PRI_MAP3,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P1_RX_DSCP_PRI_MAP4,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P1_RX_DSCP_PRI_MAP5,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P1_RX_DSCP_PRI_MAP6,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P1_RX_DSCP_PRI_MAP7,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P1_IDLE2LPI,Port 1 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x20 0.--19. 1. "P1_IDLE2LPI,Port 1 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 1 idle to LPI counter on each clock that the port 1 transmit is not idle" line.long 0x24 "P1_LPI2WAKE,Port 1 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x24 0.--19. 1. "P1_LPI2WAKE,Port 1 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 1 LPI to wake counter" group.long 0x200++0x03 line.long 0x00 "P2_CONTROL,CPSW_3GF PORT 2 control register" bitfld.long 0x00 24. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1" bitfld.long 0x00 21. "P2_VLAN_LTYPE2_EN,Port 2 VLAN LTYPE 2 enable" "0,1" bitfld.long 0x00 20. "P2_VLAN_LTYPE1_EN,Port 2 VLAN LTYPE 1 enable" "0,1" bitfld.long 0x00 16. "P2_DSCP_PRI_EN,Port 0 DSCP Priority Enable" "0,1" newline bitfld.long 0x00 14. "P2_TS_320,Port 2 Time Sync Destination Port Number 320 enable" "0,1" bitfld.long 0x00 13. "P2_TS_319,Port 2 Time Sync Destination Port Number 319 enable" "0,1" bitfld.long 0x00 12. "P2_TS_132,Port 2 Time Sync Destination IP Address 132 enable" "0,1" bitfld.long 0x00 11. "P2_TS_131,Port 2 Time Sync Destination IP Address 131 enable" "0,1" newline bitfld.long 0x00 10. "P2_TS_130,Port 2 Time Sync Destination IP Address 130 enable" "0,1" bitfld.long 0x00 9. "P2_TS_129,Port 2 Time Sync Destination IP Address 129 enable" "0,1" bitfld.long 0x00 8. "P2_TS_TTL_NONZERO,Port 2 Time Sync Time To Live Non-zero enable" "0,1" bitfld.long 0x00 4. "P2_TS_ANNEX_D_EN,Port 2 Time Sync Annex D enable" "0,1" newline bitfld.long 0x00 3. "P2_TS_LTYPE2_EN,Port 2 Time Sync LTYPE 2 enable" "0,1" bitfld.long 0x00 2. "P2_TS_LTYPE1_EN,Port 2 Time Sync LTYPE 1 enable" "0,1" bitfld.long 0x00 1. "P2_TS_TX_EN,Port 2 Time Sync Transmit Enable" "0,1" bitfld.long 0x00 0. "P2_TS_RX_EN,Port 2 Time Sync Receive Enable" "0,1" group.long 0x208++0x23 line.long 0x00 "P2_MAX_BLKS,CPSW PORT 2 maximum FIFO blocks register" bitfld.long 0x00 4.--8. "P2_TX_MAX_BLKS,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. "P2_RX_MAX_BLKS,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "P2_BLK_CNT,CPSW PORT 2 FIFO block usage count (read only)" bitfld.long 0x04 4.--8. "P2_TX_BLK_CNT,Port 2 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--3. "P2_RX_BLK_CNT,Port 2 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "P2_TX_IN_CTL,CPSW PORT 2 transmit FIFO control" bitfld.long 0x08 24.--27. "HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. "TX_RATE_EN,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--17. "TX_IN_SEL,Transmit FIFO Input Queue Type Select" "0,1,2,3" bitfld.long 0x08 12.--15. "TX_BLKS_REM,Transmit FIFO Input Blocks to subtract in dual mac mode and blocks to subtract on non rate-limited traffic in rate-limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--9. 1. "TX_PRI_WDS,Transmit FIFO Words in queue" line.long 0x0C "P2_PORT_VLAN,CPSW PORT 2 VLAN register" bitfld.long 0x0C 13.--15. "PORT_PRI,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12. "PORT_CFI,Port CFI bit" "0,1" hexmask.long.word 0x0C 0.--11. 1. "PORT_VID,Port VLAN ID" line.long 0x10 "P2_TX_PRI_MAP,CPSW PORT 2 TX header priority to switch priority mapping register" bitfld.long 0x10 28.--29. "PRI7,Priority" "0,1,2,3" bitfld.long 0x10 24.--25. "PRI6,Priority" "0,1,2,3" bitfld.long 0x10 20.--21. "PRI5,Priority" "0,1,2,3" bitfld.long 0x10 16.--17. "PRI4,Priority" "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRI3,Priority" "0,1,2,3" bitfld.long 0x10 8.--9. "PRI2,Priority" "0,1,2,3" bitfld.long 0x10 4.--5. "PRI1,Priority" "0,1,2,3" bitfld.long 0x10 0.--1. "PRI0,Priority" "0,1,2,3" line.long 0x14 "P2_TS_SEQ_MTYPE,CPSW_3GF PORT 2 time sync sequence ID offset and message type" bitfld.long 0x14 16.--21. "P2_TS_SEQ_ID_OFFSET,Port 2 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x14 0.--15. 1. "P2_TS_MSG_TYPE_EN,Port 2 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)" line.long 0x18 "P2_SA_LO,CPSW CPGMAC_SL2 source address low register" hexmask.long.byte 0x18 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits (byte 0)" hexmask.long.byte 0x18 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8 (byte 1)" line.long 0x1C "P2_SA_HI,CPSW CPGMAC_SL2 source address high register" hexmask.long.byte 0x1C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16 (byte 2)" hexmask.long.byte 0x1C 16.--23. 1. "MACSRCADDR_31_23,Source Address bits 31:23 (byte 3)" hexmask.long.byte 0x1C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32 (byte 4)" hexmask.long.byte 0x1C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40 (byte 5)" line.long 0x20 "P2_SEND_PERCENT,CPSW PORT 2 transmit queue send percentages" hexmask.long.byte 0x20 16.--22. 1. "PRI3_SEND_PERCENT,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) when theCPSW_PTYPE[21] P2_PRI3_SHAPE_EN is set (queue shaping enabled)" hexmask.long.byte 0x20 8.--14. 1. "PRI2_SEND_PERCENT,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) when theCPSW_PTYPE[20] P2_PRI2_SHAPE_EN is set (queue shaping enabled)" hexmask.long.byte 0x20 0.--6. 1. "PRI1_SEND_PERCENT,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[19] P2_PRI1_SHAPE_EN is set (queue shaping enabled)" group.long 0x230++0x27 line.long 0x00 "P2_RX_DSCP_PRI_MAP0,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x00 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x04 "P2_RX_DSCP_PRI_MAP1,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x04 28.--30. "PRI15,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. "PRI14,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. "PRI13,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. "PRI12,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 12.--14. "PRI11,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. "PRI10,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--6. "PRI9,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. "PRI8,Priority" "0,1,2,3,4,5,6,7" line.long 0x08 "P2_RX_DSCP_PRI_MAP2,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x08 28.--30. "PRI23,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 24.--26. "PRI22,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20.--22. "PRI21,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. "PRI20,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 12.--14. "PRI19,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "PRI18,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "PRI17,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. "PRI16,Priority" "0,1,2,3,4,5,6,7" line.long 0x0C "P2_RX_DSCP_PRI_MAP3,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0C 28.--30. "PRI31,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 24.--26. "PRI30,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 20.--22. "PRI29,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 16.--18. "PRI28,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 12.--14. "PRI27,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8.--10. "PRI26,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 4.--6. "PRI25,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. "PRI24,Priority" "0,1,2,3,4,5,6,7" line.long 0x10 "P2_RX_DSCP_PRI_MAP4,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x10 28.--30. "PRI39,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "PRI38,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 20.--22. "PRI37,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. "PRI36,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 12.--14. "PRI35,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--10. "PRI34,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 4.--6. "PRI33,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. "PRI32,Priority" "0,1,2,3,4,5,6,7" line.long 0x14 "P2_RX_DSCP_PRI_MAP5,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x14 28.--30. "PRI47,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "PRI46,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 20.--22. "PRI45,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 16.--18. "PRI44,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 12.--14. "PRI43,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 8.--10. "PRI42,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 4.--6. "PRI41,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x14 0.--2. "PRI40,Priority" "0,1,2,3,4,5,6,7" line.long 0x18 "P2_RX_DSCP_PRI_MAP6,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x18 28.--30. "PRI55,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "PRI54,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 20.--22. "PRI53,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 16.--18. "PRI52,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 12.--14. "PRI51,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 8.--10. "PRI50,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 4.--6. "PRI49,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "PRI48,Priority" "0,1,2,3,4,5,6,7" line.long 0x1C "P2_RX_DSCP_PRI_MAP7,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x1C 28.--30. "PRI63,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 24.--26. "PRI62,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 20.--22. "PRI61,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16.--18. "PRI60,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 12.--14. "PRI59,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8.--10. "PRI58,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "PRI57,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "PRI56,Priority" "0,1,2,3,4,5,6,7" line.long 0x20 "P2_IDLE2LPI,Port 2 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x20 0.--19. 1. "P2_IDLE2LPI,Port 2 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted this value is loaded into the port 2 idle to LPI counter on each clock that the port 2 transmit is not idle" line.long 0x24 "P2_LPI2WAKE,Port 2 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x24 0.--19. 1. "P2_LPI2WAKE,Port 2 EEE LPI to wake counter load value - When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted this value is loaded into the port 2 LPI to wake counter" tree.end repeat 2. (list 1. 2. )(list ad:0x48484D80 ad:0x48484DC0 ) tree "SL$1" base $2 rgroup.long 0x00++0x2B line.long 0x00 "SL_IDVER,CPGMAC_SL revision register" line.long 0x04 "SL_MACCONTROL,CPGMAC_SL MAC control register" bitfld.long 0x04 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory" "0,1" bitfld.long 0x04 23. "RX_CSF_EN,RX Copy Short Frames Enable - Enables frames or fragments shorter than 64 bytes to be copied to memory" "0,1" bitfld.long 0x04 22. "RX_CEF_EN,RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory" "0,1" bitfld.long 0x04 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable When set this bit limits the number of short gap packets transmitted to 100ppm" "0,1" bitfld.long 0x04 18. "EXT_EN,Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the FULLDUPLEX and GIG bits in this register" "0,1" newline bitfld.long 0x04 17. "GIG_FORCE,Gigabit Mode Force - This bit is used to force the CPGMAC_SL into gigabit mode if the input GMII_MTCLK has been stopped by the PHY" "0,1" bitfld.long 0x04 16. "IFCTL_B,Interface Control B (NOT FUNCTIONAL)" "0,1" bitfld.long 0x04 15. "IFCTL_A,Interface Control A" "0,1" bitfld.long 0x04 11. "CMD_IDLE,Command Idle" "0,1" bitfld.long 0x04 10. "TX_SHORT_GAP_EN,Transmit Short Gap Enable" "0,1" newline bitfld.long 0x04 7. "GIG,Gigabit Mode" "0,1" bitfld.long 0x04 6. "TX_PACE,Transmit Pacing Enable" "0,1" bitfld.long 0x04 5. "GMII_EN,GMII Enable" "0,1" bitfld.long 0x04 4. "TX_FLOW_EN,Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode" "0,1" bitfld.long 0x04 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1" newline bitfld.long 0x04 2. "MTEST,Manufacturing Test mode - This bit must be set to allow writes to theSL_BOFFTEST and SL_RX_PAUSE/SL_TX_PAUSE registers" "0,1" bitfld.long 0x04 1. "LOOPBACK,Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the FULLDUPLEX bit is set or not" "0,1" bitfld.long 0x04 0. "FULLDUPLEX,Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the FULLDUPLEX bit is set or not" "0,1" line.long 0x08 "SL_MACSTATUS,CPGMAC_SL MAC status register" bitfld.long 0x08 31. "IDLE,CPGMAC_SL IDLE - The CPGMAC_SL is in the idle state (valid after an idle command)" "0,1" bitfld.long 0x08 4. "EXT_GIG,External GIG - This is the value of the EXT_GIG input bit" "0,1" bitfld.long 0x08 3. "EXT_FULLDUPLEX,External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit" "0,1" bitfld.long 0x08 1. "RX_FLOW_ACT,Receive Flow Control Active - When asserted indicates that receive flow control is enabled and triggered" "0,1" bitfld.long 0x08 0. "TX_FLOW_ACT,Transmit Flow Control Active - When asserted this bit indicates that the pause time period is being observed for a received pause frame" "0,1" line.long 0x0C "SL_SOFT_RESET,CPGMAC_SL soft reset register" bitfld.long 0x0C 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPGMAC_SL logic to be reset" "0,1" line.long 0x10 "SL_RX_MAXLEN,CPGMAC_SL RX Maximum length register" hexmask.long.word 0x10 0.--13. 1. "RX_MAXLEN,RX Maximum Frame Length - This field determines the maximum length of a received frame" line.long 0x14 "SL_BOFFTEST,CPGMAC_SL backoff test register" bitfld.long 0x14 26.--30. "PACEVAL,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x14 16.--25. 1. "RNDNUM,Backoff Random Number Generator - This field allows the Backoff Random Number Generator to be read (or written in test mode only)" rbitfld.long 0x14 12.--15. "COLL_COUNT,Collision Count - The number of collisions the current frame has experienced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x14 0.--9. 1. "TX_BACKOFF,Backoff Count - This field allows the current value of the backoff counter to be observed for test purposes" line.long 0x18 "SL_RX_PAUSE,CPGMAC_SL receive pause timer register" hexmask.long.word 0x18 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode)" line.long 0x1C "SL_TX_PAUSE,CPGMAC_SL transmit pause timer register" hexmask.long.word 0x1C 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode)" line.long 0x20 "SL_EMCONTROL,CPGMAC_SL emulation control register" bitfld.long 0x20 1. "SOFT,Emulation Soft Bit" "0,1" bitfld.long 0x20 0. "FREE,Emulation Free Bit" "0,1" line.long 0x24 "SL_RX_PRI_MAP,CPGMAC_SL RX packet priority to header priority mapping register" bitfld.long 0x24 28.--30. "PRI7,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 24.--26. "PRI6,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 20.--22. "PRI5,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 16.--18. "PRI4,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 12.--14. "PRI3,Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 8.--10. "PRI2,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 4.--6. "PRI1,Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--2. "PRI0,Priority" "0,1,2,3,4,5,6,7" line.long 0x28 "SL_TX_GAP,Transmit inter-packet gap register" hexmask.long.word 0x28 0.--8. 1. "TX_GAP,Transmit Inter-Packet Gap" tree.end repeat.end tree "SS" base ad:0x48484000 rgroup.long 0x00++0x37 line.long 0x00 "CPSW_ID_VER,CPSW_3G ID version register" line.long 0x04 "CPSW_CONTROL,Switch control register" bitfld.long 0x04 4. "EEE_EN,EEE (Energy Efficient Ethernet) enable 0 - EEE is disabled" "0,1" bitfld.long 0x04 3. "DLR_EN,DLR enable" "0,1" bitfld.long 0x04 2. "RX_VLAN_ENCAP,Port 0 VLAN Encapsulation (egress)" "0,1" bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "0,1" bitfld.long 0x04 0. "FIFO_LOOPBACK,FIFO Loopback Mode" "0,1" line.long 0x08 "CPSW_SOFT_RESET,Soft reset register" bitfld.long 0x08 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the 3G logic to be reset" "0,1" line.long 0x0C "CPSW_STAT_PORT_EN,Statistics port enable register" bitfld.long 0x0C 2. "P2_STAT_EN,Port 2 (GMII2 and Port 2 FIFO) Statistics Enable" "0,1" bitfld.long 0x0C 1. "P1_STAT_EN,Port 1 (GMII1 and Port 1 FIFO) Statistics Enable" "0,1" bitfld.long 0x0C 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1" line.long 0x10 "CPSW_PTYPE,Transmit priority type register" bitfld.long 0x10 21. "P2_PRI3_SHAPE_EN,Port 2 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3" "0,1" bitfld.long 0x10 20. "P2_PRI2_SHAPE_EN,Port 2 Queue Priority 2 Transmit Shape Enable - If there are two shaping queues then they must be priorities 3 and 2" "0,1" bitfld.long 0x10 19. "P2_PRI1_SHAPE_EN,Port 2 Queue Priority 1 Transmit Shape Enable - If there are three shaping queues all three bits should be set" "0,1" bitfld.long 0x10 18. "P1_PRI3_SHAPE_EN,Port 1 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3" "0,1" bitfld.long 0x10 17. "P1_PRI2_SHAPE_EN,Port 1 Queue Priority 2 Transmit Shape Enable- If there are two shaping queues then they must be priorities 3 and 2" "0,1" bitfld.long 0x10 16. "P1_PRI1_SHAPE_EN,Port 1 Queue Priority 1 Transmit Shape Enable- If there are three shaping queues all three bits should be set" "0,1" newline bitfld.long 0x10 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1" bitfld.long 0x10 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1" bitfld.long 0x10 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1" bitfld.long 0x10 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value When a port is in escalate priority this is the number of higher priority packets sent before the next lower priority is allowed to send a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "CPSW_SOFT_IDLE,Software idle" bitfld.long 0x14 0. "SOFT_IDLE,Software Idle - Setting this bit causes the switch fabric to stop forwarding packets at the next start of packet" "0,1" line.long 0x18 "CPSW_THRU_RATE,Throughput rate" bitfld.long 0x18 12.--15. "SL_RX_THRU_RATE,CPGMAC_SL Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--3. "CPDMA_THRU_RATE,CPDMA Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "CPSW_GAP_THRESH,CPGMAC_SL short gap threshold" bitfld.long 0x1C 0.--4. "GAP_THRESH,CPGMAC_SL Short Gap Threshold - This is the CPGMAC_SL associated FIFO transmit block usage value for triggering TX_SHORT_GAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "CPSW_TX_START_WDS,Transmit start words" hexmask.long.word 0x20 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit (egress) Start Words" line.long 0x24 "CPSW_FLOW_CONTROL,Flow control" bitfld.long 0x24 2. "P2_FLOW_EN,Port 2 Receive flow control enable" "0,1" bitfld.long 0x24 1. "P1_FLOW_EN,Port 1 Receive flow control enable" "0,1" bitfld.long 0x24 0. "P0_FLOW_EN,Port 0 Receive flow control enable" "0,1" line.long 0x28 "CPSW_VLAN_LTYPE,LTYPE1 and LTYPE 2 Register" hexmask.long.word 0x28 16.--31. 1. "VLAN_LTYPE2,Time Sync VLAN LTYPE2 This VLAN LTYPE value is used for tx and rx" hexmask.long.word 0x28 0.--15. 1. "VLAN_LTYPE1,Time Sync VLAN LTYPE1 This VLAN LTYPE value is used for tx and rx" line.long 0x2C "CPSW_TS_LTYPE,VLAN_LTYPE1 and VLAN_LTYPE2 Register" hexmask.long.word 0x2C 16.--31. 1. "TS_LTYPE2,Time Sync LTYPE2 This is an Ethertype value to match for tx and rx time sync packets" hexmask.long.word 0x2C 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1 This is an ethertype value to match for tx and rx time sync packets" line.long 0x30 "CPSW_DLR_LTYPE,DLR LTYPE register" hexmask.long.word 0x30 0.--15. 1. "DLR_LTYPE,DLR LTYPE" line.long 0x34 "CPSW_EEE_PRESCALE,EEE Pre-scale Counter Load Value Register" hexmask.long.word 0x34 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value - This value is loaded into the EEE pre-scale counter each time the pre-scale count decrements to zero" tree.end tree "STATERAM" base ad:0x48484A00 group.long 0x00++0x7F line.long 0x00 "TX0_HDP,CPDMA_STATERAM TX channel 0 head descriptor pointer" line.long 0x04 "TX1_HDP,CPDMA_STATERAM TX channel 1 head descriptor pointer" line.long 0x08 "TX2_HDP,CPDMA_STATERAM TX channel 2 head descriptor pointer" line.long 0x0C "TX3_HDP,CPDMA_STATERAM TX channel 3 head descriptor pointer" line.long 0x10 "TX4_HDP,CPDMA_STATERAM TX channel 4 head descriptor pointer" line.long 0x14 "TX5_HDP,CPDMA_STATERAM TX channel 5 head descriptor pointer" line.long 0x18 "TX6_HDP,CPDMA_STATERAM TX channel 6 head descriptor pointer" line.long 0x1C "TX7_HDP,CPDMA_STATERAM TX channel 7 head descriptor pointer" line.long 0x20 "RX0_HDP,CPDMA_STATERAM RX 0 channel 0 head descriptor pointer" line.long 0x24 "RX1_HDP,CPDMA_STATERAM RX 1 channel 1 head descriptor pointer" line.long 0x28 "RX2_HDP,CPDMA_STATERAM RX 2 channel 2 head descriptor pointer" line.long 0x2C "RX3_HDP,CPDMA_STATERAM RX 3 channel 3 head descriptor pointer" line.long 0x30 "RX4_HDP,CPDMA_STATERAM RX 4 channel 4 head descriptor pointer" line.long 0x34 "RX5_HDP,CPDMA_STATERAM RX 5 channel 5 head descriptor pointer" line.long 0x38 "RX6_HDP,CPDMA_STATERAM RX 6 channel 6 head desc pointer" line.long 0x3C "RX7_HDP,CPDMA_STATERAM RX 7 channel 7 head desc pointer" line.long 0x40 "TX0_CP,CPDMA_STATERAM TX channel 0 completion pointer register" line.long 0x44 "TX1_CP,CPDMA_STATERAM TX channel 1 completion pointer register" line.long 0x48 "TX2_CP,CPDMA_STATERAM TX channel 2 completion pointer register" line.long 0x4C "TX3_CP,CPDMA_STATERAM TX channel 3 completion pointer register" line.long 0x50 "TX4_CP,CPDMA_STATERAM TX channel 4 completion pointer register" line.long 0x54 "TX5_CP,CPDMA_STATERAM TX channel 5 completion pointer register" line.long 0x58 "TX6_CP,CPDMA_STATERAM TX channel 6 completion pointer register" line.long 0x5C "TX7_CP,CPDMA_STATERAM TX channel 7 completion pointer register" line.long 0x60 "RX0_CP,CPDMA_STATERAM RX channel 0 completion pointer register" line.long 0x64 "RX1_CP,CPDMA_STATERAM RX channel 1 completion pointer register" line.long 0x68 "RX2_CP,CPDMA_STATERAM RX channel 2 completion pointer register" line.long 0x6C "RX3_CP,CPDMA_STATERAM RX channel 3 completion pointer register" line.long 0x70 "RX4_CP,CPDMA_STATERAM RX channel 4 completion pointer register" line.long 0x74 "RX5_CP,CPDMA_STATERAM RX channel 5 completion pointer register" line.long 0x78 "RX6_CP,CPDMA_STATERAM RX channel 6 completion pointer register" line.long 0x7C "RX7_CP,CPDMA_STATERAM RX channel 7 completion pointer register" tree.end tree "WR" base ad:0x48485200 rgroup.long 0x00++0x1F line.long 0x00 "WR_IDVER,Subsystem wrapper revision register" line.long 0x04 "WR_SOFT_RESET,Subsystem soft reset register" bitfld.long 0x04 0. "SOFT_RESET,Software reset - Writing a one to this bit causes the CPGMACSS_R logic to be reset (INT REGS CPPI)" "0,1" line.long 0x08 "WR_CONTROL,Subsystem control register" bitfld.long 0x08 8. "SS_EEE_EN,Subsystem Energy Efficient Ethernet enable" "0,1" bitfld.long 0x08 2.--3. "MMR_STDBYMODE,Configuration of the local initiator state management mode" "MMR_STDBYMODE_0,MMR_STDBYMODE_1,MMR_STDBYMODE_2,MMR_STDBYMODE_3" bitfld.long 0x08 0.--1. "MMR_IDLEMODE,Configuration of the local initiator state management mode" "MMR_IDLEMODE_0,MMR_IDLEMODE_1,MMR_IDLEMODE_2,MMR_IDLEMODE_3" line.long 0x0C "WR_INT_CONTROL,Subsystem interrupt control" bitfld.long 0x0C 31. "INT_TEST,Interrupt Test - Test bit to the interrupt pacing blocks" "0,1" bitfld.long 0x0C 16.--21. "INT_PACE_EN,Interrupt Pacing Enable INT_PACE_EN[0] - Enables RX_PULSE Pacing (0 is pacing bypass) INT_PACE_EN[1] - Enables TX_PULSE Pacing (0 is pacing bypass)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0C 0.--11. 1. "INT_PRESCALE,Interrupt Counter Prescaler - The number of MAIN_CLK periods in 4us" line.long 0x10 "WR_C0_RX_THRESH_EN,Subsystem core 0 receive threshold int enable register" hexmask.long.byte 0x10 0.--7. 1. "C0_RX_THRESH_EN,Core 0 Receive Threshold Enable - Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled to generate an interrupt on RX_THRESH_PULSE" line.long 0x14 "WR_C0_RX_EN,Subsystem core 0 receive interrupt enable register" hexmask.long.byte 0x14 0.--7. 1. "C0_RX_EN,Core 0 Receive Enable - Each bit in this register corresponds to the bit in the rx interrupt that is enabled to generate an interrupt on RX_PULSE" line.long 0x18 "WR_C0_TX_EN,Subsystem core 0 transmit interrupt enable register" hexmask.long.byte 0x18 0.--7. 1. "C0_TX_EN,Core 0 Transmit Enable - Each bit in this register corresponds to the bit in the tx interrupt that is enabled to generate an interrupt on TX_PULSE" line.long 0x1C "WR_C0_MISC_EN,Subsystem core 0 misc interrupt enable register" bitfld.long 0x1C 0.--4. "C0_MISC_EN,Core 0 Misc Enable - Each bit in this register corresponds to the miscellaneous interrupt (EVNT_PEND STAT_PEND HOST_PEND MDIO_LINKINT MDIO_USERINT) that is enabled to generate an interrupt on MISC_PULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x40++0x0F line.long 0x00 "WR_C0_RX_THRESH_STAT,Subsystem core 0 rx threshold masked int status register" hexmask.long.byte 0x00 0.--7. 1. "C0_RX_THRESH_STAT,Core 0 Receive Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the receive threshold interrupt that is enabled and generating an interrupt on RX_THRESH_PULSE" line.long 0x04 "WR_C0_RX_STAT,Subsystem core 0 rx interrupt masked int status register" hexmask.long.byte 0x04 0.--7. 1. "C0_RX_STAT,Core 0 Receive Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on RX_PULSE" line.long 0x08 "WR_C0_TX_STAT,Subsystem core 0 tx interrupt masked int status register" hexmask.long.byte 0x08 0.--7. 1. "C0_TX_STAT,Core 0 Transmit Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on TX_PULSE" line.long 0x0C "WR_C0_MISC_STAT,Subsystem core 0 misc interrupt masked int status register" bitfld.long 0x0C 0.--4. "C0_MISC_STAT,Core 0 Misc Masked Interrupt Status - Each bit in this register corresponds to the miscellaneous interrupt (EVNT_PEND STAT_PEND HOST_PEND MDIO_LINKINT MDIO_USERINT) that is enabled and generating an interrupt on MISC_PULSE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x70++0x07 line.long 0x00 "WR_C0_RX_IMAX,Subsystem core 0 receive interrupts per millisecond" bitfld.long 0x00 0.--5. "C0_RX_IMAX,Core 0 Receive Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on RX_PULSE if pacing is enabled for this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "WR_C0_TX_IMAX,Subsystem core 0 transmit interrupts per millisecond" bitfld.long 0x04 0.--5. "C0_TX_IMAX,Core 0 Transmit Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on TX_PULSE if pacing is enabled for this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x88++0x03 line.long 0x00 "WR_RGMII_CTL,RGMII control signal register" bitfld.long 0x00 7. "RGMII2_FULLDUPLEX,RGMII 2 Fullduplex - This is the CPRGMII fullduplex output signal" "0,1" bitfld.long 0x00 5.--6. "RGMII2_SPEED,RGMII2 Speed - This is the CPRGMII speed output signal" "0,1,2,3" bitfld.long 0x00 4. "RGMII2_LINK,RGMII2 Link Indicator - This is the CPRGMII link output signal" "0,1" bitfld.long 0x00 3. "RGMII1_FULLDUPLEX,RGMII1 Fullduplex - This is the CPRGMII fullduplex output signal" "0,1" newline bitfld.long 0x00 1.--2. "RGMII1_SPEED,RGMII1 Speed - This is the CPRGMII speed output signal" "0,1,2,3" bitfld.long 0x00 0. "RGMII1_LINK,RGMII1 Link Indicator - This is the CPRGMII link output signal" "0,1" tree.end tree.end tree.open "GPU" tree "GPU_WRAPPER" base ad:0x5600FE00 rgroup.long 0x00++0x07 line.long 0x00 "REVISION,Revision register" line.long 0x04 "HWINFO,Hardware implementation information" bitfld.long 0x04 2. "MEM_BUS_WIDTH,Memory bus width" "0,1" bitfld.long 0x04 0.--1. "SYS_BUS_WIDTH,System bus width" "0,1,2,3" group.long 0x10++0x03 line.long 0x00 "SYSCONFIG,System configuration register" bitfld.long 0x00 4.--5. "STANDBY_MODE,Clock standby mode" "0,1,2,3" bitfld.long 0x00 2.--3. "IDLE_MODE,Clock idle mode" "0,1,2,3" group.long 0x24++0x2F line.long 0x00 "IRQSTATUS_RAW_0,Raw IRQ 0 status" bitfld.long 0x00 0. "INIT_MINTERRUPT_RAW,Interrupt 0 raw event: Write" "0,1" line.long 0x04 "IRQSTATUS_RAW_1,Raw IRQ 1 status" bitfld.long 0x04 0. "TARGET_SINTERRUPT_RAW,Interrupt 1 raw event: Write" "0,1" line.long 0x08 "IRQSTATUS_RAW_2,Raw IRQ 2 status" bitfld.long 0x08 0. "THALIA_IRQ_RAW,Interrupt 0 raw event: Write" "0,1" line.long 0x0C "IRQSTATUS_0,Interrupt 0 status event" bitfld.long 0x0C 0. "INIT_MINTERRUPT_STATUS,Interrupt 0 raw event: Write" "0,1" line.long 0x10 "IRQSTATUS_1,Interrupt" bitfld.long 0x10 0. "TARGET_SINTERRUPT_STATUS,Interrupt 0 raw event: Write" "0,1" line.long 0x14 "IRQSTATUS_2,Interrupt" bitfld.long 0x14 0. "THALIA_IRQ_STATUS,Interrupt 0 raw event: Write" "0,1" line.long 0x18 "IRQENABLE_SET_0,Enable Interrupt" bitfld.long 0x18 0. "INIT_MINTERRUPT_ENABLE,To enable interrupt: Write" "0,1" line.long 0x1C "IRQENABLE_SET_1,Enable Interrupt 1" bitfld.long 0x1C 0. "TARGET_SINTERRUPT_ENABLE,To enable interrupt: Write" "0,1" line.long 0x20 "IRQENABLE_SET_2,Enable Interrupt 2" bitfld.long 0x20 0. "THALIA_IRQ_ENABLE,To enable interrupt: Write" "0,1" line.long 0x24 "IRQENABLE_CLR_0,Disable Interrupt" bitfld.long 0x24 0. "INIT_MINTERRUPT_DISABLE,To disable interrupt: Write" "0,1" line.long 0x28 "IRQENABLE_CLR_1,Disable Interrupt" bitfld.long 0x28 0. "TARGET_SINTERRUPT_DISABLE,To disable interrupt: Write" "0,1" line.long 0x2C "IRQENABLE_CLR_2,Disable Interrupt" bitfld.long 0x2C 0. "THALIA_IRQ_DISABLE,To disable interrupt: Write" "0,1" group.long 0x100++0x13 line.long 0x00 "PAGE_CONFIG,Configure memory pages" bitfld.long 0x00 31. "THALIA_INT_BYPASS,Bypass OCP IPG interrupt logic" "0,1" bitfld.long 0x00 3.--4. "OCP_PAGE_SIZE,Defines the page size on OCP memory interface" "0,1,2,3" bitfld.long 0x00 2. "MEM_PAGE_CHECK_EN,To enable page boundary" "0,1" bitfld.long 0x00 0.--1. "MEM_PAGE_SIZE,Defines the page size on internal memory interface" "0,1,2,3" line.long 0x04 "INTERRUPT_EVENT,Interrupt events" bitfld.long 0x04 18. "TARGET_INVALID_OCP_CMD,Invalid command from OCP: Write" "0,1" bitfld.long 0x04 17. "TARGET_CMD_FIFO_FULL,Command FIFO full: Write" "0,1" bitfld.long 0x04 16. "TARGET_RESP_FIFO_FULL,Response FIFO full: Write" "0,1" bitfld.long 0x04 13. "INT_MEM_REQ_FIFO_OVERRUN_1,Memory request FIFO overrun: Write" "0,1" newline bitfld.long 0x04 12. "INIT_READ_TAG_FIFO_OVERRUN_1,Read tag FIFO overrun: Write" "0,1" bitfld.long 0x04 11. "INIT_PAGE_CROSS_ERROR_1,Memory page had been crossed during a burst: Write" "0,1" bitfld.long 0x04 10. "INIT_RESP_ERROR_1,Receiving error response: Write" "0,1" bitfld.long 0x04 9. "INIT_RESP_UNUSED_TAG_1,Receiving response on an unused OCP TAG: Write" "0,1" newline bitfld.long 0x04 8. "INIT_RESP_UNEXPECTED_1,Receiving response when not expected: Write" "0,1" bitfld.long 0x04 5. "INIT_MEM_REQ_FIFO_OVERRUN_0,Memory request FIFO overrun;" "0,1" bitfld.long 0x04 4. "INIT_READ_TAG_FIFO_OVERRUN_0,Read tag FIFO overrun: Write" "0,1" bitfld.long 0x04 3. "INIT_PAGE_CROSS_ERROR_0,Memory page had been crossed during a burst" "0,1" newline bitfld.long 0x04 2. "INIT_RESP_ERROR_0,Receiving error response: Write" "0,1" bitfld.long 0x04 1. "INIT_RESP_UNUSED_TAG_0,Receiving response on an unused OCP TAG: Write" "0,1" bitfld.long 0x04 0. "INIT_RESP_UNEXPECTED_0,Receiving response when not expected: Write" "0,1" line.long 0x08 "DEBUG_CONFIG,Configuration of debug modes" bitfld.long 0x08 5. "SELECT_INT_IDLE,To select which idle the disconnect protocol should act on" "0,1" bitfld.long 0x08 4. "FORCE_PASS_DATA,Forces the initiator to pass data independent of disconnect protocol" "0,1" bitfld.long 0x08 2.--3. "FORCE_INIT_IDLE,Forces initiator idle: 0x0 " "0,1,2,3" bitfld.long 0x08 0.--1. "FORCE_TARGET_IDLE,Forces target idle: 0x0 " "0,1,2,3" line.long 0x0C "DEBUG_STATUS_0,Port0 debug status register" bitfld.long 0x0C 31. "CMD_DEBUG_STATE,Target command state-machine" "0,1" bitfld.long 0x0C 30. "CMD_RESP_DEBUG_STATE,Target response state-machine" "0,1" bitfld.long 0x0C 29. "TARGET_IDLE,Target idle" "0,1" bitfld.long 0x0C 28. "RESP_FIFO_FULL,Target response FIFO full" "0,1" newline bitfld.long 0x0C 27. "CMD_FIFO_FULL,Target command FIFO full" "0,1" bitfld.long 0x0C 26. "RESP_ERROR,Respond to OCP with error which could be caused by either address misalignment or invalid byte enable" "0,1" bitfld.long 0x0C 21.--25. "WHICH_TARGET_REGISTER,Indicates which OCP target registers to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 18.--20. "TARGET_CMD_OUT,Command received from OCP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 17. "INIT_MSTANDBY,Status of init_MStandby signal" "0,1" bitfld.long 0x0C 16. "INIT_MWAIT,Status of init_MWait signal" "0,1" bitfld.long 0x0C 15. "INIT_MDISCREQ,Request to disconnect from OCP interface" "0,1" bitfld.long 0x0C 13.--14. "INIT_MDISCACK,Disconnect status of the OCP interface" "0,1,2,3" newline bitfld.long 0x0C 12. "INIT_SCONNECT_2,Defines whether to wait in M_WAIT state for MConnect FSM" "0,1" bitfld.long 0x0C 11. "INIT_SCONNECT_1,Defines the busy-ness state of the slave" "0,1" bitfld.long 0x0C 10. "INIT_SCONNECT_0,Disconnect from slave" "0,1" bitfld.long 0x0C 8.--9. "INIT_MCONNECT,Initiator MConnect state" "0,1,2,3" newline bitfld.long 0x0C 6.--7. "TARGET_SIDLEACK,Acknowledge the SIdleAck state-machine" "0,1,2,3" bitfld.long 0x0C 4.--5. "TARGET_SDISCACK,Acknowledge the SDiscAck state-machine" "0,1,2,3" bitfld.long 0x0C 3. "TARGET_SIDLEREQ,Request the target to go idle: 0 Do not go idle or go active 1 Go idle" "0,1" bitfld.long 0x0C 2. "TARGET_SCONNECT,Target SConnect bit 0 state" "0,1" newline bitfld.long 0x0C 0.--1. "TARGET_MCONNECT,Target MConnect state" "0,1,2,3" line.long 0x10 "DEBUG_STATUS_1,Port1 debug status register" bitfld.long 0x10 31. "CMD_DEBUG_STATE,Target command state-machine" "0,1" bitfld.long 0x10 30. "CMD_RESP_DEBUG_STATE,Target response state-machine" "0,1" bitfld.long 0x10 29. "TARGET_IDLE,Target idle" "0,1" bitfld.long 0x10 28. "RESP_FIFO_FULL,Target response FIFO full" "0,1" newline bitfld.long 0x10 27. "CMD_FIFO_FULL,Target command FIFO full" "0,1" bitfld.long 0x10 26. "RESP_ERROR,Respond to OCP with error which could be caused by either address misalignment or invalid byte enable" "0,1" bitfld.long 0x10 21.--25. "WHICH_TARGET_REGISTER,Indicates which OCP target registers to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 18.--20. "TARGET_CMD_OUT,Command received from OCP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 17. "INIT_MSTANDBY,Status of init_MStandby signal" "0,1" bitfld.long 0x10 16. "INIT_MWAIT,Status of init_MWait signal" "0,1" bitfld.long 0x10 15. "INIT_MDISCREQ,Request to disconnect from OCP interface" "0,1" bitfld.long 0x10 13.--14. "INIT_MDISCACK,Disconnect status of the OCP interface" "0,1,2,3" newline bitfld.long 0x10 12. "INIT_SCONNECT_2,Defines whether to wait in M_WAIT state for MConnect FSM" "0,1" bitfld.long 0x10 11. "INIT_SCONNECT_1,Defines the busy-ness state of the slave" "0,1" bitfld.long 0x10 10. "INIT_SCONNECT_0,Disconnect from slave" "0,1" bitfld.long 0x10 8.--9. "INIT_MCONNECT,Initiator MConnect state" "0,1,2,3" newline bitfld.long 0x10 6.--7. "TARGET_SIDLEACK,Acknowledge the SIdleAck state-machine" "0,1,2,3" bitfld.long 0x10 4.--5. "TARGET_SDISCACK,Acknowledge the SDiscAck state-machine" "0,1,2,3" bitfld.long 0x10 3. "TARGET_SIDLEREQ,Request the target to go idle" "0,1" bitfld.long 0x10 2. "TARGET_SCONNECT,Target SConnect bit 0 state" "0,1" newline bitfld.long 0x10 0.--1. "TARGET_MCONNECT,Target MConnect state" "0,1,2,3" tree.end tree.end tree.open "HDQ_1_Wire" tree "HDQ1W" base ad:0x480B2000 rgroup.long 0x00++0x1B line.long 0x00 "HDQ_REVISION,This register contains the IP revision code" line.long 0x04 "HDQ_TX_DATA,This register contains the data to be transmitted" hexmask.long.byte 0x04 0.--7. 1. "TX_DATA,Transmit data (used in both HDQ and 1-Wire modes)" line.long 0x08 "HDQ_RX_DATA,This register contains the data to be received" hexmask.long.byte 0x08 0.--7. 1. "RX_DATA,Receive data (used in both HDQ and 1-Wire modes)" line.long 0x0C "HDQ_CTRL_STATUS,This register provides status information about the module" bitfld.long 0x0C 8.--10. "BITFSM,BITFSM delay value in 1.33 micros steps" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 7. "ONE_WIRE_SINGLE_BIT,Single-bit mode for 1-Wire" "ONE_WIRE_SINGLE_BIT_0,ONE_WIRE_SINGLE_BIT_1" bitfld.long 0x0C 6. "INTERRUPTMASK,Interrupt masking bit" "INTERRUPTMASK_0,INTERRUPTMASK_1" newline bitfld.long 0x0C 5. "CLOCKENABLE,Power-down mode bit" "CLOCKENABLE_0,CLOCKENABLE_1" bitfld.long 0x0C 4. "GO,Go bit" "GO_0,GO_1" rbitfld.long 0x0C 3. "PRESENCEDETECT,Slave presence indicator" "PRESENCEDETECT_0,PRESENCEDETECT_1" newline bitfld.long 0x0C 2. "INITIALIZATION,Write 1 to send initialization pulse" "INITIALIZATION_0,INITIALIZATION_1" bitfld.long 0x0C 1. "DIR,DIR bit determines if next command is read or write" "DIR_0,DIR_1" bitfld.long 0x0C 0. "MODE,Mode selection bit" "MODE_0,MODE_1" line.long 0x10 "HDQ_INT_STATUS,This register controls interrupts status" bitfld.long 0x10 2. "TXCOMPLETE,TX-complete interrupt flag" "TXCOMPLETE_0,TXCOMPLETE_1" bitfld.long 0x10 1. "RXCOMPLETE,Read-complete interrupt flag" "RXCOMPLETE_0,RXCOMPLETE_1" bitfld.long 0x10 0. "TIMEOUT,Presence detect/timeout interrupt flag" "TIMEOUT_0,TIMEOUT_1" line.long 0x14 "HDQ_SYSCONFIG,This register controls various bits" bitfld.long 0x14 1. "SOFTRESET,Start soft reset sequence" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x14 0. "AUTOIDLE,Interconnect idle" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x18 "HDQ_SYSSTATUS,This register monitors the reset sequence" bitfld.long 0x18 0. "RESETDONE,Reset monitoring" "RESETDONE_0,RESETDONE_1" tree.end tree.end tree.open "IVA_CALCulation_Engine_3" tree "CALC3_BFSW_L3_MAINInterconnect" base ad:0x5A058200 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View mode register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_CALCROBUF,View mode selection for CALCROBUF" "0,1" bitfld.long 0x00 0. "VIEW_CALCRPBUF,View mode selection for CALCRPBUF" "0,1" line.long 0x04 "MSTID1,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_CALCROBUF_B,Master selection for CALCROBUF B" "0,1" bitfld.long 0x04 2. "MST_CALCROBUF_A,Master selection for CALCROBUF A" "0,1" bitfld.long 0x04 1. "MST_CALCRPBUF_B,Master selection for CALCRPBUF B" "0,1" bitfld.long 0x04 0. "MST_CALCRPBUF_A,Master selection for CALCRPBUF A" "0,1" line.long 0x08 "MSTID2,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x08 2.--31. 1. "RSRV,Reserved" bitfld.long 0x08 1. "MST_CALCWBUF,Master selection for CALCWBUF" "0,1" bitfld.long 0x08 0. "MST_CALCQBUF,Master selection for CALCQBUF" "0,1" tree.end tree "CALC3_IPGW_L3_MAINInterconnect" base ad:0x5A058400 group.long 0x08++0x07 line.long 0x00 "CALC3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" line.long 0x04 "CALC3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "CALC3_IPQSTATUS_RAW_0,Per-event raw interrupt status vector. int_end load (LSE)" bitfld.long 0x00 0. "EVENT0,Settable raw status for int_end load (LSE)" "EVENT0_0,EVENT0_1" line.long 0x04 "CALC3_IPQSTATUS_RAW_1,Per-event raw interrupt status vector. int_end (CALC3 core)" bitfld.long 0x04 0. "EVENT0,Settable raw status for int_end (CALC3 core)" "EVENT0_0,EVENT0_1" line.long 0x08 "CALC3_IPQSTATUS_RAW_2,Per-event raw interrupt status vector. int_end store (LSE)" bitfld.long 0x08 0. "EVENT0,Settable raw status for int_end store (LSE)" "EVENT0_0,EVENT0_1" line.long 0x0C "CALC3_IPQSTATUS_RAW_3,Per-event raw interrupt status vector. int_undef (LSE)" bitfld.long 0x0C 0. "EVENT0,Settable raw status for int_undef (LSE)" "EVENT0_0,EVENT0_1" group.long 0x30++0x0F line.long 0x00 "CALC3_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. int_end load (LSE)" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for int_end load (LSE)" "EVENT0_0,EVENT0_1" line.long 0x04 "CALC3_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. int_end (CALC3 Core)" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for int_end (CALC3 core)" "EVENT0_0,EVENT0_1" line.long 0x08 "CALC3_IRQSTATUS_2,Per-event 'enabled' interrupt status vector. int_end store (LSE)" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for int_end store (LSE)" "EVENT0_0,EVENT0_1" line.long 0x0C "CALC3_IRQSTATUS_3,Per-event 'enabled' interrupt status vector. int_undef (LSE)" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for int_undef (LSE)" "EVENT0_0,EVENT0_1" group.long 0x4C++0x0F line.long 0x00 "CALC3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. int_end load (LSE)" bitfld.long 0x00 0. "ENABLE0,Enable for int_end load (LSE)" "ENABLE0_0,ENABLE0_1" line.long 0x04 "CALC3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. int_end (CALC3 core)" bitfld.long 0x04 0. "ENABLE0,Enable for int_end (CALC3 core)" "ENABLE0_0,ENABLE0_1" line.long 0x08 "CALC3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. int_end store (LSE)" bitfld.long 0x08 0. "ENABLE0,Enable for int_end store (LSE)" "ENABLE0_0,ENABLE0_1" line.long 0x0C "CALC3_IRQENABLE_SET_3,Per-event interrupt enable bit vector. int_undef (LSE)" bitfld.long 0x0C 0. "ENABLE0,Enable for int_undef (LSE)" "ENABLE0_0,ENABLE0_1" group.long 0x68++0x0F line.long 0x00 "CALC3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. int_end load (LSE)" bitfld.long 0x00 0. "ENABLE0,Enable for int_end load (LSE)" "ENABLE0_0,ENABLE0_1" line.long 0x04 "CALC3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. int_end (CALC3 core)" bitfld.long 0x04 0. "ENABLE0,Enable for int_end (CALC3 core)" "ENABLE0_0,ENABLE0_1" line.long 0x08 "CALC3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. int_end store (LSE)" bitfld.long 0x08 0. "ENABLE0,Enable for int_end store (LSE)" "ENABLE0_0,ENABLE0_1" line.long 0x0C "CALC3_IRQENABLE_CLR_3,Per-event interrupt enable bit vector. int_undef (LSE)" bitfld.long 0x0C 0. "ENABLE0,Enable for int_undef (LSE)" "ENABLE0_0,ENABLE0_1" group.long 0xC0++0x03 line.long 0x00 "CALC3_IRQSTATUS_ACLREN,Auto Clear enable" bitfld.long 0x00 3. "ACLREN3,For int_undef (LSE)" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,For int_end store (LSE)" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,For int_end (CALC3 core)" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,For int_end load (LSE)" "ACLREN0_0,ACLREN0_1" tree.end tree "CALC3_LSE_L3_MAINInterconnect" base ad:0x5A058300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" tree.end tree "CALC3_MMR_L3_MAINInterconnect" base ad:0x5A058000 rgroup.long 0x00++0x1B line.long 0x00 "CALC_PID,CALC3 PID register" line.long 0x04 "CALC_COUNT,CALC3 cycle counter register" bitfld.long 0x04 31. "CALC_CE,Cycle counter enable [1]: Active [0]: Not active" "CALC_CE_0,CALC_CE_1" bitfld.long 0x04 30. "CALC_CRST,Counter reset [1]: Reset counter [0]: No effect" "CALC_CRST_0,CALC_CRST_1" newline hexmask.long.word 0x04 0.--15. 1. "COUNT,Cycle counter 16-bit counter Cycle counter is increasing during CALC_EN = 1 in CALC_CTRL" line.long 0x08 "CALC_CTRL,CALC3 control register" bitfld.long 0x08 0. "CALC_EN,CALC3 module status and start bit Write [0]: Ignored Write [1]: Start CALC3 module" "CALC_EN_0,CALC_EN_1" line.long 0x0C "CALC_TEST,CALC3 test register It is only for debug purpose" rbitfld.long 0x0C 24. "CALC_CMD_OPECNT,MB counter register for MBAFF mode For H.264 MBAFF this status bit is used for CALC3 core and command wrapper" "CALC_CMD_OPECNT_0,CALC_CMD_OPECNT_1" bitfld.long 0x0C 13. "CALC_CMD_MNG_DIS,CALC3 command wrapper function of data management (that is neighboring pixel copying) disable flag" "CALC_CMD_MNG_DIS_0,CALC_CMD_MNG_DIS_1" newline bitfld.long 0x0C 12. "CALC_CMD_GEN_DIS,CALC3 command wrapper function of CALC3 core specific command generation disable flag" "CALC_CMD_GEN_DIS_0,CALC_CMD_GEN_DIS_1" bitfld.long 0x0C 6. "CALC_2ND_MB_DIS,CALC3 2nd Mb disable flag ( it is effective only for MBAFF ) [1]: 2nd Mb operation for MBAFF is disable for CALC3 core and command wrapper [0]: 2nd Mb operation for MBAFF is enable for CALC3 core and command wrapper" "CALC_2ND_MB_DIS_0,CALC_2ND_MB_DIS_1" newline bitfld.long 0x0C 5. "CALC_TIT_DIS,CALC3 transform function disable flag [1]: Transform function is skipped in CALC3 core" "CALC_TIT_DIS_0,CALC_TIT_DIS_1" bitfld.long 0x0C 4. "CALC_QIQ_DIS,CALC3 QIQ function disable flag [1]: QIQ function is skipped in CALC3 core" "CALC_QIQ_DIS_0,CALC_QIQ_DIS_1" newline bitfld.long 0x0C 0. "CALC_CORE_DIS,CALC3 core disable flag" "CALC_CORE_DIS_0,CALC_CORE_DIS_1" line.long 0x10 "CALC_MODE,CALC3 mode select register" bitfld.long 0x10 31. "CALC_H263_ANNEXI,In H.264[0] : Intra_8x8 Pre-Filter is active" "CALC_H263_ANNEXI_0,CALC_H263_ANNEXI_1" bitfld.long 0x10 30. "CALC_MPEG4_QUANT_TYPE,MPEG-4 QuantType set flag - It is effective for MPEG-4 only" "CALC_MPEG4_QUANT_TYPE_0,CALC_MPEG4_QUANT_TYPE_1" newline bitfld.long 0x10 29. "CALC_VC1_NONUNIQUANT,VC-1 NonUniformQuantize set flag - It is effective for VC-1 only" "CALC_VC1_NONUNIQUANT_0,CALC_VC1_NONUNIQUANT_1" bitfld.long 0x10 28. "CALC_VC1_DC_DEF_NONZERO,VC-1 DcDefaultNonZero set flag - It is effective for VC-1 only" "CALC_VC1_DC_DEF_NONZERO_0,CALC_VC1_DC_DEF_NONZERO_1" newline bitfld.long 0x10 24.--27. "CALC_CODEC_TYPE,Codec type set register[0]: JPEG" "CALC_CODEC_TYPE_0,CALC_CODEC_TYPE_1,CALC_CODEC_TYPE_2,CALC_CODEC_TYPE_3,CALC_CODEC_TYPE_4,CALC_CODEC_TYPE_5,CALC_CODEC_TYPE_6,CALC_CODEC_TYPE_7,CALC_CODEC_TYPE_8,CALC_CODEC_TYPE_9,CALC_CODEC_TYPE_10,CALC_CODEC_TYPE_11,CALC_CODEC_TYPE_12,CALC_CODEC_TYPE_13,CALC_CODEC_TYPE_14,CALC_CODEC_TYPE_15" bitfld.long 0x10 23. "CALC_CBPCNT0_INTER_EN,CBPControl #0 enable flag for Inter Block[0]: Disable" "CALC_CBPCNT0_INTER_EN_0,CALC_CBPCNT0_INTER_EN_1" newline bitfld.long 0x10 22. "CALC_CBPCNT0_LUMA_DCTRANS_EN,CBPControl #0 enable flag for Luma DC Trans mode[0]: Disable" "CALC_CBPCNT0_LUMA_DCTRANS_EN_0,CALC_CBPCNT0_LUMA_DCTRANS_EN_1" bitfld.long 0x10 21. "CALC_CBPCNT0_CHRO_DCTRANS_EN,CBPControl #0 enable flag for Chroma DC Trans mode[0]: Disable" "CALC_CBPCNT0_CHRO_DCTRANS_EN_0,CALC_CBPCNT0_CHRO_DCTRANS_EN_1" newline bitfld.long 0x10 20. "CALC_CBPCNT0_INTER_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_INTER_EN - It is effective for CALC_CBPCNT0_INTER_EN = 1" "CALC_CBPCNT0_INTER_THR_0,CALC_CBPCNT0_INTER_THR_1" bitfld.long 0x10 19. "CALC_CBPCNT0_LUMA_DCTRANS_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_LUMA_DCTRANS_EN - It is effective for CALC_CBPCNT0_LUMA_DCTRANS_EN = 1" "CALC_CBPCNT0_LUMA_DCTRANS_THR_0,CALC_CBPCNT0_LUMA_DCTRANS_THR_1" newline bitfld.long 0x10 18. "CALC_CBPCNT0_CHRO_DCTRANS_THR,# of abs ones coeffs threshold for CALC_CBPCNT0_CHRO_DCTRANS_EN - It is effective for CALC_CBPCNT0_CHRO_DCTRANS_EN = 1" "CALC_CBPCNT0_CHRO_DCTRANS_THR_0,CALC_CBPCNT0_CHRO_DCTRANS_THR_1" bitfld.long 0x10 17. "CALC_CBPCNT1_EN,CBP Control #1 enable flag[0]: OFF" "CALC_CBPCNT1_EN_0,CALC_CBPCNT1_EN_1" newline bitfld.long 0x10 16. "CALC_ENC,Enc or Dec mode flag[0]: Dec" "CALC_ENC_0,CALC_ENC_1" bitfld.long 0x10 15. "CALC_MPEG2_QSCLTYPE,q_scale_type of MPEG-2 set register for command wrapper" "CALC_MPEG2_QSCLTYPE_0,CALC_MPEG2_QSCLTYPE_1" newline bitfld.long 0x10 13.--14. "CALC_MPEG2_INTRADCPREC,intra_dc_precision of MPEG-2 set register for command wrapper" "CALC_MPEG2_INTRADCPREC_0,CALC_MPEG2_INTRADCPREC_1,CALC_MPEG2_INTRADCPREC_2,CALC_MPEG2_INTRADCPREC_3" bitfld.long 0x10 12. "CALC_ACPRED_DIS,AC prediction disable flag for command wrapper" "CALC_ACPRED_DIS_0,CALC_ACPRED_DIS_1" newline bitfld.long 0x10 11. "CALC_H264_CONST_INTRA,Constraint intra set of H.264 flag for command wrapper" "CALC_H264_CONST_INTRA_0,CALC_H264_CONST_INTRA_1" bitfld.long 0x10 9.--10. "CALC_PICTCODINGTYPE,Picture coding type set register for command wrapper[0]: I Picture" "CALC_PICTCODINGTYPE_0,CALC_PICTCODINGTYPE_1,CALC_PICTCODINGTYPE_2,CALC_PICTCODINGTYPE_3" newline bitfld.long 0x10 8. "CALC_RECON_16BIT_EN,Reconstruct format flag[0]: 8-bit mode" "CALC_RECON_16BIT_EN_0,CALC_RECON_16BIT_EN_1" bitfld.long 0x10 6.--7. "CALC_VC1_PROFILE,VC-1 Profile register for command wrapper[0]: Simple" "CALC_VC1_PROFILE_0,CALC_VC1_PROFILE_1,CALC_VC1_PROFILE_2,CALC_VC1_PROFILE_3" newline bitfld.long 0x10 5. "CALC_SORENSON_EN,Sorenson Spark setting register" "CALC_SORENSON_EN_0,CALC_SORENSON_EN_1" bitfld.long 0x10 2.--4. "CALC_JPG_FORMAT,JPEG color mode setting register" "CALC_JPG_FORMAT_0,CALC_JPG_FORMAT_1,CALC_JPG_FORMAT_2,CALC_JPG_FORMAT_3,CALC_JPG_FORMAT_4,CALC_JPG_FORMAT_5,CALC_JPG_FORMAT_6,CALC_JPG_FORMAT_7" newline bitfld.long 0x10 0.--1. "CALC_PICT_STRUCT,Picture Structure setting register[0]: Frame structure" "CALC_PICT_STRUCT_0,CALC_PICT_STRUCT_1,CALC_PICT_STRUCT_2,CALC_PICT_STRUCT_3" line.long 0x14 "CALC_FWDQ_RND_INTRA,CALC3 forward quantization's rounding coefficients and shift offsets for intra MB" hexmask.long 0x14 7.--31. 1. "CALC_Q_RND_COEF_INTRA,Forward quantization's rounding coefficients for intra MB" bitfld.long 0x14 0.--3. "CALC_Q_SHIFT_ADJ_INTRA,It can be applicable for weight matrix used codecs' encoding" "CALC_Q_SHIFT_ADJ_INTRA_0,CALC_Q_SHIFT_ADJ_INTRA_1,CALC_Q_SHIFT_ADJ_INTRA_2,CALC_Q_SHIFT_ADJ_INTRA_3,CALC_Q_SHIFT_ADJ_INTRA_4,CALC_Q_SHIFT_ADJ_INTRA_5,CALC_Q_SHIFT_ADJ_INTRA_6,CALC_Q_SHIFT_ADJ_INTRA_7,CALC_Q_SHIFT_ADJ_INTRA_8,CALC_Q_SHIFT_ADJ_INTRA_9,CALC_Q_SHIFT_ADJ_INTRA_10,CALC_Q_SHIFT_ADJ_INTRA_11,CALC_Q_SHIFT_ADJ_INTRA_12,CALC_Q_SHIFT_ADJ_INTRA_13,CALC_Q_SHIFT_ADJ_INTRA_14,CALC_Q_SHIFT_ADJ_INTRA_15" line.long 0x18 "CALC_FWDQ_RND_INTER,CALC3 forward quantization's rounding coefficients and shift offsets for inter MB" hexmask.long 0x18 7.--31. 1. "CALC_Q_RND_COEF_INTER,Forward quantization's rounding coefficients for inter MB" bitfld.long 0x18 0.--3. "CALC_Q_SHIFT_ADJ_INTER,It can be applicable for weight matrix used codecs' encoding" "CALC_Q_SHIFT_ADJ_INTER_0,CALC_Q_SHIFT_ADJ_INTER_1,CALC_Q_SHIFT_ADJ_INTER_2,CALC_Q_SHIFT_ADJ_INTER_3,CALC_Q_SHIFT_ADJ_INTER_4,CALC_Q_SHIFT_ADJ_INTER_5,CALC_Q_SHIFT_ADJ_INTER_6,CALC_Q_SHIFT_ADJ_INTER_7,CALC_Q_SHIFT_ADJ_INTER_8,CALC_Q_SHIFT_ADJ_INTER_9,CALC_Q_SHIFT_ADJ_INTER_10,CALC_Q_SHIFT_ADJ_INTER_11,CALC_Q_SHIFT_ADJ_INTER_12,CALC_Q_SHIFT_ADJ_INTER_13,CALC_Q_SHIFT_ADJ_INTER_14,CALC_Q_SHIFT_ADJ_INTER_15" group.long 0x20++0x07 line.long 0x00 "CALC_FWDQ_RND_INTRA_DC,Round offset value setting for fwd Q. intra and DC coefficient" hexmask.long 0x00 7.--31. 1. "CALC_Q_RND_COEF_INTRA_DC,Forward quantization's rounding coefficients for intra MB and its DC coefficients" line.long 0x04 "CALC_FWDQ_RND_INTER_DC,Round offset value setting for fwd Q. inter and DC coefficient" hexmask.long 0x04 7.--31. 1. "CALC_Q_RND_COEF_INTER_DC,Forward quantization's rounding coefficients for inter MB and its DC coefficients" tree.end tree.end tree.open "IVA_Entropy_Coder_Decoder" tree "ECD3_BFSW_L3_MAINInterconnect" base ad:0x5A059A00 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View Mode Register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_ERSDBUF,View mode selection for ersdbuf" "0,1" bitfld.long 0x00 0. "VIEW_ECDABUF,View mode selection for ecdabuf" "0,1" line.long 0x04 "MSTID1,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_ERSDBUF_B,Master selection for ersdbuf B" "0,1" bitfld.long 0x04 2. "MST_ERSDBUF_A,Master selection for ersdbuf A" "0,1" bitfld.long 0x04 1. "MST_ECDABUF_B,Master selection for ecdabuf B" "0,1" bitfld.long 0x04 0. "MST_ECDABUF_A,Master selection for ecdabuf A" "0,1" line.long 0x08 "MSTID2,Master ID 1 Register Select master between HWA and DMA bus" hexmask.long 0x08 1.--31. 1. "RSRV,Reserved" bitfld.long 0x08 0. "MST_ECDWBUF,Master selection for ecdwbuf" "0,1" tree.end tree "ECD3_IPGW_L3_MAINInterconnect" base ad:0x5A059C00 group.long 0x08++0x07 line.long 0x00 "ECD3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" line.long 0x04 "ECD3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--2. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1,LINE_NUMBER_2,LINE_NUMBER_3,LINE_NUMBER_4,LINE_NUMBER_5,LINE_NUMBER_6,LINE_NUMBER_7" group.long 0x18++0x0B line.long 0x00 "ECD3_IPQSTATUS_RAW_1,Per-event raw interrupt status vector. line #1" bitfld.long 0x00 0. "EVENT0,settable raw status for event #0" "EVENT0_0,EVENT0_1" line.long 0x04 "ECD3_IPQSTATUS_RAW_2,Per-event raw interrupt status vector. line #2" bitfld.long 0x04 0. "EVENT0,settable raw status for event #0" "EVENT0_0,EVENT0_1" line.long 0x08 "ECD3_IPQSTATUS_RAW_3,Per-event raw interrupt status vector. line #3" bitfld.long 0x08 1. "EVENT1,settable raw status for event #1" "EVENT1_0,EVENT1_1" bitfld.long 0x08 0. "EVENT0,settable raw status for event #0" "EVENT0_0,EVENT0_1" group.long 0x2C++0x03 line.long 0x00 "ECD3_IPQSTATUS_RAW_6,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 1. "EVENT1,settable raw status for event #1" "EVENT1_0,EVENT1_1" bitfld.long 0x00 0. "EVENT0,settable raw status for event #0" "EVENT0_0,EVENT0_1" group.long 0x34++0x07 line.long 0x00 "ECD3_IRQSTATUS_1,Per-event 'enabled' interrupt status vector. line #1" bitfld.long 0x00 0. "EVENT0,clearable enabled status for event #0" "EVENT0_0,EVENT0_1" line.long 0x04 "ECD3_IRQSTATUS_2,Per-event 'enabled' interrupt status vector. line #2" bitfld.long 0x04 0. "EVENT0,clearable enabled status for event #0" "EVENT0_0,EVENT0_1" group.long 0x50++0x07 line.long 0x00 "ECD3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line #1" bitfld.long 0x00 0. "ENABLE0,Enable for event #0" "ENABLE0_0,ENABLE0_1" line.long 0x04 "ECD3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line #2" bitfld.long 0x04 0. "ENABLE0,Enable for event #0" "ENABLE0_0,ENABLE0_1" group.long 0x6C++0x07 line.long 0x00 "ECD3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line #1" bitfld.long 0x00 0. "ENABLE0,Enable for event #0" "ENABLE0_0,ENABLE0_1" line.long 0x04 "ECD3_IRQENABLE_CLR_2,Per-event interrupt enable bit vector. line #2" bitfld.long 0x04 0. "ENABLE0,Enable for event #0" "ENABLE0_0,ENABLE0_1" group.long 0xC0++0x03 line.long 0x00 "ECD3_IRQSTATUS_ACLREN,Auto Clear enable" bitfld.long 0x00 6. "ACLREN6,For line 6" "ACLREN6_0,ACLREN6_1" bitfld.long 0x00 5. "ACLREN5,For line 5" "ACLREN5_0,ACLREN5_1" bitfld.long 0x00 4. "ACLREN4,For line 4" "ACLREN4_0,ACLREN4_1" bitfld.long 0x00 3. "ACLREN3,For line 3" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,For line 2" "ACLREN2_0,ACLREN2_1" newline bitfld.long 0x00 1. "ACLREN1,For line 1" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,For line 0" "ACLREN0_0,ACLREN0_1" repeat 2. (list 3. 6. )(list 0x00 0x0C ) group.long ($2+0x74)++0x03 line.long 0x00 "ECD3_IRQENABLE_CLR_$1,Per-event interrupt enable bit vector. line #2" bitfld.long 0x00 1. "ENABLE1,Enable for event #1" "ENABLE1_0,ENABLE1_1" bitfld.long 0x00 0. "ENABLE0,Enable for event #0" "ENABLE0_0,ENABLE0_1" repeat.end repeat 3. (list 0. 4. 5. )(list 0x00 0x10 0x14 ) group.long ($2+0x68)++0x03 line.long 0x00 "ECD3_IRQENABLE_CLR_$1,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 0. "ENABLE0,Enable for event #0" "ENABLE0_0,ENABLE0_1" repeat.end repeat 2. (list 3. 6. )(list 0x00 0x0C ) group.long ($2+0x58)++0x03 line.long 0x00 "ECD3_IRQENABLE_SET_$1,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 1. "ENABLE1,Enable for event #1" "ENABLE1_0,ENABLE1_1" bitfld.long 0x00 0. "ENABLE0,Enable for event #0" "ENABLE0_0,ENABLE0_1" repeat.end repeat 3. (list 0. 4. 5. )(list 0x00 0x10 0x14 ) group.long ($2+0x4C)++0x03 line.long 0x00 "ECD3_IRQENABLE_SET_$1,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 0. "ENABLE0,Enable for event #0" "ENABLE0_0,ENABLE0_1" repeat.end repeat 2. (list 3. 6. )(list 0x00 0x0C ) group.long ($2+0x3C)++0x03 line.long 0x00 "ECD3_IRQSTATUS_$1,Per-event 'enabled' interrupt status vector. line #3" bitfld.long 0x00 1. "EVENT1,clearable enabled status for event #1" "EVENT1_0,EVENT1_1" bitfld.long 0x00 0. "EVENT0,clearable enabled status for event #0" "EVENT0_0,EVENT0_1" repeat.end repeat 3. (list 0. 4. 5. )(list 0x00 0x10 0x14 ) group.long ($2+0x30)++0x03 line.long 0x00 "ECD3_IRQSTATUS_$1,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 0. "EVENT0,clearable enabled status for event #0" "EVENT0_0,EVENT0_1" repeat.end repeat 3. (list 0. 4. 5. )(list 0x00 0x10 0x14 ) group.long ($2+0x14)++0x03 line.long 0x00 "ECD3_IPQSTATUS_RAW_$1,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 0. "EVENT0,settable raw status for event #0" "EVENT0_0,EVENT0_1" repeat.end tree.end tree "ECD3_LSE_L3_MAINInterconnect" base ad:0x5A059B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit [11]: OCP DMA IP_CORE side [10]: OCP DMA SL2 side [9] : OCP CFG IP_CORE side" "OCP_ERR_0,OCP_ERR_1,OCP_ERR_2,OCP_ERR_3,OCP_ERR_4,OCP_ERR_5,OCP_ERR_6,OCP_ERR_7" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW change" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command Status Bit" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps need to set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps need to set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,Sync-Box Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" tree.end tree "ECD3_MMR_L3_MAINInterconnect" base ad:0x5A059800 rgroup.long 0x00++0x33 line.long 0x00 "ECD_PID,Product Identification" line.long 0x04 "ECD_COUNT,Cycle Counter" bitfld.long 0x04 31. "CNT_EN," "CNT_EN_0,CNT_EN_1" bitfld.long 0x04 30. "CNT_RST,Resets the cycle counter COUNT value to 0" "CNT_RST_0,CNT_RST_1" newline hexmask.long.word 0x04 0.--15. 1. "COUNT,Displays the current counter value" line.long 0x08 "ECD_CTRL,Control" rbitfld.long 0x08 20.--23. "CDM_ADD_15_12,Specifies the starting byte address [15:12] of command sequence stored in ECDABUF" "CDM_ADD_15_12_0,CDM_ADD_15_12_1,CDM_ADD_15_12_2,CDM_ADD_15_12_3,CDM_ADD_15_12_4,CDM_ADD_15_12_5,CDM_ADD_15_12_6,CDM_ADD_15_12_7,CDM_ADD_15_12_8,CDM_ADD_15_12_9,CDM_ADD_15_12_10,CDM_ADD_15_12_11,CDM_ADD_15_12_12,CDM_ADD_15_12_13,CDM_ADD_15_12_14,CDM_ADD_15_12_15" hexmask.long.byte 0x08 12.--19. 1. "CDM_ADD_11_4,Specifies the starting byte address [11:4] of command sequence stored in ECDABUF" newline rbitfld.long 0x08 8.--11. "CDM_ADD_3_0,Specifies the starting byte address [3:0] of command sequence stored in ECDABUF" "CDM_ADD_3_0_0,CDM_ADD_3_0_1,CDM_ADD_3_0_2,CDM_ADD_3_0_3,CDM_ADD_3_0_4,CDM_ADD_3_0_5,CDM_ADD_3_0_6,CDM_ADD_3_0_7,CDM_ADD_3_0_8,CDM_ADD_3_0_9,CDM_ADD_3_0_10,CDM_ADD_3_0_11,CDM_ADD_3_0_12,CDM_ADD_3_0_13,CDM_ADD_3_0_14,CDM_ADD_3_0_15" bitfld.long 0x08 2. "SSM," "SSM_0,SSM_1" newline rbitfld.long 0x08 1. "CSB," "CSB_0,CSB_1" bitfld.long 0x08 0. "EN," "EN_0,EN_1" line.long 0x0C "ECD_STAT,ECD Status" bitfld.long 0x0C 30. "EOS_ACK_DIS," "EOS_ACK_DIS_0,EOS_ACK_DIS_1" bitfld.long 0x0C 29. "ERR_ACK_DIS," "ERR_ACK_DIS_0,ERR_ACK_DIS_1" newline rbitfld.long 0x0C 2. "EOS," "EOS_0,EOS_1" rbitfld.long 0x0C 1. "ERR," "ERR_0,ERR_1" newline rbitfld.long 0x0C 0. "BUSY," "BUSY_0,BUSY_1" line.long 0x10 "SBC_CTRL,Stream Buffer Controller Control" bitfld.long 0x10 31. "SBC_RST,Resets the Stream Buffer Controller" "SBC_RST_0,SBC_RST_1" bitfld.long 0x10 16. "SBC_CLOSE,Close the bitstream data" "SBC_CLOSE_0,SBC_CLOSE_1" newline bitfld.long 0x10 12. "SBC_DMA_TRG_B,Start DMA to fill empty page in the Buffer B manually" "SBC_DMA_TRG_B_0,SBC_DMA_TRG_B_1" bitfld.long 0x10 8. "SBC_DMA_TRG_A,Start DMA to fill empty page in the Buffer A manually" "SBC_DMA_TRG_A_0,SBC_DMA_TRG_A_1" newline bitfld.long 0x10 4. "SBC_BIT_CNT_RST,Reset bit counter in the Stream Buffer" "SBC_BIT_CNT_RST_0,SBC_BIT_CNT_RST_1" bitfld.long 0x10 0. "SBC_BUFSEL,Selects active buffer between A and B: Write" "SBC_BUFSEL_0,SBC_BUFSEL_1" line.long 0x14 "SBC_STAT,Stream Buffer Controller Status" rbitfld.long 0x14 6. "SBC_ST_SRCH," "SBC_ST_SRCH_0,SBC_ST_SRCH_1" bitfld.long 0x14 5. "SBC_DMA_B," "SBC_DMA_B_0,SBC_DMA_B_1" newline bitfld.long 0x14 4. "SBC_DMA_A," "SBC_DMA_A_0,SBC_DMA_A_1" rbitfld.long 0x14 3. "SBC_WR_HLT," "SBC_WR_HLT_0,SBC_WR_HLT_1" newline rbitfld.long 0x14 2. "SBC_RD_HLT," "SBC_RD_HLT_0,SBC_RD_HLT_1" rbitfld.long 0x14 1. "SBC_WR," "SBC_WR_0,SBC_WR_1" newline rbitfld.long 0x14 0. "SBC_RD," "SBC_RD_0,SBC_RD_1" line.long 0x18 "SBC_BUFCFG,Stream Buffer Controller Buffer Configuration" bitfld.long 0x18 31. "SBC_FLUSH_MODE,SBC FIFO flush mode select for encoding" "SBC_FLUSH_MODE_0,SBC_FLUSH_MODE_1" bitfld.long 0x18 30. "SBC_FMO_MODE,SBC FIFO flush mode select for encoding" "SBC_FMO_MODE_0,SBC_FMO_MODE_1" newline bitfld.long 0x18 24. "SBC_DBL,Enables double buffer mode" "SBC_DBL_0,SBC_DBL_1" bitfld.long 0x18 20.--21. "SBC_PGSZ,Specifies the page size of buffer A and B in the unit of 1024 [byte]" "SBC_PGSZ_0,SBC_PGSZ_1,SBC_PGSZ_2,SBC_PGSZ_3" newline hexmask.long.word 0x18 4.--17. 1. "SBC_BUFTOP_17_4,Specifies the base address [17:4] of the bitstream buffer in SL2" rbitfld.long 0x18 0.--3. "SBC_BUFTOP_3_0,Specifies the base address [3:0] of the bitstream buffer in SL2" "SBC_BUFTOP_3_0_0,SBC_BUFTOP_3_0_1,SBC_BUFTOP_3_0_2,SBC_BUFTOP_3_0_3,SBC_BUFTOP_3_0_4,SBC_BUFTOP_3_0_5,SBC_BUFTOP_3_0_6,SBC_BUFTOP_3_0_7,SBC_BUFTOP_3_0_8,SBC_BUFTOP_3_0_9,SBC_BUFTOP_3_0_10,SBC_BUFTOP_3_0_11,SBC_BUFTOP_3_0_12,SBC_BUFTOP_3_0_13,SBC_BUFTOP_3_0_14,SBC_BUFTOP_3_0_15" line.long 0x1C "SBC_A_BITPTR,Stream Buffer Controller A Bit Pointer" bitfld.long 0x1C 28.--30. "FMO_DMA_ID,Indicates the ID number of bitstream data in SL2 memory" "FMO_DMA_ID_0,FMO_DMA_ID_1,FMO_DMA_ID_2,FMO_DMA_ID_3,FMO_DMA_ID_4,FMO_DMA_ID_5,FMO_DMA_ID_6,FMO_DMA_ID_7" bitfld.long 0x1C 24.--25. "NUM_ZERO_A,Indicates the number of 0 bytes in the past for buffer A" "NUM_ZERO_A_0,NUM_ZERO_A_1,NUM_ZERO_A_2,NUM_ZERO_A_3" newline hexmask.long.word 0x1C 8.--21. 1. "BYTEPTR_A,Indicates the current byte offset address in Buffer A of the byte containing the next bit in the bitstream" bitfld.long 0x1C 0.--2. "BITPTR_A,Indicates the next bit position in the byte at BYTEPTR_A" "BITPTR_A_0,BITPTR_A_1,BITPTR_A_2,BITPTR_A_3,BITPTR_A_4,BITPTR_A_5,BITPTR_A_6,BITPTR_A_7" line.long 0x20 "SBC_A_DMAPG,Stream Buffer Controller A DMA Page" hexmask.long.byte 0x20 0.--7. 1. "DMAPG_A,Indicates the page that is being accessed from DMA for bitstream data transferring" line.long 0x24 "SBC_B_BITPTR,Stream Buffer Controller B Bit Pointer" bitfld.long 0x24 24.--25. "NUM_ZERO_B,Indicates the number of 0 bytes in the past for buffer B" "NUM_ZERO_B_0,NUM_ZERO_B_1,NUM_ZERO_B_2,NUM_ZERO_B_3" hexmask.long.word 0x24 8.--21. 1. "BYTEPTR_B,Indicates the current byte offset address in Buffer B of the byte containing the next bit in the bitstream" newline bitfld.long 0x24 0.--2. "BITPTR_B,Indicates the next bit position in the byte at BYTEPTR_B" "BITPTR_B_0,BITPTR_B_1,BITPTR_B_2,BITPTR_B_3,BITPTR_B_4,BITPTR_B_5,BITPTR_B_6,BITPTR_B_7" line.long 0x28 "SBC_B_DMAPG,Stream Buffer Controller B DMA Page" bitfld.long 0x28 0. "DMAPG_B,Indicates the page that is being accessed from DMA for bitstream data transferring" "DMAPG_B_0,DMAPG_B_1" line.long 0x2C "SBC_TTLCNT,Stream Buffer Controller Total Bit Counter" line.long 0x30 "SBC_RSDCNT,Stream Buffer Controller Residual Layer Bit Counter" group.long 0x38++0x0B line.long 0x00 "SBC_SRCH_PG_CNT,Buffer page counter for start code searching" hexmask.long.word 0x00 0.--15. 1. "SRCH_PG_CNT,ECD3 search start code until the page counter reach this number" line.long 0x04 "SBC_FMO_DMA_STAT,FMO_DMA status register" hexmask.long.byte 0x04 0.--7. 1. "FMO_DMA,Indicates FMO_DMA_ID for stream interrupt at buffer page boundary" line.long 0x08 "MBPC_PIC_DIM,Picture Dimension" bitfld.long 0x08 31. "CUR_MBAFF,CUR_MBAFF = 1 indicates that current picture is in H.264 MBAFF mode" "CUR_MBAFF_0,CUR_MBAFF_1" hexmask.long.word 0x08 16.--29. 1. "PIC_H,PIC_H specifies the picture height in macroblocks which is calculated by PIC_H = ((picture height in pixels) + 15)/16" newline hexmask.long.word 0x08 0.--13. 1. "PIC_W,PIC_W specifies the picture width in macroblocks which is calculated by PIC_W = ((picture width in pixels) + 15)/16" group.long 0x50++0x0F line.long 0x00 "MBPC_STAT,MB Position Controller Status" bitfld.long 0x00 9. "PIC_END_FLAG,PIC_END_FLAG = 1 indicates that the macroblock will be processed is at the end of the picture" "PIC_END_FLAG_0,PIC_END_FLAG_1" bitfld.long 0x00 8. "FIRST_MB_FLAG,FIRST_MB_FLAG = 1 indicates that the macroblock will be processed is the first macroblock in the slice" "FIRST_MB_FLAG_0,FIRST_MB_FLAG_1" newline bitfld.long 0x00 4.--7. "PIC_BOUND,PIC_BOUND indicates that the picture boundary status of the current macroblock (in case of MBAFF mode the unit is macroblock-pair)" "PIC_BOUND_0,PIC_BOUND_1,PIC_BOUND_2,PIC_BOUND_3,PIC_BOUND_4,PIC_BOUND_5,PIC_BOUND_6,PIC_BOUND_7,PIC_BOUND_8,PIC_BOUND_9,PIC_BOUND_10,PIC_BOUND_11,PIC_BOUND_12,PIC_BOUND_13,PIC_BOUND_14,PIC_BOUND_15" bitfld.long 0x00 0.--3. "MB_AVAIL,MB_AVAIL indicates that the availabilities of neighboring macroblocks (in case of MBAFF mode the unit is macroblock-pair)" "MB_AVAIL_0,MB_AVAIL_1,MB_AVAIL_2,MB_AVAIL_3,MB_AVAIL_4,MB_AVAIL_5,MB_AVAIL_6,MB_AVAIL_7,MB_AVAIL_8,MB_AVAIL_9,MB_AVAIL_10,MB_AVAIL_11,MB_AVAIL_12,MB_AVAIL_13,MB_AVAIL_14,MB_AVAIL_15" line.long 0x04 "MBPC_POS,Macroblock Position" hexmask.long.word 0x04 16.--28. 1. "MB_Y,MB_Y equals the macroblock y-position in the picture" hexmask.long.word 0x04 0.--12. 1. "MB_X,MB_X equals the macroblock x-position in the picture" line.long 0x08 "MBPC_PMC,Macroblock Count In Picture" hexmask.long 0x08 0.--25. 1. "PIC_MB_CNT,PIC_MB_CNT equals the macroblock count in the picture" line.long 0x0C "MBPC_SMC,Macroblock Count In Slice" hexmask.long 0x0C 0.--25. 1. "SLC_MB_CNT,SLC_MB_CNT equals the macroblock count in the slice" group.long 0x64++0x17 line.long 0x00 "DTBC_BP_MB,Data Buffer Controller MB Base Buffer Pointer" rbitfld.long 0x00 28.--31. "BP_MB_UR_15_12,BP_MB_UR specifies the base pointer to the upper macroblock buffer" "BP_MB_UR_15_12_0,BP_MB_UR_15_12_1,BP_MB_UR_15_12_2,BP_MB_UR_15_12_3,BP_MB_UR_15_12_4,BP_MB_UR_15_12_5,BP_MB_UR_15_12_6,BP_MB_UR_15_12_7,BP_MB_UR_15_12_8,BP_MB_UR_15_12_9,BP_MB_UR_15_12_10,BP_MB_UR_15_12_11,BP_MB_UR_15_12_12,BP_MB_UR_15_12_13,BP_MB_UR_15_12_14,BP_MB_UR_15_12_15" hexmask.long.byte 0x00 20.--27. 1. "BP_MB_UR_11_4,BP_MB_UR specifies the base pointer to the upper macroblock buffer" newline rbitfld.long 0x00 16.--19. "BP_MB_UR_3_0,BP_MB_UR specifies the base pointer to the upper macroblock buffer" "BP_MB_UR_3_0_0,BP_MB_UR_3_0_1,BP_MB_UR_3_0_2,BP_MB_UR_3_0_3,BP_MB_UR_3_0_4,BP_MB_UR_3_0_5,BP_MB_UR_3_0_6,BP_MB_UR_3_0_7,BP_MB_UR_3_0_8,BP_MB_UR_3_0_9,BP_MB_UR_3_0_10,BP_MB_UR_3_0_11,BP_MB_UR_3_0_12,BP_MB_UR_3_0_13,BP_MB_UR_3_0_14,BP_MB_UR_3_0_15" rbitfld.long 0x00 12.--15. "BP_MB_CUR_15_12,BP_MB_CUR specifies the base pointer to the current macroblock buffer" "BP_MB_CUR_15_12_0,BP_MB_CUR_15_12_1,BP_MB_CUR_15_12_2,BP_MB_CUR_15_12_3,BP_MB_CUR_15_12_4,BP_MB_CUR_15_12_5,BP_MB_CUR_15_12_6,BP_MB_CUR_15_12_7,BP_MB_CUR_15_12_8,BP_MB_CUR_15_12_9,BP_MB_CUR_15_12_10,BP_MB_CUR_15_12_11,BP_MB_CUR_15_12_12,BP_MB_CUR_15_12_13,BP_MB_CUR_15_12_14,BP_MB_CUR_15_12_15" newline hexmask.long.byte 0x00 4.--11. 1. "BP_MB_CUR_11_4,BP_MB_CUR specifies the base pointer to the current macroblock buffer" rbitfld.long 0x00 0.--3. "BP_MB_CUR_3_0,BP_MB_CUR specifies the base pointer to the current macroblock buffer" "BP_MB_CUR_3_0_0,BP_MB_CUR_3_0_1,BP_MB_CUR_3_0_2,BP_MB_CUR_3_0_3,BP_MB_CUR_3_0_4,BP_MB_CUR_3_0_5,BP_MB_CUR_3_0_6,BP_MB_CUR_3_0_7,BP_MB_CUR_3_0_8,BP_MB_CUR_3_0_9,BP_MB_CUR_3_0_10,BP_MB_CUR_3_0_11,BP_MB_CUR_3_0_12,BP_MB_CUR_3_0_13,BP_MB_CUR_3_0_14,BP_MB_CUR_3_0_15" line.long 0x04 "DTBC_BP_COL,Data Buffer Controller Co-located MB Buffer Base Pointer" rbitfld.long 0x04 28.--31. "BP_COL_B_15_12,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" "BP_COL_B_15_12_0,BP_COL_B_15_12_1,BP_COL_B_15_12_2,BP_COL_B_15_12_3,BP_COL_B_15_12_4,BP_COL_B_15_12_5,BP_COL_B_15_12_6,BP_COL_B_15_12_7,BP_COL_B_15_12_8,BP_COL_B_15_12_9,BP_COL_B_15_12_10,BP_COL_B_15_12_11,BP_COL_B_15_12_12,BP_COL_B_15_12_13,BP_COL_B_15_12_14,BP_COL_B_15_12_15" hexmask.long.byte 0x04 20.--27. 1. "BP_COL_B_11_4,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" newline rbitfld.long 0x04 16.--19. "BP_COL_B_3_0,BP_COL_B specifies the base pointer to the co-located macroblock buffer B" "BP_COL_B_3_0_0,BP_COL_B_3_0_1,BP_COL_B_3_0_2,BP_COL_B_3_0_3,BP_COL_B_3_0_4,BP_COL_B_3_0_5,BP_COL_B_3_0_6,BP_COL_B_3_0_7,BP_COL_B_3_0_8,BP_COL_B_3_0_9,BP_COL_B_3_0_10,BP_COL_B_3_0_11,BP_COL_B_3_0_12,BP_COL_B_3_0_13,BP_COL_B_3_0_14,BP_COL_B_3_0_15" rbitfld.long 0x04 12.--15. "BP_COL_A_15_12,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" "BP_COL_A_15_12_0,BP_COL_A_15_12_1,BP_COL_A_15_12_2,BP_COL_A_15_12_3,BP_COL_A_15_12_4,BP_COL_A_15_12_5,BP_COL_A_15_12_6,BP_COL_A_15_12_7,BP_COL_A_15_12_8,BP_COL_A_15_12_9,BP_COL_A_15_12_10,BP_COL_A_15_12_11,BP_COL_A_15_12_12,BP_COL_A_15_12_13,BP_COL_A_15_12_14,BP_COL_A_15_12_15" newline hexmask.long.byte 0x04 4.--11. 1. "BP_COL_A_11_4,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" rbitfld.long 0x04 0.--3. "BP_COL_A_3_0,BP_COL_A specifies the base pointer to the co-located macroblock buffer A" "BP_COL_A_3_0_0,BP_COL_A_3_0_1,BP_COL_A_3_0_2,BP_COL_A_3_0_3,BP_COL_A_3_0_4,BP_COL_A_3_0_5,BP_COL_A_3_0_6,BP_COL_A_3_0_7,BP_COL_A_3_0_8,BP_COL_A_3_0_9,BP_COL_A_3_0_10,BP_COL_A_3_0_11,BP_COL_A_3_0_12,BP_COL_A_3_0_13,BP_COL_A_3_0_14,BP_COL_A_3_0_15" line.long 0x08 "DTBC_BP_RSD,Data Buffer Controller Residual Buffer Base Pointer" rbitfld.long 0x08 28.--31. "BP_RSD_15_12,BP_RSD specifies the base pointer to the residual data buffer" "BP_RSD_15_12_0,BP_RSD_15_12_1,BP_RSD_15_12_2,BP_RSD_15_12_3,BP_RSD_15_12_4,BP_RSD_15_12_5,BP_RSD_15_12_6,BP_RSD_15_12_7,BP_RSD_15_12_8,BP_RSD_15_12_9,BP_RSD_15_12_10,BP_RSD_15_12_11,BP_RSD_15_12_12,BP_RSD_15_12_13,BP_RSD_15_12_14,BP_RSD_15_12_15" hexmask.long.byte 0x08 20.--27. 1. "BP_RSD_11_4,BP_RSD specifies the base pointer to the residual data buffer" newline rbitfld.long 0x08 16.--19. "BP_RSD_3_0,BP_RSD specifies the base pointer to the residual data buffer" "BP_RSD_3_0_0,BP_RSD_3_0_1,BP_RSD_3_0_2,BP_RSD_3_0_3,BP_RSD_3_0_4,BP_RSD_3_0_5,BP_RSD_3_0_6,BP_RSD_3_0_7,BP_RSD_3_0_8,BP_RSD_3_0_9,BP_RSD_3_0_10,BP_RSD_3_0_11,BP_RSD_3_0_12,BP_RSD_3_0_13,BP_RSD_3_0_14,BP_RSD_3_0_15" line.long 0x0C "DTBC_DP_UL,Data Buffer Controller Data Pointer 0" rbitfld.long 0x0C 13.--15. "PTR_MB_UL_15_13,Current pointer [15:13] to the upper left macroblock data in work buffer" "PTR_MB_UL_15_13_0,PTR_MB_UL_15_13_1,PTR_MB_UL_15_13_2,PTR_MB_UL_15_13_3,PTR_MB_UL_15_13_4,PTR_MB_UL_15_13_5,PTR_MB_UL_15_13_6,PTR_MB_UL_15_13_7" hexmask.long.word 0x0C 4.--12. 1. "PTR_MB_UL_12_4,Current pointer [12:4] to the upper left macroblock data in work buffer" newline rbitfld.long 0x0C 0.--3. "PTR_MB_UL_3_0,Current pointer [3:0] to the upper left macroblock data in work buffer" "PTR_MB_UL_3_0_0,PTR_MB_UL_3_0_1,PTR_MB_UL_3_0_2,PTR_MB_UL_3_0_3,PTR_MB_UL_3_0_4,PTR_MB_UL_3_0_5,PTR_MB_UL_3_0_6,PTR_MB_UL_3_0_7,PTR_MB_UL_3_0_8,PTR_MB_UL_3_0_9,PTR_MB_UL_3_0_10,PTR_MB_UL_3_0_11,PTR_MB_UL_3_0_12,PTR_MB_UL_3_0_13,PTR_MB_UL_3_0_14,PTR_MB_UL_3_0_15" line.long 0x10 "DTBC_DP_UU_UR,Data Buffer Controller Data Pointer 1" rbitfld.long 0x10 29.--31. "PTR_MB_UU_15_13,Current pointer [15:13] to the upper macroblock data in work buffer" "PTR_MB_UU_15_13_0,PTR_MB_UU_15_13_1,PTR_MB_UU_15_13_2,PTR_MB_UU_15_13_3,PTR_MB_UU_15_13_4,PTR_MB_UU_15_13_5,PTR_MB_UU_15_13_6,PTR_MB_UU_15_13_7" hexmask.long.word 0x10 20.--28. 1. "PTR_MB_UU_12_4,Current pointer [12:4] to the upper macroblock data in work buffer" newline rbitfld.long 0x10 16.--19. "PTR_MB_UU_3_0,Current pointer [3:0] to the upper macroblock data in work buffer" "PTR_MB_UU_3_0_0,PTR_MB_UU_3_0_1,PTR_MB_UU_3_0_2,PTR_MB_UU_3_0_3,PTR_MB_UU_3_0_4,PTR_MB_UU_3_0_5,PTR_MB_UU_3_0_6,PTR_MB_UU_3_0_7,PTR_MB_UU_3_0_8,PTR_MB_UU_3_0_9,PTR_MB_UU_3_0_10,PTR_MB_UU_3_0_11,PTR_MB_UU_3_0_12,PTR_MB_UU_3_0_13,PTR_MB_UU_3_0_14,PTR_MB_UU_3_0_15" rbitfld.long 0x10 13.--15. "PTR_MB_UR_15_13,Current pointer [15:13] to the upper-right macroblock data in work buffer" "PTR_MB_UR_15_13_0,PTR_MB_UR_15_13_1,PTR_MB_UR_15_13_2,PTR_MB_UR_15_13_3,PTR_MB_UR_15_13_4,PTR_MB_UR_15_13_5,PTR_MB_UR_15_13_6,PTR_MB_UR_15_13_7" newline hexmask.long.word 0x10 4.--12. 1. "PTR_MB_UR_12_4,Current pointer [12:4] to the upper-right macroblock data in work buffer" rbitfld.long 0x10 0.--3. "PTR_MB_UR_3_0,Current pointer [3:0] to the upper-right macroblock data in work buffer" "PTR_MB_UR_3_0_0,PTR_MB_UR_3_0_1,PTR_MB_UR_3_0_2,PTR_MB_UR_3_0_3,PTR_MB_UR_3_0_4,PTR_MB_UR_3_0_5,PTR_MB_UR_3_0_6,PTR_MB_UR_3_0_7,PTR_MB_UR_3_0_8,PTR_MB_UR_3_0_9,PTR_MB_UR_3_0_10,PTR_MB_UR_3_0_11,PTR_MB_UR_3_0_12,PTR_MB_UR_3_0_13,PTR_MB_UR_3_0_14,PTR_MB_UR_3_0_15" line.long 0x14 "DTBC_DP_LL_CUR,Data Buffer Controller Data Pointer 2" rbitfld.long 0x14 29.--31. "PTR_MB_LL_15_13,Current pointer [15:13] to the left macroblock data in work buffer" "PTR_MB_LL_15_13_0,PTR_MB_LL_15_13_1,PTR_MB_LL_15_13_2,PTR_MB_LL_15_13_3,PTR_MB_LL_15_13_4,PTR_MB_LL_15_13_5,PTR_MB_LL_15_13_6,PTR_MB_LL_15_13_7" hexmask.long.word 0x14 20.--28. 1. "PTR_MB_LL_12_4,Current pointer [12:4] to the left macroblock data in work buffer" newline rbitfld.long 0x14 16.--19. "PTR_MB_LL_3_0,Current pointer [3:0] to the left macroblock data in work buffer" "PTR_MB_LL_3_0_0,PTR_MB_LL_3_0_1,PTR_MB_LL_3_0_2,PTR_MB_LL_3_0_3,PTR_MB_LL_3_0_4,PTR_MB_LL_3_0_5,PTR_MB_LL_3_0_6,PTR_MB_LL_3_0_7,PTR_MB_LL_3_0_8,PTR_MB_LL_3_0_9,PTR_MB_LL_3_0_10,PTR_MB_LL_3_0_11,PTR_MB_LL_3_0_12,PTR_MB_LL_3_0_13,PTR_MB_LL_3_0_14,PTR_MB_LL_3_0_15" rbitfld.long 0x14 13.--15. "PTR_MB_CUR_15_13,Current pointer [15:13] to the current macroblock data in work buffer" "PTR_MB_CUR_15_13_0,PTR_MB_CUR_15_13_1,PTR_MB_CUR_15_13_2,PTR_MB_CUR_15_13_3,PTR_MB_CUR_15_13_4,PTR_MB_CUR_15_13_5,PTR_MB_CUR_15_13_6,PTR_MB_CUR_15_13_7" newline hexmask.long.word 0x14 4.--12. 1. "PTR_MB_CUR_12_4,Current pointer [12:4] to the current macroblock data in work buffer" rbitfld.long 0x14 0.--3. "PTR_MB_CUR_3_0,Current pointer [3:0] to the current macroblock data in work buffer" "PTR_MB_CUR_3_0_0,PTR_MB_CUR_3_0_1,PTR_MB_CUR_3_0_2,PTR_MB_CUR_3_0_3,PTR_MB_CUR_3_0_4,PTR_MB_CUR_3_0_5,PTR_MB_CUR_3_0_6,PTR_MB_CUR_3_0_7,PTR_MB_CUR_3_0_8,PTR_MB_CUR_3_0_9,PTR_MB_CUR_3_0_10,PTR_MB_CUR_3_0_11,PTR_MB_CUR_3_0_12,PTR_MB_CUR_3_0_13,PTR_MB_CUR_3_0_14,PTR_MB_CUR_3_0_15" group.long 0x84++0x0F line.long 0x00 "DTBC_DP_ULUR2,Data Buffer Controller Data Pointer 5" rbitfld.long 0x00 29.--31. "PTR_MB_UL2_15_13,Current pointer [15:13] to the macroblock left to the upper left macroblock data in work buffer" "PTR_MB_UL2_15_13_0,PTR_MB_UL2_15_13_1,PTR_MB_UL2_15_13_2,PTR_MB_UL2_15_13_3,PTR_MB_UL2_15_13_4,PTR_MB_UL2_15_13_5,PTR_MB_UL2_15_13_6,PTR_MB_UL2_15_13_7" hexmask.long.word 0x00 20.--28. 1. "PTR_MB_UL2_12_4,Current pointer [12:4] to the macroblock left to the upper left macroblock data in work buffer" newline rbitfld.long 0x00 16.--19. "PTR_MB_UL2_3_0,Current pointer [3:0] to the macroblock left to the upper left macroblock data in work buffer" "PTR_MB_UL2_3_0_0,PTR_MB_UL2_3_0_1,PTR_MB_UL2_3_0_2,PTR_MB_UL2_3_0_3,PTR_MB_UL2_3_0_4,PTR_MB_UL2_3_0_5,PTR_MB_UL2_3_0_6,PTR_MB_UL2_3_0_7,PTR_MB_UL2_3_0_8,PTR_MB_UL2_3_0_9,PTR_MB_UL2_3_0_10,PTR_MB_UL2_3_0_11,PTR_MB_UL2_3_0_12,PTR_MB_UL2_3_0_13,PTR_MB_UL2_3_0_14,PTR_MB_UL2_3_0_15" rbitfld.long 0x00 13.--15. "PTR_MB_UR2_15_13,Current pointer [15:13] to the macroblock right to the upper-right macroblock data in work buffer" "PTR_MB_UR2_15_13_0,PTR_MB_UR2_15_13_1,PTR_MB_UR2_15_13_2,PTR_MB_UR2_15_13_3,PTR_MB_UR2_15_13_4,PTR_MB_UR2_15_13_5,PTR_MB_UR2_15_13_6,PTR_MB_UR2_15_13_7" newline hexmask.long.word 0x00 4.--12. 1. "PTR_MB_UR2_12_4,Current pointer [12:4] to the macroblock right to the upper-right macroblock data in work buffer" rbitfld.long 0x00 0.--3. "PTR_MB_UR2_3_0,Current pointer [3:0] to the macroblock right to the upper-right macroblock data in work buffer" "PTR_MB_UR2_3_0_0,PTR_MB_UR2_3_0_1,PTR_MB_UR2_3_0_2,PTR_MB_UR2_3_0_3,PTR_MB_UR2_3_0_4,PTR_MB_UR2_3_0_5,PTR_MB_UR2_3_0_6,PTR_MB_UR2_3_0_7,PTR_MB_UR2_3_0_8,PTR_MB_UR2_3_0_9,PTR_MB_UR2_3_0_10,PTR_MB_UR2_3_0_11,PTR_MB_UR2_3_0_12,PTR_MB_UR2_3_0_13,PTR_MB_UR2_3_0_14,PTR_MB_UR2_3_0_15" line.long 0x04 "DTBC_DP_SLICE,Slice data pointer" rbitfld.long 0x04 13.--15. "PTR_SLICE_15_13,Specifies the pointer [15:13] to slice or picture information data" "PTR_SLICE_15_13_0,PTR_SLICE_15_13_1,PTR_SLICE_15_13_2,PTR_SLICE_15_13_3,PTR_SLICE_15_13_4,PTR_SLICE_15_13_5,PTR_SLICE_15_13_6,PTR_SLICE_15_13_7" hexmask.long.word 0x04 4.--12. 1. "PTR_SLICE_12_4,Specifies the pointer [12:4] to slice or picture information data" newline rbitfld.long 0x04 0.--3. "PTR_SLICE_3_0,Specifies the pointer [3:0] to slice or picture information data" "PTR_SLICE_3_0_0,PTR_SLICE_3_0_1,PTR_SLICE_3_0_2,PTR_SLICE_3_0_3,PTR_SLICE_3_0_4,PTR_SLICE_3_0_5,PTR_SLICE_3_0_6,PTR_SLICE_3_0_7,PTR_SLICE_3_0_8,PTR_SLICE_3_0_9,PTR_SLICE_3_0_10,PTR_SLICE_3_0_11,PTR_SLICE_3_0_12,PTR_SLICE_3_0_13,PTR_SLICE_3_0_14,PTR_SLICE_3_0_15" line.long 0x08 "DTBC_DP_LL2,Data Buffer Controller data pointer" rbitfld.long 0x08 13.--15. "PTR_MB_LL2_15_13,Current pointer [15:13] to the macroblock left to the left macroblock data in work buffer" "PTR_MB_LL2_15_13_0,PTR_MB_LL2_15_13_1,PTR_MB_LL2_15_13_2,PTR_MB_LL2_15_13_3,PTR_MB_LL2_15_13_4,PTR_MB_LL2_15_13_5,PTR_MB_LL2_15_13_6,PTR_MB_LL2_15_13_7" hexmask.long.word 0x08 4.--12. 1. "PTR_MB_LL2_12_4,Current pointer [12:4] to the macroblock left to the left macroblock data in work buffer" newline rbitfld.long 0x08 0.--3. "PTR_MB_LL2_3_0,Current pointer [3:0] to the macroblock left to the left macroblock data in work buffer" "PTR_MB_LL2_3_0_0,PTR_MB_LL2_3_0_1,PTR_MB_LL2_3_0_2,PTR_MB_LL2_3_0_3,PTR_MB_LL2_3_0_4,PTR_MB_LL2_3_0_5,PTR_MB_LL2_3_0_6,PTR_MB_LL2_3_0_7,PTR_MB_LL2_3_0_8,PTR_MB_LL2_3_0_9,PTR_MB_LL2_3_0_10,PTR_MB_LL2_3_0_11,PTR_MB_LL2_3_0_12,PTR_MB_LL2_3_0_13,PTR_MB_LL2_3_0_14,PTR_MB_LL2_3_0_15" line.long 0x0C "DTBC_CUR_MB_SIZE,Current Picture Macro Block element size" hexmask.long.byte 0x0C 4.--11. 1. "CUR_MB_SIZE_11_4,Data element size for Current MB Upper-right MB in AUX buffer and Upper MB Current/Left MB in WORK buffer" rbitfld.long 0x0C 0.--3. "CUR_MB_SIZE_3_0,Data element size for Current MB Upper-right MB in AUX buffer and Upper MB Current/Left MB in WORK buffer" "CUR_MB_SIZE_3_0_0,CUR_MB_SIZE_3_0_1,CUR_MB_SIZE_3_0_2,CUR_MB_SIZE_3_0_3,CUR_MB_SIZE_3_0_4,CUR_MB_SIZE_3_0_5,CUR_MB_SIZE_3_0_6,CUR_MB_SIZE_3_0_7,CUR_MB_SIZE_3_0_8,CUR_MB_SIZE_3_0_9,CUR_MB_SIZE_3_0_10,CUR_MB_SIZE_3_0_11,CUR_MB_SIZE_3_0_12,CUR_MB_SIZE_3_0_13,CUR_MB_SIZE_3_0_14,CUR_MB_SIZE_3_0_15" group.long 0xA0++0x07 line.long 0x00 "CDC_MODE,Codec Mode (also works as view page)" bitfld.long 0x00 4. "DIR,Selects the codec direction: Write" "0,1" bitfld.long 0x00 0.--3. "MODE,Selects the active codec Selected Codec (Selected Codec Engine)" "MODE_0,MODE_1,MODE_2,MODE_3,MODE_4,MODE_5,MODE_6,MODE_7,MODE_8,MODE_9,MODE_10,?,?,?,?,?" line.long 0x04 "AVS_STAT,AVS STAT register" bitfld.long 0x04 31. "STAT_END_OF_SLICE,stat_end_of_vop ECD sets this field to 1 when the current macroblock is the last macroblock in a VOP Once this field is set ECD keeps this field to 1 until the next macroblock processing is started" "0,1" bitfld.long 0x04 9. "ERR_ILL_NEXT_START_CODE_SEARCH,err_ill_next_start_code_search If ECD founds error and ECD status is changed into ERR in error detection described in section 8.5. ECD starts to search the next start code search" "0,1" newline bitfld.long 0x04 8. "ERR_ILL_END_OF_SLICE,err_ill_end_of_slice Some encoder wrongly encode EOS" "0,1" bitfld.long 0x04 7. "ERR_ILL_MB_SKIP_RUN,err_ill_mb_skip_run If ECD founds decoded mb_skip_run is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 6. "ERR_ILL_MB_TYPE,err_ill_mb_type If ECD founds decoded mb_type is out of range this field is set to 1 by ECD; otherwise 0" "0,1" bitfld.long 0x04 5. "ERR_ILL_INTRA_CHROMA_PRED_MODE,err_ill_intra_chroma_pred_mode If ECD founds decoded intra_chroma_pred_mode is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 4. "ERR_ILL_MV_DIFF,err_ill_mv_diff If ECD founds decoded mv_diff is out of range this field is set to 1 by ECD; otherwise 0" "0,1" bitfld.long 0x04 3. "ERR_ILL_CBP,err_ill_cbp If ECD founds decoded cbp is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 2. "ERR_ILL_MB_QP_DELTA,err_ill_mb_qp_delta If ECD founds decoded mb_qp_delta is out of range this field is set to 1 by ECD; otherwise 0" "0,1" bitfld.long 0x04 1. "ERR_ILL_COEFF,err_ill_coeff If ECD founds decoded coefficient is out of range this field is set to 1 by ECD; otherwise 0" "0,1" newline bitfld.long 0x04 0. "ERR_ILL_EOB,err_ill_eob If ECD cannot found end of block in 64 coefficients this field is set to 1 by ECD; otherwise 0" "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "H264_ERR_STAT,H.264 STAT register" bitfld.long 0x00 31. "EOS," "0,1" bitfld.long 0x00 4. "SC_ERR," "0,1" newline bitfld.long 0x00 3. "MV_ERR," "0,1" bitfld.long 0x00 2. "ALGN_ERR," "0,1" newline bitfld.long 0x00 1. "IPCM_ALGN_ERR," "0,1" bitfld.long 0x00 0. "SYM_ERR," "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "INT_STATUS,INT STAT register" bitfld.long 0x00 31. "PRCS_DONE,If encoding or decoding of a picture is finished an interrupt pulse is asserted and this status bit becomes high" "PRCS_DONE_0,PRCS_DONE_1" bitfld.long 0x00 30. "EOS_DONE,If encoding of decoding of a scan is finished an interrupt pulse is asserted and this status bit becomes high" "EOS_DONE_0,EOS_DONE_1" newline bitfld.long 0x00 2. "BLK_COEF_NUM_ERR,If current MCU has a block which has more than 64 coefficients this error bit becomes high" "BLK_COEF_NUM_ERR_0,BLK_COEF_NUM_ERR_1" bitfld.long 0x00 1. "RSTRT_INTVL_ERR,If number of MCU between neighbored restart markers is not equal to restart interval this error bit becomes high" "RSTRT_INTVL_ERR_0,RSTRT_INTVL_ERR_1" newline bitfld.long 0x00 0. "VLD_TBL_ERR,If stream data which is out of table is detected the JPEG core makes this bit high" "VLD_TBL_ERR_0,VLD_TBL_ERR_1" rgroup.long 0xA4++0x03 line.long 0x00 "MP2_STAT,MP2 STAT register" bitfld.long 0x00 31. "STAT_END_OF_SLICE,Showing the current macroblock is the last macroblock in a slice" "0,1" bitfld.long 0x00 15. "ERR_DCCOEF_OVERFLOW,Showing the result of dc prediction is overflowed or under flowed" "0,1" newline bitfld.long 0x00 14. "ERR_ILL_NEXT_START_CODE_SEARCH,Showing next start code searching infinite error" "0,1" bitfld.long 0x00 13. "ERR_ILL_SLICE_START_POSITION,In decoding showing the following two data is mismatched: - macroblock position derived from slice_vertical_position and macroblock_address_increment - macroblock position in ECD MMR In encoding this field is fixed to 0" "0,1" newline bitfld.long 0x00 12. "ERR_ILL_QUANTISER_SCALE_CODE,In decoding decoded quantizer_scale_code is 0" "0,1" bitfld.long 0x00 11. "ERR_ILL_END_OF_SLICE,In decoding EOS cannot be found at the end of picture" "0,1" newline bitfld.long 0x00 10. "ERR_MB_ADDR_INCREMENT,In decoding VLD out of table in macroblock_address_increment" "0,1" bitfld.long 0x00 9. "ERR_MB_TYPE,In decoding VLD out of table in macroblock_type" "0,1" newline bitfld.long 0x00 8. "ERR_MOTION_CODE,In decoding VLD out of table in motion_code and dmv" "0,1" bitfld.long 0x00 7. "ERR_CBP,In decoding VLD out of table in coded_block_pattern" "0,1" newline bitfld.long 0x00 6. "ERR_DCT_COEF,In decoding VLD out of table in DCT coefficient" "0,1" bitfld.long 0x00 5. "ERR_ILL_MBTYPE_D_PIC,In decoding decoded macroblock_type != 1 when D-picture" "0,1" newline bitfld.long 0x00 4. "ERR_ILL_MARKER_CONCEALMENT,In decoding decoded marker_bit != 0 when both the concealment_motion_vector and macroblock_intra are equal to 1" "0,1" bitfld.long 0x00 3. "ERR_ILL_MP2_ESCAPE_LVL,In decoding decoded level from MPEG-2 ESCAPE code is 0x000 or 0x800" "0,1" newline bitfld.long 0x00 2. "ERR_ILL_MP1_ESCAPE_LVL,In decoding decoded level from MPEG-1 ESCAPE code is 0x0000 or 0x8000" "0,1" bitfld.long 0x00 1. "ERR_ILL_EOB,In decoding ECD cannot find EOB end of block in a 64 coefficient block" "0,1" newline bitfld.long 0x00 0. "ERR_ILL_EOM,In decoding ECD cannot find EOM end of macroblock at the end of macroblock when picture_type is D-picture" "0,1" rgroup.long 0xA4++0x03 line.long 0x00 "MP4_STAT,MP4 STAT register" bitfld.long 0x00 31. "STAT_END_OF_PACKET,ECD sets this field to 1 when the current macroblock is the last macroblock in a packet" "0,1" bitfld.long 0x00 25. "ERR_NEXT_START_CODE_SEARCH,ECD sets this field to 1 if next start code search is 'failed'" "0,1" newline bitfld.long 0x00 24. "ERR_PKT_RESYNC_MARKER,ECD sets this field to 1 when resync_marker at the beginning of packet header is incorrect" "0,1" bitfld.long 0x00 23. "ERR_PKT_NEXT_START_CODE,ECD sets this field to 1 when next_start_code at the end of VOP is incorrect or start_code at the beginning of slice or at the end of VOP is incorrect" "0,1" newline bitfld.long 0x00 22. "ERR_PKT_ZERO_BIT,ECD sets this field to 1 when zero_bit at the end of GOB or slice layer is incorrect or emulation_prevention_bit in slice header is incorrect" "0,1" bitfld.long 0x00 21. "ERR_PKT_MBNUM,ECD sets this field to 1 when macroblock_number in packet header is dropped" "0,1" newline bitfld.long 0x00 20. "ERR_PKT_QUANT_SCALE,ECD sets this field to 1 when quant_scale in packet header is illegal" "0,1" bitfld.long 0x00 19. "ERR_PKT_TIME,ECD sets this field to 1 when modulo_time or vop_time_increment in packet header is changed" "0,1" newline bitfld.long 0x00 18. "ERR_PKT_MARKER_BIT,ECD sets this field to 1 when marker_bit in packet header is incorrect" "0,1" bitfld.long 0x00 17. "ERR_PKT_CHG_VOP_CODING_TYPE,ECD sets this field to 1 when vop_coding_type in packet header is changed" "0,1" newline bitfld.long 0x00 16. "ERR_PKT_ILL_VOP_CODING_TYPE,ECD sets this field to 1 when vop_coding_type in packet header is illegal" "0,1" bitfld.long 0x00 15. "ERR_PKT_VOP_FCODE,ECD sets this field to 1 when vop_fcode_forward or vop_fcode_backward in packet header is illegal" "0,1" newline bitfld.long 0x00 14. "ERR_GOB_GOBNUM,ECD sets this field to 1 when gob_number is dropped or macroblock_address in slice header is dropped" "0,1" bitfld.long 0x00 13. "ERR_GOB_GOB_FRAME_ID,ECD sets this field to 1 when gob_frame_id is changed" "0,1" newline bitfld.long 0x00 12. "ERR_GOB_QUANT_SCALE,ECD sets this field to 1 when quant_scale in GOB header is illegal or slice_quantizer_information in slice header is illegal" "0,1" bitfld.long 0x00 11. "ERR_MBHD_MCBPC,ECD sets this field to 1 when mcbpc code is illegal" "0,1" newline bitfld.long 0x00 10. "ERR_MBHD_H263_4MV,ECD3 sets this field to 1 if one of the following two conditions is true: - H263_mode is ON deblocking_filter_mode = 0 no_gob_header = 0 and decoded macroblock type is INTRA4V or INTRA4V_Q" "0,1" bitfld.long 0x00 9. "ERR_MBHD_CBPY,ECD sets this field to 1 when cpby code is illegal (non-B-VOP)" "0,1" newline bitfld.long 0x00 7. "ERR_MBHD_MB_TYPE,ECD sets this field to 1 when mb_type code is illegal (B-VOP)" "0,1" bitfld.long 0x00 6. "ERR_MBHD_MV_DATA,ECD sets this field to 1 when horizontal_mv_data or vertical_mv_data code is illegal" "0,1" newline bitfld.long 0x00 5. "ERR_BLK_DCT_DC_SIZE,ECD sets this field to 1 when dct_dc_size code is illegal" "0,1" bitfld.long 0x00 4. "ERR_BLK_TCOEF,ECD sets this field to 1 when tcoef code is illegal" "0,1" newline bitfld.long 0x00 3. "ERR_BLK_MARKER_BIT,ECD sets this field to 1 when marker_bit in dct_dc_size ESCAPE3 or RVLC is incorrect" "0,1" bitfld.long 0x00 2. "ERR_BLK_ESCAPE_LEVEL,ECD sets this field to 1 when ESCAPE3 level = 0 or 0x800 RVLC ESCAPE level = 0 H.263 DC = 0x00 or 0x80 or H.263 ESCAPE level = 0 or 0x80" "0,1" newline bitfld.long 0x00 1. "ERR_BLK_RVLC_ESCAPE_CODE,ECD sets this field to 1 when the last ESCAPE code of RVLC ESCAPE is not '0000s'" "0,1" bitfld.long 0x00 0. "ERR_BLK_EOB,ECD sets this field to 1 when ECD cannot find EOB in 64 coefficients" "0,1" rgroup.long 0xA4++0x07 line.long 0x00 "VC1_STAT,VC-1 STAT register" bitfld.long 0x00 31. "INT_EOS," "0,1" bitfld.long 0x00 10. "WARN_EOS_SYNCMARKER,This issue is raised when ECD3 cannot find syncmarker header syntax even though a single-bit just after decoding last MB is equal to 0" "0,1" newline bitfld.long 0x00 9. "WARN_EOS_TRAILINGBIT," "0,1" bitfld.long 0x00 8. "WARN_MQUANT_OVERFLOW,warn_mquant_overflow" "0,1" newline bitfld.long 0x00 2. "ERR_EOS,err_eos indicates an error during search processing for next start code" "0,1" bitfld.long 0x00 1. "ERR_VLC_TABLE,err_vlc_table indicates when the following irregular cases happen" "0,1" newline bitfld.long 0x00 0. "ERR_BLK_COEF,err_blk_coef indicates when the following irregular cases happen" "0,1" line.long 0x04 "AVS_MASK,AVS MASK register" bitfld.long 0x04 31. "MASK_STAT_END_OF_SLICE,Mask flags correspond to status bits" "0,1" bitfld.long 0x04 9. "MASK_ERR_ILL_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 8. "MASK_ERR_ILL_END_OF_SLICE,Mask flags correspond to status bits" "0,1" bitfld.long 0x04 7. "MASK_ERR_ILL_MB_SKIP_RUN,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 6. "MASK_ERR_ILL_MB_TYPE,Mask flags correspond to status bits" "0,1" bitfld.long 0x04 5. "MASK_ERR_ILL_INTRA_CHROMA_PRED_MODE,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 4. "MASK_ERR_ILL_MV_DIFF,Mask flags correspond to status bits" "0,1" bitfld.long 0x04 3. "MASK_ERR_ILL_CBP,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 2. "MASK_ERR_ILL_MB_QP_DELTA,Mask flags correspond to status bits" "0,1" bitfld.long 0x04 1. "MASK_ERR_ILL_COEFF,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x04 0. "MASK_ERR_ILL_EOB,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x03 line.long 0x00 "H264_ERR_MSK,H.264 MASK register" rbitfld.long 0x00 31. "EOS_MSK,EOS_MSK = 1 enables detection of an EOS" "0,1" rbitfld.long 0x00 4. "SC_ERR_MSK,SC_ERR_MSK = 0 (fixed) which indicates that int_err will never be issued on detecting start code search error" "0,1" newline rbitfld.long 0x00 3. "MV_ERR_MSK,MV_ERR_MSK = 1 enables detection of mv errors (MV_ERR)" "0,1" bitfld.long 0x00 2. "ALGN_ERR_MSK,ALGN_ERR_MSK = 1 enables detection of CABAC alignment bits errors (ALGN_ERR)" "0,1" newline bitfld.long 0x00 1. "IPCM_ALGN_ERR_MSK,IPCM_ALGN_ERR_MSK = 1 enables detection of I_PCM alignment bits errors (IPCM_ALGN_ERR)" "0,1" rbitfld.long 0x00 0. "SYM_ERR_MSK,SYM_ERR_MSK = 1 enables detections of all other bitstream errors (SYM_ERR)" "0,1" rgroup.long 0xA8++0x03 line.long 0x00 "INT_MASK,INT MASK register" bitfld.long 0x00 31. "PRCS_DONE_MASK,Mask register for prcs_done signal" "PRCS_DONE_MASK_0,PRCS_DONE_MASK_1" bitfld.long 0x00 30. "EOS_MASK,Mask register for eos_done pulse signal" "EOS_MASK_0,EOS_MASK_1" newline bitfld.long 0x00 0. "VLD_TBL_ERR,Mask register for control of error interrupt assertion" "VLD_TBL_ERR_0,VLD_TBL_ERR_1" group.long 0xA8++0x03 line.long 0x00 "MP2_MASK,MP2 MASK register" rbitfld.long 0x00 31. "MASK_STAT_END_OF_SLICE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 15. "MASK_ERR_DCCOEF_OVERFLOW,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 14. "MASK_ERR_ILL_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 13. "MASK_ERR_ILL_SLICE_START_POSITION,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 12. "MASK_ERR_ILL_QUANTISER_SCALE_CODE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 11. "MASK_ERR_ILL_END_OF_SLICE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 10. "MASK_ERR_MB_ADDR_INCREMENT,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 9. "MASK_ERR_MB_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 8. "MASK_ERR_MOTION_CODE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 7. "MASK_ERR_CBP,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 6. "MASK_ERR_DCT_COEF,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 5. "MASK_ERR_ILL_MBTYPE_D_PIC,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 4. "MASK_ERR_ILL_MARKER_CONCEALMENT,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 3. "MASK_ERR_ILL_MP2_ESCAPE_LVL,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 2. "MASK_ERR_ILL_MP1_ESCAPE_LVL,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 1. "MASK_ERR_ILL_EOB,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 0. "MASK_ERR_ILL_EOM,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x03 line.long 0x00 "MP4_MASK,MP4 MASK register" rbitfld.long 0x00 31. "MASK_STAT_END_OF_PACKET,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 25. "MASK_ERR_NEXT_START_CODE_SEARCH,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 24. "MASK_ERR_PKT_RESYNC_MARKER,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 23. "MASK_ERR_PKT_NEXT_START_CODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 22. "MASK_ERR_PKT_ZERO_BIT,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 21. "MASK_ERR_PKT_MBNUM,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 20. "MASK_ERR_PKT_QUANT_SCALE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 19. "MASK_ERR_PKT_TIME,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 18. "MASK_ERR_PKT_MARKER_BIT,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 17. "MASK_ERR_PKT_CHG_VOP_CODING_TYPE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 16. "MASK_ERR_PKT_ILL_VOP_CODING_TYPE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 15. "MASK_ERR_PKT_VOP_FCODE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 14. "MASK_ERR_GOB_GOBNUM,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 13. "MASK_ERR_GOB_GOB_FRAME_ID,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 12. "MASK_ERR_GOB_QUANT_SCALE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 11. "MASK_ERR_MBHD_MCBPC,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 10. "MASK_ERR_MBHD_H263_4MV,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 9. "MASK_ERR_MBHD_CBPY,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 7. "MASK_ERR_MBHD_MB_TYPE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 6. "MASK_ERR_MBHD_MV_DATA,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 5. "MASK_ERR_BLK_DCT_DC_SIZE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 4. "MASK_ERR_BLK_TCOEF,Mask flags correspond to status bits" "0,1" newline bitfld.long 0x00 3. "MASK_ERR_BLK_MARKER_BIT,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 2. "MASK_ERR_BLK_ESCAPE_LEVEL,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 1. "MASK_ERR_BLK_RVLC_ESCAPE_CODE,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 0. "MASK_ERR_BLK_EOB,Mask flags correspond to status bits" "0,1" group.long 0xA8++0x07 line.long 0x00 "VC1_MASK,VC-1 MASK register" rbitfld.long 0x00 31. "MASK_INT_EOS," "0,1" rbitfld.long 0x00 10. "MASK_EOS_SYNCMARKER," "0,1" newline rbitfld.long 0x00 9. "MASK_WARN_EOS_TRAILINGBIT,Reserved" "0,1" bitfld.long 0x00 8. "MASK_MQUANT_OVERFLOW,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 2. "MASK_ERR_EOS,Mask flags correspond to status bits" "0,1" rbitfld.long 0x00 1. "MASK_ERR_VLC_TABLE,Mask flags correspond to status bits" "0,1" newline rbitfld.long 0x00 0. "MASK_ERR_BLK_COEF,Mask flags correspond to status bits" "0,1" line.long 0x04 "AVS_WORK0,AVS WORK0 register" hexmask.long.word 0x04 16.--29. 1. "SKIPMBCOUNT,SkipMbCount This field specifies SkipMbCount described in AVS standard section 9.3" bitfld.long 0x04 9. "SLICE_DATA_RD_EN,Slice data read enable flag" "0,1" newline bitfld.long 0x04 8. "NEXT_START_CODE_SEARCH,next_start_code_search This field specifies ECD starts start code search or not when error is occurred" "0,1" group.long 0xAC++0x03 line.long 0x00 "CFG_QP," bitfld.long 0x00 31. "MV_FLAG_EN,MV_FLAG_EN =1 enables motion vector and reference index comparison in decoding" "0,1" bitfld.long 0x00 30. "H264_RSV,Reserved for future use" "0,1" newline bitfld.long 0x00 29. "FORCE_SLC_LD,FORCE_SLC_LD = 1 forces slice information data loading from memory for each macroblock process" "0,1" rbitfld.long 0x00 28. "USE_CABAC,USE_CABAC = 1 indicates that the CABAC is in use for entropy coding" "0,1" newline rbitfld.long 0x00 18.--19. "COL_MB_FMT,COL_MB_FMT indicates the macroblock header format type for the co-located macroblock data" "0,1,2,3" rbitfld.long 0x00 16.--17. "MB_FMT,MB_FMT indicates the macroblock header format type for the current macroblock and neighboring macroblocks in the current picture" "0,1,2,3" newline bitfld.long 0x00 8.--13. "QP_DELTA,QP_DELTA is equal to mb_qp_delta of the last macroblock decoded or encoded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "QP,QP is equal to the quantizer parameter for the last macroblock decoded or encoded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xAC++0x03 line.long 0x00 "JPEG_CTRL,JPEG Control register" hexmask.long.word 0x00 16.--31. 1. "DC_PRED_Y,Luminance DC prediction value is stored in register" rbitfld.long 0x00 8.--10. "RSTRT_MRKR_CNT,Restart marker counter value (during encoding only) is reflected in this register" "RSTRT_MRKR_CNT_0,RSTRT_MRKR_CNT_1,RSTRT_MRKR_CNT_2,RSTRT_MRKR_CNT_3,RSTRT_MRKR_CNT_4,RSTRT_MRKR_CNT_5,RSTRT_MRKR_CNT_6,RSTRT_MRKR_CNT_7" newline bitfld.long 0x00 1. "DC_PRED_RST,If this register bit is high DC prediction for the first block of the current MCU is not executed" "DC_PRED_RST_0,DC_PRED_RST_1" bitfld.long 0x00 0. "INIT_EN,This bit controls initialization of JPEG core on ECD module" "INIT_EN_0,INIT_EN_1" group.long 0xAC++0x03 line.long 0x00 "MP2_WORK0,MP2 WORK0 register" hexmask.long.word 0x00 16.--31. 1. "MB_SKIP_RUN,Specifies the number of macroblocks to be skipped" bitfld.long 0x00 11. "START_CODE_SEARCH_FLAG,Specifies whether ECD starts searching next start code or not when error is occurred in decoding" "0,1" newline bitfld.long 0x00 10. "MACROBLOCK_MOTION_BACKWARD,Specifies macroblock_motion_backward described in MPEG-2 standard section 6.3.17.1" "0,1" bitfld.long 0x00 9. "MACROBLOCK_MOTION_FORWARD,Specifies macroblock_motion_forward described in MPEG-2 standard section 6.3.17.1" "0,1" newline bitfld.long 0x00 0.--4. "PREV_QUANTISER_SCALE_CODE,Specifies previous macroblock's quantizer_scale_code described in MPEG-2 standard section 6.3.16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAC++0x03 line.long 0x00 "MP4_WORK0,MP4 WORK0 register" bitfld.long 0x00 24.--28. "RUNNINGQP,This field is used for reserving runningQp for the next macroblock not showing the current macroblock's quantizer_scale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--22. "VOP_FCODE_BACKWARD,These fields specify vop_fcode_forward and vop_fcode_backward updated at packet header" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. "VOP_FCODE_FORWARD,These fields specify vop_fcode_forward and vop_fcode_backward updated at packet header" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. "DP_MODE,This field indicates which data is encoding or decoding in data partitioning mode" "0,1,2,3" newline bitfld.long 0x00 12.--13. "GOB_FRAME_ID,This field specifies gob_frame_id which is updated at gob header" "0,1,2,3" bitfld.long 0x00 8.--10. "INTRA_DC_VLC_THR,This is a 3-bit code that specifies a threshold value of quantizer scale used to switch between two VLC's for coding of Intra DC coefficients" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "FIRST_NON_EMPTY_HEADER,This is the flag to indicate the first non empty GOB header or not" "0,1" bitfld.long 0x00 6. "MINI_SLICE_HEADER_FLAG,In H.263 decoding this field specifies whether the current slice header is mini slice header or not" "0,1" newline bitfld.long 0x00 5. "START_CODE_SEARCH_FLAG,In decoding this field specifies whether ECD starts searching next_start_code and resync_marker or not when error is occurred in decoding" "0,1" bitfld.long 0x00 0.--4. "GOB_NUMBER,In decoding this field specifies gob_number of the current macroblock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAC++0x07 line.long 0x00 "VC1_WORK,VC-1 WORK register" bitfld.long 0x00 8. "FIXED_LENTH_CODE,Presence of Fixed Length Code (escape mode 3) Setting 1 specifies the first case of escape mode 3 in a frame" "0,1" rbitfld.long 0x00 7. "FIXED_TO_ZERO," "0,1" newline bitfld.long 0x00 4.--6. "RUN_CODE_SIZEOFESCAPE_MODE_3,Run code size of escape mode 3 Run code size of escape mode 3 In decoding this register is automatically updated when presence of fixed length code is cleared to 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. "LEVEL_CODE_SIZEOFESCAPE_MODE_3,Level code size of escape mode 3 Level code size of escape mode 3 In decoding this register is automatically updated when presence of fixed length code is cleared to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "AVS_WORK1,AVS WORK1 register" hexmask.long.word 0x04 20.--31. 1. "PTR_MVD_15_4,PTR_MVD Start address of temporary MVD info" rbitfld.long 0x04 16.--19. "PTR_MVD_3_0,PTR_MVD Start address of temporary MVD info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x04 4.--15. 1. "PTR_RUNLVL_15_4,PTR_RUNLVL Start address of temporary run level info" rbitfld.long 0x04 0.--3. "PTR_RUNLVL_3_0,PTR_RUNLVL Start address of temporary run level info" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x03 line.long 0x00 "CDC_VP_4," hexmask.long.word 0x00 3.--15. 1. "ACPREDPTR_15_3,ACPREDPTR I picture except simple/main I picture" group.long 0xB0++0x03 line.long 0x00 "MP2_WORK1,MP2 WORK1 register" hexmask.long.word 0x00 16.--26. 1. "DCT_DC_PRED1,In decoding this value specifies dct_dc_pred[1] described in MPEG-2 standard section 7.2.1" hexmask.long.word 0x00 0.--10. 1. "DCT_DC_PRED0,In decoding this value specifies dct_dc_pred[0] described in MPEG-2 standard section 7.2.1" group.long 0xB0++0x03 line.long 0x00 "MP4_WORK1,MP4 WORK1 register" hexmask.long.word 0x00 16.--29. 1. "SKIPRUN,In the case of B-VOP decoding if decoded macroblock_number in video_packet_header > the macroblock address counter ECD notices the macroblocks from the macroblock address counter to macroblock_number -1 would be not_coded macroblock" hexmask.long.byte 0x00 8.--15. 1. "SLICE_Y,In data partitioning this field shows the position of the first macroblock in a slice" newline hexmask.long.byte 0x00 0.--7. 1. "SLICE_X,In data partitioning this field shows the position of the first macroblock in a slice" group.long 0xB0++0x03 line.long 0x00 "SKIP_RUN," hexmask.long.word 0x00 0.--15. 1. "SKIP_RUN_NB,SKIP_RUN_NB indicates the number of skipped macroblocks left in CAVLC" group.long 0xB0++0x07 line.long 0x00 "VLC_HUFFPTR_DC,Pointers to Huffman table for VLC DC components" rbitfld.long 0x00 29.--31. "VLCHUFFPTR_DC_CHROMA_31_29,Indicating start address of Huffman table for VLC DC Chroma" "VLCHUFFPTR_DC_CHROMA_31_29_0,VLCHUFFPTR_DC_CHROMA_31_29_1,VLCHUFFPTR_DC_CHROMA_31_29_2,VLCHUFFPTR_DC_CHROMA_31_29_3,VLCHUFFPTR_DC_CHROMA_31_29_4,VLCHUFFPTR_DC_CHROMA_31_29_5,VLCHUFFPTR_DC_CHROMA_31_29_6,VLCHUFFPTR_DC_CHROMA_31_29_7" hexmask.long.word 0x00 19.--28. 1. "VLCHUFFPTR_DC_CHROMA_28_19,Indicating start address of Huffman table for VLC DC Chroma" newline rbitfld.long 0x00 16.--18. "VLCHUFFPTR_DC_CHROMA_18_16,Indicating start address of Huffman table for VLC DC Chroma" "VLCHUFFPTR_DC_CHROMA_18_16_0,VLCHUFFPTR_DC_CHROMA_18_16_1,VLCHUFFPTR_DC_CHROMA_18_16_2,VLCHUFFPTR_DC_CHROMA_18_16_3,VLCHUFFPTR_DC_CHROMA_18_16_4,VLCHUFFPTR_DC_CHROMA_18_16_5,VLCHUFFPTR_DC_CHROMA_18_16_6,VLCHUFFPTR_DC_CHROMA_18_16_7" rbitfld.long 0x00 13.--15. "VLCHUFFPTR_DC_LUMA_15_13,Indicating start address of Huffman table for VLC DC-luma" "VLCHUFFPTR_DC_LUMA_15_13_0,VLCHUFFPTR_DC_LUMA_15_13_1,VLCHUFFPTR_DC_LUMA_15_13_2,VLCHUFFPTR_DC_LUMA_15_13_3,VLCHUFFPTR_DC_LUMA_15_13_4,VLCHUFFPTR_DC_LUMA_15_13_5,VLCHUFFPTR_DC_LUMA_15_13_6,VLCHUFFPTR_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "VLCHUFFPTR_DC_LUMA_12_3,Indicating start address of Huffman table for VLC DC-luma" rbitfld.long 0x00 0.--2. "VLCHUFFPTR_DC_LUMA_2_0,Indicating start address of Huffman table for VLC DC-luma" "VLCHUFFPTR_DC_LUMA_2_0_0,VLCHUFFPTR_DC_LUMA_2_0_1,VLCHUFFPTR_DC_LUMA_2_0_2,VLCHUFFPTR_DC_LUMA_2_0_3,VLCHUFFPTR_DC_LUMA_2_0_4,VLCHUFFPTR_DC_LUMA_2_0_5,VLCHUFFPTR_DC_LUMA_2_0_6,VLCHUFFPTR_DC_LUMA_2_0_7" line.long 0x04 "CABAC_REG," bitfld.long 0x04 29. "PRE_SKIP,PRE_SKIP = 1 indicates that both top and bottom macroblocks in MB-AFF mode decoding are skipped" "0,1" bitfld.long 0x04 28. "FIRST_BIT,FIRST_BIT = 1 indicates that the next bit put by CABAC is the first bit since the last CABAC initialization" "0,1" newline hexmask.long.word 0x04 16.--25. 1. "C_LOW_OFST,C_LOW_OFST is equal to codILow in encoding and codIOffset in decoding" hexmask.long.word 0x04 0.--8. 1. "C_RNG,C_RNG is equal to codIRange" group.long 0xB4++0x03 line.long 0x00 "CDC_VP_5," hexmask.long.word 0x00 3.--15. 1. "OVERFLAGPTR_15_3,OVERFLAGPTR I picture except simple/main I picture" group.long 0xB4++0x03 line.long 0x00 "MP2_WORK2,MP2 WORK2 register" hexmask.long.word 0x00 0.--10. 1. "DCT_DC_PRED2,In decoding this value specifies dct_dc_pred[2] described in MPEG-2 standard section 7.2.1" group.long 0xB4++0x03 line.long 0x00 "MP4_WORK2,MP4 WORK2 register" hexmask.long.word 0x00 16.--29. 1. "SLICE_MBADDR,In data partition decoding this field shows the macroblock address of the first macroblock in the current slice" bitfld.long 0x00 0.--1. "GOB_MBROW,In the case h263_mode = 1 and decoding this field shows the vertical position of current macroblock in a slice or GOB" "0,1,2,3" group.long 0xB4++0x07 line.long 0x00 "VLC_HUFFPTR_AC,Pointers to Huffman table for VLC AC components" rbitfld.long 0x00 29.--31. "VLCHUFFPTR_AC_CHROMA_31_29,Indicating start address of Huffman table for VLC AC Chroma" "VLCHUFFPTR_AC_CHROMA_31_29_0,VLCHUFFPTR_AC_CHROMA_31_29_1,VLCHUFFPTR_AC_CHROMA_31_29_2,VLCHUFFPTR_AC_CHROMA_31_29_3,VLCHUFFPTR_AC_CHROMA_31_29_4,VLCHUFFPTR_AC_CHROMA_31_29_5,VLCHUFFPTR_AC_CHROMA_31_29_6,VLCHUFFPTR_AC_CHROMA_31_29_7" hexmask.long.word 0x00 19.--28. 1. "VLCHUFFPTR_AC_CHROMA_28_19,Indicating start address of Huffman table for VLC AC Chroma" newline rbitfld.long 0x00 16.--18. "VLCHUFFPTR_AC_CHROMA_18_16,Indicating start address of Huffman table for VLC AC Chroma" "VLCHUFFPTR_AC_CHROMA_18_16_0,VLCHUFFPTR_AC_CHROMA_18_16_1,VLCHUFFPTR_AC_CHROMA_18_16_2,VLCHUFFPTR_AC_CHROMA_18_16_3,VLCHUFFPTR_AC_CHROMA_18_16_4,VLCHUFFPTR_AC_CHROMA_18_16_5,VLCHUFFPTR_AC_CHROMA_18_16_6,VLCHUFFPTR_AC_CHROMA_18_16_7" rbitfld.long 0x00 13.--15. "VLCHUFFPTR_AC_LUMA_15_13,Indicating start address of Huffman table for VLC AC-luma" "VLCHUFFPTR_AC_LUMA_15_13_0,VLCHUFFPTR_AC_LUMA_15_13_1,VLCHUFFPTR_AC_LUMA_15_13_2,VLCHUFFPTR_AC_LUMA_15_13_3,VLCHUFFPTR_AC_LUMA_15_13_4,VLCHUFFPTR_AC_LUMA_15_13_5,VLCHUFFPTR_AC_LUMA_15_13_6,VLCHUFFPTR_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "VLCHUFFPTR_AC_LUMA_12_3,Indicating start address of Huffman table for VLC AC-luma" rbitfld.long 0x00 0.--2. "VLCHUFFPTR_AC_LUMA_2_0,Indicating start address of Huffman table for VLC AC-luma" "VLCHUFFPTR_AC_LUMA_2_0_0,VLCHUFFPTR_AC_LUMA_2_0_1,VLCHUFFPTR_AC_LUMA_2_0_2,VLCHUFFPTR_AC_LUMA_2_0_3,VLCHUFFPTR_AC_LUMA_2_0_4,VLCHUFFPTR_AC_LUMA_2_0_5,VLCHUFFPTR_AC_LUMA_2_0_6,VLCHUFFPTR_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_6," hexmask.long.word 0x04 3.--15. 1. "MVMODEPTR_15_3,MVMODEPTR Progressive P picture" group.long 0xB8++0x03 line.long 0x00 "MP2_WORK3,MP2 WORK3 register" hexmask.long.word 0x00 16.--31. 1. "PMV1,Specifies PMV[0][0][1] described in MPEG-2 standard section 7.6.3" hexmask.long.word 0x00 0.--15. 1. "PMV0,Specifies PMV[0[0][0] described in MPEG-2 standard section 7.6.3. They are half-pel precision" group.long 0xB8++0x03 line.long 0x00 "MP4_WORK3," rbitfld.long 0x00 13.--14. "PTR_MVD_14_13,This field specifies temporary MVD data pointer" "0,1,2,3" hexmask.long.word 0x00 4.--12. 1. "PTR_MVD_12_4,This field specifies temporary MVD data pointer" newline rbitfld.long 0x00 0.--3. "PTR_MVD_3_0,This field specifies temporary MVD data pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x03 line.long 0x00 "SYM_CNT," group.long 0xB8++0x07 line.long 0x00 "UVLD_CTRL_TBPTR_DC,Pointers to control table for UVLD DC components" rbitfld.long 0x00 29.--31. "UVLD_CTRL_DC_CHROMA_31_29,Indicating start address of control table for UVLD DC-chroma" "UVLD_CTRL_DC_CHROMA_31_29_0,UVLD_CTRL_DC_CHROMA_31_29_1,UVLD_CTRL_DC_CHROMA_31_29_2,UVLD_CTRL_DC_CHROMA_31_29_3,UVLD_CTRL_DC_CHROMA_31_29_4,UVLD_CTRL_DC_CHROMA_31_29_5,UVLD_CTRL_DC_CHROMA_31_29_6,UVLD_CTRL_DC_CHROMA_31_29_7" hexmask.long.word 0x00 19.--28. 1. "UVLD_CTRL_DC_CHROMA_28_19,Indicating start address of control table for UVLD DC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CTRL_DC_CHROMA_18_16,Indicating start address of control table for UVLD DC-chroma" "UVLD_CTRL_DC_CHROMA_18_16_0,UVLD_CTRL_DC_CHROMA_18_16_1,UVLD_CTRL_DC_CHROMA_18_16_2,UVLD_CTRL_DC_CHROMA_18_16_3,UVLD_CTRL_DC_CHROMA_18_16_4,UVLD_CTRL_DC_CHROMA_18_16_5,UVLD_CTRL_DC_CHROMA_18_16_6,UVLD_CTRL_DC_CHROMA_18_16_7" rbitfld.long 0x00 13.--15. "UVLD_CTRL_DC_LUMA_15_13,Indicating start address of control table for UVLD DC-luma" "UVLD_CTRL_DC_LUMA_15_13_0,UVLD_CTRL_DC_LUMA_15_13_1,UVLD_CTRL_DC_LUMA_15_13_2,UVLD_CTRL_DC_LUMA_15_13_3,UVLD_CTRL_DC_LUMA_15_13_4,UVLD_CTRL_DC_LUMA_15_13_5,UVLD_CTRL_DC_LUMA_15_13_6,UVLD_CTRL_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CTRL_DC_LUMA_12_3,Indicating start address of control table for UVLD DC-luma" rbitfld.long 0x00 0.--2. "UVLD_CTRL_DC_LUMA_2_0,Indicating start address of control table for UVLD DC-luma" "UVLD_CTRL_DC_LUMA_2_0_0,UVLD_CTRL_DC_LUMA_2_0_1,UVLD_CTRL_DC_LUMA_2_0_2,UVLD_CTRL_DC_LUMA_2_0_3,UVLD_CTRL_DC_LUMA_2_0_4,UVLD_CTRL_DC_LUMA_2_0_5,UVLD_CTRL_DC_LUMA_2_0_6,UVLD_CTRL_DC_LUMA_2_0_7" line.long 0x04 "BITS_OSTD," group.long 0xBC++0x03 line.long 0x00 "CDC_VP_7," hexmask.long.word 0x00 3.--15. 1. "SKIPMBPTR_15_3,SKIPMBPTR Progressive P/B picture Interlace Frame P/B picture" group.long 0xBC++0x03 line.long 0x00 "MP2_WORK4,MP2 WORK4 register" hexmask.long.word 0x00 16.--31. 1. "PMV4,Specifies PMV[0][1][1] described in MPEG-2 standard section 7.6.3" hexmask.long.word 0x00 0.--15. 1. "PMV3,Specifies PMV[0][1][0] described in MPEG-2 standard section 7.6.3" group.long 0xBC++0x03 line.long 0x00 "MP4_WORK4,MP4 WORK4 register" hexmask.long.word 0x00 16.--31. 1. "MVP01,MVP[0][1]: Motion Vector Predictors for B-VOP (field forward top motion vector predictor)" hexmask.long.word 0x00 0.--15. 1. "MVP00,MVP[0][0]: Motion Vector Predictors for B-VOP (field forward top motion vector predictor)" group.long 0xBC++0x07 line.long 0x00 "UVLD_CTRL_TBPTR_AC,Pointers to control table for UVLD AC components" rbitfld.long 0x00 29.--31. "UVLD_CTRL_AC_CHROMA_31_29,Indicating start address of control table for UVLD AC-chroma" "UVLD_CTRL_AC_CHROMA_31_29_0,UVLD_CTRL_AC_CHROMA_31_29_1,UVLD_CTRL_AC_CHROMA_31_29_2,UVLD_CTRL_AC_CHROMA_31_29_3,UVLD_CTRL_AC_CHROMA_31_29_4,UVLD_CTRL_AC_CHROMA_31_29_5,UVLD_CTRL_AC_CHROMA_31_29_6,UVLD_CTRL_AC_CHROMA_31_29_7" hexmask.long.word 0x00 19.--28. 1. "UVLD_CTRL_AC_CHROMA_28_19,Indicating start address of control table for UVLD AC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CTRL_AC_CHROMA_18_16,Indicating start address of control table for UVLD AC-chroma" "UVLD_CTRL_AC_CHROMA_18_16_0,UVLD_CTRL_AC_CHROMA_18_16_1,UVLD_CTRL_AC_CHROMA_18_16_2,UVLD_CTRL_AC_CHROMA_18_16_3,UVLD_CTRL_AC_CHROMA_18_16_4,UVLD_CTRL_AC_CHROMA_18_16_5,UVLD_CTRL_AC_CHROMA_18_16_6,UVLD_CTRL_AC_CHROMA_18_16_7" rbitfld.long 0x00 13.--15. "UVLD_CTRL_AC_LUMA_15_13,Indicating start address of control table for UVLD AC-luma" "UVLD_CTRL_AC_LUMA_15_13_0,UVLD_CTRL_AC_LUMA_15_13_1,UVLD_CTRL_AC_LUMA_15_13_2,UVLD_CTRL_AC_LUMA_15_13_3,UVLD_CTRL_AC_LUMA_15_13_4,UVLD_CTRL_AC_LUMA_15_13_5,UVLD_CTRL_AC_LUMA_15_13_6,UVLD_CTRL_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CTRL_AC_LUMA_12_3,Indicating start address of control table for UVLD AC-luma" rbitfld.long 0x00 0.--2. "UVLD_CTRL_AC_LUMA_2_0,Indicating start address of control table for UVLD AC-luma" "UVLD_CTRL_AC_LUMA_2_0_0,UVLD_CTRL_AC_LUMA_2_0_1,UVLD_CTRL_AC_LUMA_2_0_2,UVLD_CTRL_AC_LUMA_2_0_3,UVLD_CTRL_AC_LUMA_2_0_4,UVLD_CTRL_AC_LUMA_2_0_5,UVLD_CTRL_AC_LUMA_2_0_6,UVLD_CTRL_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_8," hexmask.long.word 0x04 3.--15. 1. "DIRECTPT_15_3,DIRECTPTR Progressive B picture Interlace Frame B picture" group.long 0xC0++0x03 line.long 0x00 "MP2_WORK5,MP2 WORK5 register" hexmask.long.word 0x00 16.--31. 1. "PMV6,Specifies PMV[1][0][1] described in MPEG-2 standard section 7.6.3" hexmask.long.word 0x00 0.--15. 1. "PMV5,Specifies PMV[1][0][0] described in MPEG-2 standard section 7.6.3" group.long 0xC0++0x03 line.long 0x00 "MP4_WORK5,MP4 WORK5 register" hexmask.long.word 0x00 16.--31. 1. "MVP11,MVP[1][1]: Motion Vector Predictors for B-VOP (field forward bottom motion vector predictor)" hexmask.long.word 0x00 0.--15. 1. "MVP10,MVP[1][0]: Motion Vector Predictors for B-VOP (field forward bottom motion vector predictor)" group.long 0xC0++0x03 line.long 0x00 "MVD_CUR_PTR," rbitfld.long 0x00 29.--31. "DP_MVD_CUR_1_15_13,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 19.--28. 1. "DP_MVD_CUR_1_12_3,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" newline rbitfld.long 0x00 16.--18. "DP_MVD_CUR_1_2_0,DP_MVD_CUR_1 specifies the pointer to motion vector delta data for bottom macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 13.--15. "DP_MVD_CUR_0_15_13,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--12. 1. "DP_MVD_CUR_0_12_3,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" rbitfld.long 0x00 0.--2. "DP_MVD_CUR_0_2_0,DP_MVD_CUR_0 specifies the pointer to motion vector delta data for the current macroblock or top macroblock of the current macroblock pair" "0,1,2,3,4,5,6,7" group.long 0xC0++0x07 line.long 0x00 "UVLD_CODE_TBPTR_DC,Pointers to code table for UVLD DC components" rbitfld.long 0x00 29.--31. "UVLD_CODE_DC_CHROMA31_29,Indicating start address of code table for UVLD DC-chroma" "UVLD_CODE_DC_CHROMA31_29_0,UVLD_CODE_DC_CHROMA31_29_1,UVLD_CODE_DC_CHROMA31_29_2,UVLD_CODE_DC_CHROMA31_29_3,UVLD_CODE_DC_CHROMA31_29_4,UVLD_CODE_DC_CHROMA31_29_5,UVLD_CODE_DC_CHROMA31_29_6,UVLD_CODE_DC_CHROMA31_29_7" hexmask.long.word 0x00 19.--28. 1. "UVLD_CODE_DC_CHROMA_28_19,Indicating start address of code table for UVLD DC-chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CODE_DC_CHROMA_18_16,Indicating start address of code table for UVLD DC-chroma" "UVLD_CODE_DC_CHROMA_18_16_0,UVLD_CODE_DC_CHROMA_18_16_1,UVLD_CODE_DC_CHROMA_18_16_2,UVLD_CODE_DC_CHROMA_18_16_3,UVLD_CODE_DC_CHROMA_18_16_4,UVLD_CODE_DC_CHROMA_18_16_5,UVLD_CODE_DC_CHROMA_18_16_6,UVLD_CODE_DC_CHROMA_18_16_7" rbitfld.long 0x00 13.--15. "UVLD_CODE_DC_LUMA_15_13,Indicating start address of code table for UVLD DC-luma" "UVLD_CODE_DC_LUMA_15_13_0,UVLD_CODE_DC_LUMA_15_13_1,UVLD_CODE_DC_LUMA_15_13_2,UVLD_CODE_DC_LUMA_15_13_3,UVLD_CODE_DC_LUMA_15_13_4,UVLD_CODE_DC_LUMA_15_13_5,UVLD_CODE_DC_LUMA_15_13_6,UVLD_CODE_DC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CODE_DC_LUMA_12_3,Indicating start address of code table for UVLD DC-luma" rbitfld.long 0x00 0.--2. "UVLD_CODE_DC_LUMA_2_0,Indicating start address of code table for UVLD DC-luma" "UVLD_CODE_DC_LUMA_2_0_0,UVLD_CODE_DC_LUMA_2_0_1,UVLD_CODE_DC_LUMA_2_0_2,UVLD_CODE_DC_LUMA_2_0_3,UVLD_CODE_DC_LUMA_2_0_4,UVLD_CODE_DC_LUMA_2_0_5,UVLD_CODE_DC_LUMA_2_0_6,UVLD_CODE_DC_LUMA_2_0_7" line.long 0x04 "CDC_VP_9," hexmask.long.word 0x04 3.--15. 1. "FIELDTXPTR_31_3,FIELDTXPTR Interlace Frame I picture" group.long 0xC4++0x03 line.long 0x00 "MP2_WORK6,MP2 WORK6 register" hexmask.long.word 0x00 16.--31. 1. "PMV8,Specifies PMV[1][1][1] described in MPEG-2 standard section 7.6.3" hexmask.long.word 0x00 0.--15. 1. "PMV7,Specifies PMV[1][1][0] described in MPEG-2 standard section 7.6.3" group.long 0xC4++0x03 line.long 0x00 "MP4_WORK6,MP4 WORK6 register" hexmask.long.word 0x00 16.--31. 1. "MVP21,MVP[2][1]: Motion Vector Predictors for B-VOP (field backward top motion vector predictor)" hexmask.long.word 0x00 0.--15. 1. "MVP20,MVP[2][0]: Motion Vector Predictors for B-VOP (field backward top motion vector predictor)" group.long 0xC4++0x03 line.long 0x00 "MVD_LFT_PTR," rbitfld.long 0x00 29.--31. "DP_MVD_LFT_1_15_13,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 19.--28. 1. "DP_MVD_LFT_1_12_3,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" newline rbitfld.long 0x00 16.--18. "DP_MVD_LFT_1_2_0,DP_MVD_LFT_1 specifies the pointer to motion vector delta data for bottom macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 13.--15. "DP_MVD_LFT_0_15_13,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 3.--12. 1. "DP_MVD_LFT_0_12_3,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" rbitfld.long 0x00 0.--2. "DP_MVD_LFT_0_2_0,DP_MVD_LFT_0 specifies the pointer to motion vector delta data for the left macroblock or top macroblock of the left macroblock pair" "0,1,2,3,4,5,6,7" group.long 0xC4++0x07 line.long 0x00 "UVLD_CODE_TBPTR_AC,Pointers to code table for UVLD AC components" rbitfld.long 0x00 29.--31. "UVLD_CODE_AC_CHROMA_31_29,Indicating start address of code table for UVLD AC Chroma" "UVLD_CODE_AC_CHROMA_31_29_0,UVLD_CODE_AC_CHROMA_31_29_1,UVLD_CODE_AC_CHROMA_31_29_2,UVLD_CODE_AC_CHROMA_31_29_3,UVLD_CODE_AC_CHROMA_31_29_4,UVLD_CODE_AC_CHROMA_31_29_5,UVLD_CODE_AC_CHROMA_31_29_6,UVLD_CODE_AC_CHROMA_31_29_7" hexmask.long.word 0x00 19.--28. 1. "UVLD_CODE_AC_CHROMA_28_19,Indicating start address of code table for UVLD AC Chroma" newline rbitfld.long 0x00 16.--18. "UVLD_CODE_AC_CHROMA_18_16,Indicating start address of code table for UVLD AC Chroma" "UVLD_CODE_AC_CHROMA_18_16_0,UVLD_CODE_AC_CHROMA_18_16_1,UVLD_CODE_AC_CHROMA_18_16_2,UVLD_CODE_AC_CHROMA_18_16_3,UVLD_CODE_AC_CHROMA_18_16_4,UVLD_CODE_AC_CHROMA_18_16_5,UVLD_CODE_AC_CHROMA_18_16_6,UVLD_CODE_AC_CHROMA_18_16_7" rbitfld.long 0x00 13.--15. "UVLD_CODE_AC_LUMA_15_13,Indicating start address of code table for UVLD AC-luma" "UVLD_CODE_AC_LUMA_15_13_0,UVLD_CODE_AC_LUMA_15_13_1,UVLD_CODE_AC_LUMA_15_13_2,UVLD_CODE_AC_LUMA_15_13_3,UVLD_CODE_AC_LUMA_15_13_4,UVLD_CODE_AC_LUMA_15_13_5,UVLD_CODE_AC_LUMA_15_13_6,UVLD_CODE_AC_LUMA_15_13_7" newline hexmask.long.word 0x00 3.--12. 1. "UVLD_CODE_AC_LUMA_12_3,Indicating start address of code table for UVLD AC-luma" rbitfld.long 0x00 0.--2. "UVLD_CODE_AC_LUMA_2_0,Indicating start address of code table for UVLD AC-luma" "UVLD_CODE_AC_LUMA_2_0_0,UVLD_CODE_AC_LUMA_2_0_1,UVLD_CODE_AC_LUMA_2_0_2,UVLD_CODE_AC_LUMA_2_0_3,UVLD_CODE_AC_LUMA_2_0_4,UVLD_CODE_AC_LUMA_2_0_5,UVLD_CODE_AC_LUMA_2_0_6,UVLD_CODE_AC_LUMA_2_0_7" line.long 0x04 "CDC_VP_A," hexmask.long.word 0x04 3.--15. 1. "FWDBITPTR_15_3,FWDBITPTR Interlace Field B picture" group.long 0xC8++0x03 line.long 0x00 "MP4_WORK7,MP4 WORK7 register" hexmask.long.word 0x00 16.--31. 1. "MVP31,MVP[3][1]: Motion Vector Predictors for B-VOP (field backward bottom motion vector predictor)" hexmask.long.word 0x00 0.--15. 1. "MVP30,MVP[3][0]: Motion Vector Predictors for B-VOP (field backward bottom motion vector predictor)" group.long 0xC8++0x07 line.long 0x00 "UVLD_TBL_TYPE,Setting for UVLD code table" bitfld.long 0x00 29. "UVLD_AC_CHROMA,Indicating type of UVLD code table for AC-chroma data" "UVLD_AC_CHROMA_0,UVLD_AC_CHROMA_1" bitfld.long 0x00 24.--28. "UVLD_AC_CHROMA_LEN_MAX,This data defines maximum code length of universal VLD code table for AC-chroma" "UVLD_AC_CHROMA_LEN_MAX_0,UVLD_AC_CHROMA_LEN_MAX_1,UVLD_AC_CHROMA_LEN_MAX_2,UVLD_AC_CHROMA_LEN_MAX_3,UVLD_AC_CHROMA_LEN_MAX_4,UVLD_AC_CHROMA_LEN_MAX_5,UVLD_AC_CHROMA_LEN_MAX_6,UVLD_AC_CHROMA_LEN_MAX_7,UVLD_AC_CHROMA_LEN_MAX_8,UVLD_AC_CHROMA_LEN_MAX_9,UVLD_AC_CHROMA_LEN_MAX_10,UVLD_AC_CHROMA_LEN_MAX_11,UVLD_AC_CHROMA_LEN_MAX_12,UVLD_AC_CHROMA_LEN_MAX_13,UVLD_AC_CHROMA_LEN_MAX_14,UVLD_AC_CHROMA_LEN_MAX_15,UVLD_AC_CHROMA_LEN_MAX_16,UVLD_AC_CHROMA_LEN_MAX_17,UVLD_AC_CHROMA_LEN_MAX_18,UVLD_AC_CHROMA_LEN_MAX_19,UVLD_AC_CHROMA_LEN_MAX_20,UVLD_AC_CHROMA_LEN_MAX_21,UVLD_AC_CHROMA_LEN_MAX_22,UVLD_AC_CHROMA_LEN_MAX_23,UVLD_AC_CHROMA_LEN_MAX_24,UVLD_AC_CHROMA_LEN_MAX_25,UVLD_AC_CHROMA_LEN_MAX_26,UVLD_AC_CHROMA_LEN_MAX_27,UVLD_AC_CHROMA_LEN_MAX_28,UVLD_AC_CHROMA_LEN_MAX_29,UVLD_AC_CHROMA_LEN_MAX_30,UVLD_AC_CHROMA_LEN_MAX_31" newline bitfld.long 0x00 21. "UVLD_AC_LUMA,Indicating type of UVLD code table for AC-luma data" "UVLD_AC_LUMA_0,UVLD_AC_LUMA_1" bitfld.long 0x00 16.--20. "UVLD_AC_LUMA_LEN_MAX,This data defines maximum code length of universal VLD code table for AC-luma" "UVLD_AC_LUMA_LEN_MAX_0,UVLD_AC_LUMA_LEN_MAX_1,UVLD_AC_LUMA_LEN_MAX_2,UVLD_AC_LUMA_LEN_MAX_3,UVLD_AC_LUMA_LEN_MAX_4,UVLD_AC_LUMA_LEN_MAX_5,UVLD_AC_LUMA_LEN_MAX_6,UVLD_AC_LUMA_LEN_MAX_7,UVLD_AC_LUMA_LEN_MAX_8,UVLD_AC_LUMA_LEN_MAX_9,UVLD_AC_LUMA_LEN_MAX_10,UVLD_AC_LUMA_LEN_MAX_11,UVLD_AC_LUMA_LEN_MAX_12,UVLD_AC_LUMA_LEN_MAX_13,UVLD_AC_LUMA_LEN_MAX_14,UVLD_AC_LUMA_LEN_MAX_15,UVLD_AC_LUMA_LEN_MAX_16,UVLD_AC_LUMA_LEN_MAX_17,UVLD_AC_LUMA_LEN_MAX_18,UVLD_AC_LUMA_LEN_MAX_19,UVLD_AC_LUMA_LEN_MAX_20,UVLD_AC_LUMA_LEN_MAX_21,UVLD_AC_LUMA_LEN_MAX_22,UVLD_AC_LUMA_LEN_MAX_23,UVLD_AC_LUMA_LEN_MAX_24,UVLD_AC_LUMA_LEN_MAX_25,UVLD_AC_LUMA_LEN_MAX_26,UVLD_AC_LUMA_LEN_MAX_27,UVLD_AC_LUMA_LEN_MAX_28,UVLD_AC_LUMA_LEN_MAX_29,UVLD_AC_LUMA_LEN_MAX_30,UVLD_AC_LUMA_LEN_MAX_31" newline bitfld.long 0x00 13. "UVLD_DC_CHROMA,Indicating type of UVLD code table for DC-chroma data" "UVLD_DC_CHROMA_0,UVLD_DC_CHROMA_1" bitfld.long 0x00 8.--12. "UVLD_DC_CHROMA_LEN_MAX,This data defines maximum code length of universal VLD code table for DC-chroma" "UVLD_DC_CHROMA_LEN_MAX_0,UVLD_DC_CHROMA_LEN_MAX_1,UVLD_DC_CHROMA_LEN_MAX_2,UVLD_DC_CHROMA_LEN_MAX_3,UVLD_DC_CHROMA_LEN_MAX_4,UVLD_DC_CHROMA_LEN_MAX_5,UVLD_DC_CHROMA_LEN_MAX_6,UVLD_DC_CHROMA_LEN_MAX_7,UVLD_DC_CHROMA_LEN_MAX_8,UVLD_DC_CHROMA_LEN_MAX_9,UVLD_DC_CHROMA_LEN_MAX_10,UVLD_DC_CHROMA_LEN_MAX_11,UVLD_DC_CHROMA_LEN_MAX_12,UVLD_DC_CHROMA_LEN_MAX_13,UVLD_DC_CHROMA_LEN_MAX_14,UVLD_DC_CHROMA_LEN_MAX_15,UVLD_DC_CHROMA_LEN_MAX_16,UVLD_DC_CHROMA_LEN_MAX_17,UVLD_DC_CHROMA_LEN_MAX_18,UVLD_DC_CHROMA_LEN_MAX_19,UVLD_DC_CHROMA_LEN_MAX_20,UVLD_DC_CHROMA_LEN_MAX_21,UVLD_DC_CHROMA_LEN_MAX_22,UVLD_DC_CHROMA_LEN_MAX_23,UVLD_DC_CHROMA_LEN_MAX_24,UVLD_DC_CHROMA_LEN_MAX_25,UVLD_DC_CHROMA_LEN_MAX_26,UVLD_DC_CHROMA_LEN_MAX_27,UVLD_DC_CHROMA_LEN_MAX_28,UVLD_DC_CHROMA_LEN_MAX_29,UVLD_DC_CHROMA_LEN_MAX_30,UVLD_DC_CHROMA_LEN_MAX_31" newline bitfld.long 0x00 5. "UVLD_DC_LUMA,Indicating type of UVLD code table for DC-luma data" "UVLD_DC_LUMA_0,UVLD_DC_LUMA_1" bitfld.long 0x00 0.--4. "UVLD_DC_LUMA_LEN_MAX,This data defines maximum code length of universal VLD code table for DC-luma" "UVLD_DC_LUMA_LEN_MAX_0,UVLD_DC_LUMA_LEN_MAX_1,UVLD_DC_LUMA_LEN_MAX_2,UVLD_DC_LUMA_LEN_MAX_3,UVLD_DC_LUMA_LEN_MAX_4,UVLD_DC_LUMA_LEN_MAX_5,UVLD_DC_LUMA_LEN_MAX_6,UVLD_DC_LUMA_LEN_MAX_7,UVLD_DC_LUMA_LEN_MAX_8,UVLD_DC_LUMA_LEN_MAX_9,UVLD_DC_LUMA_LEN_MAX_10,UVLD_DC_LUMA_LEN_MAX_11,UVLD_DC_LUMA_LEN_MAX_12,UVLD_DC_LUMA_LEN_MAX_13,UVLD_DC_LUMA_LEN_MAX_14,UVLD_DC_LUMA_LEN_MAX_15,UVLD_DC_LUMA_LEN_MAX_16,UVLD_DC_LUMA_LEN_MAX_17,UVLD_DC_LUMA_LEN_MAX_18,UVLD_DC_LUMA_LEN_MAX_19,UVLD_DC_LUMA_LEN_MAX_20,UVLD_DC_LUMA_LEN_MAX_21,UVLD_DC_LUMA_LEN_MAX_22,UVLD_DC_LUMA_LEN_MAX_23,UVLD_DC_LUMA_LEN_MAX_24,UVLD_DC_LUMA_LEN_MAX_25,UVLD_DC_LUMA_LEN_MAX_26,UVLD_DC_LUMA_LEN_MAX_27,UVLD_DC_LUMA_LEN_MAX_28,UVLD_DC_LUMA_LEN_MAX_29,UVLD_DC_LUMA_LEN_MAX_30,UVLD_DC_LUMA_LEN_MAX_31" line.long 0x04 "DC_PRED_CHROMA,JPEG DC PRED Chroma register - TI internal" hexmask.long.word 0x04 16.--31. 1. "DC_PRED_CB,Chrominance (Cb) DC prediction value is stored in register" hexmask.long.word 0x04 0.--15. 1. "DC_PRED_CR,Chrominance (Cr) DC prediction value is stored in register" repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 ) rgroup.long ($2+0xF0)++0x03 line.long 0x00 "CMDP_GPR$1,Command Processor General Purpose Register 0" repeat.end tree.end tree.end tree.open "IVA_Intra_Prediction_Estimation" tree "IPE3_BFSW_L3_MAINInterconnect" base ad:0x5A058A00 group.long 0x00++0x07 line.long 0x00 "IPE3_BFSW_VIEWMODE," bitfld.long 0x00 0. "VIEW_IPORGBUF,View mode selection for iporgbuf" "0,1" line.long 0x04 "IPE3_BFSW_MSTID,Master ID 1 register" bitfld.long 0x04 1. "MST_IPORGBUF_B,Master selection for iporgbuf B" "0,1" bitfld.long 0x04 0. "MST_IPORGBUF_A,Master selection for iporgbuf A" "0,1" tree.end tree "IPE3_IPGW_L3_MAINInterconnect" base ad:0x5A058C00 group.long 0x08++0x07 line.long 0x00 "IPE3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" line.long 0x04 "IPE3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "IPE3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Programmable raw status for event 0" "0,1" line.long 0x04 "IPE3_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Programmable raw status for event 0" "0,1" line.long 0x08 "IPE3_IRQSTATUS_RAW_2,Per-event raw interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Programmable raw status for event 0" "0,1" line.long 0x0C "IPE3_IRQSTATUS_RAW_3,Per-event raw interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Programmable raw status for event 0" "0,1" group.long 0x30++0x0F line.long 0x00 "IPE3_IRQSTATUS_0,Per-event enabled interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event 0" "EVENT0_0,EVENT0_1" line.long 0x04 "IPE3_IRQSTATUS_1,Per-event enabled interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for event 0" "EVENT0_0,EVENT0_1" line.long 0x08 "IPE3_IRQSTATUS_2,Per-event enabled interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for event 0" "EVENT0_0,EVENT0_1" line.long 0x0C "IPE3_IRQSTATUS_3,Per-event enabled interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for event 0" "EVENT0_0,EVENT0_1" group.long 0x50++0x07 line.long 0x00 "IPE3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" line.long 0x04 "IPE3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" group.long 0x68++0x07 line.long 0x00 "IPE3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" line.long 0x04 "IPE3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" group.long 0xC0++0x03 line.long 0x00 "IPE3_IRQSTATUS_ACLREN,Auto clear enable" bitfld.long 0x00 3. "ACLREN3,Auto clear enable for line 3" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,Auto clear enable for line 2" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,Auto clear enable for line 1" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,Auto clear enable for line 0" "ACLREN0_0,ACLREN0_1" repeat 2. (list 2. 3. )(list 0x00 0x04 ) group.long ($2+0x70)++0x03 line.long 0x00 "IPE3_IRQENABLE_CLR_$1,Per-event interrupt enable bit vector. line 2" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" repeat.end repeat 2. (list 0. 3. )(list 0x00 0x0C ) group.long ($2+0x4C)++0x03 line.long 0x00 "IPE3_IRQENABLE_SET_$1,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" repeat.end tree.end tree "IPE3_LSE_L3_MAINInterconnect" base ad:0x5A058B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "ERR,Error status bit [11]: DMA IP_CORE side [10]: DMA SL2 side [9]: CFG IP_CORE side" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals are initialized to recognize the prologue (first MB): -Token status signal -Token start/end signal -DMA pointer Writing 0 is ignored" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single-step mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW change" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command status bit" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task in bypass mode" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task in bypass mode" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task in bypass mode" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,Sync-Box bypass mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_ LD_BYPS,Bypass mode only" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ ST_BYPS,Bypass mode only" tree.end tree "IPE3_MMR_L3_MAINInterconnect" base ad:0x5A058800 rgroup.long 0x00++0x53 line.long 0x00 "IPE3_PID,Peripheral ID register" line.long 0x04 "IPE3_COUNT,IPE3 cycle counter register Determines the cycle number between start of IPE3 core and end (interrupt generation)" bitfld.long 0x04 31. "CNT_EN,Counter enable" "0,1" bitfld.long 0x04 30. "CNT_RST,Counter reset" "0,1" hexmask.long.word 0x04 0.--15. 1. "CNT_VALUE,Current value of the benchmark counter" line.long 0x08 "IPE3_CTRL,IPE3 control register" bitfld.long 0x08 18.--19. "IPE_ADDR,Address of parameter set" "0,1,2,3" bitfld.long 0x08 2. "IPE_SSM,Single-step mode" "0,1" bitfld.long 0x08 0. "IPE_EN,IPE3 start and status Setting this bit to 1 makes IPE3 start processing" "0,1" line.long 0x0C "IPE3_NS,Horizontal noise suppression register Do not write any value while IPE3 is running (while IPE3_EN is 1)" bitfld.long 0x0C 1. "NS1,Bottom block status for horizontal noise suppression" "0,1" bitfld.long 0x0C 0. "NS0,Top block status for horizontal noise suppression" "0,1" line.long 0x10 "IPE3_NA,nA mode register Do not write any value while IPE3 is running (while IPE3_EN is 1)" bitfld.long 0x10 28.--31. "PRED_NA7,Intraprediction mode of 4 x 4 block 15 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "PRED_NA6,Intraprediction mode of 4 x 4 block 13 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "PRED_NA5,Intraprediction mode of 4 x 4 block 7 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "PRED_NA4,Intraprediction mode of 4 x 4 block 5 of bottom MB in the previous MB pair" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 12.--15. "PRED_NA3,Intraprediction mode of 4 x 4 block 15 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "PRED_NA2,Intraprediction mode of 4 x 4 block 13 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 4.--7. "PRED_NA1,Intraprediction mode of 4 x 4 block 7 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "PRED_NA0,Intraprediction mode of 4 x 4 block 5 of left MB (or top MB in the previous MB pair in case of MBAFF)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "IPE3_L_LF_T0,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x14 24.--31. 1. "IPE_L_LF_TOP3,Luma left sample for top MB line 3" hexmask.long.byte 0x14 16.--23. 1. "IPE_L_LF_TOP2,Luma left sample for top MB line 2" hexmask.long.byte 0x14 8.--15. 1. "IPE_L_LF_TOP1,Luma left sample for top MB line 1" hexmask.long.byte 0x14 0.--7. 1. "IPE_L_LF_TOP0,Luma left sample for top MB line 0" line.long 0x18 "IPE3_L_LF_T1,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x18 24.--31. 1. "IPE_L_LF_TOP7,Luma left sample for top MB line 7" hexmask.long.byte 0x18 16.--23. 1. "IPE_L_LF_TOP6,Luma left sample for top MB line 6" hexmask.long.byte 0x18 8.--15. 1. "IPE_L_LF_TOP5,Luma left sample for top MB line 5" hexmask.long.byte 0x18 0.--7. 1. "IPE_L_LF_TOP4,Luma left sample for top MB line 4" line.long 0x1C "IPE3_L_LF_T2,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x1C 24.--31. 1. "IPE_L_LF_TOP11,Luma left sample for top MB line 11" hexmask.long.byte 0x1C 16.--23. 1. "IPE_L_LF_TOP10,Luma left sample for top MB line 10" hexmask.long.byte 0x1C 8.--15. 1. "IPE_L_LF_TOP9,Luma left sample for top MB line 9 The right-most luminance pixel of top MB line 9 in the left MB" hexmask.long.byte 0x1C 0.--7. 1. "IPE_L_LF_TOP8,Luma left sample for top MB line 8 The right-most luminance pixel of top MB line 8 in the left MB" line.long 0x20 "IPE3_L_LF_T3,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x20 24.--31. 1. "IPE_L_LF_TOP15,Luma left sample for top MB line 15" hexmask.long.byte 0x20 16.--23. 1. "IPE_L_LF_TOP14,Luma left sample for top MB line 14" hexmask.long.byte 0x20 8.--15. 1. "IPE_L_LF_TOP13,Luma left sample for top MB line 13" hexmask.long.byte 0x20 0.--7. 1. "IPE_L_LF_TOP12,Luma left sample for top MB line 12" line.long 0x24 "IPE3_L_LF_B0,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x24 24.--31. 1. "IPE_L_LF_BOT3,Luma left sample for bottom MB line 3" hexmask.long.byte 0x24 16.--23. 1. "IPE_L_LF_BOT2,Luma left sample for bottom MB line 2" hexmask.long.byte 0x24 8.--15. 1. "IPE_L_LF_BOT1,Luma left sample for bottom MB line 1" hexmask.long.byte 0x24 0.--7. 1. "IPE_L_LF_BOT0,Luma left sample for bottom MB line 0" line.long 0x28 "IPE3_L_LF_B1,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x28 24.--31. 1. "IPE_L_LF_BOT7,Luma left sample for bottom MB line 7" hexmask.long.byte 0x28 16.--23. 1. "IPE_L_LF_BOT6,Luma left sample for bottom MB line 6" hexmask.long.byte 0x28 8.--15. 1. "IPE_L_LF_BOT5,Luma left sample for bottom MB line 5" hexmask.long.byte 0x28 0.--7. 1. "IPE_L_LF_BOT4,Luma left sample for bottom MB line 4" line.long 0x2C "IPE3_L_LF_B2,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x2C 24.--31. 1. "IPE_L_LF_BOT11,Luma left sample for bottom MB line 11" hexmask.long.byte 0x2C 16.--23. 1. "IPE_L_LF_BOT10,Luma left sample for bottom MB line 10" hexmask.long.byte 0x2C 8.--15. 1. "IPE_L_LF_BOT9,Luma left sample for bottom MB line 9" hexmask.long.byte 0x2C 0.--7. 1. "IPE_L_LF_BOT8,Luma left sample for bottom MB line 8" line.long 0x30 "IPE3_L_LF_B3,Luma left neighboring data IPE3 reads this register value as Luma left samples at the beginning of estimation" hexmask.long.byte 0x30 24.--31. 1. "IPE_L_LF_BOT15,Luma left sample for bottom MB line 15" hexmask.long.byte 0x30 16.--23. 1. "IPE_L_LF_BOT14,Luma left sample for bottom MB line 14" hexmask.long.byte 0x30 8.--15. 1. "IPE_L_LF_BOT13,Luma left sample for bottom MB line 13" hexmask.long.byte 0x30 0.--7. 1. "IPE_L_LF_BOT12,Luma left sample for bottom MB line 12" line.long 0x34 "IPE3_C_LF_T0,Chroma left neighboring data IPE3 reads this register value as Chroma left samples at the beginning of estimation" hexmask.long.byte 0x34 24.--31. 1. "IPE_CR_LF_TOP1,Left Cr sample of top MB line .1 The right-most Cr pixel of top MB line 1 in the left MB" hexmask.long.byte 0x34 16.--23. 1. "IPE_CB_LF_TOP1,Left Cb sample of top MB line 1" hexmask.long.byte 0x34 8.--15. 1. "IPE_CR_LF_TOP0,Left Cr sample of top MB line 0" hexmask.long.byte 0x34 0.--7. 1. "IPE_CB_LF_TOP0,Left Cb sample of top MB line 0" line.long 0x38 "IPE3_C_LF_T1,Chroma left neighboring data IPE3 reads this register value as Chroma left samples at the beginning of estimation" hexmask.long.byte 0x38 24.--31. 1. "IPE_CR_LF_TOP3,Left Cr sample of top MB line 3" hexmask.long.byte 0x38 16.--23. 1. "IPE_CB_LF_TOP3,Left Cb sample of top MB line 3" hexmask.long.byte 0x38 8.--15. 1. "IPE_CR_LF_TOP2,Left Cr sample of top MB line 2" hexmask.long.byte 0x38 0.--7. 1. "IPE_CB_LF_TOP2,Left Cb sample of top MB line 2" line.long 0x3C "IPE3_C_LF_T2,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x3C 24.--31. 1. "IPE_CR_LF_TOP5,Left Cr sample of top MB line 5" hexmask.long.byte 0x3C 16.--23. 1. "IPE_CB_LF_TOP5,Left Cb sample of top MB line 5" hexmask.long.byte 0x3C 8.--15. 1. "IPE_CR_LF_TOP4,Left Cr sample of top MB line 4" hexmask.long.byte 0x3C 0.--7. 1. "IPE_CB_LF_TOP4,Left Cb sample of top MB line 4" line.long 0x40 "IPE3_C_LF_T3,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x40 24.--31. 1. "IPE_CR_LF_TOP7,Left Cr sample of top MB line 7" hexmask.long.byte 0x40 16.--23. 1. "IPE_CB_LF_TOP7,Left Cb sample of top MB line 7" hexmask.long.byte 0x40 8.--15. 1. "IPE_CR_LF_TOP6,Left Cr sample of top MB line 6" hexmask.long.byte 0x40 0.--7. 1. "IPE_CB_LF_TOP6,Left Cb sample of top MB line 6" line.long 0x44 "IPE3_C_LF_B0,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x44 24.--31. 1. "IPE_CR_LF_BOT1,Left Cr sample of bottom MB line 1" hexmask.long.byte 0x44 16.--23. 1. "IPE_CB_LF_BOT1,Left Cb sample of bottom MB line 1" hexmask.long.byte 0x44 8.--15. 1. "IPE_CR_LF_BOT0,Left Cr sample of bottom MB line 0" hexmask.long.byte 0x44 0.--7. 1. "IPE_CB_LF_BOT0,Left Cb sample of bottom MB line 0" line.long 0x48 "IPE3_C_LF_B1,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x48 24.--31. 1. "IPE_CR_LF_BOT3,Left Cr sample of bottom MB line 3" hexmask.long.byte 0x48 16.--23. 1. "IPE_CB_LF_BOT3,Left Cb sample of bottom MB line 3" hexmask.long.byte 0x48 8.--15. 1. "IPE_CR_LF_BOT2,Left Cr sample of bottom MB line 2" hexmask.long.byte 0x48 0.--7. 1. "IPE_CB_LF_BOT2,Left Cb sample of bottom MB line 2" line.long 0x4C "IPE3_C_LF_B2,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x4C 24.--31. 1. "IPE_CR_LF_BOT5,Left Cr sample of bottom MB line 5" hexmask.long.byte 0x4C 16.--23. 1. "IPE_CB_LF_BOT5,Left Cb sample of bottom MB line 5" hexmask.long.byte 0x4C 8.--15. 1. "IPE_CR_LF_BOT4,Left Cr sample of bottom MB line 4" hexmask.long.byte 0x4C 0.--7. 1. "IPE_CB_LF_BOT4,Left Cb sample of bottom MB line 4" line.long 0x50 "IPE3_C_LF_B3,Chroma left neighboring data IPE3 reads this register value as chroma left samples at the beginning of estimation" hexmask.long.byte 0x50 24.--31. 1. "IPE_CR_LF_BOT7,Left Cr sample of bottom MB line 7" hexmask.long.byte 0x50 16.--23. 1. "IPE_CB_LF_BOT7,Left Cb sample of bottom MB line 7" hexmask.long.byte 0x50 8.--15. 1. "IPE_CR_LF_BOT6,Left Cr sample of bottom MB line 6" hexmask.long.byte 0x50 0.--7. 1. "IPE_CB_LF_BOT6,Left Cb sample of bottom MB line 6" tree.end tree.end tree.open "IVA_Load_and_Store_Engine" tree "CALC3_LSE_L3_MAINInterconnect" base ad:0x5A058300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" tree.end tree "ECD3_LSE_L3_MAINInterconnect" base ad:0x5A059B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" tree.end tree "IPE3_LSE_L3_MAINInterconnect" base ad:0x5A058B00 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" tree.end tree "MC3_LSE_L3_MAINInterconnect" base ad:0x5A059300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through bit" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr=1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals will be initialized to understand prologue(1st MB) as below" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single Step Mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command Status Bit - These bits remain 1 until RESET or Token_clr or until the host sets to 1" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on Byps mode Target ParamAddr_ld_byps must be set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on Byps mode - In the single step mode LSE access to ParamAddr_ld_byps and execute the command for Comp task" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on Byps mode Target ParamAddr_st_byps must be set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SyncBox Byps mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in the bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in the bypass mode" tree.end tree.end tree.open "IVA_Loop_Filter" tree "ILF3_L3_MAINInterconnect" base ad:0x5A052000 repeat 12. (list 136. 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147. ) tree "Channel_$1" group.long 0x3E8++0x03 line.long 0x00 "ILF3_BS_l_136,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x63C++0x03 line.long 0x00 "ILF3_IPB_n_136,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end repeat.end repeat 16. (list 120. 121. 122. 123. 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. ) tree "Channel_$1" group.long 0x3A8++0x03 line.long 0x00 "ILF3_BS_l_120,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5FC++0x03 line.long 0x00 "ILF3_IPB_n_120,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end repeat.end repeat 16. (list 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. ) tree "Channel_$1" group.long 0x368++0x03 line.long 0x00 "ILF3_BS_l_104,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5BC++0x03 line.long 0x00 "ILF3_IPB_n_104,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end repeat.end repeat 16. (list 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. ) tree "Channel_$1" group.long 0x358++0x03 line.long 0x00 "ILF3_BS_l_100,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5AC++0x03 line.long 0x00 "ILF3_IPB_n_100,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end repeat.end repeat 16. (list 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. ) tree "Channel_$1" group.long 0x2E8++0x03 line.long 0x00 "ILF3_BS_l_72,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x53C++0x03 line.long 0x00 "ILF3_IPB_n_72,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end repeat.end repeat 16. (list 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. ) tree "Channel_$1" group.long 0x2A8++0x03 line.long 0x00 "ILF3_BS_l_56,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4FC++0x03 line.long 0x00 "ILF3_IPB_n_56,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end repeat.end repeat 16. (list 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. ) tree "Channel_$1" group.long 0x268++0x03 line.long 0x00 "ILF3_BS_l_40,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4BC++0x03 line.long 0x00 "ILF3_IPB_n_40,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" tree.end repeat.end repeat 6. (list 34. 35. 36. 37. 38. 39. ) tree "Channel_$1" group.long 0x250++0x03 line.long 0x00 "ILF3_BS_l_34,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A4++0x03 line.long 0x00 "ILF3_IPB_n_34,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x1B0++0x03 line.long 0x00 "ILF3_QP_IDX_j_34,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end repeat.end repeat 16. (list 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. ) tree "Channel_$1" group.long 0x210++0x03 line.long 0x00 "ILF3_BS_l_18,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x464++0x03 line.long 0x00 "ILF3_IPB_n_18,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x170++0x03 line.long 0x00 "ILF3_QP_IDX_j_18,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" tree.end repeat.end repeat 2. (list 16. 17. ) tree "Channel_$1" group.long 0x208++0x03 line.long 0x00 "ILF3_BS_l_16,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x45C++0x03 line.long 0x00 "ILF3_IPB_n_16,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x168++0x03 line.long 0x00 "ILF3_QP_IDX_j_16,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x120++0x03 line.long 0x00 "ILF3_QP_m_16,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end repeat.end repeat 12. (list 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. ) tree "Channel_$1" group.long 0x1F0++0x03 line.long 0x00 "ILF3_BS_l_10,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x444++0x03 line.long 0x00 "ILF3_IPB_n_10,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x74++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_10,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x150++0x03 line.long 0x00 "ILF3_QP_IDX_j_10,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0x108++0x03 line.long 0x00 "ILF3_QP_m_10,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end repeat.end repeat 3. (list 0. 1. 2. ) tree "Channel_$1" group.long 0x1C8++0x03 line.long 0x00 "ILF3_BS_l_0,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41C++0x03 line.long 0x00 "ILF3_IPB_n_0,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0x94++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_0,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x40++0x03 line.long 0x00 "ILF3_MBCONFIG_MBINFO_k_0,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "MBCONFIG_ADDRESS_HIGH,Parameter" hexmask.long.word 0x00 0.--15. 1. "MBCONFIG_ADDRESS_LOW,Parameter" group.long 0x4C++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_0,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x128++0x03 line.long 0x00 "ILF3_QP_IDX_j_0,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xE0++0x03 line.long 0x00 "ILF3_QP_m_0,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xBC++0x03 line.long 0x00 "ILF3_SLICESTATUS_k_0,MBConfig table contains pointers used by program to control the ILF3 units" tree.end repeat.end tree "Channel_148" group.long 0x418++0x03 line.long 0x00 "ILF3_BS_l_148,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 12. (list 692. 693. 694. 695. 696. 697. 698. 699. 700. 701. 702. 703. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C ) group.long ($2+0xEEC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 676. 677. 678. 679. 680. 681. 682. 683. 684. 685. 686. 687. 688. 689. 690. 691. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xEAC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 660. 661. 662. 663. 664. 665. 666. 667. 668. 669. 670. 671. 672. 673. 674. 675. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xE6C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 644. 645. 646. 647. 648. 649. 650. 651. 652. 653. 654. 655. 656. 657. 658. 659. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xE2C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 628. 629. 630. 631. 632. 633. 634. 635. 636. 637. 638. 639. 640. 641. 642. 643. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xDEC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 612. 613. 614. 615. 616. 617. 618. 619. 620. 621. 622. 623. 624. 625. 626. 627. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xDAC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 596. 597. 598. 599. 600. 601. 602. 603. 604. 605. 606. 607. 608. 609. 610. 611. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xD6C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 580. 581. 582. 583. 584. 585. 586. 587. 588. 589. 590. 591. 592. 593. 594. 595. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xD2C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 564. 565. 566. 567. 568. 569. 570. 571. 572. 573. 574. 575. 576. 577. 578. 579. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xCEC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 548. 549. 550. 551. 552. 553. 554. 555. 556. 557. 558. 559. 560. 561. 562. 563. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xCAC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 532. 533. 534. 535. 536. 537. 538. 539. 540. 541. 542. 543. 544. 545. 546. 547. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC6C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 516. 517. 518. 519. 520. 521. 522. 523. 524. 525. 526. 527. 528. 529. 530. 531. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC2C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 500. 501. 502. 503. 504. 505. 506. 507. 508. 509. 510. 511. 512. 513. 514. 515. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xBEC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 484. 485. 486. 487. 488. 489. 490. 491. 492. 493. 494. 495. 496. 497. 498. 499. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xBAC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 468. 469. 470. 471. 472. 473. 474. 475. 476. 477. 478. 479. 480. 481. 482. 483. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xB6C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 452. 453. 454. 455. 456. 457. 458. 459. 460. 461. 462. 463. 464. 465. 466. 467. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xB2C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 436. 437. 438. 439. 440. 441. 442. 443. 444. 445. 446. 447. 448. 449. 450. 451. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xAEC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 420. 421. 422. 423. 424. 425. 426. 427. 428. 429. 430. 431. 432. 433. 434. 435. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xAAC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 404. 405. 406. 407. 408. 409. 410. 411. 412. 413. 414. 415. 416. 417. 418. 419. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA6C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 388. 389. 390. 391. 392. 393. 394. 395. 396. 397. 398. 399. 400. 401. 402. 403. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA2C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 372. 373. 374. 375. 376. 377. 378. 379. 380. 381. 382. 383. 384. 385. 386. 387. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x9EC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 356. 357. 358. 359. 360. 361. 362. 363. 364. 365. 366. 367. 368. 369. 370. 371. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x9AC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 340. 341. 342. 343. 344. 345. 346. 347. 348. 349. 350. 351. 352. 353. 354. 355. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x96C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 324. 325. 326. 327. 328. 329. 330. 331. 332. 333. 334. 335. 336. 337. 338. 339. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x92C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 308. 309. 310. 311. 312. 313. 314. 315. 316. 317. 318. 319. 320. 321. 322. 323. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x8EC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 292. 293. 294. 295. 296. 297. 298. 299. 300. 301. 302. 303. 304. 305. 306. 307. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x8AC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 276. 277. 278. 279. 280. 281. 282. 283. 284. 285. 286. 287. 288. 289. 290. 291. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x86C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 260. 261. 262. 263. 264. 265. 266. 267. 268. 269. 270. 271. 272. 273. 274. 275. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x82C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 244. 245. 246. 247. 248. 249. 250. 251. 252. 253. 254. 255. 256. 257. 258. 259. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x7EC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 228. 229. 230. 231. 232. 233. 234. 235. 236. 237. 238. 239. 240. 241. 242. 243. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x7AC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 212. 213. 214. 215. 216. 217. 218. 219. 220. 221. 222. 223. 224. 225. 226. 227. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x76C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. 207. 208. 209. 210. 211. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x72C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 180. 181. 182. 183. 184. 185. 186. 187. 188. 189. 190. 191. 192. 193. 194. 195. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x6EC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. 176. 177. 178. 179. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x6AC)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end repeat 16. (list 148. 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x66C)++0x03 line.long 0x00 "ILF3_IPB_n_$1,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" repeat.end tree.end tree "Channel_3" group.long 0x1D4++0x03 line.long 0x00 "ILF3_BS_l_3,Boundary strength" bitfld.long 0x00 0.--3. "BS,Boundary strength for H.264 but those fields are also used for filter flag for other codecs such as V1 and OVT Luma and Chroma when they are different" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x428++0x03 line.long 0x00 "ILF3_IPB_n_3,Input buffer bank" bitfld.long 0x00 8.--10. "IPB_BYTE_EXT,3-bit extension used in V1 OVT process" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. "IPB_BYTE,Byte element of IPB" group.long 0xA0++0x03 line.long 0x00 "ILF3_MBCONFIG_GDPCONFIG_i_3,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 27.--30. "RND,Rounding selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--26. "RIGHT_SHIFT,Shift right value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. "SELC7,Coefficient selection for GDP P7 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "SELC6,Coefficient selection for GDP P6 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. "SELC5,Coefficient selection for GDP P5 multiplication" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "SELC4,Coefficient selection for GDP P4 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. "SELC3,Coefficient selection for GDP P3 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. "SELC2,Coefficient selection for GDP P2 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. "SELC1,Coefficient selection for GDP P1 multiplication" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SELC0,Coefficient selection for GDP P0 multiplication" "0,1,2,3,4,5,6,7" group.long 0x58++0x03 line.long 0x00 "ILF3_MBCONFIG_MB_o_3,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 23.--26. "SHIFT_OR_WE,Parameter see and" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--22. 1. "STRIDE,This field allows to increment the base address with the stride value at each iteration" hexmask.long.word 0x00 0.--15. 1. "LUMA_CHROMA_ADDRESS,SL2 address pointer" group.long 0x134++0x03 line.long 0x00 "ILF3_QP_IDX_j_3,Quantization parameter index" bitfld.long 0x00 0.--2. "QP_IDX,QP index" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "ILF3_QP_m_3,Quantization parameter" bitfld.long 0x00 0.--5. "QP,Quantization parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end group.long 0xFFC++0x03 line.long 0x00 "ILF3_COMMAND,ILF3 command register: A write to this register decodes a command" bitfld.long 0x00 0.--2. "CMD,DATA/COMMAND 0x1 -> Start() 0x2 -> Stop() 0x3 -> DbgEn() 0x4 -> DbgDis() 0x5 -> DbgStep()" "0,1,2,3,4,5,6,7" group.long 0x30++0x03 line.long 0x00 "ILF3_CONFIG,Configuration register" hexmask.long.byte 0x00 24.--31. 1. "AUTOINCCOUNTER,This field indicates the current increment in MB for the auto-increment mechanism" bitfld.long 0x00 17.--18. "MBINFO_SIZE,Selects one of the three different MBinfo sizes to be loaded" "MBINFO_SIZE_0,MBINFO_SIZE_1,MBINFO_SIZE_2,MBINFO_SIZE_3" newline bitfld.long 0x00 16. "IRQAUTOCLEAR_EN," "0,1" hexmask.long.byte 0x00 8.--15. 1. "CODEC,Indicates the codec to be used" newline bitfld.long 0x00 0.--4. "PPA_TASK,Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x18++0x03 line.long 0x00 "ILF3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" group.long 0x28++0x03 line.long 0x00 "ILF3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x24++0x03 line.long 0x00 "ILF3_IRQENABLE_SET_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x20++0x03 line.long 0x00 "ILF3_IRQSTATUS_0,Per-event 'enabled' interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event" "EVENT0_0_r,EVENT0_1_w" group.long 0x1C++0x03 line.long 0x00 "ILF3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Settable raw status for event" "EVENT0_0_r,EVENT0_1_w" group.long 0xB0++0x03 line.long 0x00 "ILF3_MBCONFIG_AUTOINC,MBConfig table contains pointers used by program to control the ILF3 units" bitfld.long 0x00 11. "AUTOINC,This bit must set to 1 to activate the auto-increment scheme" "0,1" bitfld.long 0x00 8.--10. "PIXEL_FORMAT,This field indicates the number of pixel rows in the top-row buffer and also the number of rows of 8-bit pixels and 16-bit pixels (VC-1 case with OVT activated)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. "MAX_COUNT,Maximum value of Counter for auto-increment" repeat 2. (list 0123. 4567. )(list 0x00 0x04 ) group.long ($2+0x8C)++0x03 line.long 0x00 "ILF3_MBCONFIG_COEFFICIENTS$1,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.byte 0x00 24.--31. 1. "COEFF3,GDP coefficient 3" hexmask.long.byte 0x00 16.--23. 1. "COEFF2,GDP coefficient 2" newline hexmask.long.byte 0x00 8.--15. 1. "COEFF1,GDP coefficient 1" hexmask.long.byte 0x00 0.--7. 1. "COEFF0,GDP coefficient 0" repeat.end group.long 0xB4++0x03 line.long 0x00 "ILF3_MBCONFIG_NEXTMBCONFIG,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 0.--15. 1. "NEXTMBCONFIGADDRESS,Contains the next MB address" group.long 0x38++0x07 line.long 0x00 "ILF3_MBCONFIG_SLICEINFO01,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x00 16.--31. 1. "SLICEINFO1,Parameter" hexmask.long.word 0x00 0.--15. 1. "SLICEINFO0,Parameter" line.long 0x04 "ILF3_MBCONFIG_SLICEINFO2,MBConfig table contains pointers used by program to control the ILF3 units" hexmask.long.word 0x04 0.--15. 1. "MBCONFIG_ADDRESS_SLICEINFO2,Parameter" group.long 0xB8++0x03 line.long 0x00 "ILF3_MBSTATUS,Provides MB properties" bitfld.long 0x00 25. "ISFIRSTMB,Indicates which MB of the MB pair is being processed" "ISFIRSTMB_0,ISFIRSTMB_1" bitfld.long 0x00 23.--24. "COMPONENT,Indicates if IPB contains Luma or Chroma pixels" "0,1,2,3" newline bitfld.long 0x00 22. "TOP_LEFT_FIELD,Indicates the type of the top-left MB pair" "TOP_LEFT_FIELD_0_r,TOP_LEFT_FIELD_1_r" bitfld.long 0x00 21. "TOP_FIELD,Indicates the type of the top MB pair" "TOP_FIELD_0_r,TOP_FIELD_1_r" newline bitfld.long 0x00 20. "LEFT_FIELD,Indicates the type of the left MB pair" "LEFT_FIELD_0_r,LEFT_FIELD_1_r" bitfld.long 0x00 19. "CUR_FIELD,Indicates the type of the current MB" "CUR_FIELD_0_r,CUR_FIELD_1_r" newline bitfld.long 0x00 17.--18. "ALT_V,Indicates the type of left edge" "ALT_V_0_r,ALT_V_1_r,ALT_V_2_r,ALT_V_3_r" bitfld.long 0x00 16. "ALT_H,Indicates the type of the top horizontal edge" "ALT_H_0_r,ALT_H_1_r" newline bitfld.long 0x00 8. "LOAD_SLICEINFO,This flag indicates if the slice information must be updated or not" "LOAD_SLICEINFO_0_r,LOAD_SLICEINFO_1_r" rbitfld.long 0x00 0.--4. "PPA_TASK_STATUS,1 means which elementary task has been executed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x00++0x03 line.long 0x00 "ILF3_REVISION,IP revision identifier (X.Y.R) Used by software to track features. bugs. and compatibility" rgroup.long 0x34++0x03 line.long 0x00 "ILF3_STATUS,Provides information on the progress of the ILF3 execution" bitfld.long 0x00 27. "WRITEREGERROR,This bit is cleared by a Start() command when in INITIALIZED or COMPLETED state" "WRITEREGERROR_0_r,WRITEREGERROR_1_r" bitfld.long 0x00 24.--25. "EXECSTATE,Execution states" "EXECSTATE_0_r,EXECSTATE_1_r,EXECSTATE_2_r,EXECSTATE_3_r" newline hexmask.long.word 0x00 0.--15. 1. "CYCLECOUNT,Total number of cycles executed" group.long 0x10++0x03 line.long 0x00 "ILF3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0. "SOFTRESET,Software reset (optional)" "SOFTRESET_0_w,SOFTRESET_1_r" tree.end tree.end tree.open "IVA_Motion_Compensation" tree "MC3_BFSW_L3_MAINInterconnect" base ad:0x5A059200 group.long 0x00++0x0B line.long 0x00 "VIEWMODE,View mode register" hexmask.long 0x00 2.--31. 1. "RSRV,Reserved" bitfld.long 0x00 1. "VIEW_YBUF,View mode selection for Y buffer" "VIEW_YBUF_0,VIEW_YBUF_1" bitfld.long 0x00 0. "VIEW_XBUF,View mode selection for X buffer" "VIEW_XBUF_0,VIEW_XBUF_1" line.long 0x04 "MSTID1,Master ID 1 register Select master between HWA and DMA bus" hexmask.long 0x04 4.--31. 1. "RSRV,Reserved" bitfld.long 0x04 3. "MST_YBUF_B,Master selection for Y buffer B" "MST_YBUF_B_0,MST_YBUF_B_1" bitfld.long 0x04 2. "MST_YBUF_A,Master selection for Y buffer A" "MST_YBUF_A_0,MST_YBUF_A_1" bitfld.long 0x04 1. "MST_XBUF_B,Master selection for X buffer B" "MST_XBUF_B_0,MST_XBUF_B_1" bitfld.long 0x04 0. "MST_XBUF_A,Master selection for X buffer A" "MST_XBUF_A_0,MST_XBUF_A_1" line.long 0x08 "MSTID2,Master ID 1 register Select master between HWA and DMA bus" hexmask.long 0x08 2.--31. 1. "RSRV,Reserved" bitfld.long 0x08 1. "MST_JBUF,Master selection for J buffer" "MST_JBUF_0,MST_JBUF_1" bitfld.long 0x08 0. "MST_IBUF,Master selection for I buffer" "MST_IBUF_0,MST_IBUF_1" tree.end tree "MC3_IPGW_L3_MAINInterconnect" base ad:0x5A059400 group.long 0x08++0x07 line.long 0x00 "MC3_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" line.long 0x04 "MC3_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x04 0.--1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w,LINE_NUMBER_2_w,LINE_NUMBER_3_w" group.long 0x14++0x0F line.long 0x00 "MC3_IRQSTATUS_RAW_0,Per-event raw interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Settable raw status for event 0" "0,1" line.long 0x04 "MC3_IRQSTATUS_RAW_1,Per-event raw interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Settable raw status for event 0" "0,1" line.long 0x08 "MC3_IRQSTATUS_RAW_2,Per-event raw interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Settable raw status for event 0" "0,1" line.long 0x0C "MC3_IRQSTATUS_RAW_3,Per-event raw interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Settable raw status for event 0" "0,1" group.long 0x30++0x0F line.long 0x00 "MC3_IRQSTATUS_0,Per-event enabled interrupt status vector. line 0" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event 0" "EVENT0_0,EVENT0_1" line.long 0x04 "MC3_IRQSTATUS_1,Per-event enabled interrupt status vector. line 1" bitfld.long 0x04 0. "EVENT0,Clearable enabled status for event 0" "EVENT0_0,EVENT0_1" line.long 0x08 "MC3_IRQSTATUS_2,Per-event enabled interrupt status vector. line 2" bitfld.long 0x08 0. "EVENT0,Clearable enabled status for event 0" "EVENT0_0,EVENT0_1" line.long 0x0C "MC3_IRQSTATUS_3,Per-event enabled interrupt status vector. line 3" bitfld.long 0x0C 0. "EVENT0,Clearable enabled status for event 0" "EVENT0_0,EVENT0_1" group.long 0x50++0x07 line.long 0x00 "MC3_IRQENABLE_SET_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" line.long 0x04 "MC3_IRQENABLE_SET_2,Per-event interrupt enable bit vector. line 2" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" group.long 0x68++0x07 line.long 0x00 "MC3_IRQENABLE_CLR_0,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" line.long 0x04 "MC3_IRQENABLE_CLR_1,Per-event interrupt enable bit vector. line 1" bitfld.long 0x04 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" group.long 0xC0++0x03 line.long 0x00 "MC3_IRQSTATUS_ACLREN,Auto clear enable" bitfld.long 0x00 3. "ACLREN3,For line 3" "ACLREN3_0,ACLREN3_1" bitfld.long 0x00 2. "ACLREN2,For line 2" "ACLREN2_0,ACLREN2_1" bitfld.long 0x00 1. "ACLREN1,For line 1" "ACLREN1_0,ACLREN1_1" bitfld.long 0x00 0. "ACLREN0,For line 0" "ACLREN0_0,ACLREN0_1" repeat 2. (list 2. 3. )(list 0x00 0x04 ) group.long ($2+0x70)++0x03 line.long 0x00 "MC3_IRQENABLE_CLR_$1,Per-event interrupt enable bit vector. line 2" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" repeat.end repeat 2. (list 0. 3. )(list 0x00 0x0C ) group.long ($2+0x4C)++0x03 line.long 0x00 "MC3_IRQENABLE_SET_$1,Per-event interrupt enable bit vector. line 0" bitfld.long 0x00 0. "ENABLE0,Enable for event 0" "ENABLE0_0,ENABLE0_1" repeat.end tree.end tree "MC3_LSE_L3_MAINInterconnect" base ad:0x5A059300 group.long 0x00++0x07 line.long 0x00 "LSE_CTRL,Controller" bitfld.long 0x00 12. "INT_EOS_THRU,int_eos through" "INT_EOS_THRU_0,INT_EOS_THRU_1" bitfld.long 0x00 9.--11. "OCP_ERR,OCP error status bit [11]: OCP DMA IP_CORE side [10]: OCP DMA SL2 side [9]: OCP CFG IP_CORE side" "OCP_ERR_0,OCP_ERR_1,?,?,?,?,?,?" rbitfld.long 0x00 8. "ADPTV_VALUE,Status Adaptv_add() value This signal is cleared if Token_clr = 1" "ADPTV_VALUE_0,ADPTV_VALUE_1" bitfld.long 0x00 7. "TOKEN_CLR,LSE internal signals are initialized to understand prologue(first MB) as below: -token status signal -token start/end signal -DMA pointer" "TOKEN_CLR_0,TOKEN_CLR_1" newline bitfld.long 0x00 6. "SSM,Single step mode" "SSM_0,SSM_1" bitfld.long 0x00 5. "BFSW_CHG_DIS,Disabled internal BFSW" "BFSW_CHG_DIS_0,BFSW_CHG_DIS_1" bitfld.long 0x00 4. "CSB,Command status" "CSB_0,CSB_1" bitfld.long 0x00 3. "LD_GO,Execute LOAD task on bypass mode Target ParamAddr_ld_byps need to set before this bit is set" "LD_GO_0,LD_GO_1" newline bitfld.long 0x00 2. "COMP_GO,Execute Comp task on bypass mode" "COMP_GO_0,COMP_GO_1" bitfld.long 0x00 1. "ST_GO,Execute Store task on bypass mode Target ParamAddr_st_byps needs to set before this bit is set" "ST_GO_0,ST_GO_1" bitfld.long 0x00 0. "SB_BYPS,SYNCBOX_MC3 bypass mode" "SB_BYPS_0,SB_BYPS_1" line.long 0x04 "LSE_PARAM,Parameter address for SB Bypass mode" hexmask.long.word 0x04 16.--31. 1. "PARAMADDR_LD_BYPS,Only used in bypass mode" hexmask.long.word 0x04 0.--15. 1. "PARAMADDR_ST_BYPS,Only used in bypass mode" tree.end tree "MC3_MMR_L3_MAINInterconnect" base ad:0x5A059000 rgroup.long 0x00++0x0F line.long 0x00 "MC_PID,PID register" line.long 0x04 "MC_CNT,Benchmark counter register" bitfld.long 0x04 31. "MC_CNT_EN,Counter enable (MC_CNT_EN)" "MC_CNT_EN_0,MC_CNT_EN_1" bitfld.long 0x04 30. "MC_CNT_RST,Counter reset (MC_CNT_RST) Writing 0 results in no effect" "MC_CNT_RST_0,MC_CNT_RST_1" hexmask.long.word 0x04 0.--15. 1. "MC_COUNT,Counter value (MC_COUNT)" line.long 0x08 "MC_CTRL,Control register" bitfld.long 0x08 2. "MC_DBG,H.264 MBAFF debug mode bit (MC_DBG)" "MC_DBG_0,MC_DBG_1" bitfld.long 0x08 0. "MC_EN,Module start and status (MC_EN)" "MC_EN_0,MC_EN_1" line.long 0x0C "MC_PARAM0,Motion compression parameter register" bitfld.long 0x0C 29. "VC1_SMP_MOD,VC-1 sample mode" "VC1_SMP_MOD_0,VC1_SMP_MOD_1" bitfld.long 0x0C 28. "VC1_RND_CTRL,VC-1 round control bit" "VC1_RND_CTRL_0,VC1_RND_CTRL_1" bitfld.long 0x0C 10.--11. "H264_WGT_BIPRD_IDC,H.264 weighted_bipred_idc" "H264_WGT_BIPRD_IDC_0,H264_WGT_BIPRD_IDC_1,H264_WGT_BIPRD_IDC_2,H264_WGT_BIPRD_IDC_3" newline bitfld.long 0x0C 9. "H264_WGT_PRD,H.264 weighted_pred_flag" "H264_WGT_PRD_0,H264_WGT_PRD_1" bitfld.long 0x0C 0.--3. "CODEC_TYPE,Codec_type select" "CODEC_TYPE_0,CODEC_TYPE_1,CODEC_TYPE_2,CODEC_TYPE_3,CODEC_TYPE_4,CODEC_TYPE_5,CODEC_TYPE_6,CODEC_TYPE_7,CODEC_TYPE_8,CODEC_TYPE_9,CODEC_TYPE_10,CODEC_TYPE_11,CODEC_TYPE_12,CODEC_TYPE_13,CODEC_TYPE_14,CODEC_TYPE_15" hgroup.long 0x10++0x03 hide.long 0x00 "MC_PARAM1,Motion compression parameter register" group.long 0x18++0x0F line.long 0x00 "MC_ADDR_0,Base address of reference data Luma L0" hexmask.long.word 0x00 16.--31. 1. "BASE_YREF_BOT_L0_ADD,Base address of reference data Y L0 bottom (BASE_YREF_BOT_L0_ADD) (Reference for bottom field)" hexmask.long.word 0x00 0.--15. 1. "BASE_YREF_TOP_L0_ADD,Base address of reference data Y L0 top (BASE_YREF_TOP_L0_ADD) (Reference for progressive/top field)" line.long 0x04 "MC_ADDR_1,Base address of reference data Luma L1" hexmask.long.word 0x04 16.--31. 1. "BASE_YREF_BOT_L1_ADD,Base address of reference data Y L1 bottom (BASE_YREF_BOT_L1_ADD) (Reference for bottom field)" hexmask.long.word 0x04 0.--15. 1. "BASE_YREF_TOP_L1_ADD,Base address of reference data Y L1 top (BASE_YREF_TOP_L1_ADD) (Reference for progressive/top field)" line.long 0x08 "MC_ADDR_2,Base address of reference data chroma L0" hexmask.long.word 0x08 16.--31. 1. "BASE_CREF_BOT_L0_ADD,Base address of reference data C L0 bottom (BASE_CREF_BOT_L0_ADD) (Reference for bottom field)" hexmask.long.word 0x08 0.--15. 1. "BASE_CREF_TOP_L0_ADD,Base address of reference data C L0 top (BASE_CREF_TOP_L0_ADD) (Reference for progressive/top field)" line.long 0x0C "MC_ADDR_3," hexmask.long.word 0x0C 16.--31. 1. "BASE_CREF_BOT_L1_ADD,Base address of reference data C L1 bottom (BASE_CREF_BOT_L1_ADD) (Reference for bottom field)" hexmask.long.word 0x0C 0.--15. 1. "BASE_CREF_TOP_L1_ADD,Base address of reference data C L1 top (BASE_CREF_TOP_L1_ADD) (Reference for progressive/top field)" tree.end tree.end tree.open "IVA_Motion_Estimation" tree "IME3_L3Interconnect" base ad:0x5A054000 repeat 15. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. ) tree "Channel_$1" group.long 0x1C0++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_48,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x20C0++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_48,Program Memory 32-bit word" tree.end repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. ) tree "Channel_$1" group.long 0x180++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_32,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x2080++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_32,Program Memory 32-bit word" tree.end repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. ) tree "Channel_$1" group.long 0x140++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_16,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x280++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_16,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_16,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xC0++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_16,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2040++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_16,Program Memory 32-bit word" tree.end repeat.end repeat 12. (list 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. ) tree "Channel_$1" group.long 0x350++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x3D0++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_10,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x354++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x3D4++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_10,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x128++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_10,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x250++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_10,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_10,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0xA8++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_10,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2028++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_10,Program Memory 32-bit word" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" group.long 0x300++0x03 line.long 0x00 "IME3_BMTABLELSB0_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 30.--31. "L0_L1_BI," "0,1,2,3" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" newline hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x380++0x03 line.long 0x00 "IME3_BMTABLELSB1_j_0,Best Match Table : register file contain result of Error Table comparisson" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELBOTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" group.long 0x304++0x03 line.long 0x00 "IME3_BMTABLEMSB0_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x384++0x03 line.long 0x00 "IME3_BMTABLEMSB1_j_0,Best Match Table : register file contain result of Error Table comparisson" bitfld.long 0x00 29.--31. "REF_IDX,Reference Frame Idx provided by software" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x00 0.--15. 1. "ERRORVALUE,error field" group.long 0x100++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_0,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x200++0x07 line.long 0x00 "IME3_ERRTABLELSB_i_0,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x00 16.--29. 1. "DY,dy coordinate field" rbitfld.long 0x00 14.--15. "FRAME_FIELDTOP_FIELDBOTTOM,Read returns 0" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. "DX,dx coordinate field" line.long 0x04 "IME3_ERRTABLEMSB_i_0,Error Table : Register File for SAD computation final errors" hexmask.long.word 0x04 16.--28. 1. "MV_COST,MV cost" hexmask.long.word 0x04 0.--15. 1. "ERRORVALUE,error field" group.long 0x40++0x03 line.long 0x00 "IME3_INTERPOL_PARAMETER_STACK_k_0,Interpolation Filter Pass Configuration" bitfld.long 0x00 26.--31. "COEFF0,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 20.--25. "COEFF1,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14.--19. "COEFF2,Coefficient vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 11.--13. "ROUND_EXPONENT,Rounding value - shift part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 5.--10. "ROUND_MANTISSA,Rounding value - data part" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--4. "SHIFT,Shift value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x03 line.long 0x00 "IME3_PARAMETERSTACK_i_0,Parameter Stack register 0 to 31 (32-bit wide)" group.long 0x2000++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_0,Program Memory 32-bit word" tree.end repeat.end tree "Channel_63" group.long 0x1FC++0x03 line.long 0x00 "IME3_CURRENTBLOCK_l_63,Current Macroblock : 16 lines of 16 bytes containing the Current MacroBlock for SAD computation" group.long 0x3FFC++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_2047,Program Memory 32-bit word" repeat 16. (list 2031. 2032. 2033. 2034. 2035. 2036. 2037. 2038. 2039. 2040. 2041. 2042. 2043. 2044. 2045. 2046. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3FBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 2015. 2016. 2017. 2018. 2019. 2020. 2021. 2022. 2023. 2024. 2025. 2026. 2027. 2028. 2029. 2030. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3F7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1999. 2000. 2001. 2002. 2003. 2004. 2005. 2006. 2007. 2008. 2009. 2010. 2011. 2012. 2013. 2014. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3F3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1983. 1984. 1985. 1986. 1987. 1988. 1989. 1990. 1991. 1992. 1993. 1994. 1995. 1996. 1997. 1998. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3EFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1967. 1968. 1969. 1970. 1971. 1972. 1973. 1974. 1975. 1976. 1977. 1978. 1979. 1980. 1981. 1982. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3EBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1951. 1952. 1953. 1954. 1955. 1956. 1957. 1958. 1959. 1960. 1961. 1962. 1963. 1964. 1965. 1966. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3E7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1935. 1936. 1937. 1938. 1939. 1940. 1941. 1942. 1943. 1944. 1945. 1946. 1947. 1948. 1949. 1950. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3E3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1919. 1920. 1921. 1922. 1923. 1924. 1925. 1926. 1927. 1928. 1929. 1930. 1931. 1932. 1933. 1934. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3DFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1903. 1904. 1905. 1906. 1907. 1908. 1909. 1910. 1911. 1912. 1913. 1914. 1915. 1916. 1917. 1918. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3DBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1887. 1888. 1889. 1890. 1891. 1892. 1893. 1894. 1895. 1896. 1897. 1898. 1899. 1900. 1901. 1902. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3D7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1871. 1872. 1873. 1874. 1875. 1876. 1877. 1878. 1879. 1880. 1881. 1882. 1883. 1884. 1885. 1886. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3D3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1855. 1856. 1857. 1858. 1859. 1860. 1861. 1862. 1863. 1864. 1865. 1866. 1867. 1868. 1869. 1870. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3CFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1839. 1840. 1841. 1842. 1843. 1844. 1845. 1846. 1847. 1848. 1849. 1850. 1851. 1852. 1853. 1854. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3CBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1823. 1824. 1825. 1826. 1827. 1828. 1829. 1830. 1831. 1832. 1833. 1834. 1835. 1836. 1837. 1838. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3C7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1807. 1808. 1809. 1810. 1811. 1812. 1813. 1814. 1815. 1816. 1817. 1818. 1819. 1820. 1821. 1822. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3C3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1791. 1792. 1793. 1794. 1795. 1796. 1797. 1798. 1799. 1800. 1801. 1802. 1803. 1804. 1805. 1806. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3BFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1775. 1776. 1777. 1778. 1779. 1780. 1781. 1782. 1783. 1784. 1785. 1786. 1787. 1788. 1789. 1790. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3BBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1759. 1760. 1761. 1762. 1763. 1764. 1765. 1766. 1767. 1768. 1769. 1770. 1771. 1772. 1773. 1774. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3B7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1743. 1744. 1745. 1746. 1747. 1748. 1749. 1750. 1751. 1752. 1753. 1754. 1755. 1756. 1757. 1758. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3B3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1727. 1728. 1729. 1730. 1731. 1732. 1733. 1734. 1735. 1736. 1737. 1738. 1739. 1740. 1741. 1742. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3AFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1711. 1712. 1713. 1714. 1715. 1716. 1717. 1718. 1719. 1720. 1721. 1722. 1723. 1724. 1725. 1726. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3ABC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1695. 1696. 1697. 1698. 1699. 1700. 1701. 1702. 1703. 1704. 1705. 1706. 1707. 1708. 1709. 1710. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3A7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1679. 1680. 1681. 1682. 1683. 1684. 1685. 1686. 1687. 1688. 1689. 1690. 1691. 1692. 1693. 1694. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x3A3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1663. 1664. 1665. 1666. 1667. 1668. 1669. 1670. 1671. 1672. 1673. 1674. 1675. 1676. 1677. 1678. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x39FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1647. 1648. 1649. 1650. 1651. 1652. 1653. 1654. 1655. 1656. 1657. 1658. 1659. 1660. 1661. 1662. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x39BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1631. 1632. 1633. 1634. 1635. 1636. 1637. 1638. 1639. 1640. 1641. 1642. 1643. 1644. 1645. 1646. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x397C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1615. 1616. 1617. 1618. 1619. 1620. 1621. 1622. 1623. 1624. 1625. 1626. 1627. 1628. 1629. 1630. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x393C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1599. 1600. 1601. 1602. 1603. 1604. 1605. 1606. 1607. 1608. 1609. 1610. 1611. 1612. 1613. 1614. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x38FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1583. 1584. 1585. 1586. 1587. 1588. 1589. 1590. 1591. 1592. 1593. 1594. 1595. 1596. 1597. 1598. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x38BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1567. 1568. 1569. 1570. 1571. 1572. 1573. 1574. 1575. 1576. 1577. 1578. 1579. 1580. 1581. 1582. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x387C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1551. 1552. 1553. 1554. 1555. 1556. 1557. 1558. 1559. 1560. 1561. 1562. 1563. 1564. 1565. 1566. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x383C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1535. 1536. 1537. 1538. 1539. 1540. 1541. 1542. 1543. 1544. 1545. 1546. 1547. 1548. 1549. 1550. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x37FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1519. 1520. 1521. 1522. 1523. 1524. 1525. 1526. 1527. 1528. 1529. 1530. 1531. 1532. 1533. 1534. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x37BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1503. 1504. 1505. 1506. 1507. 1508. 1509. 1510. 1511. 1512. 1513. 1514. 1515. 1516. 1517. 1518. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x377C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1487. 1488. 1489. 1490. 1491. 1492. 1493. 1494. 1495. 1496. 1497. 1498. 1499. 1500. 1501. 1502. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x373C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1471. 1472. 1473. 1474. 1475. 1476. 1477. 1478. 1479. 1480. 1481. 1482. 1483. 1484. 1485. 1486. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x36FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1455. 1456. 1457. 1458. 1459. 1460. 1461. 1462. 1463. 1464. 1465. 1466. 1467. 1468. 1469. 1470. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x36BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1439. 1440. 1441. 1442. 1443. 1444. 1445. 1446. 1447. 1448. 1449. 1450. 1451. 1452. 1453. 1454. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x367C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1423. 1424. 1425. 1426. 1427. 1428. 1429. 1430. 1431. 1432. 1433. 1434. 1435. 1436. 1437. 1438. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x363C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1407. 1408. 1409. 1410. 1411. 1412. 1413. 1414. 1415. 1416. 1417. 1418. 1419. 1420. 1421. 1422. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x35FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1391. 1392. 1393. 1394. 1395. 1396. 1397. 1398. 1399. 1400. 1401. 1402. 1403. 1404. 1405. 1406. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x35BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1375. 1376. 1377. 1378. 1379. 1380. 1381. 1382. 1383. 1384. 1385. 1386. 1387. 1388. 1389. 1390. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x357C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1359. 1360. 1361. 1362. 1363. 1364. 1365. 1366. 1367. 1368. 1369. 1370. 1371. 1372. 1373. 1374. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x353C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1343. 1344. 1345. 1346. 1347. 1348. 1349. 1350. 1351. 1352. 1353. 1354. 1355. 1356. 1357. 1358. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x34FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1327. 1328. 1329. 1330. 1331. 1332. 1333. 1334. 1335. 1336. 1337. 1338. 1339. 1340. 1341. 1342. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x34BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1311. 1312. 1313. 1314. 1315. 1316. 1317. 1318. 1319. 1320. 1321. 1322. 1323. 1324. 1325. 1326. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x347C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1295. 1296. 1297. 1298. 1299. 1300. 1301. 1302. 1303. 1304. 1305. 1306. 1307. 1308. 1309. 1310. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x343C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1279. 1280. 1281. 1282. 1283. 1284. 1285. 1286. 1287. 1288. 1289. 1290. 1291. 1292. 1293. 1294. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x33FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1263. 1264. 1265. 1266. 1267. 1268. 1269. 1270. 1271. 1272. 1273. 1274. 1275. 1276. 1277. 1278. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x33BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1247. 1248. 1249. 1250. 1251. 1252. 1253. 1254. 1255. 1256. 1257. 1258. 1259. 1260. 1261. 1262. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x337C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1231. 1232. 1233. 1234. 1235. 1236. 1237. 1238. 1239. 1240. 1241. 1242. 1243. 1244. 1245. 1246. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x333C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1215. 1216. 1217. 1218. 1219. 1220. 1221. 1222. 1223. 1224. 1225. 1226. 1227. 1228. 1229. 1230. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x32FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1199. 1200. 1201. 1202. 1203. 1204. 1205. 1206. 1207. 1208. 1209. 1210. 1211. 1212. 1213. 1214. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x32BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1183. 1184. 1185. 1186. 1187. 1188. 1189. 1190. 1191. 1192. 1193. 1194. 1195. 1196. 1197. 1198. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x327C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1167. 1168. 1169. 1170. 1171. 1172. 1173. 1174. 1175. 1176. 1177. 1178. 1179. 1180. 1181. 1182. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x323C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1151. 1152. 1153. 1154. 1155. 1156. 1157. 1158. 1159. 1160. 1161. 1162. 1163. 1164. 1165. 1166. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x31FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1135. 1136. 1137. 1138. 1139. 1140. 1141. 1142. 1143. 1144. 1145. 1146. 1147. 1148. 1149. 1150. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x31BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1119. 1120. 1121. 1122. 1123. 1124. 1125. 1126. 1127. 1128. 1129. 1130. 1131. 1132. 1133. 1134. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x317C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1103. 1104. 1105. 1106. 1107. 1108. 1109. 1110. 1111. 1112. 1113. 1114. 1115. 1116. 1117. 1118. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x313C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1087. 1088. 1089. 1090. 1091. 1092. 1093. 1094. 1095. 1096. 1097. 1098. 1099. 1100. 1101. 1102. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x30FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1071. 1072. 1073. 1074. 1075. 1076. 1077. 1078. 1079. 1080. 1081. 1082. 1083. 1084. 1085. 1086. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x30BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1055. 1056. 1057. 1058. 1059. 1060. 1061. 1062. 1063. 1064. 1065. 1066. 1067. 1068. 1069. 1070. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x307C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1039. 1040. 1041. 1042. 1043. 1044. 1045. 1046. 1047. 1048. 1049. 1050. 1051. 1052. 1053. 1054. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x303C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1023. 1024. 1025. 1026. 1027. 1028. 1029. 1030. 1031. 1032. 1033. 1034. 1035. 1036. 1037. 1038. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2FFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 1007. 1008. 1009. 1010. 1011. 1012. 1013. 1014. 1015. 1016. 1017. 1018. 1019. 1020. 1021. 1022. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2FBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 991. 992. 993. 994. 995. 996. 997. 998. 999. 1000. 1001. 1002. 1003. 1004. 1005. 1006. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2F7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 975. 976. 977. 978. 979. 980. 981. 982. 983. 984. 985. 986. 987. 988. 989. 990. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2F3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 959. 960. 961. 962. 963. 964. 965. 966. 967. 968. 969. 970. 971. 972. 973. 974. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2EFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 943. 944. 945. 946. 947. 948. 949. 950. 951. 952. 953. 954. 955. 956. 957. 958. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2EBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 927. 928. 929. 930. 931. 932. 933. 934. 935. 936. 937. 938. 939. 940. 941. 942. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2E7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 911. 912. 913. 914. 915. 916. 917. 918. 919. 920. 921. 922. 923. 924. 925. 926. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2E3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 895. 896. 897. 898. 899. 900. 901. 902. 903. 904. 905. 906. 907. 908. 909. 910. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2DFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 879. 880. 881. 882. 883. 884. 885. 886. 887. 888. 889. 890. 891. 892. 893. 894. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2DBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 863. 864. 865. 866. 867. 868. 869. 870. 871. 872. 873. 874. 875. 876. 877. 878. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2D7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 847. 848. 849. 850. 851. 852. 853. 854. 855. 856. 857. 858. 859. 860. 861. 862. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2D3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 831. 832. 833. 834. 835. 836. 837. 838. 839. 840. 841. 842. 843. 844. 845. 846. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2CFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 815. 816. 817. 818. 819. 820. 821. 822. 823. 824. 825. 826. 827. 828. 829. 830. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2CBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 799. 800. 801. 802. 803. 804. 805. 806. 807. 808. 809. 810. 811. 812. 813. 814. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2C7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 783. 784. 785. 786. 787. 788. 789. 790. 791. 792. 793. 794. 795. 796. 797. 798. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2C3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 767. 768. 769. 770. 771. 772. 773. 774. 775. 776. 777. 778. 779. 780. 781. 782. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2BFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 751. 752. 753. 754. 755. 756. 757. 758. 759. 760. 761. 762. 763. 764. 765. 766. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2BBC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 735. 736. 737. 738. 739. 740. 741. 742. 743. 744. 745. 746. 747. 748. 749. 750. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2B7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 719. 720. 721. 722. 723. 724. 725. 726. 727. 728. 729. 730. 731. 732. 733. 734. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2B3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 703. 704. 705. 706. 707. 708. 709. 710. 711. 712. 713. 714. 715. 716. 717. 718. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2AFC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 687. 688. 689. 690. 691. 692. 693. 694. 695. 696. 697. 698. 699. 700. 701. 702. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2ABC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 671. 672. 673. 674. 675. 676. 677. 678. 679. 680. 681. 682. 683. 684. 685. 686. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2A7C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 655. 656. 657. 658. 659. 660. 661. 662. 663. 664. 665. 666. 667. 668. 669. 670. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x2A3C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 639. 640. 641. 642. 643. 644. 645. 646. 647. 648. 649. 650. 651. 652. 653. 654. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x29FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 623. 624. 625. 626. 627. 628. 629. 630. 631. 632. 633. 634. 635. 636. 637. 638. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x29BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 607. 608. 609. 610. 611. 612. 613. 614. 615. 616. 617. 618. 619. 620. 621. 622. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x297C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 591. 592. 593. 594. 595. 596. 597. 598. 599. 600. 601. 602. 603. 604. 605. 606. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x293C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 575. 576. 577. 578. 579. 580. 581. 582. 583. 584. 585. 586. 587. 588. 589. 590. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x28FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 559. 560. 561. 562. 563. 564. 565. 566. 567. 568. 569. 570. 571. 572. 573. 574. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x28BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 543. 544. 545. 546. 547. 548. 549. 550. 551. 552. 553. 554. 555. 556. 557. 558. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x287C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 527. 528. 529. 530. 531. 532. 533. 534. 535. 536. 537. 538. 539. 540. 541. 542. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x283C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 511. 512. 513. 514. 515. 516. 517. 518. 519. 520. 521. 522. 523. 524. 525. 526. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x27FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 495. 496. 497. 498. 499. 500. 501. 502. 503. 504. 505. 506. 507. 508. 509. 510. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x27BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 479. 480. 481. 482. 483. 484. 485. 486. 487. 488. 489. 490. 491. 492. 493. 494. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x277C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 463. 464. 465. 466. 467. 468. 469. 470. 471. 472. 473. 474. 475. 476. 477. 478. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x273C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 447. 448. 449. 450. 451. 452. 453. 454. 455. 456. 457. 458. 459. 460. 461. 462. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x26FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 431. 432. 433. 434. 435. 436. 437. 438. 439. 440. 441. 442. 443. 444. 445. 446. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x26BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 415. 416. 417. 418. 419. 420. 421. 422. 423. 424. 425. 426. 427. 428. 429. 430. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x267C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 399. 400. 401. 402. 403. 404. 405. 406. 407. 408. 409. 410. 411. 412. 413. 414. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x263C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 383. 384. 385. 386. 387. 388. 389. 390. 391. 392. 393. 394. 395. 396. 397. 398. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x25FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 367. 368. 369. 370. 371. 372. 373. 374. 375. 376. 377. 378. 379. 380. 381. 382. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x25BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 351. 352. 353. 354. 355. 356. 357. 358. 359. 360. 361. 362. 363. 364. 365. 366. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x257C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 335. 336. 337. 338. 339. 340. 341. 342. 343. 344. 345. 346. 347. 348. 349. 350. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x253C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 319. 320. 321. 322. 323. 324. 325. 326. 327. 328. 329. 330. 331. 332. 333. 334. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x24FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 303. 304. 305. 306. 307. 308. 309. 310. 311. 312. 313. 314. 315. 316. 317. 318. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x24BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 287. 288. 289. 290. 291. 292. 293. 294. 295. 296. 297. 298. 299. 300. 301. 302. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x247C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 271. 272. 273. 274. 275. 276. 277. 278. 279. 280. 281. 282. 283. 284. 285. 286. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x243C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 255. 256. 257. 258. 259. 260. 261. 262. 263. 264. 265. 266. 267. 268. 269. 270. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x23FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 239. 240. 241. 242. 243. 244. 245. 246. 247. 248. 249. 250. 251. 252. 253. 254. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x23BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 223. 224. 225. 226. 227. 228. 229. 230. 231. 232. 233. 234. 235. 236. 237. 238. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x237C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 207. 208. 209. 210. 211. 212. 213. 214. 215. 216. 217. 218. 219. 220. 221. 222. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x233C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 191. 192. 193. 194. 195. 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x22FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 175. 176. 177. 178. 179. 180. 181. 182. 183. 184. 185. 186. 187. 188. 189. 190. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x22BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x227C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 143. 144. 145. 146. 147. 148. 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x223C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x21FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x21BC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x217C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x213C)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end repeat 16. (list 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x20FC)++0x03 line.long 0x00 "IME3_PROGRAMBUFFER_m_$1,Program Memory 32-bit word" repeat.end tree.end group.long 0x450++0x07 line.long 0x00 "IME3_CIRCULAR_BUFFER_CURRENT_POSITION0,Current position in the circular buffer" hexmask.long.word 0x00 18.--31. 1. "Y0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x00 2.--15. 1. "X0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (X coordinate pixel precision)" line.long 0x04 "IME3_CIRCULAR_BUFFER_CURRENT_POSITION1," hexmask.long.word 0x04 18.--31. 1. "Y0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x04 2.--15. 1. "X0,Position of colocated MB in the circular buffer when origin is taken at top left corner of circular buffer (X coordinate pixel precision)" repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x428)++0x03 line.long 0x00 "IME3_CIRCULAR_BUFFER_DESC$1,Circular Buffer 0" bitfld.long 0x00 24. "DIRECTION,Horizontal or Vertical Circularity" "DIRECTION_0,DIRECTION_1" hexmask.long.byte 0x00 16.--23. 1. "OFFSET,In MBs" newline hexmask.long.byte 0x00 8.--15. 1. "CBW,Circular Buffer Width in MBs" hexmask.long.byte 0x00 0.--7. 1. "CBH,Circular Buffer Height in MBs" repeat.end repeat 2. (list 0. 1. )(list 0x00 0x04 ) group.long ($2+0x474)++0x03 line.long 0x00 "IME3_CIRCULAR_BUFFER_SLIDING_POSITION$1," hexmask.long.word 0x00 18.--31. 1. "Y0,Position of colocated MB in the circular buffer (Y coordinate pixel precision)" hexmask.long.word 0x00 2.--15. 1. "X0,Position of colocated MB in the circular buffer (X coordinate pixel precision)" repeat.end group.long 0x1FFC++0x03 line.long 0x00 "IME3_COMMANDREG,IME3 command register: a write to this register decodes a command. a read returns 0" group.long 0x440++0x03 line.long 0x00 "IME3_CONDITIONREGISTER,Absolute Minimum Reached bit register. used in Mcomp() operator" hexmask.long.byte 0x00 24.--31. 1. "APPLICATIONCOUNTER1,Counter 1" hexmask.long.byte 0x00 16.--23. 1. "APPLICATIONCOUNTER0,Counter 0" newline bitfld.long 0x00 11. "PARTITIONVALID,Reset by ClearStatus()" "PARTITIONVALID_0,PARTITIONVALID_1" bitfld.long 0x00 9.--10. "BOTTOMRIGHTREFERENCE,L0 L1 Bi" "BOTTOMRIGHTREFERENCE_0,BOTTOMRIGHTREFERENCE_1,BOTTOMRIGHTREFERENCE_2,BOTTOMRIGHTREFERENCE_3" newline bitfld.long 0x00 7.--8. "BOTTOMLEFTREFERENCE,L0 L1 Bi" "BOTTOMLEFTREFERENCE_0,BOTTOMLEFTREFERENCE_1,BOTTOMLEFTREFERENCE_2,BOTTOMLEFTREFERENCE_3" bitfld.long 0x00 5.--6. "TOPRIGHTREFERENCE,L0 L1 Bi" "TOPRIGHTREFERENCE_0,TOPRIGHTREFERENCE_1,TOPRIGHTREFERENCE_2,TOPRIGHTREFERENCE_3" newline bitfld.long 0x00 3.--4. "TOPLEFTREFERENCE,L0 L1 Bi" "TOPLEFTREFERENCE_0,TOPLEFTREFERENCE_1,TOPLEFTREFERENCE_2,TOPLEFTREFERENCE_3" bitfld.long 0x00 1.--2. "PARTITIONTYPE,16x16 16x8 8x16 8x8" "PARTITIONTYPE_0,PARTITIONTYPE_1,PARTITIONTYPE_2,PARTITIONTYPE_3" newline bitfld.long 0x00 0. "ABSMINREACHED,Abs Min Reached bit in Mcomp block" "ABSMINREACHED_0,ABSMINREACHED_1" group.long 0x430++0x07 line.long 0x00 "IME3_CPUSTATUSREG,CPU Status Register provides information on the progress of the CPU execution" bitfld.long 0x00 31. "START_OR_STEP_TAKEN,Set to 1 when Step() Local Interconnect command is received" "START_OR_STEP_TAKEN_0,START_OR_STEP_TAKEN_1" rbitfld.long 0x00 30. "DETECTEDENDOFPGM,This bit is set to '1' when in Debug mode an EndOfPgm instruction or the last instruction of ProgramBuffer has been reached" "DETECTEDENDOFPGM_0,DETECTEDENDOFPGM_1" newline rbitfld.long 0x00 29. "DETECTEDSTOP,This bit is set to '1' when a Stop() command is received" "DETECTEDSTOP_0,DETECTEDSTOP_1" rbitfld.long 0x00 28. "REJECTED_ACCESS,Set when a Local Interconnect read to the Program Memory or an Local Interconnect write are perfromed while the IME3 is still in the EXECUTING state" "0,1" newline rbitfld.long 0x00 24.--25. "EXECSTATE," "EXECSTATE_0,EXECSTATE_1,EXECSTATE_2,EXECSTATE_3" rbitfld.long 0x00 19. "RECEIVEDSIGNAL1,Indicates that module has received a Local Interconnect Signal1 Command" "RECEIVEDSIGNAL1_0,RECEIVEDSIGNAL1_1" newline rbitfld.long 0x00 18. "WAITINGONSIGNAL1,Indicates that module is waiting for Local Interconnect Signal1 Command" "WAITINGONSIGNAL1_0,WAITINGONSIGNAL1_1" rbitfld.long 0x00 17. "RECEIVEDSIGNAL0,Indicates that module has received a Local Interconnect Signal0 Command" "RECEIVEDSIGNAL0_0,RECEIVEDSIGNAL0_1" newline rbitfld.long 0x00 16. "WAITINGONSIGNAL0,Indicates that module is waiting for Local Interconnect Signal0 Command" "WAITINGONSIGNAL0_0,WAITINGONSIGNAL0_1" hexmask.long.word 0x00 0.--15. 1. "PC,Address of the instruction currently issued" line.long 0x04 "IME3_CYCLECOUNT,Cycle count register" bitfld.long 0x04 31. "CYCLECOUNTENABLE,When set to 1 cycle counting is enabled" "CYCLECOUNTENABLE_0,CYCLECOUNTENABLE_1" bitfld.long 0x04 30. "CYCLECOUNTRESET,Writing 0 results in no effect" "CYCLECOUNTRESET_0,CYCLECOUNTRESET_1" newline hexmask.long.word 0x04 0.--15. 1. "CYCLECOUNT,Incremets at each cycle if cycleCountEnable equals 1 and if CpuState is EXECUTING" group.long 0x470++0x03 line.long 0x00 "IME3_INTERPOLATION_REFERENCE,The Interpol Reference is the MV based on which the last interpolation has been performed" hexmask.long.word 0x00 16.--31. 1. "Y,This is the 'y' coordinate of the {0 0} point of the interpol planes" hexmask.long.word 0x00 0.--15. 1. "X,x coordinate for the origin point of the interpolation" hgroup.long 0x20++0x03 hide.long 0x00 "IME3_IRQ_EOI,End Of Interrupt number specification" group.long 0x30++0x03 line.long 0x00 "IME3_IRQENABLE_CLR,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 1. "ENABLE1,Enable for event #1 (Gen_It) - disabled" "ENABLE1_0_r,ENABLE1_1_w" bitfld.long 0x00 0. "ENABLE0,Enable for event #0 (End_Pgm) - disabled" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x2C++0x03 line.long 0x00 "IME3_IRQENABLE_SET,Per-event interrupt enable bit vector. line #0" bitfld.long 0x00 1. "ENABLE1,Enable for event #1 (Gen_It) - disabled" "ENABLE1_0_r,ENABLE1_1_w" bitfld.long 0x00 0. "ENABLE0,Enable for event #0 (End_Pgm) - disabled" "ENABLE0_0_r,ENABLE0_1_w" group.long 0x28++0x03 line.long 0x00 "IME3_IRQSTATUS,Per-event 'enabled' interrupt status vector. line #0" bitfld.long 0x00 1. "EVENT1,Clearable enabled status for event #1 (Gen_it) - noevent" "EVENT1_0_r,EVENT1_1_w" bitfld.long 0x00 0. "EVENT0,Clearable enabled status for event #0 (End_Pgm) - noevent" "EVENT0_0_r,EVENT0_1_w" group.long 0x24++0x03 line.long 0x00 "IME3_IRQSTATUS_RAW,Per-event raw interrupt status vector. line #0" bitfld.long 0x00 1. "EVENT1,Settable raw status for event #1 (Gen_It) - noevent" "EVENT1_0_r,EVENT1_1_w" bitfld.long 0x00 0. "EVENT0,Settable raw status for event #0 (End_Pgm) - noevent" "EVENT0_0_r,EVENT0_1_w" group.long 0x44C++0x03 line.long 0x00 "IME3_MINERRORTHRESHOLD,Minimum Error Threshold register. used in Mcomp() operator" hexmask.long.word 0x00 0.--15. 1. "MINTHRESHOLD,Min Threshold value in Mcomp() block" group.long 0x400++0x03 line.long 0x00 "IME3_MVCT0_3,MV Cost Table" bitfld.long 0x00 24.--28. "MVCT_3,MV Cost Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "MVCT_2,MV Cost Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "MVCT_1,MV Cost Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "MVCT_0,MV Cost Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40C++0x03 line.long 0x00 "IME3_MVCT12_14,MV Cost Table" bitfld.long 0x00 16.--20. "MVCT_14,MV Cost Table 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. "MVCT_13,MV Cost Table 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "MVCT_12,MV Cost Table 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x404++0x07 line.long 0x00 "IME3_MVCT4_7,MV Cost Table" bitfld.long 0x00 24.--28. "MVCT_7,MV Cost Table 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "MVCT_6,MV Cost Table 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "MVCT_5,MV Cost Table 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "MVCT_4,MV Cost Table 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "IME3_MVCT8_11,MV Cost Table" bitfld.long 0x04 24.--28. "MVCT_11,MV Cost Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--20. "MVCT_10,MV Cost Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 8.--12. "MVCT_9,MV Cost Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. "MVCT_8,MV Cost Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x00++0x03 line.long 0x00 "IME3_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.long 0x10++0x03 line.long 0x00 "IME3_SYSCONFIG,Clock management configuration" rbitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0_r,?,?,?" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline rbitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "?,FREEEMU_1_r" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_r" group.long 0x45C++0x03 line.long 0x00 "IME3_VALID_AREA0_BOTTOM_RIGHT_COORDINATES,Bottom right coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area bottom right limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x458++0x03 line.long 0x00 "IME3_VALID_AREA0_TOP_LEFT_COORDINATES,Top left coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area top left limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x460++0x03 line.long 0x00 "IME3_VALID_AREA1_TOP_LEFT_COORDINATES,Top left coordinates" hexmask.long.word 0x00 16.--31. 1. "Y,Valid area bottom right limit in the circular buffer (Y coordinate quarter pixel precision)" hexmask.long.word 0x00 0.--15. 1. "X,Valid area top left limit in the circular buffer (X coordinate quarter pixel precision)" group.long 0x414++0x03 line.long 0x00 "IME3_VEC_VAR_HOR_HI,horizontal vector variable (higher bits)" hexmask.long.byte 0x00 0.--6. 1. "VEC_VAR_HI," group.long 0x410++0x03 line.long 0x00 "IME3_VEC_VAR_HOR_LO,horizontal vector variable (lower bits)" group.long 0x41C++0x03 line.long 0x00 "IME3_VEC_VAR_VER_HI,vertical vector variable (higher bits)" hexmask.long.byte 0x00 0.--6. 1. "VEC_VAR_HI," group.long 0x418++0x03 line.long 0x00 "IME3_VEC_VAR_VER_LO,vertical vector variable (lower bits)" group.long 0x420++0x07 line.long 0x00 "IME3_VECABSMEANHOR," hexmask.long 0x00 0.--28. 1. "VEC_ABS_MEAN_HOR,Accumulates |BMT0[0].dx|" line.long 0x04 "IME3_VECABSMEANVER," hexmask.long 0x04 0.--28. 1. "VEC_ABS_MEAN_VER,Accumulates |BMT0[0].dy|" group.long 0x468++0x07 line.long 0x00 "IME3_VECMEANHOR," hexmask.long 0x00 0.--28. 1. "VEC_MEAN_HOR,Accumulates BMT0[0].dx" line.long 0x04 "IME3_VECMEANVER," hexmask.long 0x04 0.--28. 1. "VEC_MEAN_VER,Accumulates BMT0[0].dy" tree.end tree.end tree.open "IVA_Overview" tree "SYSCTRL_L3_MAINInterconnect" base ad:0x5A05A400 rgroup.long 0x00++0x07 line.long 0x00 "IVAHD_REVISION,IP revision identifier (X.Y.R)" line.long 0x04 "IVAHD_HWINFO,Information about the IP module's hardware configuration" bitfld.long 0x04 14. "ECD3,ECD3 available" "ECD3_0,ECD3_1" bitfld.long 0x04 13. "MC3,MC3 available" "MC3_0,MC3_1" bitfld.long 0x04 12. "IPE3,IPE3 available" "IPE3_0,IPE3_1" bitfld.long 0x04 11. "CALC3,CALC3 available" "CALC3_0,CALC3_1" newline bitfld.long 0x04 10. "IME3,IME3 available" "IME3_0,IME3_1" bitfld.long 0x04 9. "ILF3,ILF3 available" "ILF3_0,ILF3_1" bitfld.long 0x04 8. "DMA_IVA,DMA_IVA available" "0,1" bitfld.long 0x04 7. "ICONT2,ICONT2 available" "ICONT2_0,ICONT2_1" newline bitfld.long 0x04 6. "ICONT1,ICONT1 available" "ICONT1_0,ICONT1_1" bitfld.long 0x04 4.--5. "SL2BANK,- 1bank" "SL2BANK_0_r,SL2BANK_1_r,SL2BANK_2_r,SL2BANK_3_r" bitfld.long 0x04 0.--3. "SL2SIZE,Size of SL2 memory - 16kB" "?,SL2SIZE_1_r,SL2SIZE_2_r,SL2SIZE_3_r,SL2SIZE_4_r,SL2SIZE_5_r,SL2SIZE_6_r,SL2SIZE_7_r,SL2SIZE_8_r,SL2SIZE_9_r,SL2SIZE_10_r,SL2SIZE_11_r,SL2SIZE_12_r,SL2SIZE_13_r,SL2SIZE_14_r,?" group.long 0x10++0x03 line.long 0x00 "IVAHD_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "?,STANDBYMODE_1,STANDBYMODE_2,?" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "?,IDLEMODE_1,IDLEMODE_2,?" group.long 0x20++0x23 line.long 0x00 "IVAHD_IRQ_EOI,End Of Interrupt number specification" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0_r,LINE_NUMBER_1_w" line.long 0x04 "IVAHD_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.long 0x04 0. "SYSCTRL_CLKERR,Settable raw status for Clock Programming Error event - noevent" "SYSCTRL_CLKERR_0_r,SYSCTRL_CLKERR_1_w" line.long 0x08 "IVAHD_IRQSTATUS,Per-event 'enabled' interrupt status vector. line 0" bitfld.long 0x08 0. "SYSCTRL_CLKERR,Clearable enabled status for Clock Programming Error event - noevent" "SYSCTRL_CLKERR_0_r,SYSCTRL_CLKERR_1_w" line.long 0x0C "IVAHD_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.long 0x0C 0. "SYSCTRL_CLKERR,Clock Programing Error - disabled" "SYSCTRL_CLKERR_0_r,SYSCTRL_CLKERR_1_w" line.long 0x10 "IVAHD_IRQENABLE_CLR,Per-event interrupt enable bit vector" bitfld.long 0x10 0. "SYSCTRL_CLKERR,Clock Programing Error - disabled" "SYSCTRL_CLKERR_0_r,SYSCTRL_CLKERR_1_w" line.long 0x14 "IVAHD_SYNC_IRQSTATUS_RAW,Per-event raw interrupt status vector" hexmask.long.byte 0x14 0.--7. 1. "SYNC_INPUT7_0,Settable raw status for SYNC INPUT event" line.long 0x18 "IVAHD_SYNC_IRQSTATUS,Per-event 'enabled' interrupt status vector. line 0" hexmask.long.byte 0x18 0.--7. 1. "SYNC_INPUT7_0,Clearable enabled status for SYNC INPUT event" line.long 0x1C "IVAHD_SYNC_IRQENABLE_SET,Per-event interrupt enable bit vector" hexmask.long.byte 0x1C 0.--7. 1. "SYNC_INPUT7_0,Enable for interrupt event" line.long 0x20 "IVAHD_SYNC_IRQENABLE_CLR,Per-event interrupt enable bit vector" hexmask.long.byte 0x20 0.--7. 1. "SYNC_INPUT7_0,Enable for interrupt event" group.long 0x50++0x0B line.long 0x00 "IVAHD_CLKCTRL,IVA clock control register" bitfld.long 0x00 10. "SMSET,Clock control of SMSET" "SMSET_0,SMSET_1" bitfld.long 0x00 9. "MSGIF,Clock control of MSGIF" "MSGIF_0,MSGIF_1" bitfld.long 0x00 8. "ECD3,Clock control of ECD3" "ECD3_0,ECD3_1" bitfld.long 0x00 7. "MC3,Clock control of MC3" "MC3_0,MC3_1" newline bitfld.long 0x00 6. "IPE3,Clock control of IPE3" "IPE3_0,IPE3_1" bitfld.long 0x00 5. "CALC3,Clock control of CALC3" "CALC3_0,CALC3_1" bitfld.long 0x00 4. "ILF3,Clock control of ILF3" "ILF3_0,ILF3_1" bitfld.long 0x00 3. "IME3,Clock control of IME3" "IME3_0,IME3_1" newline bitfld.long 0x00 2. "DMA_IVA,Clock control of DMA_IVA" "0,1" bitfld.long 0x00 1. "ICONT2,Clock control of ICONT2" "ICONT2_0,ICONT2_1" bitfld.long 0x00 0. "ICONT1,Clock control of ICONT1" "ICONT1_0,ICONT1_1" line.long 0x04 "IVAHD_CLKST,IVA clock status register" bitfld.long 0x04 10. "SMSET,Clock status of SMSET" "SMSET_0,SMSET_1" bitfld.long 0x04 9. "MSGIF,Clock status of MSGIF" "MSGIF_0,MSGIF_1" bitfld.long 0x04 8. "ECD3,Clock status of ECD3" "ECD3_0,ECD3_1" bitfld.long 0x04 7. "MC3,Clock status of MC3" "MC3_0,MC3_1" newline bitfld.long 0x04 6. "IPE3,Clock status of IPE3" "IPE3_0,IPE3_1" bitfld.long 0x04 5. "CALC3,Clock status of CALC3" "CALC3_0,CALC3_1" bitfld.long 0x04 4. "ILF3,Clock status of ILF3" "ILF3_0,ILF3_1" bitfld.long 0x04 3. "IME3,Clock status of IME3" "IME3_0,IME3_1" newline bitfld.long 0x04 2. "DMA_IVA,Clock status of DMA_IVA" "0,1" bitfld.long 0x04 1. "ICONT2,Clock status of ICONT2" "ICONT2_0,ICONT2_1" bitfld.long 0x04 0. "ICONT1,Clock status of ICONT1" "ICONT1_0,ICONT1_1" line.long 0x08 "IVAHD_STDBYST,IVA STANDBY status" bitfld.long 0x08 2. "DMA_IVA,DMA_IVA Standby status" "0,1" bitfld.long 0x08 1. "ICONT2,ICONT2 Standby status" "ICONT2_0,ICONT2_1" bitfld.long 0x08 0. "ICONT1,ICONT1 Standby status" "ICONT1_0,ICONT1_1" tree.end tree.end tree.open "IVA_Synchronization_Box" tree "SYNCBOX_CALC3_L3_MAINInterconnect" base ad:0x5A062000 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) group.long ($2+0xC4)++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_$1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" newline bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "0,1" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" newline bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" newline bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" tree.end tree "SYNCBOX_ECD3_L3_MAINInterconnect" base ad:0x5A063800 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) group.long ($2+0xC4)++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_$1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" newline bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "0,1" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" newline bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" newline bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" tree.end tree "SYNCBOX_IPE3_L3_MAINInterconnect" base ad:0x5A062800 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) group.long ($2+0xC4)++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_$1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" newline bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "0,1" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" newline bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" newline bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" tree.end tree "SYNCBOX_MC3_L3_MAINInterconnect" base ad:0x5A063000 tree "Channel_0" rgroup.long 0x114++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_0,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x110++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_0,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x118++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_0,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_0,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x128++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_0,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x124++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_0,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_0,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_0,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Channel_1" rgroup.long 0x194++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONCONTROL_i_1,Contains the four activation counters" bitfld.long 0x00 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x00 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x190++0x03 line.long 0x00 "SYNCBOX_ACTIVATIONMASK_i_1,Applies for synchronous task description of bit fields given below" bitfld.long 0x00 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x198++0x03 line.long 0x00 "SYNCBOX_NEWTASKCOUNTER_i_1,NewTask counter" hexmask.long.word 0x00 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x1A0++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i_1,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" rgroup.long 0x1A8++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_IF_i_1,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" group.long 0x1A4++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_INC_i_1,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x00 0.--15. 1. "VALUE,Value of the increment" group.long 0x180++0x0F line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i_1,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 ) group.long ($2+0xC4)++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j_$1,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat.end tree.end group.long 0x50++0x03 line.long 0x00 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x00 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x00 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x00 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x00 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" bitfld.long 0x00 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" newline bitfld.long 0x00 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" group.long 0x4C++0x03 line.long 0x00 "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x00 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48++0x03 line.long 0x00 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x00 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x00 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x44++0x03 line.long 0x00 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x00 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x00 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x40++0x03 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "0,1" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" newline bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" newline bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" tree.end tree "SYNCBOX_ILF3_L3_MAINInterconnect" base ad:0x5A061000 rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x40++0x17 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "0,1" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x04 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x08 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x08 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x0C 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x10 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x10 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x10 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x10 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x10 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x10 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" line.long 0x14 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x14 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x1B line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ACTIVATIONMASK_i,Applies for synchronous task description of bit fields given below" bitfld.long 0x10 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SYNCBOX_ACTIVATIONCONTROL_i,Contains the four activation counters" bitfld.long 0x14 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x14 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "SYNCBOX_NEWTASKCOUNTER_i,NewTask counter" hexmask.long.word 0x18 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x0B line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" line.long 0x04 "SYNCBOX_PARAMADDR_INC_i,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x04 0.--15. 1. "VALUE,Value of the increment" line.long 0x08 "SYNCBOX_PARAMADDR_IF_i,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x08 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" tree.end tree "SYNCBOX_IME3_L3_MAINInterconnect" base ad:0x5A061800 rgroup.long 0x00++0x03 line.long 0x00 "SYNCBOX_REVISION,IP revision identifier" group.long 0x10++0x03 line.long 0x00 "SYNCBOX_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 1. "CLEARSTATUS,Set to 1 to clear dynamic registers" "CLEARSTATUS_0_w,CLEARSTATUS_1_r" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" group.long 0x40++0x17 line.long 0x00 "SYNCBOX_RXMESSAGE,Register containing the received message. from the CTL_IN interface or MSG_IN interface" bitfld.long 0x00 15. "RECONFIG,Bit to allow dynamic reconfiguration - not used" "0,1" bitfld.long 0x00 14. "ACK_REQ,Bit set to 1 in input message if an acknowledge message must be returned" "0,1" bitfld.long 0x00 13. "MSG_TYPE,Message type" "0,1" bitfld.long 0x00 12. "SYNCMODE,Synchronous message type: 0 Synchronous" "0,1" newline bitfld.long 0x00 8.--11. "DESTTASKID,Task identifier of the destination node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "SOURCETASKID,Task identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "SOURCENODEID,Node identifier of the message sender" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_NODEIDENTIFIER,Contains the node identifier" bitfld.long 0x04 0.--3. "VALUE,Node identifier value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_ERRORMSGDEST,Register containing the node and task identifier to send an activation message when an error is detected" bitfld.long 0x08 8. "VALID_BIT,Validity bit use to send or not the error message to a CPU based node" "0,1" bitfld.long 0x08 4.--7. "TASK_ID,Identifier for the task in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "NODE_ID,Identifier for the node in charge of recovering error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_ERRORLOG,Contains the different errors latched during message decoding" bitfld.long 0x0C 4.--7. "TASK_ID,Identifier of the task (or event line) to which error is attached" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "ERR_CODE,4 bits coding the error code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ASYNCEVENTACKREQ,Each bit in this register defines whether the corresponding asynchronous line event need an acknowledge upon task completion or directly when the line is raised" bitfld.long 0x10 5. "ACKTASK5," "ACKTASK5_0,ACKTASK5_1" bitfld.long 0x10 4. "ACKTASK4," "ACKTASK4_0,ACKTASK4_1" bitfld.long 0x10 3. "ACKTASK3," "ACKTASK3_0,ACKTASK3_1" bitfld.long 0x10 2. "ACKTASK2," "ACKTASK2_0,ACKTASK2_1" newline bitfld.long 0x10 1. "ACKTASK1," "ACKTASK1_0,ACKTASK1_1" bitfld.long 0x10 0. "ACKTASK0," "ACKTASK0_0,ACKTASK0_1" line.long 0x14 "SYNCBOX_PARAMADDR_MOD,Modulo value for the configuration parameter pointer computed by SYNCBOX" hexmask.long.byte 0x14 0.--7. 1. "VALUE,Number of macroblock configuration arrays in pipeline" rgroup.long 0x60++0x03 line.long 0x00 "SYNCBOX_STATUS," bitfld.long 0x00 11. "EOTFIFO_5,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 10. "COREFSM_5,Status bit for task 5" "0,1" bitfld.long 0x00 9. "EOTFIFO_4,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 8. "COREFSM_4,Status bit for task 4" "0,1" newline bitfld.long 0x00 7. "EOTFIFO_3,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 6. "COREFSM_3,Status bit for task 3" "0,1" bitfld.long 0x00 5. "EOTFIFO_2,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 4. "COREFSM_2,Status bit for task 2" "0,1" newline bitfld.long 0x00 3. "EOTFIFO_1,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 2. "COREFSM_1,Status bit for task 1" "0,1" bitfld.long 0x00 1. "EOTFIFO_0,EndOfTask FIFO empty (0) or not empty (1)" "0,1" bitfld.long 0x00 0. "COREFSM_0,Status bit for task 0" "0,1" group.long 0xC0++0x03 line.long 0x00 "SYNCBOX_REMOTEASYNCACTMSG_j,Contains the task and node identifier to send the activation message to. upon detection of an asynchronous event" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x1B line.long 0x00 "SYNCBOX_REMOTESYNCACTMSGREG1_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x00 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x00 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "SYNCBOX_REMOTESYNCACTMSGREG2_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x04 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if f set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x04 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "SYNCBOX_REMOTESYNCACTMSGREG3_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x08 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x08 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "SYNCBOX_REMOTESYNCACTMSGREG4_i,Contains destination task identifier and destination node identifier for activation messages to be sent upon task completion" bitfld.long 0x0C 8. "VALID_BIT,Validity bit of current register content: If set to 0 the two fields dest_node_id and dest_task_id can be ignored; if set to 1 the two fields dest_node_id and dest_task_id are used to send activation message" "0,1" bitfld.long 0x0C 4.--7. "DEST_TASK_ID,Destination task identifier telling at which task in the destination node the activation message must be sent upon task completion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. "DEST_NODE_ID,Destination node identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "SYNCBOX_ACTIVATIONMASK_i,Applies for synchronous task description of bit fields given below" bitfld.long 0x10 28.--31. "TASK_ID3,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. "TASK_ID2,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 20.--23. "TASK_ID1,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 16.--19. "TASK_ID0,For synchronous message: Each quad bit contains the task ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 12.--15. "NODE_ID3,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 8.--11. "NODE_ID2,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 4.--7. "NODE_ID1,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. "NODE_ID0,For synchronous message: Each quad bit contains the node ID of a potential activator for asynchronous message" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "SYNCBOX_ACTIVATIONCONTROL_i,Contains the four activation counters" bitfld.long 0x14 20. "MATCHFLAG,Bit set to 1 when all activation messages received" "0,1" bitfld.long 0x14 15.--19. "COUNTER3,Associated counter with the fourth activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 10.--14. "COUNTER2,Associated counter with the third activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 5.--9. "COUNTER1,Associated counter with the second activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x14 0.--4. "COUNTER0,Associated counter with the first activator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x18 "SYNCBOX_NEWTASKCOUNTER_i,NewTask counter" hexmask.long.word 0x18 0.--12. 1. "VALUE,Counter of the number of times the NewTask signal has been activated" group.long 0x120++0x0B line.long 0x00 "SYNCBOX_PARAMADDR_BASE_i,Base address for the node configuration parameters" hexmask.long.word 0x00 0.--15. 1. "VALUE,128-bit address" line.long 0x04 "SYNCBOX_PARAMADDR_INC_i,Contains the parameter address increment to be added to the current parameter address pointer" hexmask.long.word 0x04 0.--15. 1. "VALUE,Value of the increment" line.long 0x08 "SYNCBOX_PARAMADDR_IF_i,Interface register containing the current value of the MB configuration parameters" hexmask.long.word 0x08 0.--15. 1. "VALUE,16-bit value containing a 128-bit pointer" tree.end tree.end tree.open "IVA_Video_Direct_Memory_Access" tree "VDMA_L3_MAINInterconnect" base ad:0x5A050000 rgroup.long 0x00++0x03 line.long 0x00 "VDMA_REVISION,IP revision identifier" group.long 0x10++0x03 line.long 0x00 "VDMA_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x20++0x57 line.long 0x00 "VDMA_IRQ_EOI,End Of Interrupt number specification" hexmask.long.byte 0x00 0.--7. 1. "LINE_NUMBER,Software End Of Interrupt (EOI) control" line.long 0x04 "VDMA_IRQSTATUS_RAW_0,Per-end of group (31 down to 0) internal signaling raw interrupt status vector. line #0" line.long 0x08 "VDMA_IRQSTATUS_0,Per-end of group (31 down to 0) internal signaling 'enabled' interrupt status vector. line #0" line.long 0x0C "VDMA_IRQENABLE_SET_0,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #0" line.long 0x10 "VDMA_IRQENABLE_CLR_0,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #0" line.long 0x14 "VDMA_IRQSTATUS_RAW_1,Per-end of group (31 down to 0) internal signaling raw interrupt status vector. line #1" line.long 0x18 "VDMA_IRQSTATUS_1,Per-end of group (31 down to 0) internal signaling 'enabled' interrupt status vector. line #1" line.long 0x1C "VDMA_IRQENABLE_SET_1,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #1" line.long 0x20 "VDMA_IRQENABLE_CLR_1,Per-end of group (31 down to 0) internal event interrupt enable bit vector. line #1" line.long 0x24 "VDMA_IRQSTATUS_RAW_2,Per-error event raw interrupt status vector. line #2" bitfld.long 0x24 3. "MASTER_SRESPERR,Interrupt fires when one VDMA OCP master port (SL2R SL2W or L3_MAIN) received Sresp=ERR from platform" "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x24 2. "DIR_INTERLEAVE,Interrupt fires (if enabled) in case U/V bit is set and DIR field is different from 0b10" "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x24 1. "TRIGGER_TWICE,From software user perspective: interrupt fires when same group has been triggered twice without having received end of corresponding group signaling in between" "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x24 0. "COHERENCY_ERROR,Interrupt fires (if enabled) in case descriptors pushed into lists (either asynchronous or synchronous) do not match with current group being scheduled" "COHERENCY_ERROR_0,COHERENCY_ERROR_1" line.long 0x28 "VDMA_IRQSTATUS_2,Per-error event 'enabled' interrupt status vector. line #2" bitfld.long 0x28 3. "MASTER_SRESPERR,Interrupt fires when one VDMA OCP master port (SL2R SL2W or L3_MAIN) received Sresp=ERR from platform" "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x28 2. "DIR_INTERLEAVE,Interrupt fires (if enabled) in case U/V bit is set and DIR field is different from 0b10" "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x28 1. "TRIGGER_TWICE,From software user perspective: interrupt fires when same group has been triggered twice without having received end of corresponding group signaling in between" "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x28 0. "COHERENCY_ERROR,Interrupt fires (if enabled) in case descriptors pushed into lists (either asynchronous or synchronous) do not match with current group being scheduled" "COHERENCY_ERROR_0,COHERENCY_ERROR_1" line.long 0x2C "VDMA_IRQENABLE_SET_2,Per-error event interrupt enable bit vector. line #2" bitfld.long 0x2C 3. "MASTER_SRESPERR," "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x2C 2. "DIR_INTERLEAVE," "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x2C 1. "TRIGGER_TWICE," "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x2C 0. "COHERENCY_ERROR," "COHERENCY_ERROR_0,COHERENCY_ERROR_1" line.long 0x30 "VDMA_IRQENABLE_CLR_2,Per-error event interrupt enable bit vector. line #2" bitfld.long 0x30 3. "MASTER_SRESPERR," "MASTER_SRESPERR_0,MASTER_SRESPERR_1" bitfld.long 0x30 2. "DIR_INTERLEAVE," "DIR_INTERLEAVE_0,DIR_INTERLEAVE_1" newline bitfld.long 0x30 1. "TRIGGER_TWICE," "TRIGGER_TWICE_0,TRIGGER_TWICE_1" bitfld.long 0x30 0. "COHERENCY_ERROR," "COHERENCY_ERROR_0,COHERENCY_ERROR_1" line.long 0x34 "VDMA_SYNCHR_LIST_LEVEL," bitfld.long 0x34 0.--3. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for breakdown logic to pick them from list) entries of synchronous transfer list" "LEVEL_0,LEVEL_1,LEVEL_2,LEVEL_3,LEVEL_4,LEVEL_5,LEVEL_6,LEVEL_7,LEVEL_8,LEVEL_9,LEVEL_10,LEVEL_11,LEVEL_12,LEVEL_13,LEVEL_14,LEVEL_15" line.long 0x38 "VDMA_ASYNCHR_LIST_LEVEL," bitfld.long 0x38 0.--3. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for breakdown logic to pick them from list) entries of asynchronous transfer list" "LEVEL_0,LEVEL_1,LEVEL_2,LEVEL_3,LEVEL_4,LEVEL_5,LEVEL_6,LEVEL_7,LEVEL_8,LEVEL_9,LEVEL_10,LEVEL_11,LEVEL_12,LEVEL_13,LEVEL_14,LEVEL_15" line.long 0x3C "VDMA_NON_DETERM_FIFO_LEVEL," hexmask.long.byte 0x3C 0.--7. 1. "LEVEL,Indicates number of pending (that is which have been pushed into and wait for read address generator to pick them from list) entries of nondeterministic object descriptor FIFO" line.long 0x40 "VDMA_TBA,TILER address mapping" bitfld.long 0x40 0.--2. "OCP_3MSB," "OCP_3MSB_0,OCP_3MSB_1,OCP_3MSB_2,OCP_3MSB_3,OCP_3MSB_4,OCP_3MSB_5,OCP_3MSB_6,OCP_3MSB_7" line.long 0x44 "VDMA_CONTEXT_STATUS,When individual bit is reset. corresponding context is available" bitfld.long 0x44 15. "CONTEXT15," "CONTEXT15_0,CONTEXT15_1" bitfld.long 0x44 14. "CONTEXT14," "CONTEXT14_0,CONTEXT14_1" newline bitfld.long 0x44 13. "CONTEXT13," "CONTEXT13_0,CONTEXT13_1" bitfld.long 0x44 12. "CONTEXT12," "CONTEXT12_0,CONTEXT12_1" newline bitfld.long 0x44 11. "CONTEXT11," "CONTEXT11_0,CONTEXT11_1" bitfld.long 0x44 10. "CONTEXT10," "CONTEXT10_0,CONTEXT10_1" newline bitfld.long 0x44 9. "CONTEXT9," "CONTEXT9_0,CONTEXT9_1" bitfld.long 0x44 8. "CONTEXT8," "CONTEXT8_0,CONTEXT8_1" newline bitfld.long 0x44 7. "CONTEXT7," "CONTEXT7_0,CONTEXT7_1" bitfld.long 0x44 6. "CONTEXT6," "CONTEXT6_0,CONTEXT6_1" newline bitfld.long 0x44 5. "CONTEXT5," "CONTEXT5_0,CONTEXT5_1" bitfld.long 0x44 4. "CONTEXT4," "CONTEXT4_0,CONTEXT4_1" newline bitfld.long 0x44 3. "CONTEXT3," "CONTEXT3_0,CONTEXT3_1" bitfld.long 0x44 2. "CONTEXT2," "CONTEXT2_0,CONTEXT2_1" newline bitfld.long 0x44 1. "CONTEXT1," "CONTEXT1_0,CONTEXT1_1" bitfld.long 0x44 0. "CONTEXT0," "CONTEXT0_0,CONTEXT0_1" line.long 0x48 "VDMA_GROUP_TRIGGER,Register entry for software user to trigger deterministic (only) groups through CPU writes" line.long 0x4C "VDMA_MAX_CONTEXT_SYNCHR,Software user configurable maximum number of context synchronous list can get benefit of" bitfld.long 0x4C 0.--3. "MAX_VALUE,(max_value + 1) is the actual number of context allocatable to synchronous list" "MAX_VALUE_0,MAX_VALUE_1,MAX_VALUE_2,MAX_VALUE_3,MAX_VALUE_4,MAX_VALUE_5,MAX_VALUE_6,MAX_VALUE_7,MAX_VALUE_8,MAX_VALUE_9,MAX_VALUE_10,MAX_VALUE_11,MAX_VALUE_12,MAX_VALUE_13,MAX_VALUE_14,MAX_VALUE_15" line.long 0x50 "VDMA_MAX_CONTEXT_ASYNCHR,Software user configurable maximum number of context asynchronous list can get benefit of" bitfld.long 0x50 0.--3. "MAX_VALUE,(max_value + 1) is the actual number of context allocatable to asynchronous list" "MAX_VALUE_0,MAX_VALUE_1,MAX_VALUE_2,MAX_VALUE_3,MAX_VALUE_4,MAX_VALUE_5,MAX_VALUE_6,MAX_VALUE_7,MAX_VALUE_8,MAX_VALUE_9,MAX_VALUE_10,MAX_VALUE_11,MAX_VALUE_12,MAX_VALUE_13,MAX_VALUE_14,MAX_VALUE_15" line.long 0x54 "VDMA_IRQ_NEOG,Sets whether end of group signaling should be set through external hardware lines (like the deterministic group triggers) or wrap into interrupt line" repeat 16. (list 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. ) tree "DMA_Channel_$1" group.long 0x1E1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_112,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_112,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_112,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_112,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1E0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_112,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1E00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_112,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_112,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_112,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x9C0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_112," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end repeat 16. (list 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. ) tree "DMA_Channel_$1" group.long 0x1C9C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_100,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C90++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_100,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_100,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_100,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1C8C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_100,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1C80++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_100,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_100,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_100,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x990++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_100," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end repeat 16. (list 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. ) tree "DMA_Channel_$1" group.long 0x1A1C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_80,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A10++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_80,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_80,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_80,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1A0C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_80,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1A00++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_80,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_80,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_80,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x940++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_80," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end repeat 16. (list 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. ) tree "DMA_Channel_$1" group.long 0x181C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_64,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1810++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_64,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_64,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_64,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x180C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_64,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1800++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_64,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_64,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_64,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x900++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_64," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. ) tree "DMA_Channel_$1" group.long 0x161C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_48,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1610++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_48,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_48,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_48,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x160C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_48,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1600++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_48,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_48,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_48,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x8C0++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_48," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. ) tree "DMA_Channel_$1" group.long 0x141C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_32,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1410++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_32,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_32,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_32,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x140C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_32,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1400++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_32,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_32,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_32,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x880++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_32," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end repeat 12. (list 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. ) tree "DMA_Channel_$1" group.long 0x148++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_20,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xC8++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_20," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x129C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_20,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1290++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_20,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_20,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_20,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x128C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_20,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1280++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_20,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_20,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_20,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x850++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_20," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end repeat 16. (list 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. ) tree "DMA_Channel_$1" group.long 0x120++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_10,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0xA0++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_10," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x115C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_10,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1150++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_10,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_10,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_10,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x114C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_10,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1140++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_10,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_10,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_10,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x828++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_10," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "DMA_Channel_$1" group.long 0xF8++0x03 line.long 0x00 "VDMA_GROUP_DEFINITION_j_0,Group_definition register set is the software user entry to define groups mapping and routing into and through event engine: - throw group into synchronous or asynchronous list - pick descriptors from nondeterministic or.." bitfld.long 0x00 13. "NON_DETERM_DETERM,Group is made of nondeterministic object descriptors when reset and of deterministic object descriptors when set" "0,1" bitfld.long 0x00 12. "ASYNCHR_SYNCHR,When reset indicates that this (these) group descriptor(s) are to be pushed into asynchronous transfer queue when set into synchronous transfer queue" "0,1" hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS,In case of deterministic transfers shall be the very first descriptor address of group" rgroup.long 0x78++0x03 line.long 0x00 "VDMA_GROUP_STATUS_j_0," bitfld.long 0x00 11. "LAST,When set means that last breakdown of last descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 10. "FIRST,When set means that first breakdown of first descriptor of group has been attributed to one context" "0,1" bitfld.long 0x00 5.--9. "PENDING_DATA_PROCESSING,Current number of data chunks (each of 128bytes max) that will require some data processing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "SERVICING_CONTEXTS,Number of contexts currently allocated to service this group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x101C++0x03 line.long 0x00 "VDMA_H_DETERM_127_96_i_0,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x1010++0x0B line.long 0x00 "VDMA_H_DETERM_31_0_i_0,Least significant 32b word of deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x04 "VDMA_H_DETERM_63_32_i_0,32b word positioned at bits [63..32] in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" line.long 0x08 "VDMA_H_DETERM_95_64_i_0,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of most significant 128b word of 256b descriptor" group.long 0x100C++0x03 line.long 0x00 "VDMA_L_DETERM_127_96_i_0,32b word positioned at bits 127 to 96 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x1000++0x0B line.long 0x00 "VDMA_L_DETERM_31_0_i_0,Least significant 32b word of deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x04 "VDMA_L_DETERM_63_32_i_0,32b word positioned at bits [63..32] in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" line.long 0x08 "VDMA_L_DETERM_95_64_i_0,32b word positioned at bits 95 to 64 in deterministic memory 128b word entry of least significant 128b word of 256b descriptor" group.long 0x178++0x03 line.long 0x00 "VDMA_NON_DETERM_k_0,Non deterministic descriptor FIFO width being 128b and configuration port width being 32b. four OCP write commands into four different (incremental) addresses to create one (short) nondeterministic descriptor" group.long 0x800++0x03 line.long 0x00 "VDMA_TRIGGER_COUNTER_i_0," hexmask.long.byte 0x00 8.--15. 1. "DESTINATION,Byte slot to write intended counter value to start with for the destination side of the transfer" hexmask.long.byte 0x00 0.--7. 1. "SOURCE,Byte slot to write intended counter value to start with for the source side of the transfer" tree.end repeat.end tree.end tree.end tree.open "Keyboard_Controller" tree "KBD" base ad:0x4AE1C000 rgroup.long 0x00++0x03 line.long 0x00 "KBD_REVISION,This register contains the IP revision code" group.long 0x10++0x03 line.long 0x00 "KBD_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x00 5. "EMUFREE,Emulation mode - module_frozen" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 3.--4. "IDLEMODE,Power Management req/ack control - force_idle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" group.long 0x1C++0x53 line.long 0x00 "KBD_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "LINE_NUMBER_0,LINE_NUMBER_1" line.long 0x04 "KBD_IRQSTATUS_RAW,Per-event raw interrupt status vector Raw status is set even if event is not enabled" bitfld.long 0x04 3. "MISS_EVENT,IRQ status for Miss event" "0,1" bitfld.long 0x04 2. "IT_TIMEOUT,IRQ status for Timeout" "0,1" bitfld.long 0x04 1. "IT_LONG_KEY,IRQ status for Long key" "0,1" newline bitfld.long 0x04 0. "IT_EVENT,IRQ status for Event" "0,1" line.long 0x08 "KBD_IRQSTATUS,Per-event 'enabled' interrupt status vector" bitfld.long 0x08 3. "MISS_EVENT,IRQ status for Miss event Read always returns zero" "MISS_EVENT_0,MISS_EVENT_1" bitfld.long 0x08 2. "IT_TIMEOUT,IRQ status for Timeout" "IT_TIMEOUT_0,IT_TIMEOUT_1" bitfld.long 0x08 1. "IT_LONG_KEY,IRQ status for Long key" "IT_LONG_KEY_0,IT_LONG_KEY_1" newline bitfld.long 0x08 0. "IT_EVENT,IRQ status for Event" "IT_EVENT_0,IT_EVENT_1" line.long 0x0C "KBD_IRQENABLE_SET,Per-event interrupt enable bit vector Write 1 to set (enable interrupt)" bitfld.long 0x0C 2. "IT_TIMEOUT_EN,IRQ enable for Timeout" "0,1" bitfld.long 0x0C 1. "IT_LONG_KEY_EN,IRQ enable for Long key" "0,1" bitfld.long 0x0C 0. "IT_EVENT_EN,IRQ enable for Event" "0,1" line.long 0x10 "KBD_IRQENABLE_CLR,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt)" bitfld.long 0x10 2. "IT_TIMEOUT_EN,IRQ enable for Timeout" "0,1" bitfld.long 0x10 1. "IT_LONG_KEY_EN,IRQ enable for Long key" "0,1" bitfld.long 0x10 0. "IT_EVENT_EN,IRQ enable for Event" "0,1" line.long 0x14 "KBD_IRQWAKEEN,The Keyboard Wake-up Enable Register allows the user to mask the expected source of wake-up event that will generate a wake-up request" bitfld.long 0x14 2. "WUP_TIMEOUT_ENA,Timeout wakeup enable" "WUP_TIMEOUT_ENA_0,WUP_TIMEOUT_ENA_1" bitfld.long 0x14 1. "WUP_LONG_KEY_ENA,Long key wakeup enable" "WUP_LONG_KEY_ENA_0,WUP_LONG_KEY_ENA_1" bitfld.long 0x14 0. "WUP_EVENT_ENA,Event wakeup enable" "WUP_EVENT_ENA_0,WUP_EVENT_ENA_1" line.long 0x18 "KBD_PENDING,The software must read the pending write bits to insure that following write access will not be discarded due to on going write synchronization process" bitfld.long 0x18 3. "PEND_TIMEOUT,Write pending bit forKBD_TIMEOUT register - PEND_TIMEOUT_1" "PEND_TIMEOUT_0_r,PEND_TIMEOUT_1_r" bitfld.long 0x18 2. "PEND_LONG_KEY,Write pending bit forKBD_KEYLONGTIME register - PEND_LONGKEY_1" "PEND_LONG_KEY_0_r,PEND_LONG_KEY_1_r" bitfld.long 0x18 1. "PEND_DEBOUNCING,Write pending bit forKBD_DEBOUNCINGTIME register - PEND_DEBOUNCING_1" "PEND_DEBOUNCING_0_r,PEND_DEBOUNCING_1_r" newline bitfld.long 0x18 0. "PEND_CTRL,Write pending bit forKBD_CTRL register - PEND_CTRL_1" "PEND_CTRL_0_r,PEND_CTRL_1_r" line.long 0x1C "KBD_CTRL,This register sets the functional configuration of the module" bitfld.long 0x1C 8. "REPEAT_MODE,Repeat mode enable" "REPEAT_MODE_0,REPEAT_MODE_1" bitfld.long 0x1C 7. "TIMEOUT_LONG_KEY,Timeout long key mode enable" "TIMEOUT_LONG_KEY_0,TIMEOUT_LONG_KEY_1" bitfld.long 0x1C 6. "TIMEOUT_EMPTY,Timeout empty mode enable" "TIMEOUT_EMPTY_0,TIMEOUT_EMPTY_1" newline bitfld.long 0x1C 5. "LONG_KEY,Long key mode enable" "LONG_KEY_0,LONG_KEY_1" bitfld.long 0x1C 2.--4. "PTV,Pre-scale clock timer value" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" bitfld.long 0x1C 1. "NSOFTWARE_MODE,Select hardware or software mode for key decoding" "NSOFTWARE_MODE_0,NSOFTWARE_MODE_1" line.long 0x20 "KBD_DEBOUNCINGTIME,This register is used to filter glitches on the press key or release key" bitfld.long 0x20 0.--5. "DEBOUNCING_VALUE,This value correspond to the desired value of debouncing time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "KBD_KEYLONGTIME,This register is used to measure duration of a key press. to allow. shortcut detection" hexmask.long.word 0x24 0.--11. 1. "LONG_KEY_VALUE,This value correspond to the desired value of the long key interrupt or repeat mode value" line.long 0x28 "KBD_TIMEOUT,This register is used to detect a long inactivity on the keyboard" hexmask.long.word 0x28 0.--15. 1. "TIMEOUT_VALUE,This value correspond to the desired value of the time out interrupt" line.long 0x2C "KBD_STATEMACHINE,This register indicates the state of the sequencer" bitfld.long 0x2C 0.--3. "STATE_MACHINE,The state of internal state machine" "STATE_MACHINE_0,STATE_MACHINE_1,STATE_MACHINE_2,STATE_MACHINE_3,STATE_MACHINE_4,STATE_MACHINE_5,STATE_MACHINE_6,STATE_MACHINE_7,STATE_MACHINE_8,STATE_MACHINE_9,STATE_MACHINE_10,STATE_MACHINE_11,STATE_MACHINE_12,STATE_MACHINE_13,STATE_MACHINE_14,STATE_MACHINE_15" line.long 0x30 "KBD_ROWINPUTS,This register stores the value of the rows input" hexmask.long.word 0x30 0.--8. 1. "KBR_LATCH,The value of the rows input" line.long 0x34 "KBD_COLUMNOUTPUTS,This register holds the value of the columns output" hexmask.long.word 0x34 0.--8. 1. "KBC_REG,The value of the columns output" line.long 0x38 "KBD_FULLCODE31_0,The register codes the row 0. row 1. row 2 and row 3" line.long 0x3C "KBD_FULLCODE63_32,The register codes the row 4. row 5. row 6 and row 7" line.long 0x40 "KBD_FULLCODE17_0,The register codes the row 0 and row 1" hexmask.long.word 0x40 16.--24. 1. "ROW1,A bit at one indicate that the corresponding key is pressed" hexmask.long.word 0x40 0.--8. 1. "ROW0,A bit at one indicate that the corresponding key is pressed" line.long 0x44 "KBD_FULLCODE35_18,The register codes the row 2 and row 3" hexmask.long.word 0x44 16.--24. 1. "ROW3,A bit at one indicate that the corresponding key is pressed" hexmask.long.word 0x44 0.--8. 1. "ROW2,A bit at one indicate that the corresponding key is pressed" line.long 0x48 "KBD_FULLCODE53_36,The register codes the row 4 and row 5" hexmask.long.word 0x48 16.--24. 1. "ROW5,A bit at one indicate that the corresponding key is pressed" hexmask.long.word 0x48 0.--8. 1. "ROW4,A bit at one indicate that the corresponding key is pressed" line.long 0x4C "KBD_FULLCODE71_54,The register codes the row 6 and row 7" hexmask.long.word 0x4C 16.--24. 1. "ROW7,A bit at one indicate that the corresponding key is pressed" hexmask.long.word 0x4C 0.--8. 1. "ROW6,A bit at one indicate that the corresponding key is pressed" line.long 0x50 "KBD_FULLCODE80_72,The register codes the row 8" hexmask.long.word 0x50 0.--8. 1. "ROW8,A bit at one indicate that the corresponding key is pressed" tree.end tree.end tree.open "L3_MAIN_Interconnect" tree "CLK1_2_BB2D_P1_BW_LIMITER" base ad:0x44805900 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_BB2D_P2_BW_LIMITER" base ad:0x44805A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_GPU_P1_BW_LIMITER" base ad:0x44805B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_GPU_P2_BW_LIMITER" base ad:0x44805C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_MMU1_BW_LIMITER" base ad:0x44803A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_TPTC1_RD_BW_LIMITER" base ad:0x44803C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_TPTC1_WR_BW_LIMITER" base ad:0x44803E00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_TPTC2_RD_BW_LIMITER" base ad:0x44803D00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_TPTC2_WR_BW_LIMITER" base ad:0x44803F00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_VPE_P1_BW_LIMITER" base ad:0x44804100 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_VPE_P2_BW_LIMITER" base ad:0x44804000 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_LIMITER_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL," bitfld.long 0x08 0.--4. "BANDWIDTH_FRACTIONAL,Fractional part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "L3_BW_LIMITER_BANDWIDTH_INTEGER," bitfld.long 0x0C 0.--3. "BANDWIDTH_INTEGER,Integer part of bandwitdh in terms of bytes per second Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_BW_LIMITER_WATERMARK_0," hexmask.long.word 0x10 0.--13. 1. "WATERMARK_0,Peak bandwidth allowed Type: Control" line.long 0x14 "L3_BW_LIMITER_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_BB2D_P1_BW_REGULATOR" base ad:0x4480E000 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_BB2D_P2_BW_REGULATOR" base ad:0x44805100 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_DSP1_EDMA_BW_REGULATOR" base ad:0x44804B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_DSP1_MDMA_BW_REGULATOR" base ad:0x44804C00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_DSP2_EDMA_BW_REGULATOR" base ad:0x44804A00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_DSP2_MDMA_BW_REGULATOR" base ad:0x44804D00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_EVE1_TC0_BW_REGULATOR" base ad:0x44804200 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_EVE1_TC1_BW_REGULATOR" base ad:0x44804600 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_EVE2_TC0_BW_REGULATOR" base ad:0x44804300 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_EVE2_TC1_BW_REGULATOR" base ad:0x44804700 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_GMAC_SW_BW_REGULATOR" base ad:0x44805600 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_GPU_P1_BW_REGULATOR" base ad:0x44805200 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_GPU_P2_BW_REGULATOR" base ad:0x44805300 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_IVA_BW_REGULATOR" base ad:0x44805000 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_MMU2_BW_REGULATOR" base ad:0x44803B00 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_PCIESS1_BW_REGULATOR" base ad:0x44805500 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_2_PCIESS2_BW_REGULATOR" base ad:0x44805400 rgroup.long 0x00++0x17 line.long 0x00 "L3_BW_REGULATOR_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_BW_REGULATOR_BANDWIDTH," hexmask.long.word 0x08 0.--15. 1. "BANDWIDTH,Bandwidth in bytes per second" line.long 0x0C "L3_BW_REGULATOR_WATERMARK," hexmask.long.word 0x0C 0.--11. 1. "WATERMARK,Peak permissible bandwidth in bytes" line.long 0x10 "L3_BW_REGULATOR_PRESS," bitfld.long 0x10 1. "PRESS_LOW,Pressure value inserted if the measured bandwidth is over the watermark" "0,1" bitfld.long 0x10 0. "PRESS_HIGH,Pressure value inserted if the measured bandwidth is under the watermark" "0,1" line.long 0x14 "L3_BW_REGULATOR_CLEARHISTORY," bitfld.long 0x14 0. "CLEARHISTORY,Write a 1 clear the traffic counter Type: Give_AutoCleared" "0,1" tree.end tree "CLK1_FLAGMUX_CLK1" base ad:0x44000000 rgroup.long 0x805700++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT1_MASK0," hexmask.long 0x08 0.--24. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_TIMEOUT1_REGERR0," hexmask.long 0x0C 0.--24. 1. "REGERR0,flag inputs 0 Type: Status" rgroup.long 0x805800++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT2_MASK0," hexmask.long.tbyte 0x08 0.--20. 1. "MASK0,mask flag inputs 0 Type: Control" line.long 0x0C "L3_FLAGMUX_TIMEOUT2_REGERR0," hexmask.long.tbyte 0x0C 0.--20. 1. "REGERR0,flag inputs 0 Type: Status" tree.end repeat 2. (list 1. 2. )(list ad:0x44803500 ad:0x44803600 ) tree "CLK1_FLAGMUX_CLK1_$1" base $2 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," line.long 0x14 "L3_FLAGMUX_REGERR1," tree.end repeat.end tree "CLK2_FLAGMUX_CLK2_1" base ad:0x45000200 rgroup.long 0x00++0x17 line.long 0x00 "L3_FLAGMUX_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_MASK0," line.long 0x0C "L3_FLAGMUX_REGERR0," line.long 0x10 "L3_FLAGMUX_MASK1," line.long 0x14 "L3_FLAGMUX_REGERR1," tree.end tree "CLK1_FLAGMUX_CLK1MERGE" base ad:0x44000000 rgroup.long 0x800400++0x07 line.long 0x00 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" repeat 2. (list 0. 1. )(list 0x00 0x08 ) group.long ($2+0x80040C)++0x03 line.long 0x00 "L3_FLAGMUX_CLK1MERGE_REGERR$1," bitfld.long 0x00 0.--1. "REGERR0,Mask flag inputs 0 Type: Control" "0,1,2,3" repeat.end repeat 2. (list 0. 1. )(list 0x00 0x08 ) group.long ($2+0x800408)++0x03 line.long 0x00 "L3_FLAGMUX_CLK1MERGE_MASK$1," bitfld.long 0x00 0.--1. "MASK0,Mask flag inputs 0 Type: Control" "0,1,2,3" repeat.end tree.end repeat 2. (list 1. 2. )(list ad:0x44000000 ad:0x44800000 ) tree "CLK1_HOST_CLK1_$1" base $2 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" tree.end repeat.end tree "CLK2_HOST_CLK2_1" base ad:0x45000000 rgroup.long 0x00++0x0B line.long 0x00 "L3_HOST_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_HOST_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_HOST_STDHOSTHDR_MAINCTLREG," bitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Fault is asserted when the Fault Control register field indicates a Fault and de-asserted when FltCnt is reset" "0,1" group.long 0x40++0x37 line.long 0x00 "L3_HOST_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_HOST_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_HOST_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_HOST_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_HOST_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_HOST_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_HOST_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_HOST_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,Type: Status" line.long 0x28 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Type: Status" line.long 0x2C "L3_HOST_STDERRLOG_CUSTOMINFO_WR," bitfld.long 0x2C 0. "STDERRLOG_CUSTOMINFO_WR,Type: Status" "0,1" line.long 0x30 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR," hexmask.long.tbyte 0x30 0.--20. 1. "STDERRLOG_CUSTOMINFO_ADDR,Type: Status" line.long 0x34 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR," bitfld.long 0x34 0. "STDERRLOG_CUSTOMINFO_DECERR,Type: Status" "0,1" tree.end tree "CLK2_FLAGMUX_CLK2" base ad:0x45000000 rgroup.long 0x400++0x0F line.long 0x00 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constantreporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constantreporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constantreporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_FLAGMUX_TIMEOUT_MASK0," bitfld.long 0x08 0.--1. "MASK0,mask flag inputs 0 Type: Control" "0,1,2,3" line.long 0x0C "L3_FLAGMUX_TIMEOUT_REGERR0," bitfld.long 0x0C 0.--1. "REGERR0,flag inputs 0 Type: Status" "0,1,2,3" tree.end tree "CLK2_STATCOLL0" base ad:0x45001000 group.long 0x00++0x8B line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_EN," bitfld.long 0x08 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" line.long 0x0C "L3_STCOL_SOFTEN," bitfld.long 0x0C 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" line.long 0x10 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x10 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" line.long 0x14 "L3_STCOL_TRIGEN," bitfld.long 0x14 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" line.long 0x18 "L3_STCOL_REQEVT," bitfld.long 0x18 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x1C "L3_STCOL_RSPEVT," bitfld.long 0x1C 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" line.long 0x20 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x20 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x24 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x24 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x28 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x28 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x2C "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x2C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x30 "L3_STCOL_EVTMUX_SEL4," bitfld.long 0x30 0.--2. "EVTMUX_SEL4,The select of the mux 4 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x34 "L3_STCOL_EVTMUX_SEL5," bitfld.long 0x34 0.--2. "EVTMUX_SEL5,The select of the mux 5 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x38 "L3_STCOL_EVTMUX_SEL6," bitfld.long 0x38 0.--2. "EVTMUX_SEL6,The select of the mux 6 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x3C "L3_STCOL_EVTMUX_SEL7," bitfld.long 0x3C 0.--2. "EVTMUX_SEL7,The select of the mux 7 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x40 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x40 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "L3_STCOL_DUMP_COLLECTTIME," line.long 0x48 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x48 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" line.long 0x4C "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x4C 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" line.long 0x50 "L3_STCOL_DUMP_SLVOFS," line.long 0x54 "L3_STCOL_DUMP_MODE," bitfld.long 0x54 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x54 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" line.long 0x58 "L3_STCOL_DUMP_SEND," bitfld.long 0x58 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" line.long 0x5C "L3_STCOL_DUMP_DISABLE," bitfld.long 0x5C 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" line.long 0x60 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x60 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" line.long 0x64 "L3_STCOL_DUMP_ALARM_MINVAL," line.long 0x68 "L3_STCOL_DUMP_ALARM_MAXVAL," line.long 0x6C "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x6C 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x70 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x70 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x74 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x74 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x78 "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x78 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" line.long 0x7C "L3_STCOL_DUMP_ALARM_MODE4," bitfld.long 0x7C 0.--1. "DUMP_ALARM_MODE4,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE4_0,DUMP_ALARM_MODE4_1,DUMP_ALARM_MODE4_2,DUMP_ALARM_MODE4_3" line.long 0x80 "L3_STCOL_DUMP_ALARM_MODE5," bitfld.long 0x80 0.--1. "DUMP_ALARM_MODE5,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE5_0,DUMP_ALARM_MODE5_1,DUMP_ALARM_MODE5_2,DUMP_ALARM_MODE5_3" line.long 0x84 "L3_STCOL_DUMP_ALARM_MODE6," bitfld.long 0x84 0.--1. "DUMP_ALARM_MODE6,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE6_0,DUMP_ALARM_MODE6_1,DUMP_ALARM_MODE6_2,DUMP_ALARM_MODE6_3" line.long 0x88 "L3_STCOL_DUMP_ALARM_MODE7," bitfld.long 0x88 0.--1. "DUMP_ALARM_MODE7,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE7_0,DUMP_ALARM_MODE7_1,DUMP_ALARM_MODE7_2,DUMP_ALARM_MODE7_3" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_USERINFO_0," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MASK_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xF4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_0," hexmask.long.tbyte 0x00 0.--17. 1. "FILTER_i_MATCH_m_USERINFO,Mask/Match of UserInfo Type: Control" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end repeat.end tree.end tree "CLK2_STATCOLL1" base ad:0x45002000 group.long 0x00++0x37 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_EN," bitfld.long 0x08 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" line.long 0x0C "L3_STCOL_SOFTEN," bitfld.long 0x0C 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" line.long 0x10 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x10 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" line.long 0x14 "L3_STCOL_TRIGEN," bitfld.long 0x14 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" line.long 0x18 "L3_STCOL_REQEVT," bitfld.long 0x18 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x1C "L3_STCOL_RSPEVT," bitfld.long 0x1C 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" line.long 0x20 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x20 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x24 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x24 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x28 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x28 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x2C "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x2C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x30 "L3_STCOL_EVTMUX_SEL4," bitfld.long 0x30 0.--2. "EVTMUX_SEL4,The select of the mux 4 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x34 "L3_STCOL_EVTMUX_SEL5," bitfld.long 0x34 0.--2. "EVTMUX_SEL5,The select of the mux 5 Type: Control" "0,1,2,3,4,5,6,7" rgroup.long 0x40++0x43 line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "L3_STCOL_DUMP_COLLECTTIME," line.long 0x08 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x08 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" line.long 0x0C "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x0C 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" line.long 0x10 "L3_STCOL_DUMP_SLVOFS," line.long 0x14 "L3_STCOL_DUMP_MODE," bitfld.long 0x14 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x14 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" line.long 0x18 "L3_STCOL_DUMP_SEND," bitfld.long 0x18 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" line.long 0x1C "L3_STCOL_DUMP_DISABLE," bitfld.long 0x1C 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" line.long 0x20 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x20 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" line.long 0x24 "L3_STCOL_DUMP_ALARM_MINVAL," line.long 0x28 "L3_STCOL_DUMP_ALARM_MAXVAL," line.long 0x2C "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x2C 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x30 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x30 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x34 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x34 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x38 "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x38 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" line.long 0x3C "L3_STCOL_DUMP_ALARM_MODE4," bitfld.long 0x3C 0.--1. "DUMP_ALARM_MODE4,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE4_0,DUMP_ALARM_MODE4_1,DUMP_ALARM_MODE4_2,DUMP_ALARM_MODE4_3" line.long 0x40 "L3_STCOL_DUMP_ALARM_MODE5," bitfld.long 0x40 0.--1. "DUMP_ALARM_MODE5,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE5_0,DUMP_ALARM_MODE5_1,DUMP_ALARM_MODE5_2,DUMP_ALARM_MODE5_3" repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end repeat 6. (list 0. 1. 2. 3. 4. 5. ) tree "Channel_$1" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xF4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end repeat.end tree.end repeat 6. (list 2. 4. 6. 7. 8. 9. )(list ad:0x45003000 ad:0x45005000 ad:0x45007000 ad:0x45008000 ad:0x45009000 ad:0x4500A000 ) tree "CLK2_STATCOLL$1" base $2 group.long 0x00++0x2F line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_EN," bitfld.long 0x08 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" line.long 0x0C "L3_STCOL_SOFTEN," bitfld.long 0x0C 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" line.long 0x10 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x10 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" line.long 0x14 "L3_STCOL_TRIGEN," bitfld.long 0x14 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" line.long 0x18 "L3_STCOL_REQEVT," bitfld.long 0x18 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x1C "L3_STCOL_RSPEVT," bitfld.long 0x1C 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" line.long 0x20 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x20 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x24 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x24 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x28 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x28 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x2C "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x2C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" rgroup.long 0x40++0x3B line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "L3_STCOL_DUMP_COLLECTTIME," line.long 0x08 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x08 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" line.long 0x0C "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x0C 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" line.long 0x10 "L3_STCOL_DUMP_SLVOFS," line.long 0x14 "L3_STCOL_DUMP_MODE," bitfld.long 0x14 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x14 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" line.long 0x18 "L3_STCOL_DUMP_SEND," bitfld.long 0x18 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" line.long 0x1C "L3_STCOL_DUMP_DISABLE," bitfld.long 0x1C 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" line.long 0x20 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x20 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" line.long 0x24 "L3_STCOL_DUMP_ALARM_MINVAL," line.long 0x28 "L3_STCOL_DUMP_ALARM_MAXVAL," line.long 0x2C "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x2C 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x30 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x30 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x34 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x34 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x38 "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x38 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xF4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end repeat.end tree.end repeat.end tree "CLK2_STATCOLL3" base ad:0x45004000 group.long 0x00++0x8B line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_EN," bitfld.long 0x08 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" line.long 0x0C "L3_STCOL_SOFTEN," bitfld.long 0x0C 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" line.long 0x10 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x10 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" line.long 0x14 "L3_STCOL_TRIGEN," bitfld.long 0x14 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" line.long 0x18 "L3_STCOL_REQEVT," bitfld.long 0x18 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x1C "L3_STCOL_RSPEVT," bitfld.long 0x1C 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" line.long 0x20 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x20 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x24 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x24 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x28 "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x28 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x2C "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x2C 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x30 "L3_STCOL_EVTMUX_SEL4," bitfld.long 0x30 0.--2. "EVTMUX_SEL4,The select of the mux 4 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x34 "L3_STCOL_EVTMUX_SEL5," bitfld.long 0x34 0.--2. "EVTMUX_SEL5,The select of the mux 5 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x38 "L3_STCOL_EVTMUX_SEL6," bitfld.long 0x38 0.--2. "EVTMUX_SEL6,The select of the mux 6 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x3C "L3_STCOL_EVTMUX_SEL7," bitfld.long 0x3C 0.--2. "EVTMUX_SEL7,The select of the mux 7 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x40 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x40 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x44 "L3_STCOL_DUMP_COLLECTTIME," line.long 0x48 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x48 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" line.long 0x4C "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x4C 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" line.long 0x50 "L3_STCOL_DUMP_SLVOFS," line.long 0x54 "L3_STCOL_DUMP_MODE," bitfld.long 0x54 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x54 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" line.long 0x58 "L3_STCOL_DUMP_SEND," bitfld.long 0x58 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" line.long 0x5C "L3_STCOL_DUMP_DISABLE," bitfld.long 0x5C 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" line.long 0x60 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x60 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" line.long 0x64 "L3_STCOL_DUMP_ALARM_MINVAL," line.long 0x68 "L3_STCOL_DUMP_ALARM_MAXVAL," line.long 0x6C "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x6C 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x70 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x70 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x74 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x74 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x78 "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x78 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" line.long 0x7C "L3_STCOL_DUMP_ALARM_MODE4," bitfld.long 0x7C 0.--1. "DUMP_ALARM_MODE4,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE4_0,DUMP_ALARM_MODE4_1,DUMP_ALARM_MODE4_2,DUMP_ALARM_MODE4_3" line.long 0x80 "L3_STCOL_DUMP_ALARM_MODE5," bitfld.long 0x80 0.--1. "DUMP_ALARM_MODE5,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE5_0,DUMP_ALARM_MODE5_1,DUMP_ALARM_MODE5_2,DUMP_ALARM_MODE5_3" line.long 0x84 "L3_STCOL_DUMP_ALARM_MODE6," bitfld.long 0x84 0.--1. "DUMP_ALARM_MODE6,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE6_0,DUMP_ALARM_MODE6_1,DUMP_ALARM_MODE6_2,DUMP_ALARM_MODE6_3" line.long 0x88 "L3_STCOL_DUMP_ALARM_MODE7," bitfld.long 0x88 0.--1. "DUMP_ALARM_MODE7,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE7_0,DUMP_ALARM_MODE7_1,DUMP_ALARM_MODE7_2,DUMP_ALARM_MODE7_3" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xF4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end repeat.end tree.end tree "CLK2_STATCOLL5" base ad:0x45006000 group.long 0x00++0x07 line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" group.long 0x0C++0x23 line.long 0x00 "L3_STCOL_SOFTEN," bitfld.long 0x00 0. "SOFTEN,Software enable for performance monitoring Type: Control" "0,1" line.long 0x04 "L3_STCOL_IGNORESUSPEND," bitfld.long 0x04 0. "IGNORESUSPEND,Ignore suspend if set to one for suspend mechanism Type: Control" "0,1" line.long 0x08 "L3_STCOL_TRIGEN," bitfld.long 0x08 0. "TRIGEN,TrigEn when set it enable the external trigger start and stop Type: Control" "0,1" line.long 0x0C "L3_STCOL_REQEVT," bitfld.long 0x0C 0.--3. "REQEVT,Req event select Type: Control" "REQEVT_0,REQEVT_1,REQEVT_2,REQEVT_3,REQEVT_4,REQEVT_5,REQEVT_6,REQEVT_7,REQEVT_8,?,?,?,?,?,?,?" line.long 0x10 "L3_STCOL_RSPEVT," bitfld.long 0x10 0.--3. "RSPEVT,Rsp event select Type: Control" "RSPEVT_0,RSPEVT_1,RSPEVT_2,RSPEVT_3,RSPEVT_4,RSPEVT_5,RSPEVT_6,RSPEVT_7,RSPEVT_8,?,?,?,?,?,?,?" line.long 0x14 "L3_STCOL_EVTMUX_SEL0," bitfld.long 0x14 0.--2. "EVTMUX_SEL0,The select of the mux 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x18 "L3_STCOL_EVTMUX_SEL1," bitfld.long 0x18 0.--2. "EVTMUX_SEL1,The select of the mux 1 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x1C "L3_STCOL_EVTMUX_SEL2," bitfld.long 0x1C 0.--2. "EVTMUX_SEL2,The select of the mux 2 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x20 "L3_STCOL_EVTMUX_SEL3," bitfld.long 0x20 0.--2. "EVTMUX_SEL3,The select of the mux 3 Type: Control" "0,1,2,3,4,5,6,7" rgroup.long 0x40++0x3B line.long 0x00 "L3_STCOL_DUMP_IDENTIFIER," bitfld.long 0x00 0.--3. "DUMP_IDENTIFIER,Probe identifier Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "L3_STCOL_DUMP_COLLECTTIME," line.long 0x08 "L3_STCOL_DUMP_SLVADDR," hexmask.long.byte 0x08 0.--6. 1. "DUMP_SLVADDR,Dump slave address Type: Control" line.long 0x0C "L3_STCOL_DUMP_MSTADDR," hexmask.long.byte 0x0C 0.--7. 1. "DUMP_MSTADDR,Dump master address Type: Control" line.long 0x10 "L3_STCOL_DUMP_SLVOFS," line.long 0x14 "L3_STCOL_DUMP_MODE," bitfld.long 0x14 1. "DUMP_MODE_CONDITIONAL,Define the stat conditional dump if one a dump will be generated when alarm is trigged Type: Control" "0,1" newline bitfld.long 0x14 0. "DUMP_MODE_MANUAL,Define the dump mode: if != 0 the dump is controlled by the Send register" "0,1" line.long 0x18 "L3_STCOL_DUMP_SEND," bitfld.long 0x18 0. "DUMP_SEND,In manual mode is used to send the dump content and initialize the counters" "0,1" line.long 0x1C "L3_STCOL_DUMP_DISABLE," bitfld.long 0x1C 0. "DUMP_DISABLE,If 1 the dump frame will be disabled but counters still active.This is typically used when counters monitoring is enabled Type: Control" "0,1" line.long 0x20 "L3_STCOL_DUMP_ALARM_TRIG," bitfld.long 0x20 0. "DUMP_ALARM_TRIG,In Alarm Mode is used to reset Alarm Type: Take" "0,1" line.long 0x24 "L3_STCOL_DUMP_ALARM_MINVAL," line.long 0x28 "L3_STCOL_DUMP_ALARM_MAXVAL," line.long 0x2C "L3_STCOL_DUMP_ALARM_MODE0," bitfld.long 0x2C 0.--1. "DUMP_ALARM_MODE0,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE0_0,DUMP_ALARM_MODE0_1,DUMP_ALARM_MODE0_2,DUMP_ALARM_MODE0_3" line.long 0x30 "L3_STCOL_DUMP_ALARM_MODE1," bitfld.long 0x30 0.--1. "DUMP_ALARM_MODE1,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE1_0,DUMP_ALARM_MODE1_1,DUMP_ALARM_MODE1_2,DUMP_ALARM_MODE1_3" line.long 0x34 "L3_STCOL_DUMP_ALARM_MODE2," bitfld.long 0x34 0.--1. "DUMP_ALARM_MODE2,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE2_0,DUMP_ALARM_MODE2_1,DUMP_ALARM_MODE2_2,DUMP_ALARM_MODE2_3" line.long 0x38 "L3_STCOL_DUMP_ALARM_MODE3," bitfld.long 0x38 0.--1. "DUMP_ALARM_MODE3,Alarm Mode off/min/max/both Type: Control" "DUMP_ALARM_MODE3_0,DUMP_ALARM_MODE3_1,DUMP_ALARM_MODE3_2,DUMP_ALARM_MODE3_3" group.long 0x40B05B008++0x03 line.long 0x00 "L3_STCOL_EN," bitfld.long 0x00 0. "EN,Enable performance monitoring this will also shut down the clock if En = 0 Type: Control" "0,1" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0x8C)++0x03 line.long 0x00 "L3_STCOL_DUMP_CNT$1," repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" group.long 0xB8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDREN_0," bitfld.long 0x00 0. "FILTER0_ADDREN,max filtering enable Type: Control" "0,1" group.long 0xB4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMAX_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMAX,Max addr range Type: Control" group.long 0xB0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_ADDRMIN_0," hexmask.long.tbyte 0x00 0.--22. 1. "FILTER0_ADDRMIN,Min addr range Type: Control" group.long 0xBC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_EN_k_0," bitfld.long 0x00 0. "FILTER_i_EN0,Enable filter stage 0 Type: Control" "0,1" group.long 0xAC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_GLOBALEN_0," bitfld.long 0x00 0. "FILTER_i_GLOBALEN,Filter global enable Type: Control" "0,1" group.long 0xD0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xC8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MASK_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xC0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0xD4++0x07 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" line.long 0x04 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0," bitfld.long 0x04 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xCC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0," hexmask.long.byte 0x00 0.--6. 1. "FILTER_i_MASK_m_SLVADDR,Mask/Match of SlvAddr Type: Control" group.long 0xC4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MASK_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MASK_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0xF0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_ERR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_ERR,Mask/Match of Err Type: Control" "0,1" group.long 0xE8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0," hexmask.long.byte 0x00 0.--7. 1. "FILTER_i_MATCH_m_MSTADDR,Mask/Match of MstAddr Type: Control" group.long 0xE0++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RD_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_RD,Mask/Match of Rd Type: Control" "0,1" group.long 0x40B0200F4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0," hexmask.long 0x00 0.--27. 1. "FILTER_i_MASK_m_REQUSERINFO,Mask/Match of ReqUserInfo Type: Control" group.long 0xF8++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0," bitfld.long 0x00 0.--2. "FILTER_i_MASK_m_RSPUSERINFO,Mask/Match of RspUserInfo Type: Control" "0,1,2,3,4,5,6,7" group.long 0xEC++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0," bitfld.long 0x00 0.--4. "FILTER0_MATCH0_SLVADDR,Mask/Match of SlvAddr Type: Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE4++0x03 line.long 0x00 "L3_STCOL_FILTER_i_MATCH_m_WR_0," bitfld.long 0x00 0. "FILTER_i_MATCH_m_WR,Mask/Match of Wr Type: Control" "0,1" group.long 0x1F8++0x07 line.long 0x00 "L3_STCOL_OP_i_EVTINFOSEL_0," bitfld.long 0x00 0.--1. "OP_i_EVTINFOSEL,Select event info data to add to counter (len/press or latency) Type: Control" "OP_i_EVTINFOSEL_0,OP_i_EVTINFOSEL_1,OP_i_EVTINFOSEL_2,?" line.long 0x04 "L3_STCOL_OP_i_SEL_0," bitfld.long 0x04 0.--3. "OP_i_SEL,Select logical operation Type: Control" "OP_i_SEL_0,OP_i_SEL_1,OP_i_SEL_2,OP_i_SEL_3,OP_i_SEL_4,OP_i_SEL_5,OP_i_SEL_6,OP_i_SEL_7,OP_i_SEL_8,?,?,?,?,?,?,?" group.long 0x1F4++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MAXVAL,Max value Type: Control" group.long 0x1F0++0x03 line.long 0x00 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0," hexmask.long.word 0x00 0.--12. 1. "OP_i_THRESHOLD_MINVAL,Min value Type: Control" tree.end repeat.end tree.end tree "CLK3_FLAGMUX_STATCOLL" base ad:0x45000500 group.long 0x00++0x0F line.long 0x00 "L3_STCOL_STDHOSTHDR_COREREG," rbitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0. "STDHOSTHDR_COREREG_VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_VENDORCODE_0_r,STDHOSTHDR_COREREG_VENDORCODE_1_r" line.long 0x04 "L3_STCOL_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_STCOL_MASK0," bitfld.long 0x08 0.--2. "MASK0,mask flag inputs 0 Type: Control" "0,1,2,3,4,5,6,7" line.long 0x0C "L3_STCOL_REGERR0," bitfld.long 0x0C 0.--2. "REGERR0,flag inputs 0 Type: Status" "0,1,2,3,4,5,6,7" tree.end tree "EMIF_FW" base ad:0x4A20C000 tree "Channel_0" group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k_0,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" newline bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" newline bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" newline bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end repeat 6. (list 2. 3. 4. 5. 6. 7. ) tree "REG_Bundle_$1" group.long 0xA4++0x03 line.long 0x00 "END_REGION_i_2,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0xAC++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0xA8++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0xA0++0x03 line.long 0x00 "START_REGION_i_2,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x10++0x07 line.long 0x00 "ERROR_LOG_k_1,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "BB2D_FW" base ad:0x4A21A000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "DEBUGSS_CT_TBR_FW" base ad:0x4A224000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "DSP1_SDMA_FW" base ad:0x4A171000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "DSP2_SDMA_FW" base ad:0x4A173000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "EDMA_TPCC_FW" base ad:0x4A161000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "EVE1_FW" base ad:0x4A151000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "EVE2_FW" base ad:0x4A153000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "GPU_FW" base ad:0x4A214000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "IVA_CONFIG_FW" base ad:0x4A220000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "L3_INSTR_FW" base ad:0x4A226000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "MCASP1_FW" base ad:0x4A167000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "MCASP2_FW" base ad:0x4A169000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "MCASP3_FW" base ad:0x4A16B000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "VCP1_FW" base ad:0x4A15D000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "VCP2_FW" base ad:0x4A15F000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" group.long 0x88++0x07 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" line.long 0x04 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x04 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x04 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x04 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x04 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x04 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x04 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x04 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x04 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x04 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x04 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x04 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x04 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x04 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x04 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x04 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x04 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x04 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x04 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x04 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x04 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x04 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x04 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x04 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x04 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x04 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x04 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x04 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x04 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x04 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x04 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x04 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x04 0. "R0,Master NIU ConnID = 0 read permission" "0,1" tree.end tree "BB2D_TARG" base ad:0x44000900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "DEBUGSS_CT_TBR_TARG" base ad:0x45000300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "DMM_P1_TARG" base ad:0x44000200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "DMM_P2_TARG" base ad:0x44001300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "DSP1_SDMA_TARG" base ad:0x44000300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "DSP2_SDMA_TARG" base ad:0x44000600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "DSS_TARG" base ad:0x44002900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "EVE1_TARG" base ad:0x44000A00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "EVE2_TARG" base ad:0x44000B00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "GPMC_TARG" base ad:0x44000100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "GPU_TARG" base ad:0x44001200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "IPU1_TARG" base ad:0x44001000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "IPU2_TARG" base ad:0x44001100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "IVA_CONFIG_TARG" base ad:0x44001600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "IVA_SL2IF_TARG" base ad:0x44001800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L3_INSTR" base ad:0x45000100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_CFG_TARG" base ad:0x44000500 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER1_P1_TARG" base ad:0x44001C00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER1_P2_TARG" base ad:0x44001F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER1_P3_TARG" base ad:0x44002100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER2_P1_TARG" base ad:0x44002300 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER2_P2_TARG" base ad:0x44002400 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER2_P3_TARG" base ad:0x44002500 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER3_P1_TARG" base ad:0x44002600 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER3_P2_TARG" base ad:0x44002700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_PER3_P3_TARG" base ad:0x44000E00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "L4_WKUP_TARG" base ad:0x44001D00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "MCASP1_TARG" base ad:0x44002F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "MCASP2_TARG" base ad:0x44003000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "MCASP3_TARG" base ad:0x44003100 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "MMU1_TARG" base ad:0x44002200 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "MMU2_TARG" base ad:0x44002800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "OCMC_RAM1_TARG" base ad:0x44000F00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "OCMC_RAM2_TARG" base ad:0x44001700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "OCMC_RAM3_TARG" base ad:0x44001900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "PCIE1_TARG" base ad:0x44003700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "PCIE2_TARG" base ad:0x44003800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "QSPI_TARG" base ad:0x44003900 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "TPCC_TARG" base ad:0x44002000 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "TPTC1_TARG" base ad:0x44002E00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "TPTC2_TARG" base ad:0x44002B00 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "VCP1_TARG" base ad:0x44000700 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "VCP2_TARG" base ad:0x44000800 rgroup.long 0x00++0x0B line.long 0x00 "L3_TARG_STDHOSTHDR_COREREG," bitfld.long 0x00 16.--21. "STDHOSTHDR_COREREG_ CORECODE,The Core Code field is a constant reporting a vendor-specific core generator code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0. "STDHOSTHDR_COREREG_ VENDORCODE,The Vendor Code field is a constant reporting the core generator vendor code" "STDHOSTHDR_COREREG_ VENDORCODE_0_r,STDHOSTHDR_COREREG_ VENDORCODE_1_r" line.long 0x04 "L3_TARG_STDHOSTHDR_VERSIONREG," hexmask.long.byte 0x04 24.--31. 1. "STDHOSTHDR_VERSIONREG_REVISIONID,The Revision Identifier field is a constant reporting the core generator revision number" newline hexmask.long.tbyte 0x04 0.--23. 1. "STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM,Reserved" line.long 0x08 "L3_TARG_STDHOSTHDR_MAINCTLREG," rbitfld.long 0x08 3. "STDHOSTHDR_MAINCTLREG_CM,Reserved for internal testing" "0,1" newline rbitfld.long 0x08 2. "STDHOSTHDR_MAINCTLREG_FLT,Asserted when a Fault condition is detected: if the unit includes Error Logging Flt is asserted when the FltCnt register field indicates a Fault and deasserted when FltCnt is reset" "0,1" newline bitfld.long 0x08 0. "STDHOSTHDR_MAINCTLREG_EN,Sets the global core enable" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "L3_TARG_STDHOSTHDR_NTTPADDR_0," hexmask.long.byte 0x00 0.--6. 1. "STDHOSTHDR_NTTPADDR_0,Sets the Rx port address" group.long 0x40++0x2F line.long 0x00 "L3_TARG_STDERRLOG_SVRTSTDLVL," bitfld.long 0x00 0.--1. "STDERRLOG_SVRTSTDLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTSTDLVL_0_0,STDERRLOG_SVRTSTDLVL_0_1,STDERRLOG_SVRTSTDLVL_0_2,?" line.long 0x04 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL," bitfld.long 0x04 0.--1. "STDERRLOG_SVRTCUSTOMLVL_0,Severity level parameters Type: Control" "STDERRLOG_SVRTCUSTOMLVL_0_0,STDERRLOG_SVRTCUSTOMLVL_0_1,STDERRLOG_SVRTCUSTOMLVL_0_2,?" line.long 0x08 "L3_TARG_STDERRLOG_MAIN," bitfld.long 0x08 31. "STDERRLOG_MAIN_CLRLOG,Clears 'Error Logging Valid' bit when written to 1" "0,1" newline bitfld.long 0x08 19. "STDERRLOG_MAIN_FLTCNT,Asserted when at least one error with severity level FAULT is detected" "0,1" newline bitfld.long 0x08 18. "STDERRLOG_MAIN_ERRCNT,Asserted when at least one error with severity level ERROR is detected" "0,1" newline rbitfld.long 0x08 1. "STDERRLOG_MAIN_ERRTYPE,Indicates logging type" "STDERRLOG_MAIN_ERRTYPE_0_r,STDERRLOG_MAIN_ERRTYPE_1_r" newline rbitfld.long 0x08 0. "STDERRLOG_MAIN_ERRLOGVLD,Error Logging Valid" "0,1" line.long 0x0C "L3_TARG_STDERRLOG_HDR," hexmask.long.word 0x0C 18.--27. 1. "STDERRLOG_HDR_LEN1,This field contains the number of payload cell(s) minus one of the logged packet" newline bitfld.long 0x0C 12.--15. "STDERRLOG_HDR_STOPOFSWRPSZ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x0C 11. "STDERRLOG_HDR_ERR,Err bit of the logged packet" "0,1" newline bitfld.long 0x0C 6.--7. "STDERRLOG_HDR_PRESSURE,Pressure field of the logged packet" "0,1,2,3" newline bitfld.long 0x0C 0.--3. "STDERRLOG_HDR_OPCODE,Opcode of the logged packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "L3_TARG_STDERRLOG_MSTADDR," hexmask.long.byte 0x10 0.--7. 1. "STDERRLOG_MSTADDR,Master Address field of the logged packet" line.long 0x14 "L3_TARG_STDERRLOG_SLVADDR," hexmask.long.byte 0x14 0.--6. 1. "STDERRLOG_SLVADDR,Slave Address field of the logged packet" line.long 0x18 "L3_TARG_STDERRLOG_INFO," hexmask.long.byte 0x18 0.--7. 1. "STDERRLOG_INFO,Info field of the logged packet" line.long 0x1C "L3_TARG_STDERRLOG_SLVOFSLSB," line.long 0x20 "L3_TARG_STDERRLOG_SLVOFSMSB," bitfld.long 0x20 0. "STDERRLOG_SLVOFSMSB,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0 if any)" "0,1" line.long 0x24 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO," hexmask.long.byte 0x24 0.--7. 1. "STDERRLOG_CUSTOMINFO_INFO,Info field of the response packet" line.long 0x28 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR," hexmask.long.byte 0x28 0.--7. 1. "STDERRLOG_CUSTOMINFO_MSTADDR,MstAddr field of the response packet" line.long 0x2C "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE," bitfld.long 0x2C 0.--1. "STDERRLOG_CUSTOMINFO_OPCODE,Opcode of the response packet" "0,1,2,3" group.long 0x80++0x03 line.long 0x00 "L3_TARG_ADDRSPACESIZELOG," bitfld.long 0x00 0.--4. "ADDRSPACESIZELOG,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "IPU1_FW" base ad:0x4A15B000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 3. (list 1. 2. 3. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "IPU2_FW" base ad:0x4A218000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 3. (list 1. 2. 3. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "IVA_SL2IF_FW" base ad:0x4A21E000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 3. (list 1. 2. 3. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "OCMC_RAM1_FW" base ad:0x4A212000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 15. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "OCMC_RAM2_FW" base ad:0x4A20E000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 15. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "OCMC_RAM3_FW" base ad:0x4A22A000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 15. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "DSS_FW" base ad:0x4A21C000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 7. (list 1. 2. 3. 4. 5. 6. 7. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "GPMC_FW" base ad:0x4A210000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 7. (list 1. 2. 3. 4. 5. 6. 7. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "PCIE1_FW" base ad:0x4A165000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 7. (list 1. 2. 3. 4. 5. 6. 7. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "PCIE2_FW" base ad:0x4A159000 group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" repeat 7. (list 1. 2. 3. 4. 5. 6. 7. ) tree "REG_Bundle_$1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end repeat.end tree "REG_Bundle_0" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" newline bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" newline bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" newline bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" newline bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree "TPTC_FW" base ad:0x4A163000 tree "Channel_0" group.long 0x00++0x07 line.long 0x00 "ERROR_LOG_k_0,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" group.long 0x8C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" newline bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" newline bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" newline bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" newline bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" newline bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x88++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" newline bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" tree.end tree "REG_Bundle_1" group.long 0x94++0x03 line.long 0x00 "END_REGION_i_1,End physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "END_REGION,Physical target end address of firewall region i" bitfld.long 0x00 1. "END_REGION_i_ENABLE_CORE1,Enable this region for port 1" "0,1" bitfld.long 0x00 0. "END_REGION_i_ENABLE_CORE0,Enable this region for port 0" "0,1" group.long 0x10++0x07 line.long 0x00 "ERROR_LOG_k_1,Error log register for port k" bitfld.long 0x00 23. "BLK_BURST_VIOLATION," "0,1" bitfld.long 0x00 17.--21. "REGION_START_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. "REGION_END_ERRLOG,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--11. 1. "REQINFO_ERRLOG,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" line.long 0x04 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" group.long 0x9C++0x03 line.long 0x00 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x00 31. "W15,Master NIU ConnID = 115 write permission" "0,1" bitfld.long 0x00 30. "R15,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x00 29. "W14,Master NIU ConnID = 14 write permission" "0,1" bitfld.long 0x00 28. "R14,Master NIU ConnID = 14 read permission" "0,1" newline bitfld.long 0x00 27. "W13,Master NIU ConnID = 13 write permission" "0,1" bitfld.long 0x00 26. "R13,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x00 25. "W12,Master NIU ConnID = 12 write permission" "0,1" bitfld.long 0x00 24. "R12,Master NIU ConnID = 12 read permission" "0,1" newline bitfld.long 0x00 23. "W11,Master NIU ConnID = 11 write permission" "0,1" bitfld.long 0x00 22. "R11,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x00 21. "W10,Master NIU ConnID = 10 write permission" "0,1" bitfld.long 0x00 20. "R10,Master NIU ConnID = 10 read permission" "0,1" newline bitfld.long 0x00 19. "W9,Master NIU ConnID = 9 write permission" "0,1" bitfld.long 0x00 18. "R9,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x00 17. "W8,Master NIU ConnID = 8 write permission" "0,1" bitfld.long 0x00 16. "R8,Master NIU ConnID = 8 read permission" "0,1" newline bitfld.long 0x00 15. "W7,Master NIU ConnID = 7 write permission" "0,1" bitfld.long 0x00 14. "R7,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x00 13. "W6,Master NIU ConnID = 6 write permission" "0,1" bitfld.long 0x00 12. "R6,Master NIU ConnID = 6 read permission" "0,1" newline bitfld.long 0x00 11. "W5,Master NIU ConnID = 5 write permission" "0,1" bitfld.long 0x00 10. "R5,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x00 9. "W4,Master NIU ConnID = 4 write permission" "0,1" bitfld.long 0x00 8. "R4,Master NIU ConnID = 4 read permission" "0,1" newline bitfld.long 0x00 7. "W3,Master NIU ConnID = 3 write permission" "0,1" bitfld.long 0x00 6. "R3,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x00 5. "W2,Master NIU ConnID = 2 write permission" "0,1" bitfld.long 0x00 4. "R2,Master NIU ConnID = 2 read permission" "0,1" newline bitfld.long 0x00 3. "W1,Master NIU ConnID = 1 write permission" "0,1" bitfld.long 0x00 2. "R1,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x00 1. "W0,Master NIU ConnID = 0 write permission" "0,1" bitfld.long 0x00 0. "R0,Master NIU ConnID = 0 read permission" "0,1" group.long 0x98++0x03 line.long 0x00 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x00 15. "PUB_PRV_DEBUG,Public Privilege Debug Allowed" "0,1" bitfld.long 0x00 14. "PUB_USR_DEBUG,Public User Debug Allowed" "0,1" bitfld.long 0x00 11. "PUB_PRV_WRITE,Public Privilege Write Allowed" "0,1" bitfld.long 0x00 10. "PUB_PRV_READ,Public Privilege Read Allowed" "0,1" newline bitfld.long 0x00 9. "PUB_PRV_EXE,Public Privilege Exe Allowed" "0,1" bitfld.long 0x00 8. "PUB_USR_WRITE,Public User Write Access Allowed" "0,1" bitfld.long 0x00 7. "PUB_USR_READ,Public User Read Access Allowed" "0,1" bitfld.long 0x00 6. "PUB_USR_EXE,Public User Exe Access Allowed" "0,1" group.long 0x90++0x03 line.long 0x00 "START_REGION_i_1,Start physical address of region i" hexmask.long.tbyte 0x00 10.--31. 1. "START_REGION,Physical target start address of firewall region i" tree.end group.long 0x40++0x03 line.long 0x00 "REGUPDATE_CONTROL,Register update control register" rbitfld.long 0x00 16.--19. "FW_ADDR_SPACE_MSB,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 1. "FW_LOAD_REQ,Hadrdware set/Software clear" "FW_LOAD_REQ_0,FW_LOAD_REQ_1" bitfld.long 0x00 0. "BUSY_REQ,Busy request" "BUSY_REQ_0,BUSY_REQ_1" tree.end tree.end tree.open "L4_Interconnects" tree "CFG_AP" base ad:0x4A000000 rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" repeat 9. (list 120. 121. 122. 123. 124. 125. 126. 127. 128. ) tree "REG_Bundle_$1" group.long 0x6C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_120,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x6C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_120,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. ) tree "REG_Bundle_$1" group.long 0x644++0x03 line.long 0x00 "L4_AP_REGION_l_H_104,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x640++0x03 line.long 0x00 "L4_AP_REGION_l_L_104,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. ) tree "REG_Bundle_$1" group.long 0x624++0x03 line.long 0x00 "L4_AP_REGION_l_H_100,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x620++0x03 line.long 0x00 "L4_AP_REGION_l_L_100,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. ) tree "REG_Bundle_$1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. ) tree "REG_Bundle_$1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. ) tree "REG_Bundle_$1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. ) tree "REG_Bundle_$1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. ) tree "REG_Bundle_$1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 5. (list 3. 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x218++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x29C++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group" rgroup.word 0x298++0x01 line.word 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group" group.long 0x31C++0x03 line.long 0x00 "L4_AP_REGION_l_H_3,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x318++0x03 line.long 0x00 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 3. (list 0. 1. 2. ) tree "Channel_$1" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.word 0x280++0x01 line.word 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" tree.end repeat.end tree.end tree "CFG_LA" base ad:0x4A000800 rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x13 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x04 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x04 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--23. 1. "NUMBER_REGIONS,Number of regions in the current L4" bitfld.long 0x04 0.--3. "SEGMENTS,Number of segments in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x08 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x0C 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "0,1,2,3,4,5,6,7" line.long 0x10 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x10 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x10 20. "THREAD0_PRI,Sets thread priority" "0,1" rbitfld.long 0x10 8. "EXT_CLOCK,Global external clock control" "0,1" tree.end tree "WKUP_LA" base ad:0x4AE00800 rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x13 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x04 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x04 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--23. 1. "NUMBER_REGIONS,Number of regions in the current L4" bitfld.long 0x04 0.--3. "SEGMENTS,Number of segments in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x08 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x0C 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "0,1,2,3,4,5,6,7" line.long 0x10 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x10 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x10 20. "THREAD0_PRI,Sets thread priority" "0,1" rbitfld.long 0x10 8. "EXT_CLOCK,Global external clock control" "0,1" tree.end tree "MAILBOX_TARG" base ad:0x4A0F5000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x0F line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" hgroup.long 0x28++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" group.long 0x2C++0x03 line.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x00 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x00 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x00 0. "OCP_RESET,L3 Reset" "0,1" tree.end tree "OCP_WP_NOC_TARG" base ad:0x4A103000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x0F line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" hgroup.long 0x28++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" group.long 0x2C++0x03 line.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x00 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x00 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x00 0. "OCP_RESET,L3 Reset" "0,1" tree.end tree "SPINLOCK_TARG" base ad:0x4A0F7000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x0F line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" hgroup.long 0x28++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" group.long 0x2C++0x03 line.long 0x00 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x00 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x00 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x00 0. "OCP_RESET,L3 Reset" "0,1" tree.end tree "OCMC_RAM3_TARG" base ad:0x48811000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x2004++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x2018++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x202C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PER1_AP" base ad:0x48000000 rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" repeat 13. (list 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. ) tree "REG_Bundle_$1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. ) tree "REG_Bundle_$1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. ) tree "REG_Bundle_$1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. ) tree "REG_Bundle_$1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. ) tree "REG_Bundle_$1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 6. (list 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x210++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x294++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group" rgroup.word 0x290++0x01 line.word 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group" group.long 0x314++0x03 line.long 0x00 "L4_AP_REGION_l_H_2,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x310++0x03 line.long 0x00 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 2. (list 0. 1. ) tree "Channel_$1" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.word 0x280++0x01 line.word 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" tree.end repeat.end tree.end tree "CFG_IA_IP0" base ad:0x4A001000 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "0,1,2,3" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" tree.end repeat 3. (list 0. 1. 2. )(list ad:0x48001000 ad:0x48001400 ad:0x48001800 ) tree "PER1_IA_IP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "0,1,2,3" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" tree.end repeat.end repeat 3. (list 0. 1. 2. )(list ad:0x48401000 ad:0x48401400 ad:0x48401800 ) tree "PER2_IA_IP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "0,1,2,3" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" tree.end repeat.end repeat 3. (list 0. 1. 2. )(list ad:0x48801000 ad:0x48801400 ad:0x48801800 ) tree "PER3_IA_IP$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "0,1,2,3" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" tree.end repeat.end tree "WKUP_IA_IP0" base ad:0x4AE01000 rgroup.long 0x00++0x03 line.long 0x00 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs" rgroup.long 0x18++0x0B line.long 0x00 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" bitfld.long 0x08 31. "PROT_ERROR_SECONDARY_REP,Out-of-band reporting of protection mechanism secondary errors" "0,1" bitfld.long 0x08 30. "PROT_ERROR_PRIMARY_REP,Out-of-band reporting of protection mechanism primary errors" "0,1" bitfld.long 0x08 27. "INBAND_ERROR_REP,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register" "0,1" rbitfld.long 0x08 24. "MERROR_REP,OCP MError reporting control" "0,1" hgroup.long 0x24++0x03 hide.long 0x00 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface" group.long 0x28++0x03 line.long 0x00 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator" bitfld.long 0x00 31. "PROT_ERROR_SECONDARY," "0,1" bitfld.long 0x00 30. "PROT_ERROR_PRIMARY," "0,1" bitfld.long 0x00 27. "INBAND_ERROR,0x0 No In-Band error present.0x1 In-Band error present" "0,1" rbitfld.long 0x00 24. "MERROR,Value of the OCP MError signal" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator" group.long 0x58++0x0B line.long 0x00 "L4_IA_ERROR_LOG_L,Log information about error conditions" bitfld.long 0x00 31. "MULTI,Multiple errors detected" "0,1" bitfld.long 0x00 30. "SECONDARY,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x00 24.--25. "CODE,The error code of an initiator request" "0,1,2,3" rbitfld.long 0x00 8.--13. "CONNID,ConnID of request causing the error refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0.--2. "CMD,Command that caused error" "0,1,2,3,4,5,6,7" line.long 0x04 "L4_IA_ERROR_LOG_H,Log information about error conditions" hexmask.long.word 0x04 0.--15. 1. "REQ_INFO,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor REQ_INFO[1] = Debug" line.long 0x08 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hgroup.long 0x64++0x03 hide.long 0x00 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" tree.end tree "PER1_LA" base ad:0x48000800 rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x13 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x04 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x04 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--23. 1. "NUMBER_REGIONS,Number of regions in the current L4" bitfld.long 0x04 0.--3. "SEGMENTS,Number of segments in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x08 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x0C 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "0,1,2,3,4,5,6,7" line.long 0x10 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x10 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x10 20. "THREAD0_PRI,Sets thread priority" "0,1" rbitfld.long 0x10 8. "EXT_CLOCK,Global external clock control" "0,1" repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end repeat.end tree.end tree "PER2_LA" base ad:0x48400800 rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x13 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x04 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x04 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--23. 1. "NUMBER_REGIONS,Number of regions in the current L4" bitfld.long 0x04 0.--3. "SEGMENTS,Number of segments in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x08 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x0C 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "0,1,2,3,4,5,6,7" line.long 0x10 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x10 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x10 20. "THREAD0_PRI,Sets thread priority" "0,1" rbitfld.long 0x10 8. "EXT_CLOCK,Global external clock control" "0,1" repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end repeat.end tree.end tree "PER3_LA" base ad:0x48800800 rgroup.long 0x00++0x03 line.long 0x00 "L4_LA_COMPONENT_L,Contain a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_LA_COMPONENT_H,Contain a component code and revision. which are used to identify the hardware of the component" hgroup.long 0x10++0x03 hide.long 0x00 "L4_LA_NETWORK_L,Identify the interconnect" rgroup.long 0x14++0x13 line.long 0x00 "L4_LA_NETWORK_H,Identify the interconnect" line.long 0x04 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information" bitfld.long 0x04 24.--27. "PROT_GROUPS,Number of protection group of in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--23. 1. "NUMBER_REGIONS,Number of regions in the current L4" bitfld.long 0x04 0.--3. "SEGMENTS,Number of segments in the current L4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information" bitfld.long 0x08 16.--18. "THREADS,The THREADS field specifies the number of initiator threads connected to the interconnect" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. "CONNID_WIDTH,The initiator subsystem ConnID width" "0,1,2,3,4,5,6,7" bitfld.long 0x08 8.--10. "BYTE_DATA_WIDTH_EXP,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--5. "ADDR_WIDTH,This field specifies the initiator subsystem address width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values" bitfld.long 0x0C 8.--10. "TIMEOUT_BASE,The TIMEOUT_BASE field indicates the time-out period (that is base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled" "0,1,2,3,4,5,6,7" line.long 0x10 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" bitfld.long 0x10 24. "CLOCK_GATE_DISABLE,When set to 1 this field disables all clock gating" "0,1" rbitfld.long 0x10 20. "THREAD0_PRI,Sets thread priority" "0,1" rbitfld.long 0x10 8. "EXT_CLOCK,Global external clock control" "0,1" repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x100++0x03 line.long 0x00 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x00 0.--3. "MASK,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x03 line.long 0x00 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x00 0.--3. "STATUS,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end repeat.end tree.end tree "PER2_AP" base ad:0x48400000 rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x07 line.long 0x00 "L4_AP_SEGMENT_i_L,Define the base address of each segments" line.long 0x04 "L4_AP_SEGMENT_i_H,Define the size of each segments" bitfld.long 0x04 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat 7. (list 56. 57. 58. 59. 60. 61. 62. ) tree "REG_Bundle_$1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. ) tree "REG_Bundle_$1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. ) tree "REG_Bundle_$1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. ) tree "REG_Bundle_$1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.word 0x280++0x01 line.word 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end tree.end tree "PER3_AP" base ad:0x48800000 rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" rgroup.long 0x100++0x07 line.long 0x00 "L4_AP_SEGMENT_i_L,Define the base address of each segments" line.long 0x04 "L4_AP_SEGMENT_i_H,Define the size of each segments" bitfld.long 0x04 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat 9. (list 88. 89. 90. 91. 92. 93. 94. 95. 96. ) tree "REG_Bundle_$1" group.long 0x5C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_88,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x5C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_88,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. ) tree "REG_Bundle_$1" group.long 0x544++0x03 line.long 0x00 "L4_AP_REGION_l_H_72,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x540++0x03 line.long 0x00 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. ) tree "REG_Bundle_$1" group.long 0x4C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_56,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x4C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. ) tree "REG_Bundle_$1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. ) tree "REG_Bundle_$1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. ) tree "REG_Bundle_$1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.word 0x280++0x01 line.word 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end tree.end tree "ATL_TARG" base ad:0x4843D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CM_CORE_AON_TARG" base ad:0x4A006000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CM_CORE_TARG" base ad:0x4A00A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "COUNTER_32K_TARG" base ad:0x4AE05000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CTRL_MODULE_CORE_TARG" base ad:0x4A004000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "CTRL_MODULE_WKUP_TARG" base ad:0x4AE0D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "DCAN1_TARG" base ad:0x4AE3E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "DCAN2_TARG" base ad:0x48482000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "DEBUGSS_CT_TBR_FW_CFG_TARG" base ad:0x4A225000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "DMA_SYSTEM_TARG" base ad:0x4A057000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "DSP1_SDMA_FW_CFG_TARG" base ad:0x4A172000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "DSP2_SDMA_FW_CFG_TARG" base ad:0x4A174000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "DSS_FW_CFG_TARG" base ad:0x4A21D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "ELM_TARG" base ad:0x48079000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "EMIF_OCP_FW_CFG_TARG" base ad:0x4A20D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "EVE1_FW_CFG_TARG" base ad:0x4A152000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "EVE2_FW_CFG_TARG" base ad:0x4A154000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GMAC_TARG" base ad:0x48488000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPIO1_TARG" base ad:0x4AE11000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPIO2_TARG" base ad:0x48056000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPIO3_TARG" base ad:0x48058000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPIO4_TARG" base ad:0x4805A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPIO5_TARG" base ad:0x4805C000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPIO6_TARG" base ad:0x4805E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPIO7_TARG" base ad:0x48052000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPIO8_TARG" base ad:0x48054000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPMC_FW_CFG_TARG" base ad:0x4A211000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "GPU_FW_CFG_TARG" base ad:0x4A215000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "HDQ1W_TARG" base ad:0x480B3000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "I2C1_TARG" base ad:0x48071000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "I2C2_TARG" base ad:0x48073000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "I2C3_TARG" base ad:0x48061000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "I2C4_TARG" base ad:0x4807B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "I2C5_TARG" base ad:0x4807D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "IPU1_FW_CFG_TARG" base ad:0x4A15C000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "IPU2_FW_CFG_TARG" base ad:0x4A219000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "IVA_CONFIG_FW_CFG_TARG" base ad:0x4A221000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "IVA_SL2IF_FW_CFG_TARG" base ad:0x4A21F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "KBD_TARG" base ad:0x4AE1D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "L3_INSTR_FW_CFG_TARG" base ad:0x4A227000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MA_MPU_NTTP_FW_CFG_TARG" base ad:0x4A20B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX10_TARG" base ad:0x48861000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX11_TARG" base ad:0x48863000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX12_TARG" base ad:0x48865000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX13_TARG" base ad:0x48803000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX2_TARG" base ad:0x4883B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX3_TARG" base ad:0x4883D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX4_TARG" base ad:0x4883F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX5_TARG" base ad:0x48841000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX6_TARG" base ad:0x48843000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX7_TARG" base ad:0x48845000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX8_TARG" base ad:0x48847000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MBX9_TARG" base ad:0x4885F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP1_CFG_TARG" base ad:0x48462000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP1_FW_CFG_TARG" base ad:0x4A168000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP2_CFG_TARG" base ad:0x48466000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP2_FW_CFG_TARG" base ad:0x4A16A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP3_CFG_TARG" base ad:0x4846A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP3_FW_CFG_TARG" base ad:0x4A16C000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP4_CFG_TARG" base ad:0x4846E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP4_DAT_TARG" base ad:0x48437000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP5_CFG_TARG" base ad:0x48472000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP5_DAT_TARG" base ad:0x4843B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP6_CFG_TARG" base ad:0x48476000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP6_DAT_TARG" base ad:0x4844D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP7_CFG_TARG" base ad:0x4847A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP7_DAT_TARG" base ad:0x48451000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP8_CFG_TARG" base ad:0x4847E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCASP8_DAT_TARG" base ad:0x48455000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCSPI1_TARG" base ad:0x48099000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCSPI2_TARG" base ad:0x4809B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCSPI3_TARG" base ad:0x480B9000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MCSPI4_TARG" base ad:0x480BB000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MLB_TARG" base ad:0x4842D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MMC1_TARG" base ad:0x4809D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MMC2_TARG" base ad:0x480B5000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MMC3_TARG" base ad:0x480AE000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MMC4_TARG" base ad:0x480D2000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MMU1_TARG" base ad:0x4881D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "MMU2_TARG" base ad:0x4881F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "OCMC_RAM1_FW_CFG_TARG" base ad:0x4A213000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "OCMC_RAM1_TARG" base ad:0x48805000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "OCMC_RAM2_FW_CFG_TARG" base ad:0x4A20F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "OCMC_RAM2_TARG" base ad:0x4880B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "OCMC_RAM3_FW_CFG_TARG" base ad:0x4A22B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PCIESS1_FW_CFG_TARG" base ad:0x4A166000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PCIESS2_FW_CFG_TARG" base ad:0x4A15A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PRM_TARG" base ad:0x4AE08000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PWM1_TARG" base ad:0x4843F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PWM2_TARG" base ad:0x48441000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "PWM3_TARG" base ad:0x48443000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "QSPI_FW_CFG_TARG" base ad:0x4A17A000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "RTC_TARG" base ad:0x48839000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "SCP1_TARG" base ad:0x4A088000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "SCP2_TARG" base ad:0x4A0A8000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "SCP3_TARG" base ad:0x4A098000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "SMARTREFLEX_CORE_TARG" base ad:0x4A0DE000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "SMARTREFLEX_DSPEVE_TARG" base ad:0x4A184000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "SMARTREFLEX_GPU_TARG" base ad:0x4A186000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "SMARTREFLEX_IVA_TARG" base ad:0x4A188000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "SMARTREFLEX_MPU_TARG" base ad:0x4A0DA000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER10_TARG" base ad:0x48087000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER11_TARG" base ad:0x48089000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER12_TARG" base ad:0x4AE21000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER13_TARG" base ad:0x48829000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER14_TARG" base ad:0x4882B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER15_TARG" base ad:0x4882D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER16_TARG" base ad:0x4882F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER1_TARG" base ad:0x4AE19000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER2_TARG" base ad:0x48033000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER3_TARG" base ad:0x48035000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER4_TARG" base ad:0x48037000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER5_TARG" base ad:0x48821000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER6_TARG" base ad:0x48823000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER7_TARG" base ad:0x48825000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER8_TARG" base ad:0x48827000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TIMER9_TARG" base ad:0x4803F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TPCC_FW_CFG_TARG" base ad:0x4A162000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "TPTC_FW_CFG_TARG" base ad:0x4A164000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART10_TARG" base ad:0x4AE2C000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART1_TARG" base ad:0x4806B000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART2_TARG" base ad:0x4806D000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART3_TARG" base ad:0x48021000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART4_TARG" base ad:0x4806F000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART5_TARG" base ad:0x48067000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART6_TARG" base ad:0x48069000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART7_TARG" base ad:0x48421000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART8_TARG" base ad:0x48423000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "UART9_TARG" base ad:0x48425000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "USB1_CFG_TARG" base ad:0x488A0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "USB2_CFG_TARG" base ad:0x488E0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "USB3_CFG_TARG" base ad:0x48920000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "USB4_CFG_TARG" base ad:0x48960000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "VCP1_CFG_TARG" base ad:0x48447000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "VCP1_FW_CFG_TARG" base ad:0x4A15E000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "VCP2_CFG_TARG" base ad:0x48449000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "VCP2_FW_CFG_TARG" base ad:0x4A160000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "VIP1_TARG" base ad:0x48980000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "VIP2_TARG" base ad:0x489A0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "VIP3_TARG" base ad:0x489C0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "VPE_TARG" base ad:0x489E0000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WD_TIMER2_TARG" base ad:0x4AE15000 rgroup.long 0x00++0x03 line.long 0x00 "L4_TA_COMPONENT_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_TA_COMPONENT_H,Contains a component code and revision" rgroup.long 0x18++0x13 line.long 0x00 "L4_TA_CORE_L,Contains a component code and revision" hexmask.long.word 0x00 16.--31. 1. "CORE_CODE,Interconnect core code" hexmask.long.word 0x00 0.--15. 1. "CORE_REV,Component revision code code" line.long 0x04 "L4_TA_CORE_H,Contains a component code and revision" hexmask.long.word 0x04 0.--15. 1. "VENDOR_CODE,Vendor revision core code" line.long 0x08 "L4_TA_AGENT_CONTROL_L,Enable error reporting" rbitfld.long 0x08 24. "SERROR_REP,Enable logging of error" "0,1" bitfld.long 0x08 8.--10. "REQ_TIMEOUT,Time-out Bound" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. "OCP_RESET,The OCP_RESET field controls the OCP reset signal to the attached core" "0,1" line.long 0x0C "L4_TA_AGENT_CONTROL_H,Enable clock power management" bitfld.long 0x0C 9. "AUTO_WAKEUP_RESP_CODE," "0,1" bitfld.long 0x0C 8. "EXT_CLOCK,When set to 1 the ext_clk_off_i signal on a target agent indicates when the target agent should shut off" "0,1" line.long 0x10 "L4_TA_AGENT_STATUS_L,Error reporting" rbitfld.long 0x10 24. "SERROR,Value of OCP SError signal" "0,1" bitfld.long 0x10 8. "REQ_TIMEOUT,Time-out status" "0,1" rbitfld.long 0x10 0. "OCP_RESET,L3 Reset" "0,1" hgroup.long 0x2C++0x03 hide.long 0x00 "L4_TA_AGENT_STATUS_H,Error reporting" tree.end tree "WKUP_AP" base ad:0x4AE00000 rgroup.long 0x00++0x03 line.long 0x00 "L4_AP_COMPONENT_L,Contains a component code and revision. which are used to identify the hardware of the component" hexmask.long.word 0x00 16.--31. 1. "CODE,Interconnect code" hexmask.long.word 0x00 0.--15. 1. "REV,Component revision code" hgroup.long 0x04++0x03 hide.long 0x00 "L4_AP_COMPONENT_H,Contains a component code and revision. which are used to identify the hardware of the component" repeat 4. (list 40. 41. 42. 43. ) tree "REG_Bundle_$1" group.long 0x444++0x03 line.long 0x00 "L4_AP_REGION_l_H_40,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x440++0x03 line.long 0x00 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. ) tree "REG_Bundle_$1" group.long 0x3C4++0x03 line.long 0x00 "L4_AP_REGION_l_H_24,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x3C0++0x03 line.long 0x00 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 16. (list 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. ) tree "REG_Bundle_$1" group.long 0x354++0x03 line.long 0x00 "L4_AP_REGION_l_H_10,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x350++0x03 line.long 0x00 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 4. (list 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x220++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x2A4++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group" rgroup.word 0x2A0++0x01 line.word 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group" group.long 0x324++0x03 line.long 0x00 "L4_AP_REGION_l_H_4,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x320++0x03 line.long 0x00 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" rgroup.long 0x200++0x03 line.long 0x00 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group" hexmask.long.word 0x00 0.--15. 1. "CONNID_BIT_VECTOR,Specifies protection group members N is 2**W where W is the connID width" rgroup.long 0x284++0x03 line.long 0x00 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group" rgroup.word 0x280++0x01 line.word 0x00 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group" group.long 0x304++0x03 line.long 0x00 "L4_AP_REGION_l_H_0,Define the size. protection group and segment ID of the region" rbitfld.long 0x00 28.--31. "MADDRSPACE,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 24.--26. "SEGMENT_ID,Segment ID of the region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "PROT_GROUP_ID,Protection group ID" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 17.--18. "BYTE_DATA_WIDTH_EXP,Target data byte width" "0,1,2,3" hexmask.long.byte 0x00 8.--14. 1. "PHY_TARGET_ID,Physical target ID" newline rbitfld.long 0x00 1.--6. "SIZE,Define the size of the region in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0. "ENABLE," "0,1" rgroup.long 0x300++0x03 line.long 0x00 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to" hexmask.long.tbyte 0x00 0.--20. 1. "BASE,Sets the base address of the region relative to its segment base" rgroup.long 0x104++0x03 line.long 0x00 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x00 0.--4. "SIZE,Segment size is a power of 2 where 2 is the byte size of a segment (all segment registers use the same size)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x100++0x03 line.long 0x00 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" tree.end repeat.end tree.end tree.end tree.open "Mailbox" repeat 3. (list 0. 1. 2. )(list ad:0x4218B000 ad:0x4218C000 ad:0x4218D000 ) tree "EVE2_MBOX$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MAILBOX_REVISION,This register contains the IP revision code" group.long 0x10++0x03 line.long 0x00 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x00 2.--3. "SIDLEMODE,Idle Mode - b00" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Softreset - b0" "SOFTRESET_0_w,SOFTRESET_1_w" group.long 0x140++0x03 line.long 0x00 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse" bitfld.long 0x00 0.--1. "EOIVAL,EOI value - B0" "EOIVAL_0,EOIVAL_1,?,?" repeat 12. (list 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. ) tree "Channel_$1" rgroup.long 0xA8++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x68++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox" rgroup.long 0xE8++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" rgroup.long 0x80++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x10C++0x03 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x108++0x03 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x104++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSENUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB15_0_w,NOTFULLSTATUSENUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSENUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB15_0_w,NEWMSGSTATUSENUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSENUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB14_0_w,NOTFULLSTATUSENUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSENUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB14_0_w,NEWMSGSTATUSENUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSENUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB13_0_w,NOTFULLSTATUSENUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSENUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB13_0_w,NEWMSGSTATUSENUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSENUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB12_0_w,NOTFULLSTATUSENUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSENUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB12_0_w,NEWMSGSTATUSENUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSENUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB11_0_w,NOTFULLSTATUSENUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSENUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB11_0_w,NEWMSGSTATUSENUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSENUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB10_0_w,NOTFULLSTATUSENUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSENUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB10_0_w,NEWMSGSTATUSENUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSENUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB9_0_w,NOTFULLSTATUSENUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSENUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB9_0_w,NEWMSGSTATUSENUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSENUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB8_0_w,NOTFULLSTATUSENUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSENUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB8_0_w,NEWMSGSTATUSENUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSENUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB7_0_w,NOTFULLSTATUSENUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSENUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB7_0_w,NEWMSGSTATUSENUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSENUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB6_0_w,NOTFULLSTATUSENUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSENUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB6_0_w,NEWMSGSTATUSENUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSENUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB5_0_w,NOTFULLSTATUSENUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSENUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB5_0_w,NEWMSGSTATUSENUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSENUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB4_0_w,NOTFULLSTATUSENUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSENUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB4_0_w,NEWMSGSTATUSENUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSENUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB3_0_w,NOTFULLSTATUSENUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSENUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB3_0_w,NEWMSGSTATUSENUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSENUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB2_0_w,NOTFULLSTATUSENUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSENUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB2_0_w,NEWMSGSTATUSENUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSENUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB1_0_w,NOTFULLSTATUSENUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSENUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB1_0_w,NEWMSGSTATUSENUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSENUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB0_0_w,NOTFULLSTATUSENUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSENUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB0_0_w,NEWMSGSTATUSENUUMB0_1_w" group.long 0x100++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB15_0_w,NOTFULLSTATUSUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB15_0_w,NEWMSGSTATUSUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB14_0_w,NOTFULLSTATUSUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB14_0_w,NEWMSGSTATUSUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB13_0_w,NOTFULLSTATUSUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB13_0_w,NEWMSGSTATUSUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB12_0_w,NOTFULLSTATUSUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB12_0_w,NEWMSGSTATUSUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB11_0_w,NOTFULLSTATUSUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB11_0_w,NEWMSGSTATUSUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB10_0_w,NOTFULLSTATUSUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB10_0_w,NEWMSGSTATUSUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB9_0_w,NOTFULLSTATUSUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB9_0_w,NEWMSGSTATUSUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB8_0_w,NOTFULLSTATUSUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB8_0_w,NEWMSGSTATUSUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB7_0_w,NOTFULLSTATUSUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB7_0_w,NEWMSGSTATUSUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB6_0_w,NOTFULLSTATUSUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB6_0_w,NEWMSGSTATUSUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB5_0_w,NOTFULLSTATUSUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB5_0_w,NEWMSGSTATUSUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB4_0_w,NOTFULLSTATUSUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB4_0_w,NEWMSGSTATUSUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB3_0_w,NOTFULLSTATUSUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB3_0_w,NEWMSGSTATUSUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB2_0_w,NOTFULLSTATUSUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB2_0_w,NEWMSGSTATUSUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB1_0_w,NOTFULLSTATUSUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB1_0_w,NEWMSGSTATUSUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB0_0_w,NOTFULLSTATUSUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB0_0_w,NEWMSGSTATUSUUMB0_1_w" group.long 0x40++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox" rgroup.long 0xC0++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end tree.end repeat.end repeat 3. (list 0. 1. 2. )(list ad:0x4208B000 ad:0x4208C000 ad:0x4208D000 ) tree "EVE1_MBOX$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MAILBOX_REVISION,This register contains the IP revision code" group.long 0x10++0x03 line.long 0x00 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x00 2.--3. "SIDLEMODE,Idle Mode - b00" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Softreset - b0" "SOFTRESET_0_w,SOFTRESET_1_w" group.long 0x140++0x03 line.long 0x00 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse" bitfld.long 0x00 0.--1. "EOIVAL,EOI value - B0" "EOIVAL_0,EOIVAL_1,?,?" repeat 12. (list 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. ) tree "Channel_$1" rgroup.long 0xA8++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x68++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox" rgroup.long 0xE8++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" rgroup.long 0x80++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x10C++0x03 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x108++0x03 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x104++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSENUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB15_0_w,NOTFULLSTATUSENUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSENUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB15_0_w,NEWMSGSTATUSENUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSENUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB14_0_w,NOTFULLSTATUSENUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSENUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB14_0_w,NEWMSGSTATUSENUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSENUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB13_0_w,NOTFULLSTATUSENUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSENUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB13_0_w,NEWMSGSTATUSENUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSENUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB12_0_w,NOTFULLSTATUSENUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSENUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB12_0_w,NEWMSGSTATUSENUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSENUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB11_0_w,NOTFULLSTATUSENUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSENUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB11_0_w,NEWMSGSTATUSENUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSENUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB10_0_w,NOTFULLSTATUSENUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSENUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB10_0_w,NEWMSGSTATUSENUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSENUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB9_0_w,NOTFULLSTATUSENUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSENUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB9_0_w,NEWMSGSTATUSENUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSENUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB8_0_w,NOTFULLSTATUSENUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSENUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB8_0_w,NEWMSGSTATUSENUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSENUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB7_0_w,NOTFULLSTATUSENUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSENUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB7_0_w,NEWMSGSTATUSENUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSENUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB6_0_w,NOTFULLSTATUSENUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSENUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB6_0_w,NEWMSGSTATUSENUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSENUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB5_0_w,NOTFULLSTATUSENUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSENUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB5_0_w,NEWMSGSTATUSENUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSENUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB4_0_w,NOTFULLSTATUSENUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSENUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB4_0_w,NEWMSGSTATUSENUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSENUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB3_0_w,NOTFULLSTATUSENUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSENUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB3_0_w,NEWMSGSTATUSENUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSENUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB2_0_w,NOTFULLSTATUSENUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSENUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB2_0_w,NEWMSGSTATUSENUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSENUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB1_0_w,NOTFULLSTATUSENUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSENUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB1_0_w,NEWMSGSTATUSENUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSENUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB0_0_w,NOTFULLSTATUSENUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSENUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB0_0_w,NEWMSGSTATUSENUUMB0_1_w" group.long 0x100++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB15_0_w,NOTFULLSTATUSUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB15_0_w,NEWMSGSTATUSUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB14_0_w,NOTFULLSTATUSUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB14_0_w,NEWMSGSTATUSUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB13_0_w,NOTFULLSTATUSUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB13_0_w,NEWMSGSTATUSUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB12_0_w,NOTFULLSTATUSUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB12_0_w,NEWMSGSTATUSUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB11_0_w,NOTFULLSTATUSUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB11_0_w,NEWMSGSTATUSUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB10_0_w,NOTFULLSTATUSUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB10_0_w,NEWMSGSTATUSUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB9_0_w,NOTFULLSTATUSUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB9_0_w,NEWMSGSTATUSUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB8_0_w,NOTFULLSTATUSUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB8_0_w,NEWMSGSTATUSUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB7_0_w,NOTFULLSTATUSUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB7_0_w,NEWMSGSTATUSUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB6_0_w,NOTFULLSTATUSUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB6_0_w,NEWMSGSTATUSUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB5_0_w,NOTFULLSTATUSUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB5_0_w,NEWMSGSTATUSUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB4_0_w,NOTFULLSTATUSUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB4_0_w,NEWMSGSTATUSUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB3_0_w,NOTFULLSTATUSUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB3_0_w,NEWMSGSTATUSUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB2_0_w,NOTFULLSTATUSUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB2_0_w,NEWMSGSTATUSUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB1_0_w,NOTFULLSTATUSUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB1_0_w,NEWMSGSTATUSUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB0_0_w,NOTFULLSTATUSUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB0_0_w,NEWMSGSTATUSUUMB0_1_w" group.long 0x40++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox" rgroup.long 0xC0++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end tree.end repeat.end tree "IVA_MBOX" base ad:0x5A05A800 rgroup.long 0x00++0x03 line.long 0x00 "MAILBOX_REVISION,This register contains the IP revision code" group.long 0x10++0x03 line.long 0x00 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x00 2.--3. "SIDLEMODE,Idle Mode - b00" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Softreset - b0" "SOFTRESET_0_w,SOFTRESET_1_w" group.long 0x140++0x03 line.long 0x00 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse" bitfld.long 0x00 0.--1. "EOIVAL,EOI value - B0" "EOIVAL_0,EOIVAL_1,?,?" repeat 2. (list 4. 5. ) tree "Channel_$1" rgroup.long 0x90++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x50++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox" rgroup.long 0xD0++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" rgroup.long 0x80++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x10C++0x03 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x108++0x03 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x104++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSENUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB15_0_w,NOTFULLSTATUSENUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSENUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB15_0_w,NEWMSGSTATUSENUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSENUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB14_0_w,NOTFULLSTATUSENUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSENUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB14_0_w,NEWMSGSTATUSENUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSENUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB13_0_w,NOTFULLSTATUSENUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSENUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB13_0_w,NEWMSGSTATUSENUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSENUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB12_0_w,NOTFULLSTATUSENUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSENUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB12_0_w,NEWMSGSTATUSENUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSENUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB11_0_w,NOTFULLSTATUSENUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSENUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB11_0_w,NEWMSGSTATUSENUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSENUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB10_0_w,NOTFULLSTATUSENUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSENUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB10_0_w,NEWMSGSTATUSENUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSENUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB9_0_w,NOTFULLSTATUSENUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSENUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB9_0_w,NEWMSGSTATUSENUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSENUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB8_0_w,NOTFULLSTATUSENUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSENUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB8_0_w,NEWMSGSTATUSENUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSENUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB7_0_w,NOTFULLSTATUSENUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSENUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB7_0_w,NEWMSGSTATUSENUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSENUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB6_0_w,NOTFULLSTATUSENUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSENUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB6_0_w,NEWMSGSTATUSENUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSENUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB5_0_w,NOTFULLSTATUSENUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSENUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB5_0_w,NEWMSGSTATUSENUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSENUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB4_0_w,NOTFULLSTATUSENUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSENUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB4_0_w,NEWMSGSTATUSENUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSENUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB3_0_w,NOTFULLSTATUSENUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSENUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB3_0_w,NEWMSGSTATUSENUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSENUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB2_0_w,NOTFULLSTATUSENUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSENUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB2_0_w,NEWMSGSTATUSENUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSENUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB1_0_w,NOTFULLSTATUSENUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSENUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB1_0_w,NEWMSGSTATUSENUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSENUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB0_0_w,NOTFULLSTATUSENUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSENUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB0_0_w,NEWMSGSTATUSENUUMB0_1_w" group.long 0x100++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB15_0_w,NOTFULLSTATUSUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB15_0_w,NEWMSGSTATUSUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB14_0_w,NOTFULLSTATUSUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB14_0_w,NEWMSGSTATUSUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB13_0_w,NOTFULLSTATUSUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB13_0_w,NEWMSGSTATUSUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB12_0_w,NOTFULLSTATUSUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB12_0_w,NEWMSGSTATUSUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB11_0_w,NOTFULLSTATUSUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB11_0_w,NEWMSGSTATUSUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB10_0_w,NOTFULLSTATUSUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB10_0_w,NEWMSGSTATUSUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB9_0_w,NOTFULLSTATUSUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB9_0_w,NEWMSGSTATUSUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB8_0_w,NOTFULLSTATUSUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB8_0_w,NEWMSGSTATUSUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB7_0_w,NOTFULLSTATUSUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB7_0_w,NEWMSGSTATUSUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB6_0_w,NOTFULLSTATUSUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB6_0_w,NEWMSGSTATUSUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB5_0_w,NOTFULLSTATUSUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB5_0_w,NEWMSGSTATUSUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB4_0_w,NOTFULLSTATUSUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB4_0_w,NEWMSGSTATUSUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB3_0_w,NOTFULLSTATUSUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB3_0_w,NEWMSGSTATUSUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB2_0_w,NOTFULLSTATUSUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB2_0_w,NEWMSGSTATUSUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB1_0_w,NOTFULLSTATUSUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB1_0_w,NEWMSGSTATUSUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB0_0_w,NOTFULLSTATUSUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB0_0_w,NEWMSGSTATUSUUMB0_1_w" group.long 0x40++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox" rgroup.long 0xC0++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end tree.end tree "MAILBOX1" base ad:0x4A0F4000 rgroup.long 0x00++0x03 line.long 0x00 "MAILBOX_REVISION,This register contains the IP revision code" group.long 0x10++0x03 line.long 0x00 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x00 2.--3. "SIDLEMODE,Idle Mode - b00" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Softreset - b0" "SOFTRESET_0_w,SOFTRESET_1_w" group.long 0x140++0x03 line.long 0x00 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse" bitfld.long 0x00 0.--1. "EOIVAL,EOI value - B0" "EOIVAL_0,EOIVAL_1,?,?" repeat 5. (list 3. 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x8C++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x4C++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox" rgroup.long 0xCC++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end repeat 3. (list 0. 1. 2. ) tree "Channel_$1" rgroup.long 0x80++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x10C++0x03 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x108++0x03 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x104++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSENUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB15_0_w,NOTFULLSTATUSENUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSENUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB15_0_w,NEWMSGSTATUSENUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSENUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB14_0_w,NOTFULLSTATUSENUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSENUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB14_0_w,NEWMSGSTATUSENUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSENUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB13_0_w,NOTFULLSTATUSENUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSENUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB13_0_w,NEWMSGSTATUSENUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSENUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB12_0_w,NOTFULLSTATUSENUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSENUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB12_0_w,NEWMSGSTATUSENUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSENUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB11_0_w,NOTFULLSTATUSENUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSENUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB11_0_w,NEWMSGSTATUSENUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSENUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB10_0_w,NOTFULLSTATUSENUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSENUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB10_0_w,NEWMSGSTATUSENUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSENUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB9_0_w,NOTFULLSTATUSENUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSENUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB9_0_w,NEWMSGSTATUSENUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSENUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB8_0_w,NOTFULLSTATUSENUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSENUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB8_0_w,NEWMSGSTATUSENUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSENUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB7_0_w,NOTFULLSTATUSENUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSENUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB7_0_w,NEWMSGSTATUSENUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSENUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB6_0_w,NOTFULLSTATUSENUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSENUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB6_0_w,NEWMSGSTATUSENUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSENUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB5_0_w,NOTFULLSTATUSENUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSENUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB5_0_w,NEWMSGSTATUSENUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSENUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB4_0_w,NOTFULLSTATUSENUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSENUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB4_0_w,NEWMSGSTATUSENUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSENUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB3_0_w,NOTFULLSTATUSENUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSENUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB3_0_w,NEWMSGSTATUSENUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSENUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB2_0_w,NOTFULLSTATUSENUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSENUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB2_0_w,NEWMSGSTATUSENUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSENUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB1_0_w,NOTFULLSTATUSENUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSENUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB1_0_w,NEWMSGSTATUSENUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSENUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB0_0_w,NOTFULLSTATUSENUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSENUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB0_0_w,NEWMSGSTATUSENUUMB0_1_w" group.long 0x100++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB15_0_w,NOTFULLSTATUSUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB15_0_w,NEWMSGSTATUSUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB14_0_w,NOTFULLSTATUSUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB14_0_w,NEWMSGSTATUSUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB13_0_w,NOTFULLSTATUSUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB13_0_w,NEWMSGSTATUSUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB12_0_w,NOTFULLSTATUSUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB12_0_w,NEWMSGSTATUSUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB11_0_w,NOTFULLSTATUSUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB11_0_w,NEWMSGSTATUSUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB10_0_w,NOTFULLSTATUSUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB10_0_w,NEWMSGSTATUSUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB9_0_w,NOTFULLSTATUSUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB9_0_w,NEWMSGSTATUSUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB8_0_w,NOTFULLSTATUSUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB8_0_w,NEWMSGSTATUSUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB7_0_w,NOTFULLSTATUSUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB7_0_w,NEWMSGSTATUSUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB6_0_w,NOTFULLSTATUSUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB6_0_w,NEWMSGSTATUSUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB5_0_w,NOTFULLSTATUSUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB5_0_w,NEWMSGSTATUSUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB4_0_w,NOTFULLSTATUSUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB4_0_w,NEWMSGSTATUSUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB3_0_w,NOTFULLSTATUSUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB3_0_w,NEWMSGSTATUSUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB2_0_w,NOTFULLSTATUSUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB2_0_w,NEWMSGSTATUSUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB1_0_w,NOTFULLSTATUSUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB1_0_w,NEWMSGSTATUSUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB0_0_w,NOTFULLSTATUSUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB0_0_w,NEWMSGSTATUSUUMB0_1_w" group.long 0x40++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox" rgroup.long 0xC0++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end tree.end repeat 12. (list 13. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. )(list ad:0x48802000 ad:0x4883A000 ad:0x4883C000 ad:0x4883E000 ad:0x48840000 ad:0x48842000 ad:0x48844000 ad:0x48846000 ad:0x4885E000 ad:0x48860000 ad:0x48862000 ad:0x48864000 ) tree "MAILBOX$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "MAILBOX_REVISION,This register contains the IP revision code" group.long 0x10++0x03 line.long 0x00 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x00 2.--3. "SIDLEMODE,Idle Mode - b00" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Softreset - b0" "SOFTRESET_0_w,SOFTRESET_1_w" group.long 0x140++0x03 line.long 0x00 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse" bitfld.long 0x00 0.--1. "EOIVAL,EOI value - B0" "EOIVAL_0,EOIVAL_1,?,?" repeat 8. (list 4. 5. 6. 7. 8. 9. 10. 11. ) tree "Channel_$1" rgroup.long 0xA8++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x68++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox" rgroup.long 0xE8++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" rgroup.long 0x80++0x03 line.long 0x00 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x00 0. "FIFOFULLMBM,Full flag for Mailbox" "FIFOFULLMBM_0_r,FIFOFULLMBM_1_r" group.long 0x10C++0x03 line.long 0x00 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x108++0x03 line.long 0x00 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user" bitfld.long 0x00 31. "NOTFULLENABLEUUMB15,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB15_0_w,NOTFULLENABLEUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGENABLEUUMB15,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB15_0_w,NEWMSGENABLEUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLENABLEUUMB14,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB14_0_w,NOTFULLENABLEUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGENABLEUUMB14,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB14_0_w,NEWMSGENABLEUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLENABLEUUMB13,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB13_0_w,NOTFULLENABLEUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGENABLEUUMB13,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB13_0_w,NEWMSGENABLEUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLENABLEUUMB12,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB12_0_w,NOTFULLENABLEUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGENABLEUUMB12,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB12_0_w,NEWMSGENABLEUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLENABLEUUMB11,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB11_0_w,NOTFULLENABLEUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGENABLEUUMB11,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB11_0_w,NEWMSGENABLEUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLENABLEUUMB10,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB10_0_w,NOTFULLENABLEUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGENABLEUUMB10,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB10_0_w,NEWMSGENABLEUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLENABLEUUMB9,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB9_0_w,NOTFULLENABLEUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGENABLEUUMB9,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB9_0_w,NEWMSGENABLEUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLENABLEUUMB8,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB8_0_w,NOTFULLENABLEUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGENABLEUUMB8,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB8_0_w,NEWMSGENABLEUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLENABLEUUMB7,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB7_0_w,NOTFULLENABLEUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGENABLEUUMB7,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB7_0_w,NEWMSGENABLEUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLENABLEUUMB6,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB6_0_w,NOTFULLENABLEUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGENABLEUUMB6,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB6_0_w,NEWMSGENABLEUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLENABLEUUMB5,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB5_0_w,NOTFULLENABLEUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGENABLEUUMB5,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB5_0_w,NEWMSGENABLEUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLENABLEUUMB4,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB4_0_w,NOTFULLENABLEUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGENABLEUUMB4,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB4_0_w,NEWMSGENABLEUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLENABLEUUMB3,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB3_0_w,NOTFULLENABLEUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGENABLEUUMB3,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB3_0_w,NEWMSGENABLEUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLENABLEUUMB2,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB2_0_w,NOTFULLENABLEUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGENABLEUUMB2,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB2_0_w,NEWMSGENABLEUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLENABLEUUMB1,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB1_0_w,NOTFULLENABLEUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGENABLEUUMB1,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB1_0_w,NEWMSGENABLEUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLENABLEUUMB0,NotFull Enable bit for User u Mailbox" "NOTFULLENABLEUUMB0_0_w,NOTFULLENABLEUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGENABLEUUMB0,NewMessage Enable bit for User u Mailbox" "NEWMSGENABLEUUMB0_0_w,NEWMSGENABLEUUMB0_1_w" group.long 0x104++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSENUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB15_0_w,NOTFULLSTATUSENUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSENUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB15_0_w,NEWMSGSTATUSENUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSENUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB14_0_w,NOTFULLSTATUSENUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSENUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB14_0_w,NEWMSGSTATUSENUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSENUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB13_0_w,NOTFULLSTATUSENUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSENUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB13_0_w,NEWMSGSTATUSENUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSENUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB12_0_w,NOTFULLSTATUSENUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSENUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB12_0_w,NEWMSGSTATUSENUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSENUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB11_0_w,NOTFULLSTATUSENUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSENUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB11_0_w,NEWMSGSTATUSENUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSENUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB10_0_w,NOTFULLSTATUSENUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSENUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB10_0_w,NEWMSGSTATUSENUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSENUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB9_0_w,NOTFULLSTATUSENUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSENUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB9_0_w,NEWMSGSTATUSENUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSENUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB8_0_w,NOTFULLSTATUSENUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSENUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB8_0_w,NEWMSGSTATUSENUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSENUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB7_0_w,NOTFULLSTATUSENUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSENUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB7_0_w,NEWMSGSTATUSENUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSENUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB6_0_w,NOTFULLSTATUSENUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSENUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB6_0_w,NEWMSGSTATUSENUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSENUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB5_0_w,NOTFULLSTATUSENUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSENUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB5_0_w,NEWMSGSTATUSENUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSENUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB4_0_w,NOTFULLSTATUSENUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSENUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB4_0_w,NEWMSGSTATUSENUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSENUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB3_0_w,NOTFULLSTATUSENUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSENUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB3_0_w,NEWMSGSTATUSENUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSENUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB2_0_w,NOTFULLSTATUSENUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSENUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB2_0_w,NEWMSGSTATUSENUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSENUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB1_0_w,NOTFULLSTATUSENUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSENUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB1_0_w,NEWMSGSTATUSENUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSENUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSENUUMB0_0_w,NOTFULLSTATUSENUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSENUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSENUUMB0_0_w,NEWMSGSTATUSENUUMB0_1_w" group.long 0x100++0x03 line.long 0x00 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit" bitfld.long 0x00 31. "NOTFULLSTATUSUUMB15,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB15_0_w,NOTFULLSTATUSUUMB15_1_w" bitfld.long 0x00 30. "NEWMSGSTATUSUUMB15,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB15_0_w,NEWMSGSTATUSUUMB15_1_w" newline bitfld.long 0x00 29. "NOTFULLSTATUSUUMB14,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB14_0_w,NOTFULLSTATUSUUMB14_1_w" bitfld.long 0x00 28. "NEWMSGSTATUSUUMB14,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB14_0_w,NEWMSGSTATUSUUMB14_1_w" newline bitfld.long 0x00 27. "NOTFULLSTATUSUUMB13,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB13_0_w,NOTFULLSTATUSUUMB13_1_w" bitfld.long 0x00 26. "NEWMSGSTATUSUUMB13,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB13_0_w,NEWMSGSTATUSUUMB13_1_w" newline bitfld.long 0x00 25. "NOTFULLSTATUSUUMB12,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB12_0_w,NOTFULLSTATUSUUMB12_1_w" bitfld.long 0x00 24. "NEWMSGSTATUSUUMB12,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB12_0_w,NEWMSGSTATUSUUMB12_1_w" newline bitfld.long 0x00 23. "NOTFULLSTATUSUUMB11,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB11_0_w,NOTFULLSTATUSUUMB11_1_w" bitfld.long 0x00 22. "NEWMSGSTATUSUUMB11,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB11_0_w,NEWMSGSTATUSUUMB11_1_w" newline bitfld.long 0x00 21. "NOTFULLSTATUSUUMB10,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB10_0_w,NOTFULLSTATUSUUMB10_1_w" bitfld.long 0x00 20. "NEWMSGSTATUSUUMB10,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB10_0_w,NEWMSGSTATUSUUMB10_1_w" newline bitfld.long 0x00 19. "NOTFULLSTATUSUUMB9,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB9_0_w,NOTFULLSTATUSUUMB9_1_w" bitfld.long 0x00 18. "NEWMSGSTATUSUUMB9,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB9_0_w,NEWMSGSTATUSUUMB9_1_w" newline bitfld.long 0x00 17. "NOTFULLSTATUSUUMB8,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB8_0_w,NOTFULLSTATUSUUMB8_1_w" bitfld.long 0x00 16. "NEWMSGSTATUSUUMB8,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB8_0_w,NEWMSGSTATUSUUMB8_1_w" newline bitfld.long 0x00 15. "NOTFULLSTATUSUUMB7,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB7_0_w,NOTFULLSTATUSUUMB7_1_w" bitfld.long 0x00 14. "NEWMSGSTATUSUUMB7,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB7_0_w,NEWMSGSTATUSUUMB7_1_w" newline bitfld.long 0x00 13. "NOTFULLSTATUSUUMB6,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB6_0_w,NOTFULLSTATUSUUMB6_1_w" bitfld.long 0x00 12. "NEWMSGSTATUSUUMB6,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB6_0_w,NEWMSGSTATUSUUMB6_1_w" newline bitfld.long 0x00 11. "NOTFULLSTATUSUUMB5,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB5_0_w,NOTFULLSTATUSUUMB5_1_w" bitfld.long 0x00 10. "NEWMSGSTATUSUUMB5,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB5_0_w,NEWMSGSTATUSUUMB5_1_w" newline bitfld.long 0x00 9. "NOTFULLSTATUSUUMB4,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB4_0_w,NOTFULLSTATUSUUMB4_1_w" bitfld.long 0x00 8. "NEWMSGSTATUSUUMB4,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB4_0_w,NEWMSGSTATUSUUMB4_1_w" newline bitfld.long 0x00 7. "NOTFULLSTATUSUUMB3,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB3_0_w,NOTFULLSTATUSUUMB3_1_w" bitfld.long 0x00 6. "NEWMSGSTATUSUUMB3,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB3_0_w,NEWMSGSTATUSUUMB3_1_w" newline bitfld.long 0x00 5. "NOTFULLSTATUSUUMB2,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB2_0_w,NOTFULLSTATUSUUMB2_1_w" bitfld.long 0x00 4. "NEWMSGSTATUSUUMB2,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB2_0_w,NEWMSGSTATUSUUMB2_1_w" newline bitfld.long 0x00 3. "NOTFULLSTATUSUUMB1,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB1_0_w,NOTFULLSTATUSUUMB1_1_w" bitfld.long 0x00 2. "NEWMSGSTATUSUUMB1,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB1_0_w,NEWMSGSTATUSUUMB1_1_w" newline bitfld.long 0x00 1. "NOTFULLSTATUSUUMB0,NotFull Status bit for User u Mailbox" "NOTFULLSTATUSUUMB0_0_w,NOTFULLSTATUSUUMB0_1_w" bitfld.long 0x00 0. "NEWMSGSTATUSUUMB0,NewMessage Status bit for User u Mailbox" "NEWMSGSTATUSUUMB0_0_w,NEWMSGSTATUSUUMB0_1_w" group.long 0x40++0x03 line.long 0x00 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox" rgroup.long 0xC0++0x03 line.long 0x00 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. "NBOFMSGMBM,Number of unread messages in Mailbox Note: Limited to four messages per mailbox" "0,1,2,3,4,5,6,7" tree.end repeat.end tree.end repeat.end tree.end tree.open "Media_Local_Bus_MLB" tree "MLB" base ad:0x4842C000 rgroup.long 0x00++0x07 line.long 0x00 "MLB_MLBSSREV,Revision Register" line.long 0x04 "MLB_MLBSSPWR,MLBSS Power management Register" bitfld.long 0x04 0. "MSTANDBY,Value to be driven in the MStandby bus of the power management interface Writing a 1 to this bit asserts the MStandby output of MLBSS thereby initiating the clock disabling sequence for the MLBSS" "0,1" group.long 0x100++0x03 line.long 0x00 "MLB_MLBSSPRF,This register is used to define the values of MFLAG pressure to on-chip network. MREQINFO priority to EMIF. and the non-posted write behavior of the L3_MAIN DMA master interface" bitfld.long 0x00 16. "WRNP,The WRNP bit controls whether the writes issued by the DMA OCP interface are posted (no write reponse required to complete transaction) or non posted (write response required to complete transaction)" "0,1" bitfld.long 0x00 12.--14. "ASYNC_PRI,ASYNC_PRI controls the priority carried in MREQINFO attribute of OCP DMA interface when a asynchronous transaction is requested at the DMA interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "SYNC_PRI,SYNC_PRI controls the priority carried in MREQINFO attribute of OCP interface when a synchronous transaction is requested at the DMA interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--5. "ASYNC_FLAG,ASYNC_FLAG controls the value carried in MFLAG attribute of OCP DMA interface" "0,1,2,3" bitfld.long 0x00 0.--1. "SYNC_FLAG,SYNC_FLAG controls the value carried in MFLAG attribute of OCP DMA interface" "0,1,2,3" group.long 0x400++0x03 line.long 0x00 "MLB_MLBC0,MediaLB Control 0 Register" bitfld.long 0x00 15.--17. "FCNT,The number of frames per sub-buffer for synchronous channels" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14. "CTLRETRY,Control Tx packet retry" "0,1" bitfld.long 0x00 12. "ASYRETRY,Asynchronous Tx packet retry" "0,1" rbitfld.long 0x00 7. "MLBLK,MediaLB lock status" "0,1" bitfld.long 0x00 5. "MLBPEN,MediaLB 6-pin enable" "0,1" bitfld.long 0x00 2.--4. "MLBCLK,MediaLB clock speed select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "MLBEN,MediaLB enable" "0,1" group.long 0x40C++0x03 line.long 0x00 "MLB_MS0,MediaLB Channel Status 0 Register" group.long 0x414++0x03 line.long 0x00 "MLB_MS1,MediaLB Channel Status 1 Register" group.long 0x420++0x07 line.long 0x00 "MLB_MSS,MediaLB System Status Register" bitfld.long 0x00 5. "SERVREQ,Service request enabled" "0,1" bitfld.long 0x00 4. "SWSYSCMD,Software system command detected (in the system quadlet)" "0,1" bitfld.long 0x00 3. "CSSYSCMD,Channel scan system command detected (in the system quadlet)" "0,1" bitfld.long 0x00 2. "ULKSYSCMD,Network unlock system command detected (in the system quadlet)" "0,1" bitfld.long 0x00 1. "LKSYSCMD,Network lock system command detected (in the system quadlet)" "0,1" bitfld.long 0x00 0. "RSTSYSCMD,Reset system command detected (in the system quadlet)" "0,1" line.long 0x04 "MLB_MSD,MediaLB System Data Register" hexmask.long.byte 0x04 24.--31. 1. "SD3,System data (byte 3)" hexmask.long.byte 0x04 16.--23. 1. "SD2,System data (byte 2)" hexmask.long.byte 0x04 8.--15. 1. "SD1,System data (byte 1)" hexmask.long.byte 0x04 0.--7. 1. "SD0,System data (byte 0)" group.long 0x42C++0x03 line.long 0x00 "MLB_MIEN,MediaLB Interrupt Enable Register" bitfld.long 0x00 29. "CTX_BREAK,Control Tx break enable" "0,1" bitfld.long 0x00 28. "CTX_PE,Control Tx protocol error enable" "0,1" bitfld.long 0x00 27. "CTX_DONE,Control Tx packet done enable" "0,1" bitfld.long 0x00 26. "CRX_BREAK,Control Rx break enable" "0,1" bitfld.long 0x00 25. "CRX_PE,Control Rx protocol error enable" "0,1" bitfld.long 0x00 24. "CRX_DONE,Control Rx packet done enable" "0,1" bitfld.long 0x00 22. "ATX_BREAK,Asynchronous Tx break enable" "0,1" bitfld.long 0x00 21. "ATX_PE,Asynchronous Tx protocol error enable" "0,1" bitfld.long 0x00 20. "ATX_DONE,Asynchronous Tx packet done enable" "0,1" newline bitfld.long 0x00 19. "ARX_BREAK,Asynchronous Rx break enable" "0,1" bitfld.long 0x00 18. "ARX_PE,Asynchronous Rx protocol error enable" "0,1" bitfld.long 0x00 17. "ARX_DONE,Asynchronous Rx packet done enable" "0,1" bitfld.long 0x00 16. "SYNC_PE,Synchronous protocol error enable" "0,1" bitfld.long 0x00 1. "ISOC_BUFO,Isochronous Rx buffer overflow enable" "0,1" bitfld.long 0x00 0. "ISOC_PE,Isochronous Rx protocol error enable" "0,1" group.long 0x43C++0x03 line.long 0x00 "MLB_MLBC1,MediaLB Control 1 Register" hexmask.long.byte 0x00 8.--15. 1. "NDA,Node device address" bitfld.long 0x00 7. "CLKMERR,MediaLB clock missing status" "0,1" bitfld.long 0x00 6. "LOCKERR,MediaLB lock error status" "0,1" group.long 0x480++0x03 line.long 0x00 "MLB_DIENR,Internal DMA Enable Register" bitfld.long 0x00 15. "EN,DMA enable" "0,1" group.long 0x488++0x07 line.long 0x00 "MLB_DICER0,Internal DMA Channel Enable Register 0" line.long 0x04 "MLB_DICER1,Internal DMA Channel Enable Register 1" group.long 0x4C0++0x27 line.long 0x00 "MLB_MDAT0,Memory Interface Data 0 Register" line.long 0x04 "MLB_MDAT1,Memory Interface Data 1 Register" line.long 0x08 "MLB_MDAT2,Memory Interface Data 2 Register" line.long 0x0C "MLB_MDAT3,Memory Interface Data 3 Register" line.long 0x10 "MLB_MDWE0,Memory Interface Data Write Enable 0 Register" line.long 0x14 "MLB_MDWE1,Memory Interface Data Write Enable 1 Register" line.long 0x18 "MLB_MDWE2,Memory Interface Data Write Enable 2 Register" line.long 0x1C "MLB_MDWE3,Memory Interface Data Write Enable 3 Register" line.long 0x20 "MLB_MCTL,Memory Interface Control Register" bitfld.long 0x20 0. "XCMP,Transfer complete (write 0 to clear)" "0,1" line.long 0x24 "MLB_MADR,Memory Interface Address Register" bitfld.long 0x24 31. "WNR,Write-Not-Read selection" "0,1" hexmask.long.byte 0x24 0.--7. 1. "ADDR,CTR address of 128-bit entry" group.long 0x7C0++0x03 line.long 0x00 "MLB_DCTL,DMA Control Register" bitfld.long 0x00 4. "PKT_MODE,Packet mode for async/control packets" "0,1" bitfld.long 0x00 2. "DMA_MODE,DMA mode" "0,1" bitfld.long 0x00 1. "SMX,DMA interrupt mux enable" "0,1" bitfld.long 0x00 0. "SCE,Software clear enable" "0,1" group.long 0x7D0++0x0F line.long 0x00 "MLB_DCSR0,DMA Control Status 0 Register" line.long 0x04 "MLB_DCSR1,DMA Control Status 1 Register" line.long 0x08 "MLB_DCMR0,DMA Channel Mask 0 Register" line.long 0x0C "MLB_DCMR1,DMA Channel Mask 1 Register" tree.end tree.end tree.open "MMU" tree "EVE1_MMU0_EVE1" base ad:0x40081000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE1_MMU0_L3_MAINInterconnect" base ad:0x42081000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE1_MMU1_EVE1" base ad:0x40082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE1_MMU1_L3_MAINInterconnect" base ad:0x42082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE2_MMU0_EVE2" base ad:0x40081000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE2_MMU0_L3_MAINInterconnect" base ad:0x42181000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE2_MMU1_EVE2" base ad:0x40082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE2_MMU1_L3_MAINInterconnect" base ad:0x42182000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE3_MMU0_EVE3" base ad:0x40081000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE3_MMU0_L3_MAINInterconnect" base ad:0x42281000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE3_MMU1_EVE3" base ad:0x40082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE3_MMU1_L3_MAINInterconnect" base ad:0x42282000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE4_MMU0_EVE4" base ad:0x40081000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE4_MMU0_L3_MAINInterconnect" base ad:0x42381000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE4_MMU1_EVE4" base ad:0x40082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EVE4_MMU1_L3_MAINInterconnect" base ad:0x42382000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "IPU1_MMU_IPU1" base ad:0x55082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "IPU1_MMU_L3_MAINInterconnect" base ad:0x58882000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "IPU2_MMU_IPU2" base ad:0x55082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "IPU2_MMU_L3_MAINInterconnect" base ad:0x55082000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "SYS_MMU1_L3_MAINInterconnect" base ad:0x4881C000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "SYS_MMU2_L3_MAINInterconnect" base ad:0x4881E000 rgroup.long 0x00++0x03 line.long 0x00 "MMU_REVISION,This register contains the IP revision code" group.long 0x10++0x0F line.long 0x00 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clock activity during wake-up mode" "CLOCKACTIVITY_0,?,?,?" bitfld.long 0x00 3.--4. "IDLEMODE,Idle mode - SFIDLE" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_w" newline bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy - CLKFREE" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MMU_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - RSTONGOING" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - NMHF_R" "MULTIHITFAULT_0_w,MULTIHITFAULT_1_r" bitfld.long 0x08 3. "TABLEWALKFAULT,Error response received during a Table Walk - NTWF_R" "TABLEWALKFAULT_0_w,TABLEWALKFAULT_1_r" bitfld.long 0x08 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - NEMUM_R" "EMUMISS_0_w,EMUMISS_1_r" newline bitfld.long 0x08 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - NFAULT_R" "TRANSLATIONFAULT_0_w,TRANSLATIONFAULT_1_r" bitfld.long 0x08 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - NTLBM_R" "TLBMISS_0_w,TLBMISS_1_r" line.long 0x0C "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis" bitfld.long 0x0C 4. "MULTIHITFAULT,Error due to multiple matches in the TLB - MHFLTMASK" "MULTIHITFAULT_0,MULTIHITFAULT_1" bitfld.long 0x0C 3. "TABLEWALKFAULT,Error response received during a Table Walk - TWLFLTMASK" "TABLEWALKFAULT_0,TABLEWALKFAULT_1" bitfld.long 0x0C 2. "EMUMISS,Unrecoverable TLB miss during debug (hardware TWL disabled) - EMUMFLTMASK" "EMUMISS_0,EMUMISS_1" newline bitfld.long 0x0C 1. "TRANSLATIONFAULT,Invalid descriptor in translation tables (translation fault) - TRANFLTMASK" "TRANSLATIONFAULT_0,TRANSLATIONFAULT_1" bitfld.long 0x0C 0. "TLBMISS,Unrecoverable TLB miss (hardware TWL disabled) - TRMISSINTM" "TLBMISS_0,TLBMISS_1" rgroup.long 0x40++0x33 line.long 0x00 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x00 0. "TWLRUNNING,Table Walking Logic is running - TWLCOMP" "TWLRUNNING_0_r,TWLRUNNING_1_r" line.long 0x04 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x04 3. "EMUTLBUPDATE,Enable TLB update on emulator table walk - EMUDIS" "EMUTLBUPDATE_0,EMUTLBUPDATE_1" bitfld.long 0x04 2. "TWLENABLE,Table Walking Logic enable - TWLDIS" "TWLENABLE_0,TWLENABLE_1" bitfld.long 0x04 1. "MMUENABLE,MMU enable - MMUDIS" "MMUENABLE_0,MMUENABLE_1" line.long 0x08 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" line.long 0x0C "MMU_TTB,This register contains the Translation Table Base address" hexmask.long 0x0C 7.--31. 1. "TTBADDRESS,Translation Table Base Address" line.long 0x10 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x10 10.--14. "BASEVALUE,Locked entries base value" "BASEVALUE_0,BASEVALUE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x10 4.--8. "CURRENTVICTIM,Current entry to be updated either by the TWL or by the software" "CURRENTVICTIM_0,CURRENTVICTIM_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x14 0. "LDTLBITEM,Write (load) data in the TLB" "LDTLBITEM_0_w,LDTLBITEM_1_w" line.long 0x18 "MMU_CAM,This register holds a CAM entry" hexmask.long.tbyte 0x18 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x18 3. "P,Preserved bit - CANFLUSH" "P_0,P_1" bitfld.long 0x18 2. "V,Valid bit - INVALID" "V_0,V_1" newline bitfld.long 0x18 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0,PAGESIZE_1,PAGESIZE_2,PAGESIZE_3" line.long 0x1C "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register" hexmask.long.tbyte 0x1C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x20 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x20 0. "GLOBALFLUSH,Flush all the non-protected TLB entries when set" "GLOBALFLUSH_0_w,GLOBALFLUSH_1_w" line.long 0x24 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x24 0. "FLUSHENTRY,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register even if this entry is set protected" "FLUSHENTRY_0_w,FLUSHENTRY_1_w" line.long 0x28 "MMU_READ_CAM,This register reads CAM data from a CAM entry" hexmask.long.tbyte 0x28 12.--31. 1. "VATAG,Virtual address tag" bitfld.long 0x28 3. "P,Preserved bit - CANFLUSH" "P_0_r,P_1_r" bitfld.long 0x28 2. "V,Valid bit - INVALID" "V_0_r,V_1_r" newline bitfld.long 0x28 0.--1. "PAGESIZE,Page size - SECTION" "PAGESIZE_0_r,PAGESIZE_1_r,PAGESIZE_2_r,PAGESIZE_3_r" line.long 0x2C "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register" hexmask.long.tbyte 0x2C 12.--31. 1. "PHYSICALADDRESS,Physical address of the page" line.long 0x30 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" rgroup.long 0x80++0x0B line.long 0x00 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault" line.long 0x04 "MMU_FAULT_STATUS,Fault status register" rbitfld.long 0x04 4.--8. "MMU_FAULT_TRANS_ID,MtagID of the transaction that caused fault" "MMU_FAULT_TRANS_ID_0,MMU_FAULT_TRANS_ID_1,MMU_FAULT_TRANS_ID_2,MMU_FAULT_TRANS_ID_3,MMU_FAULT_TRANS_ID_4,MMU_FAULT_TRANS_ID_5,MMU_FAULT_TRANS_ID_6,MMU_FAULT_TRANS_ID_7,MMU_FAULT_TRANS_ID_8,MMU_FAULT_TRANS_ID_9,MMU_FAULT_TRANS_ID_10,MMU_FAULT_TRANS_ID_11,MMU_FAULT_TRANS_ID_12,MMU_FAULT_TRANS_ID_13,MMU_FAULT_TRANS_ID_14,MMU_FAULT_TRANS_ID_15,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x04 3. "RD_WR,Indicates read or write" "RD_WR_0,RD_WR_1" rbitfld.long 0x04 1.--2. "MMU_FAULT_TYPE,MReqInfo[1:0] is captured as fault type" "MMU_FAULT_TYPE_0,MMU_FAULT_TYPE_1,MMU_FAULT_TYPE_2,MMU_FAULT_TYPE_3" newline bitfld.long 0x04 0. "FAULTINDICATION,Indicates an MMU fault" "FAULTINDICATION_0,FAULTINDICATION_1" line.long 0x08 "MMU_GPR,General purpose register" hexmask.long.word 0x08 16.--31. 1. "GPO,General purpose output sent out as MMU output" bitfld.long 0x08 0. "FAULT_INTR_DIS,Disable generation of interrupt on fault" "0,1" group.long 0x90++0x1F line.long 0x00 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x00 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x04 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x04 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x08 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x0C "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x10 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x14 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x14 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x18 16.--31. 1. "START_ADDR,Start address of NO TRANSLATION REGION for 2D bursts" line.long 0x1C "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x1C 0.--3. "SIZE,Size of the NO TRANSLATION REGION of 2D bursts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end tree.open "Multichannel_Audio_Serial_Ports" tree "McASP1_CFG" base ad:0x48460000 group.long 0x1000++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count (32-bit) to generate TX event to host" hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count (32-bit words)" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.byte 0x04 0.--7. 1. "WLVL,Write level (read-only)" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" hexmask.long.byte 0x08 8.--15. 1. "RNUMEVT,Read word count (32-bit) to generate RX event to host" hexmask.long.byte 0x08 0.--7. 1. "RNUMDMA,Read word count (32-bit words)" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0C 0.--7. 1. "RLVL,Read level (read-only)" tree.end tree "McASP2_CFG" base ad:0x48464000 group.long 0x1000++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count (32-bit) to generate TX event to host" hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count (32-bit words)" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.byte 0x04 0.--7. 1. "WLVL,Write level (read-only)" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" hexmask.long.byte 0x08 8.--15. 1. "RNUMEVT,Read word count (32-bit) to generate RX event to host" hexmask.long.byte 0x08 0.--7. 1. "RNUMDMA,Read word count (32-bit words)" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0C 0.--7. 1. "RLVL,Read level (read-only)" tree.end tree "McASP3_CFG" base ad:0x48468000 group.long 0x1000++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count (32-bit) to generate TX event to host" hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count (32-bit words)" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.byte 0x04 0.--7. 1. "WLVL,Write level (read-only)" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" hexmask.long.byte 0x08 8.--15. 1. "RNUMEVT,Read word count (32-bit) to generate RX event to host" hexmask.long.byte 0x08 0.--7. 1. "RNUMDMA,Read word count (32-bit words)" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0C 0.--7. 1. "RLVL,Read level (read-only)" tree.end tree "McASP4_CFG" base ad:0x4846C000 group.long 0x1000++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count (32-bit) to generate TX event to host" hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count (32-bit words)" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.byte 0x04 0.--7. 1. "WLVL,Write level (read-only)" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" hexmask.long.byte 0x08 8.--15. 1. "RNUMEVT,Read word count (32-bit) to generate RX event to host" hexmask.long.byte 0x08 0.--7. 1. "RNUMDMA,Read word count (32-bit words)" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0C 0.--7. 1. "RLVL,Read level (read-only)" tree.end tree "McASP5_CFG" base ad:0x48470000 group.long 0x1000++0x0F line.long 0x00 "WFIFOCTL,The Write FIFO control register" bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "WENA_0,WENA_1" hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count (32-bit) to generate TX event to host" hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count (32-bit words)" line.long 0x04 "WFIFOSTS,The Write FIFO status register" hexmask.long.byte 0x04 0.--7. 1. "WLVL,Write level (read-only)" line.long 0x08 "RFIFOCTL,The Read FIFO control register" bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "RENA_0,RENA_1" hexmask.long.byte 0x08 8.--15. 1. "RNUMEVT,Read word count (32-bit) to generate RX event to host" hexmask.long.byte 0x08 0.--7. 1. "RNUMDMA,Read word count (32-bit words)" line.long 0x0C "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0C 0.--7. 1. "RLVL,Read level (read-only)" tree.end tree "McASP1_DAT" base ad:0x45800000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" tree.end tree "McASP2_DAT" base ad:0x45C00000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" tree.end tree "McASP3_DAT" base ad:0x46000000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" tree.end tree "McASP4_DAT" base ad:0x48436000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" tree.end tree "McASP5_DAT" base ad:0x4843A000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" tree.end tree "McASP6_DAT" base ad:0x4844C000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" tree.end tree "McASP7_DAT" base ad:0x48450000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" tree.end tree "McASP8_DAT" base ad:0x48454000 rgroup.long 0x00++0x03 line.long 0x00 "MCASP_RXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" group.long 0x00++0x03 line.long 0x00 "MCASP_TXBUF,Through the DATA port . the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers" tree.end tree "McASP6_CFG" base ad:0x48474000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" hexmask.long.word 0x00 16.--27. 1. "FUNCTION,McASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" newline bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x04 0.--1. "IDLE_MODE," "IDLE_MODE_0,IDLE_MODE_1,IDLE_MODE_2,IDLE_MODE_3" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level mcaspx_axr[15] signal) functions as McASP or GPIO" "AXR15_0,AXR15_1" bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level mcaspx_axr[14] signal) functions as McASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level mcaspx_axr[13] signal) functions as McASP or GPIO" "AXR13_0,AXR13_1" bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level mcaspx_axr[12] signal) functions as McASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level mcaspx_axr[11] signal) functions as McASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level mcaspx_axr[10] signal) functions as McASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level mcaspx_axr[9] signal) functions as McASP or GPIO" "AXR9_0,AXR9_1" bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level mcaspx_axr[8] signal) functions as McASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level mcaspx_axr[7] signal) functions as McASP or GPIO" "AXR7_0,AXR7_1" bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level mcaspx_axr[6] signal) functions as McASP or GPIO" "AXR6_0,AXR6_1" newline bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level mcaspx_axr[5] signal) functions as McASP or GPIO" "AXR5_0,AXR5_1" bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level mcaspx_axr[4] signal) functions as McASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level mcaspi_axr[3] signal) functions as McASP or GPIO" "AXR3_0,AXR3_1" bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level mcaspi_axr[2] signal) functions as McASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level mcaspi_axr[1] signal) functions as McASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level mcaspi_axr[0] signal) functions as McASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the McASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" newline bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" newline bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the McASP mute output pin - AMUTE (device level - not implemented)" group.long 0x4C++0x07 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (McASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x04 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the McASP" bitfld.long 0x04 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x04 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x04 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "CLKRADJ_0,CLKRADJ_1,CLKRADJ_2,CLKRADJ_3" bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "HCLKRADJ_0,HCLKRADJ_1,HCLKRADJ_2,HCLKRADJ_3" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the McASP receive interrupt (RINT)" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" newline rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame-sync mode select bits" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "CLKXADJ_0,CLKXADJ_1,CLKXADJ_2,CLKXADJ_3" bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" newline bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "CLKXDIV_0,CLKXDIV_1,CLKXDIV_2,CLKXDIV_3,CLKXDIV_4,CLKXDIV_5,CLKXDIV_6,CLKXDIV_7,CLKXDIV_8,CLKXDIV_9,CLKXDIV_10,CLKXDIV_11,CLKXDIV_12,CLKXDIV_13,CLKXDIV_14,CLKXDIV_15,CLKXDIV_16,CLKXDIV_17,CLKXDIV_18,CLKXDIV_19,CLKXDIV_20,CLKXDIV_21,CLKXDIV_22,CLKXDIV_23,CLKXDIV_24,CLKXDIV_25,CLKXDIV_26,CLKXDIV_27,CLKXDIV_28,CLKXDIV_29,CLKXDIV_30,CLKXDIV_31" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "HCLKXADJ_0,HCLKXADJ_1,HCLKXADJ_2,HCLKXADJ_3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority and the flag remains set" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "XPS_0,XPS_1,XPS_2,XPS_3,XPS_4,XPS_5,XPS_6,XPS_7,XPS_8,XPS_9,XPS_10,XPS_11,XPS_12,XPS_13,XPS_14,XPS_15" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable - DISABLE" "ENABLE_0,ENABLE_1" repeat 2. (list 4. 5. ) tree "Channel_$1" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end repeat.end tree.end tree "McASP7_CFG" base ad:0x48478000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" hexmask.long.word 0x00 16.--27. 1. "FUNCTION,McASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" newline bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x04 0.--1. "IDLE_MODE," "IDLE_MODE_0,IDLE_MODE_1,IDLE_MODE_2,IDLE_MODE_3" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level mcaspx_axr[15] signal) functions as McASP or GPIO" "AXR15_0,AXR15_1" bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level mcaspx_axr[14] signal) functions as McASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level mcaspx_axr[13] signal) functions as McASP or GPIO" "AXR13_0,AXR13_1" bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level mcaspx_axr[12] signal) functions as McASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level mcaspx_axr[11] signal) functions as McASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level mcaspx_axr[10] signal) functions as McASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level mcaspx_axr[9] signal) functions as McASP or GPIO" "AXR9_0,AXR9_1" bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level mcaspx_axr[8] signal) functions as McASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level mcaspx_axr[7] signal) functions as McASP or GPIO" "AXR7_0,AXR7_1" bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level mcaspx_axr[6] signal) functions as McASP or GPIO" "AXR6_0,AXR6_1" newline bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level mcaspx_axr[5] signal) functions as McASP or GPIO" "AXR5_0,AXR5_1" bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level mcaspx_axr[4] signal) functions as McASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level mcaspi_axr[3] signal) functions as McASP or GPIO" "AXR3_0,AXR3_1" bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level mcaspi_axr[2] signal) functions as McASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level mcaspi_axr[1] signal) functions as McASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level mcaspi_axr[0] signal) functions as McASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the McASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" newline bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" newline bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the McASP mute output pin - AMUTE (device level - not implemented)" group.long 0x4C++0x07 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (McASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x04 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the McASP" bitfld.long 0x04 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x04 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x04 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "CLKRADJ_0,CLKRADJ_1,CLKRADJ_2,CLKRADJ_3" bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "HCLKRADJ_0,HCLKRADJ_1,HCLKRADJ_2,HCLKRADJ_3" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the McASP receive interrupt (RINT)" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" newline rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame-sync mode select bits" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "CLKXADJ_0,CLKXADJ_1,CLKXADJ_2,CLKXADJ_3" bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" newline bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "CLKXDIV_0,CLKXDIV_1,CLKXDIV_2,CLKXDIV_3,CLKXDIV_4,CLKXDIV_5,CLKXDIV_6,CLKXDIV_7,CLKXDIV_8,CLKXDIV_9,CLKXDIV_10,CLKXDIV_11,CLKXDIV_12,CLKXDIV_13,CLKXDIV_14,CLKXDIV_15,CLKXDIV_16,CLKXDIV_17,CLKXDIV_18,CLKXDIV_19,CLKXDIV_20,CLKXDIV_21,CLKXDIV_22,CLKXDIV_23,CLKXDIV_24,CLKXDIV_25,CLKXDIV_26,CLKXDIV_27,CLKXDIV_28,CLKXDIV_29,CLKXDIV_30,CLKXDIV_31" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "HCLKXADJ_0,HCLKXADJ_1,HCLKXADJ_2,HCLKXADJ_3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority and the flag remains set" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "XPS_0,XPS_1,XPS_2,XPS_3,XPS_4,XPS_5,XPS_6,XPS_7,XPS_8,XPS_9,XPS_10,XPS_11,XPS_12,XPS_13,XPS_14,XPS_15" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable - DISABLE" "ENABLE_0,ENABLE_1" repeat 2. (list 4. 5. ) tree "Channel_$1" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end repeat.end tree.end tree "McASP8_CFG" base ad:0x4847C000 rgroup.long 0x00++0x07 line.long 0x00 "MCASP_PID,Peripheral identification register" bitfld.long 0x00 30.--31. "SCHEME,Scheme" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" bitfld.long 0x00 28.--29. "RESV,Reserved" "RESV_0,RESV_1,RESV_2,RESV_3" hexmask.long.word 0x00 16.--27. 1. "FUNCTION,McASP" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" bitfld.long 0x00 8.--10. "REVMAJOR,Major revision number" "REVMAJOR_0,REVMAJOR_1,REVMAJOR_2,REVMAJOR_3,REVMAJOR_4,REVMAJOR_5,REVMAJOR_6,REVMAJOR_7" newline bitfld.long 0x00 6.--7. "CUSTOM,Non-custom" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" bitfld.long 0x00 0.--5. "REVMINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PWRIDLESYSCONFIG,Power idle module configuration register" bitfld.long 0x04 2.--5. "OTHER,Reserved for future expansion" "OTHER_0,OTHER_1,OTHER_2,OTHER_3,OTHER_4,OTHER_5,OTHER_6,OTHER_7,OTHER_8,OTHER_9,OTHER_10,OTHER_11,OTHER_12,OTHER_13,OTHER_14,OTHER_15" bitfld.long 0x04 0.--1. "IDLE_MODE," "IDLE_MODE_0,IDLE_MODE_1,IDLE_MODE_2,IDLE_MODE_3" group.long 0x10++0x0F line.long 0x00 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x00 31. "AFSR,Determines if AFSR pin (device level mcaspi_fsr signal) functions as MCASP or GPIO" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin (device level mcaspi_aclkr signal) functions as MCASP or GPIO" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Determines if AFSX pin (device level mcaspi_fsx signal) functions as MCASP or GPIO" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin (device level mcaspi_ahclkx signal) functions as MCASP or GPIO" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin (device level mcaspi_aclkx signal) functions as MCASP or GPIO" "ACLKX_0,ACLKX_1" newline bitfld.long 0x00 15. "AXR15,Determines if AXR15 pin (device level mcaspx_axr[15] signal) functions as McASP or GPIO" "AXR15_0,AXR15_1" bitfld.long 0x00 14. "AXR14,Determines if AXR14 pin (device level mcaspx_axr[14] signal) functions as McASP or GPIO" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Determines if AXR13 pin (device level mcaspx_axr[13] signal) functions as McASP or GPIO" "AXR13_0,AXR13_1" bitfld.long 0x00 12. "AXR12,Determines if AXR12 pin (device level mcaspx_axr[12] signal) functions as McASP or GPIO" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Determines if AXR11 pin (device level mcaspx_axr[11] signal) functions as McASP or GPIO" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Determines if AXR10 pin (device level mcaspx_axr[10] signal) functions as McASP or GPIO" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Determines if AXR9 pin (device level mcaspx_axr[9] signal) functions as McASP or GPIO" "AXR9_0,AXR9_1" bitfld.long 0x00 8. "AXR8,Determines if AXR8 pin (device level mcaspx_axr[8] signal) functions as McASP or GPIO" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Determines if AXR7 pin (device level mcaspx_axr[7] signal) functions as McASP or GPIO" "AXR7_0,AXR7_1" bitfld.long 0x00 6. "AXR6,Determines if AXR6 pin (device level mcaspx_axr[6] signal) functions as McASP or GPIO" "AXR6_0,AXR6_1" newline bitfld.long 0x00 5. "AXR5,Determines if AXR5 pin (device level mcaspx_axr[5] signal) functions as McASP or GPIO" "AXR5_0,AXR5_1" bitfld.long 0x00 4. "AXR4,Determines if AXR4 pin (device level mcaspx_axr[4] signal) functions as McASP or GPIO" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Determines if AXR3 pin (device level mcaspi_axr[3] signal) functions as McASP or GPIO" "AXR3_0,AXR3_1" bitfld.long 0x00 2. "AXR2,Determines if AXR2 pin (device level mcaspi_axr[2] signal) functions as McASP or GPIO" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Determines if AXR1 pin (device level mcaspi_axr[1] signal) functions as McASP or GPIO" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Determines if AXR0 pin (device level mcaspi_axr[0] signal) functions as McASP or GPIO" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin" bitfld.long 0x04 31. "AFSR,Determines if AFSR pin (device level mcaspi_fsr signal) functions as an input or output" "AFSR_0,AFSR_1" bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin (device level mcaspi_aclkr signal) functions as an input or output" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Determines if AFSX pin (device level mcaspi_fsx signal) functions as an input or output" "AFSX_0,AFSX_1" bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin (device level mcaspi_ahclkx signal) functions as an input or output" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin (device level mcaspi_aclkx signal) functions as an input or output" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Determines if AXR15 pin (device level mcaspi_axr[15] signal) functions as an input or output" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Determines if AXR14 pin (device level mcaspi_axr[14] signal) functions as an input or output" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Determines if AXR13 pin (device level mcaspi_axr[13] signal) functions as an input or output" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Determines if AXR12 pin (device level mcaspi_axr[12] signal) functions as an input or output" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Determines if AXR11 pin (device level mcaspi_axr[11] signal) functions as an input or output" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Determines if AXR10 pin (device level mcaspi_axr[10] signal) functions as an input or output" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Determines if AXR9 pin (device level mcaspi_axr[9] signal) functions as an input or output" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Determines if AXR8 pin (device level mcaspi_axr[8] signal) functions as an input or output" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Determines if AXR7 pin (device level mcaspi_axr[7] signal) functions as an input or output" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Determines if AXR6 pin (device level mcaspi_axr[6] signal) functions as an input or output" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Determines if AXR5 pin (device level mcaspi_axr[5] signal) functions as an input or output" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Determines if AXR4 pin (device level mcaspi_axr[4] signal) functions as an input or output" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Determines if AXR3 pin (device level mcaspi_axr[3] signal) functions as an input or output" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Determines if AXR2 pin (device level mcaspi_axr[2] signal) functions as an input or output" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Determines if AXR1 pin (device level mcaspi_axr[1] signal) functions as an input or output" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Determines if AXR0 pin (device level mcaspi_axr[0] signal) functions as an input or output" "AXR0_0,AXR0_1" line.long 0x08 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times. and may be read back at all times" bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1" "AFSR_0,AFSR_1" bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1" "AHCLKR_0,AHCLKR_1" bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to" "ACLKR_0,ACLKR_1" bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1" "AFSX_0,AFSX_1" bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1" "AHCLKX_0,AHCLKX_1" newline bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to" "ACLKX_0,ACLKX_1" bitfld.long 0x08 15. "AXR15,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1" "AXR15_0,AXR15_1" bitfld.long 0x08 14. "AXR14,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1" "AXR14_0,AXR14_1" bitfld.long 0x08 13. "AXR13,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1" "AXR13_0,AXR13_1" bitfld.long 0x08 12. "AXR12,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1" "AXR12_0,AXR12_1" newline bitfld.long 0x08 11. "AXR11,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1" "AXR11_0,AXR11_1" bitfld.long 0x08 10. "AXR10,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1" "AXR10_0,AXR10_1" bitfld.long 0x08 9. "AXR9,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1" "AXR9_0,AXR9_1" bitfld.long 0x08 8. "AXR8,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1" "AXR8_0,AXR8_1" bitfld.long 0x08 7. "AXR7,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1" "AXR7_0,AXR7_1" newline bitfld.long 0x08 6. "AXR6,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1" "AXR6_0,AXR6_1" bitfld.long 0x08 5. "AXR5,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1" "AXR5_0,AXR5_1" bitfld.long 0x08 4. "AXR4,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1" "AXR4_0,AXR4_1" bitfld.long 0x08 3. "AXR3,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1" "AXR3_0,AXR3_1" bitfld.long 0x08 2. "AXR2,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1" "AXR2_0,AXR2_1" newline bitfld.long 0x08 1. "AXR1,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1" "AXR1_0,AXR1_1" bitfld.long 0x08 0. "AXR0,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1" "AXR0_0,AXR0_1" line.long 0x0C "MCASP_PDIN,Pin data input register - holds the state of all the McASP pins" bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin (device level mcaspi_fsr signal)" "AFSR_0,AFSR_1" bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin (device level mcaspi_aclkr signal)" "ACLKR_0,ACLKR_1" bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin (device level mcaspi_fsx signal)" "AFSX_0,AFSX_1" bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin (device level mcaspi_ahclkx signal)" "AHCLKX_0,AHCLKX_1" bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin (device level mcaspi_aclkx signal)" "ACLKX_0,ACLKX_1" newline bitfld.long 0x0C 15. "AXR15,Logic level on AXR15 pin (device level mcaspi_axr[15] signal)" "AXR15_0,AXR15_1" bitfld.long 0x0C 14. "AXR14,Logic level on AXR14 pin (device level mcaspi_axr[14] signal)" "AXR14_0,AXR14_1" bitfld.long 0x0C 13. "AXR13,Logic level on AXR13 pin (device level mcaspi_axr[13] signal)" "AXR13_0,AXR13_1" bitfld.long 0x0C 12. "AXR12,Logic level on AXR12 pin (device level mcaspi_axr[12] signal)" "AXR12_0,AXR12_1" bitfld.long 0x0C 11. "AXR11,Logic level on AXR11 pin (device level mcaspi_axr[11] signal)" "AXR11_0,AXR11_1" newline bitfld.long 0x0C 10. "AXR10,Logic level on AXR10 pin (device level mcaspi_axr[10] signal)" "AXR10_0,AXR10_1" bitfld.long 0x0C 9. "AXR9,Logic level on AXR9 pin (device level mcaspi_axr[9] signal)" "AXR9_0,AXR9_1" bitfld.long 0x0C 8. "AXR8,Logic level on AXR8 pin (device level mcaspi_axr[8] signal)" "AXR8_0,AXR8_1" bitfld.long 0x0C 7. "AXR7,Logic level on AXR7 pin (device level mcaspi_axr[7] signal)" "AXR7_0,AXR7_1" bitfld.long 0x0C 6. "AXR6,Logic level on AXR6 pin (device level mcaspi_axr[6] signal)" "AXR6_0,AXR6_1" newline bitfld.long 0x0C 5. "AXR5,Logic level on AXR5 pin (device level mcaspi_axr[5] signal)" "AXR5_0,AXR5_1" bitfld.long 0x0C 4. "AXR4,Logic level on AXR4 pin (device level mcaspi_axr[4] signal)" "AXR4_0,AXR4_1" bitfld.long 0x0C 3. "AXR3,Logic level on AXR3 pin (device level mcaspi_axr[3] signal)" "AXR3_0,AXR3_1" bitfld.long 0x0C 2. "AXR2,Logic level on AXR2 pin (device level mcaspi_axr[2] signal)" "AXR2_0,AXR2_1" bitfld.long 0x0C 1. "AXR1,Logic level on AXR1 pin (device level mcaspi_axr[1] signal)" "AXR1_0,AXR1_1" newline bitfld.long 0x0C 0. "AXR0,Logic level on AXR0 pin (device level mcaspi_axr[0] signal)" "AXR0_0,AXR0_1" group.long 0x1C++0x07 line.long 0x00 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only" bitfld.long 0x00 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x00 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x00 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x00 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x00 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline bitfld.long 0x00 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" bitfld.long 0x00 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x00 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" bitfld.long 0x00 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x00 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x00 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x00 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" bitfld.long 0x00 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x00 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" bitfld.long 0x00 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" newline bitfld.long 0x00 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" bitfld.long 0x00 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x00 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" bitfld.long 0x00 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x00 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x00 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" line.long 0x04 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only" bitfld.long 0x04 31. "AFSR,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSR_0,AFSR_1" bitfld.long 0x04 29. "ACLKR,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKR_0,ACLKR_1" bitfld.long 0x04 28. "AFSX,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AFSX_0,AFSX_1" bitfld.long 0x04 27. "AHCLKX,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AHCLKX_0,AHCLKX_1" bitfld.long 0x04 26. "ACLKX,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "ACLKX_0,ACLKX_1" newline bitfld.long 0x04 15. "AXR15,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR15_0,AXR15_1" bitfld.long 0x04 14. "AXR14,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR14_0,AXR14_1" bitfld.long 0x04 13. "AXR13,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR13_0,AXR13_1" bitfld.long 0x04 12. "AXR12,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR12_0,AXR12_1" bitfld.long 0x04 11. "AXR11,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR11_0,AXR11_1" newline bitfld.long 0x04 10. "AXR10,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR10_0,AXR10_1" bitfld.long 0x04 9. "AXR9,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR9_0,AXR9_1" bitfld.long 0x04 8. "AXR8,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR8_0,AXR8_1" bitfld.long 0x04 7. "AXR7,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR7_0,AXR7_1" bitfld.long 0x04 6. "AXR6,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR6_0,AXR6_1" newline bitfld.long 0x04 5. "AXR5,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR5_0,AXR5_1" bitfld.long 0x04 4. "AXR4,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR4_0,AXR4_1" bitfld.long 0x04 3. "AXR3,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR3_0,AXR3_1" bitfld.long 0x04 2. "AXR2,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR2_0,AXR2_1" bitfld.long 0x04 1. "AXR1,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR1_0,AXR1_1" newline bitfld.long 0x04 0. "AXR0,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "AXR0_0,AXR0_1" group.long 0x44++0x03 line.long 0x00 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections" bitfld.long 0x00 12. "XFRST,Transmit frame-sync generator reset enable bit - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,Transmit state-machine reset enable bit - RESET" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit - RESET" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit - RESET" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "RFRST_0,RFRST_1" bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "RSRCLR_0,RSRCLR_1" bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "RCLKRST_0,RCLKRST_1" hgroup.long 0x48++0x03 hide.long 0x00 "MCASP_AMUTE,Mute control register - Controls the McASP mute output pin - AMUTE (device level - not implemented)" group.long 0x4C++0x07 line.long 0x00 "MCASP_LBCTL,The digital loopback control register () controls the internal (McASP module)- level and chip-level loopback settings of the MCASP in TDM mode" bitfld.long 0x00 4. "IOLBEN,If DLBEN=0b1 the IOLBEN bit selects between and loopback modes" "IOLBEN_0,IOLBEN_1" bitfld.long 0x00 2.--3. "MODE,Loopback generator mode bits" "MODE_0,MODE_1,?,?" bitfld.long 0x00 1. "ORD,Loopback order bit when loopback mode is enabled (DLBEN = 1)" "ORD_0,ORD_1" bitfld.long 0x00 0. "DLBEN,Loop back mode enable bit" "DLBEN_0,DLBEN_1" line.long 0x04 "MCASP_TXDITCTL,Transmit DIT mode control register. controls DIT operations of the McASP" bitfld.long 0x04 3. "VB,Valid bit for odd time slots (DIT right subframe)" "VB_0,VB_1" bitfld.long 0x04 2. "VA,Valid bit for even time slots (DIT left subframe)" "VA_0,VA_1" bitfld.long 0x04 0. "DITEN,DIT mode enable bit - I2S" "DITEN_0,DITEN_1" group.long 0x60++0x2F line.long 0x00 "MCASP_GBLCTLR,Alias of GBLCTL" rbitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" rbitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" rbitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" rbitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" rbitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" newline bitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" bitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" bitfld.long 0x00 2. "RSRCLR,RCV serializer clear - CLEAR" "RSRCLR_0,RSRCLR_1" bitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" bitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU" line.long 0x08 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format" bitfld.long 0x08 16.--17. "RDATDLY,Receive Frame sync delay of AXR[n] - 0BIT" "RDATDLY_0,RDATDLY_1,RDATDLY_2,RDATDLY_3" bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order - LSBFIRST" "RRVRS_0,RRVRS_1" bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "RPAD_0,RPAD_1,RPAD_2,RPAD_3" bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits" "RPBIT_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "RSSZ,Receive slot size.0x0" "?,?,?,RSSZ_3,RSSZ_4,RSSZ_5,RSSZ_6,RSSZ_7,RSSZ_8,RSSZ_9,RSSZ_10,RSSZ_11,RSSZ_12,RSSZ_13,RSSZ_14,RSSZ_15" newline bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port" "RBUSEL_0,RBUSEL_1" bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "RROT_0,RROT_1,RROT_2,RROT_3,RROT_4,RROT_5,RROT_6,RROT_7" line.long 0x0C "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)" hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select" bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "FRWID_0,FRWID_1" bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "FSRM_0,FSRM_1" bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "FSRP_0,FSRP_1" line.long 0x10 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "CLKRADJ_0,CLKRADJ_1,CLKRADJ_2,CLKRADJ_3" bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "CLKRP_0,CLKRP_1" newline bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "CLKRM_0,CLKRM_1" bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "CLKRDIV_0,CLKRDIV_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x14 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "HCLKRADJ_0,HCLKRADJ_1,HCLKRADJ_2,HCLKRADJ_3" bitfld.long 0x14 15. "HCLKRM,High Freq" "HCLKRM_0,HCLKRM_1" newline bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "HCLKRP_0,HCLKRP_1" hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" line.long 0x18 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active" line.long 0x1C "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the McASP receive interrupt (RINT)" bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit - ENABLE" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x1C 5. "RDATA,Receive data-ready interrupt enable bit - ENABLE" "RDATA_0,RDATA_1" bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit - ENABLE" "RLAST_0,RLAST_1" bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit - ENABLE" "RDMAERR_0,RDMAERR_1" bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit - ENABLE" "RCKFAIL_0,RCKFAIL_1" newline bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame-sync interrupt enable bit - ENABLE" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit - ENABLE" "ROVRN_0,ROVRN_1" line.long 0x20 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number" bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred" "RERR_0,RERR_1" bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "RDMAERR_0,RDMAERR_1" bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "RSTAFRM_0,RSTAFRM_1" bitfld.long 0x20 5. "RDATA,Receive data ready flag" "RDATA_0,RDATA_1" bitfld.long 0x20 4. "RLAST,Receive last slot flag" "RLAST_0,RLAST_1" newline bitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "RTDMSLOT_0,RTDMSLOT_1" bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "RCKFAIL_0,RCKFAIL_1" bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "RSYNCERR_0,RSYNCERR_1" bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "ROVRN_0,ROVRN_1" line.long 0x24 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame" hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT," line.long 0x28 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "RCNT," hexmask.long.byte 0x28 16.--23. 1. "RMAX," hexmask.long.byte 0x28 8.--15. 1. "RMIN," bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "RPS_0,RPS_1,RPS_2,RPS_3,RPS_4,RPS_5,RPS_6,RPS_7,RPS_8,?,?,?,?,?,?,?" line.long 0x2C "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "RDATDMA_0,RDATDMA_1" group.long 0xA0++0x33 line.long 0x00 "MCASP_GBLCTLX,Alias of GBLCTL" bitfld.long 0x00 12. "XFRST,Frame sync generator reset - RESET" "XFRST_0,XFRST_1" bitfld.long 0x00 11. "XSMRST,XMT state machine reset - RESET" "XSMRST_0,XSMRST_1" bitfld.long 0x00 10. "XSRCLR,XMT serializer clear - CLEAR" "XSRCLR_0,XSRCLR_1" bitfld.long 0x00 9. "XHCLKRST,XMT High Freq" "XHCLKRST_0,XHCLKRST_1" bitfld.long 0x00 8. "XCLKRST,XMT clock divder reset - RESET" "XCLKRST_0,XCLKRST_1" newline rbitfld.long 0x00 4. "RFRST,Frame sync generator reset - RESET" "RFRST_0,RFRST_1" rbitfld.long 0x00 3. "RSMRST,RCV state machine reset - RESET" "RSMRST_0,RSMRST_1" rbitfld.long 0x00 2. "RSRCLKR,RCV serializer clear - CLEAR" "RSRCLKR_0,RSRCLKR_1" rbitfld.long 0x00 1. "RHCLKRST,RCV High Freq" "RHCLKRST_0,RHCLKRST_1" rbitfld.long 0x00 0. "RCLKRST,RCV clock divder reset - RESET" "RCLKRST_0,RCLKRST_1" line.long 0x04 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" line.long 0x08 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay - 0BIT" "XDATDLY_0,XDATDLY_1,XDATDLY_2,XDATDLY_3" bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "XRVRS_0,XRVRS_1" bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "XPAD_0,XPAD_1,XPAD_2,XPAD_3" bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "XPBIT_0,XPBIT_1,XPBIT_2,XPBIT_3,XPBIT_4,XPBIT_5,XPBIT_6,XPBIT_7,XPBIT_8,XPBIT_9,XPBIT_10,XPBIT_11,XPBIT_12,XPBIT_13,XPBIT_14,XPBIT_15,XPBIT_16,XPBIT_17,XPBIT_18,XPBIT_19,XPBIT_20,XPBIT_21,XPBIT_22,XPBIT_23,XPBIT_24,XPBIT_25,XPBIT_26,XPBIT_27,XPBIT_28,XPBIT_29,XPBIT_30,XPBIT_31" bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size0x0" "?,?,?,XSSZ_3,XSSZ_4,XSSZ_5,XSSZ_6,XSSZ_7,XSSZ_8,XSSZ_9,XSSZ_10,XSSZ_11,XSSZ_12,XSSZ_13,XSSZ_14,XSSZ_15" newline bitfld.long 0x08 3. "XBUSEL,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port" "XBUSEL_0,XBUSEL_1" bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit - 12BITS" "XROT_0,XROT_1,XROT_2,XROT_3,XROT_4,XROT_5,XROT_6,XROT_7" line.long 0x0C "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)" hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame-sync mode select bits" bitfld.long 0x0C 4. "FXWID,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period" "FXWID_0,FXWID_1" bitfld.long 0x0C 1. "FSXM,Transmit frame-sync generation select bit - INTERNAL" "FSXM_0,FSXM_1" bitfld.long 0x0C 0. "FSXP,Transmit frame-sync polarity select bit - FALLINGEDGE" "FSXP_0,FSXP_1" line.long 0x10 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator" bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "CLKXADJ_0,CLKXADJ_1,CLKXADJ_2,CLKXADJ_3" bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "CLKXP_0,CLKXP_1" newline bitfld.long 0x10 6. "ASYNC,Transmit operation asynchronous enable bit - ASYNC" "ASYNC_0,ASYNC_1" bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit - INTERNAL" "CLKXM_0,CLKXM_1" bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "CLKXDIV_0,CLKXDIV_1,CLKXDIV_2,CLKXDIV_3,CLKXDIV_4,CLKXDIV_5,CLKXDIV_6,CLKXDIV_7,CLKXDIV_8,CLKXDIV_9,CLKXDIV_10,CLKXDIV_11,CLKXDIV_12,CLKXDIV_13,CLKXDIV_14,CLKXDIV_15,CLKXDIV_16,CLKXDIV_17,CLKXDIV_18,CLKXDIV_19,CLKXDIV_20,CLKXDIV_21,CLKXDIV_22,CLKXDIV_23,CLKXDIV_24,CLKXDIV_25,CLKXDIV_26,CLKXDIV_27,CLKXDIV_28,CLKXDIV_29,CLKXDIV_30,CLKXDIV_31" line.long 0x14 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator" bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "BUSY_0,BUSY_1" bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "DIVBUSY_0,DIVBUSY_1" bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "ADJBUSY_0,ADJBUSY_1" bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "HCLKXADJ_0,HCLKXADJ_1,HCLKXADJ_2,HCLKXADJ_3" bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit - INTERNAL" "HCLKXM_0,HCLKXM_1" newline bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "HCLKXP_0,HCLKXP_1" hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx" line.long 0x18 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)" line.long 0x1C "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT)" bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit - ENABLE" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x1C 5. "XDATA,Transmit data-ready interrupt enable bit - ENABLE" "XDATA_0,XDATA_1" bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit - ENABLE" "XLAST_0,XLAST_1" bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit - ENABLE" "XDMAERR_0,XDMAERR_1" bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit - ENABLE" "XCKFAIL_0,XCKFAIL_1" newline bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame-sync interrupt enable bit - ENABLE" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit - ENABLE" "XUNDRN_0,XUNDRN_1" line.long 0x20 "MCASP_TXSTAT,Transmitter status register - If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it. the McASP logic has priority and the flag remains set" bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR" "XERR_0,XERR_1" bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "XDMAERR_0,XDMAERR_1" bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "XSTAFRM_0,XSTAFRM_1" bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "XDATA_0,XDATA_1" bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "XLAST_0,XLAST_1" newline rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "XTDMSLOT_0_r,XTDMSLOT_1_r" bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "XCKFAIL_0,XCKFAIL_1" bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame-sync flag" "XSYNCERR_0,XSYNCERR_1" bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "XUNDRN_0,XUNDRN_1" line.long 0x24 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x24 0.--8. 1. "XSLOTCNT,Current transmit time slot count" line.long 0x28 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit" hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value (from previous measurement)" hexmask.long.byte 0x28 16.--23. 1. "XMAX,0x0 to" hexmask.long.byte 0x28 8.--15. 1. "XMIN,0x0 to" bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "XPS_0,XPS_1,XPS_2,XPS_3,XPS_4,XPS_5,XPS_6,XPS_7,XPS_8,XPS_9,XPS_10,XPS_11,XPS_12,XPS_13,XPS_14,XPS_15" line.long 0x2C "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "XDATDMA_0,XDATDMA_1" line.long 0x30 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x30 0. "ENABLE,One-shot clock adjust enable - DISABLE" "ENABLE_0,ENABLE_1" repeat 2. (list 4. 5. ) tree "Channel_$1" group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot)" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot)" group.long 0x280++0x03 line.long 0x00 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit" group.long 0x200++0x03 line.long 0x00 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit" group.long 0x180++0x03 line.long 0x00 "MCASP_XRSRCTLn_0,Serializer n control register" rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "RRDY_0_r,RRDY_1_r" rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "XRDY_0_r,XRDY_1_r" bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "DISMOD_0,DISMOD_1,DISMOD_2,DISMOD_3" bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit - INACTIVE" "SRMOD_0,SRMOD_1,SRMOD_2,SRMOD_3" tree.end repeat.end tree.end tree.end tree.open "Multichannel_Serial_Peripheral_Interface" tree "MCSPI1" base ad:0x48098000 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "0,1" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x1B line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period - None" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 3.--4. "SIDLEMODE,Power management - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control - NoWakeUp" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy - Off" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - InProgress" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - NoEvnt_r" "WKS_0_w,WKS_1_r" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" newline bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" newline bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" newline bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - IrqDisabled" "WKE_0,WKE_1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" newline bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" newline bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" newline bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - NoWakeUp" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" bitfld.long 0x14 11. "SSB,Set status bit - Off" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" newline bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "SPICLK_0,SPICLK_1" newline bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this register" "SPIDAT_1_0,SPIDAT_1_1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this register" "SPIDAT_0_0,SPIDAT_0_1" bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this register" "SPIEN_3_0,SPIEN_3_1" newline bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this register" "SPIEN_2_0,SPIEN_2_1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this register" "SPIEN_1_0,SPIEN_1_1" bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this register" "SPIEN_0_0,SPIEN_0_1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" newline bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode - Off" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave - Master" "MS_0,MS_1" bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode" "PIN34_0,PIN34_1" newline bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only) - Multi" "SINGLE_0,SINGLE_1" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x00 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. "AFL,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x00 0.--7. 1. "AEL,Buffer almost empty" repeat 4. (list 0. 1. 2. 3. ) tree "Channel_$1" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" newline bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1 (SPIDATAGZEN[1])" "DPE1_0,DPE1_1" bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0 (SPIDATAGZEN[0])" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x134++0x03 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word received through the serial link. what ever SPI word length is" group.long 0x138++0x03 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is" tree.end repeat.end tree.end tree "MCSPI2" base ad:0x4809A000 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "0,1" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x1B line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period - None" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 3.--4. "SIDLEMODE,Power management - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control - NoWakeUp" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy - Off" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - InProgress" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - NoEvnt_r" "WKS_0_w,WKS_1_r" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" newline bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" newline bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" newline bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - IrqDisabled" "WKE_0,WKE_1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" newline bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" newline bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" newline bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - NoWakeUp" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" bitfld.long 0x14 11. "SSB,Set status bit - Off" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" newline bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "SPICLK_0,SPICLK_1" newline bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this register" "SPIDAT_1_0,SPIDAT_1_1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this register" "SPIDAT_0_0,SPIDAT_0_1" bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this register" "SPIEN_3_0,SPIEN_3_1" newline bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this register" "SPIEN_2_0,SPIEN_2_1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this register" "SPIEN_1_0,SPIEN_1_1" bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this register" "SPIEN_0_0,SPIEN_0_1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" newline bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode - Off" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave - Master" "MS_0,MS_1" bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode" "PIN34_0,PIN34_1" newline bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only) - Multi" "SINGLE_0,SINGLE_1" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x00 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. "AFL,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x00 0.--7. 1. "AEL,Buffer almost empty" repeat 2. (list 0. 1. ) tree "Channel_$1" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x00 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" bitfld.long 0x00 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" bitfld.long 0x00 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x00 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" bitfld.long 0x00 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" bitfld.long 0x00 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" newline bitfld.long 0x00 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" bitfld.long 0x00 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" bitfld.long 0x00 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x00 17. "DPE1,Transmission enable for data line 1 (SPIDATAGZEN[1])" "DPE1_0,DPE1_1" bitfld.long 0x00 16. "DPE0,Transmission Enable for data line 0 (SPIDATAGZEN[0])" "DPE0_0,DPE0_1" bitfld.long 0x00 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x00 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" newline bitfld.long 0x00 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" bitfld.long 0x00 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x00 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" bitfld.long 0x00 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" bitfld.long 0x00 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x00 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" group.long 0x134++0x03 line.long 0x00 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel 0" hexmask.long.byte 0x00 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" bitfld.long 0x00 0. "EN,Channel enable" "EN_0,EN_1" rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel 0" bitfld.long 0x00 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x00 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" bitfld.long 0x00 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" bitfld.long 0x00 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x00 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" bitfld.long 0x00 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" bitfld.long 0x00 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RXx_0,This register contains a single SPI word received through the serial link. what ever SPI word length is" group.long 0x138++0x03 line.long 0x00 "MCSPI_TXx_0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is" tree.end repeat.end tree.end repeat 2. (list 3. 4. )(list ad:0x480B8000 ad:0x480BA000 ) tree "MCSPI$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration. that is. typically the module's HDL generics (if any)" hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to 0 and writes to them are ignored" bitfld.long 0x04 6. "RETMODE,Retention Mode generic parameter" "0,1" bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "?,FFNBYTE_1_r,FFNBYTE_2_r,?,FFNBYTE_4_r,?,?,?,FFNBYTE_8_r,?,?,?,?,?,?,?,FFNBYTE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management" "USEFIFO_0_r,USEFIFO_1_r" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" hexmask.long 0x00 4.--31. 1. "RSVD," bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation (debug) suspend input signal" "FREEEMU_0,FREEEMU_1" newline bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0_r,SOFTRESET_1_w" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the revision number" group.long 0x110++0x2F line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake-up mode period - None" "CLOCKACTIVITY_0,CLOCKACTIVITY_1,CLOCKACTIVITY_2,CLOCKACTIVITY_3" bitfld.long 0x00 3.--4. "SIDLEMODE,Power management - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" bitfld.long 0x00 2. "ENAWAKEUP,Wake-up feature control - NoWakeUp" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock-gating strategy - Off" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x04 0. "RESETDONE,Internal reset monitoring - InProgress" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]" "EOW_0_r,EOW_1_w" bitfld.long 0x08 16. "WKS,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - NoEvnt_r" "WKS_0_w,WKS_1_r" bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full" "RX3_FULL_0_w,RX3_FULL_1_r" newline bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow" "TX3_UNDERFLOW_0_w,TX3_UNDERFLOW_1_r" bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty" "TX3_EMPTY_0_w,TX3_EMPTY_1_r" bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full" "RX2_FULL_0_w,RX2_FULL_1_r" newline bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow" "TX2_UNDERFLOW_0_w,TX2_UNDERFLOW_1_r" bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty" "TX2_EMPTY_0_w,TX2_EMPTY_1_r" bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full" "RX1_FULL_0_w,RX1_FULL_1_r" newline bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow" "TX1_UNDERFLOW_0_w,TX1_UNDERFLOW_1_r" bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty" "TX1_EMPTY_0_w,TX1_EMPTY_1_r" bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow (slave mode only)" "RX0_OVERFLOW_0_w,RX0_OVERFLOW_1_r" newline bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full" "RX0_FULL_0_w,RX0_FULL_1_r" bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow" "TX0_UNDERFLOW_0_w,TX0_UNDERFLOW_1_r" bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty" "TX0_EMPTY_0_w,TX0_EMPTY_1_r" line.long 0x0C "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt. on an event-by-event basis" bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "EOW_ENABLE_0,EOW_ENABLE_1" bitfld.long 0x0C 16. "WKE,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - IrqDisabled" "WKE_0,WKE_1" bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX3_FULL_ENABLE_0,RX3_FULL_ENABLE_1" newline bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX3_UNDERFLOW_ENABLE_0,TX3_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX3_EMPTY_ENABLE_0,TX3_EMPTY_ENABLE_1" bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX2_FULL_ENABLE_0,RX2_FULL_ENABLE_1" newline bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX2_UNDERFLOW_ENABLE_0,TX2_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX2_EMPTY_ENABLE_0,TX2_EMPTY_ENABLE_1" bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX1_FULL_ENABLE_0,RX1_FULL_ENABLE_1" newline bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX1_UNDERFLOW_ENABLE_0,TX1_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX1_EMPTY_ENABLE_0,TX1_EMPTY_ENABLE_1" bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable" "RX0_OVERFLOW_ENABLE_0,RX0_OVERFLOW_ENABLE_1" newline bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable" "RX0_FULL_ENABLE_0,RX0_FULL_ENABLE_1" bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable" "TX0_UNDERFLOW_ENABLE_0,TX0_UNDERFLOW_ENABLE_1" bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable" "TX0_EMPTY_ENABLE_0,TX0_EMPTY_ENABLE_1" line.long 0x10 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis" bitfld.long 0x10 0. "WKEN,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit - NoWakeUp" "WKEN_0,WKEN_1" line.long 0x14 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device I/O pads. when the module is configured in system test (SYSTEST) mode" bitfld.long 0x14 11. "SSB,Set status bit - Off" "SSB_0,SSB_1" bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "SPIENDIR_0,SPIENDIR_1" bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "SPIDATDIR1_0,SPIDATDIR1_1" newline bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "SPIDATDIR0_0,SPIDATDIR0_1" bitfld.long 0x14 7. "WAKD,SWAKEUP output (signal data value of internal signal to system)" "WAKD_0,WAKD_1" bitfld.long 0x14 6. "SPICLK,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction) this bit returns the value on the CLKSPI line (high or low) and a write into this bit has no effect" "SPICLK_0,SPICLK_1" newline bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction) the SPIDAT[1] line is driven high or low according to the value written into this register" "SPIDAT_1_0,SPIDAT_1_1" bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction) the SPIDAT[0] line is driven high or low according to the value written into this register" "SPIDAT_0_0,SPIDAT_0_1" bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[3] line is driven high or low according to the value written into this register" "SPIEN_3_0,SPIEN_3_1" newline bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[2] line is driven high or low according to the value written into this register" "SPIEN_2_0,SPIEN_2_1" bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[1] line is driven high or low according to the value written into this register" "SPIEN_1_0,SPIEN_1_1" bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction) the SPIENT[0] line is driven high or low according to the value written into this register" "SPIEN_0_0,SPIEN_0_1" line.long 0x18 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x18 8. "FDAA,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address" "FDAA_0,FDAA_1" bitfld.long 0x18 7. "MOA,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO" "MOA_0,MOA_1" bitfld.long 0x18 4.--6. "INITDLY,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode" "INITDLY_0,INITDLY_1,INITDLY_2,INITDLY_3,INITDLY_4,?,?,?" newline bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode - Off" "SYSTEM_TEST_0,SYSTEM_TEST_1" bitfld.long 0x18 2. "MS,Master/slave - Master" "MS_0,MS_1" bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode" "PIN34_0,PIN34_1" newline bitfld.long 0x18 0. "SINGLE,Single channel/Multi Channel (master mode only) - Multi" "SINGLE_0,SINGLE_1" line.long 0x1C "MCSPI_CHxCONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity" "CLKG_0,CLKG_1" bitfld.long 0x1C 28. "FFER,FIFO enabled for receive: Only one channel can have this bit field set" "FFER_0,FFER_1" bitfld.long 0x1C 27. "FFEW,FIFO enabled for transmit: Only one channel can have this bit field set" "FFEW_0,FFEW_1" newline bitfld.long 0x1C 25.--26. "TCS0,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "TCS0_0,TCS0_1,TCS0_2,TCS0_3" bitfld.long 0x1C 24. "SBPOL,Start-bit polarity" "SBPOL_0,SBPOL_1" bitfld.long 0x1C 23. "SBE,Start-bit enable for SPI transfer" "SBE_0,SBE_1" newline bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection" "SPIENSLV_0,SPIENSLV_1,SPIENSLV_2,SPIENSLV_3" bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)" "FORCE_0,FORCE_1" bitfld.long 0x1C 19. "TURBO,Turbo mode" "TURBO_0,TURBO_1" newline bitfld.long 0x1C 18. "IS,Input Select" "IS_0,IS_1" bitfld.long 0x1C 17. "DPE1,Transmission enable for data line 1 (SPIDATAGZEN[1])" "DPE1_0,DPE1_1" bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 (SPIDATAGZEN[0])" "DPE0_0,DPE0_1" newline bitfld.long 0x1C 15. "DMAR,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel" "DMAR_0,DMAR_1" bitfld.long 0x1C 14. "DMAW,DMA write request" "DMAW_0,DMAW_1" bitfld.long 0x1C 12.--13. "TRM,Transmit/receive modes" "TRM_0,TRM_1,TRM_2,TRM_3" newline bitfld.long 0x1C 7.--11. "WL,SPI word length" "WL_0,WL_1,WL_2,WL_3,WL_4,WL_5,WL_6,WL_7,WL_8,WL_9,WL_10,WL_11,WL_12,WL_13,WL_14,WL_15,WL_16,WL_17,WL_18,WL_19,WL_20,WL_21,WL_22,WL_23,WL_24,WL_25,WL_26,WL_27,WL_28,WL_29,WL_30,WL_31" bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "EPOL_0,EPOL_1" bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK (only when the module is a Master SPI device)" "CLKD_0,CLKD_1,CLKD_2,CLKD_3,CLKD_4,CLKD_5,CLKD_6,CLKD_7,CLKD_8,CLKD_9,CLKD_10,CLKD_11,CLKD_12,CLKD_13,CLKD_14,CLKD_15" newline bitfld.long 0x1C 1. "POL,SPICLK polarity (see )" "POL_0,POL_1" bitfld.long 0x1C 0. "PHA,SPICLK phase (see )" "PHA_0,PHA_1" line.long 0x20 "MCSPI_CHxSTAT,This register provides status information about transmitter and receiver registers of channel 0" bitfld.long 0x20 6. "RXFFF,Channel 'i' FIFO receive buffer full status" "RXFFF_0_r,RXFFF_1_r" bitfld.long 0x20 5. "RXFFE,Channel 'i' FIFO receive buffer empty status" "RXFFE_0_r,RXFFE_1_r" bitfld.long 0x20 4. "TXFFF,Channel 'i' FIFO transmit buffer full status" "TXFFF_0_r,TXFFF_1_r" newline bitfld.long 0x20 3. "TXFFE,Channel 'i' FIFO transmit buffer empty status" "TXFFE_0_r,TXFFE_1_r" bitfld.long 0x20 2. "EOT,Channel 'i' end of transfer status" "EOT_0_r,EOT_1_r" bitfld.long 0x20 1. "TXS,Channel 'i' transmitter register status" "TXS_0_r,TXS_1_r" newline bitfld.long 0x20 0. "RXS,Channel 'i' receiver register status" "RXS_0_r,RXS_1_r" line.long 0x24 "MCSPI_CHxCTRL,This register is dedicated to enable channel 0" hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1)" bitfld.long 0x24 0. "EN,Channel enable" "EN_0,EN_1" line.long 0x28 "MCSPI_TXx,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is" line.long 0x2C "MCSPI_RXx,This register contains a single SPI word received through the serial link. what ever SPI word length is" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.word 0x00 16.--31. 1. "WCNT,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. "AFL,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition" hexmask.long.byte 0x00 0.--7. 1. "AEL,Buffer almost empty" tree.end repeat.end tree.end tree.open "Multimaster_High_Speed_I2C_Controller" repeat 5. (list 3. 1. 2. 4. 5. )(list ad:0x48060000 ad:0x48070000 ad:0x48072000 ad:0x4807A000 ad:0x4807C000 ) tree "I2C$1" base $2 rgroup.long 0x00++0x07 line.long 0x00 "I2C_REVNB_LO,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" line.long 0x04 "I2C_REVNB_HI,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility" group.word 0x10++0x01 line.word 0x00 "I2C_SYSC,System Configuration register" bitfld.word 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits - boothoff" "CLKACTIVITY_0,CLKACTIVITY_1,CLKACTIVITY_2,CLKACTIVITY_3" bitfld.word 0x00 3.--4. "IDLEMODE,Idle Mode selection bits - smartidle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.word 0x00 2. "ENAWAKEUP,Enable Wakeup control bit - disable" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.word 0x00 1. "SRST,SoftReset bit - nmode" "SRST_0,SRST_1" bitfld.word 0x00 0. "AUTOIDLE,Autoidle bit - disable" "AUTOIDLE_0,AUTOIDLE_1" group.word 0x20++0x01 line.word 0x00 "I2C_EOI,End Of Interrupt number specification" bitfld.word 0x00 0. "LINE_NUMBER,Software End Of Interrupt (EOI) control" "0,1" group.word 0x24++0x01 line.word 0x00 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector" bitfld.word 0x00 14. "XDR,Transmit draining IRQ status" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive draining IRQ status" "RDR_0,RDR_1" rbitfld.word 0x00 12. "BB,Bus busy status" "BB_0_r,BB_1_r" newline bitfld.word 0x00 11. "ROVR,Receive overrun status" "ROVR_0_r,ROVR_1_r" bitfld.word 0x00 10. "XUDF,Transmit underflow status" "XUDF_0_r,XUDF_1_r" bitfld.word 0x00 9. "AAS,Address recognized as slave IRQ status" "AAS_0,AAS_1" newline bitfld.word 0x00 8. "BF,Bus Free IRQ status" "BF_0,BF_1" bitfld.word 0x00 7. "AERR,Access Error IRQ status" "AERR_0,AERR_1" bitfld.word 0x00 6. "STC,Start Condition IRQ status" "STC_0,STC_1" newline bitfld.word 0x00 5. "GC,General call IRQ status" "GC_0,GC_1" bitfld.word 0x00 4. "XRDY,Transmit data ready IRQ status" "XRDY_0,XRDY_1" bitfld.word 0x00 3. "RRDY,Receive data ready IRQ status" "RRDY_0,RRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ status" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgement IRQ status" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ status" "AL_0,AL_1" group.word 0x28++0x01 line.word 0x00 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x00 14. "XDR,Transmit draining IRQ enabled status" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive draining IRQ enabled status" "RDR_0,RDR_1" rbitfld.word 0x00 12. "BB,Bus busy enabled status" "BB_0_r,BB_1_r" newline bitfld.word 0x00 11. "ROVR,Receive overrun enabled status" "ROVR_0_r,ROVR_1_r" bitfld.word 0x00 10. "XUDF,Transmit underflow enabled status" "XUDF_0_r,XUDF_1_r" bitfld.word 0x00 9. "AAS,Address recognized as slave IRQ enabled status" "AAS_0,AAS_1" newline bitfld.word 0x00 8. "BF,Bus Free IRQ enabled status" "BF_0,BF_1" bitfld.word 0x00 7. "AERR,Access Error IRQ enabled status" "AERR_0,AERR_1" bitfld.word 0x00 6. "STC,Start Condition IRQ enabled status" "STC_0,STC_1" newline bitfld.word 0x00 5. "GC,General call IRQ enabled status" "GC_0,GC_1" bitfld.word 0x00 4. "XRDY,Transmit data ready IRQ enabled status" "XRDY_0,XRDY_1" bitfld.word 0x00 3. "RRDY,Receive data ready IRQ enabled status" "RRDY_0,RRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ enabled status" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgement IRQ enabled status" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ enabled status" "AL_0,AL_1" group.word 0x2C++0x01 line.word 0x00 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector" bitfld.word 0x00 14. "XDR_IE,Transmit Draining interrupt enable set" "XDR_IE_0,XDR_IE_1" bitfld.word 0x00 13. "RDR_IE,Receive Draining interrupt enable set" "RDR_IE_0,RDR_IE_1" bitfld.word 0x00 11. "ROVR,Receive overrun enable set" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow enable set" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "ASS_IE,Addressed as Slave interrupt enable set" "ASS_IE_0,ASS_IE_1" bitfld.word 0x00 8. "BF_IE,Bus Free interrupt enable set" "BF_IE_0,BF_IE_1" newline bitfld.word 0x00 7. "AERR_IE,Access Error interrupt enable set" "AERR_IE_0,AERR_IE_1" bitfld.word 0x00 6. "STC_IE,Start Condition interrupt enable set" "STC_IE_0,STC_IE_1" bitfld.word 0x00 5. "GC_IE,General call Interrupt enable set" "GC_IE_0,GC_IE_1" newline bitfld.word 0x00 4. "XRDY_IE,Transmit data ready interrupt enable set" "XRDY_IE_0,XRDY_IE_1" bitfld.word 0x00 3. "RRDY_IE,Receive data ready interrupt enable set" "RRDY_IE_0,RRDY_IE_1" bitfld.word 0x00 2. "ARDY_IE,Register access ready interrupt enable set" "ARDY_IE_0,ARDY_IE_1" newline bitfld.word 0x00 1. "NACK_IE,No acknowledgement interrupt enable set" "NACK_IE_0,NACK_IE_1" bitfld.word 0x00 0. "AL_IE,Arbitration lost interrupt enable set" "AL_IE_0,AL_IE_1" group.word 0x30++0x01 line.word 0x00 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector" bitfld.word 0x00 14. "XDR_IE,Transmit Draining interrupt enable clear" "XDR_IE_0,XDR_IE_1" bitfld.word 0x00 13. "RDR_IE,Receive Draining interrupt enable clear" "RDR_IE_0,RDR_IE_1" bitfld.word 0x00 11. "ROVR,Receive overrun enable clear" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow enable clear" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "ASS_IE,Addressed as Slave interrupt enable clear" "ASS_IE_0,ASS_IE_1" bitfld.word 0x00 8. "BF_IE,Bus Free interrupt enable clear" "BF_IE_0,BF_IE_1" newline bitfld.word 0x00 7. "AERR_IE,Access Error interrupt enable clear" "AERR_IE_0,AERR_IE_1" bitfld.word 0x00 6. "STC_IE,Start Condition interrupt enable clear" "STC_IE_0,STC_IE_1" bitfld.word 0x00 5. "GC_IE,General call Interrupt enable clear" "GC_IE_0,GC_IE_1" newline bitfld.word 0x00 4. "XRDY_IE,Transmit data ready interrupt enable clear" "XRDY_IE_0,XRDY_IE_1" bitfld.word 0x00 3. "RRDY_IE,Receive data ready interrupt enable clear" "RRDY_IE_0,RRDY_IE_1" bitfld.word 0x00 2. "ARDY_IE,Register access ready interrupt enable clear" "ARDY_IE_0,ARDY_IE_1" newline bitfld.word 0x00 1. "NACK_IE,No acknowledgement interrupt enable clear" "NACK_IE_0,NACK_IE_1" bitfld.word 0x00 0. "AL_IE,Arbitration lost interrupt enable clear" "AL_IE_0,AL_IE_1" group.word 0x34++0x01 line.word 0x00 "I2C_WE,I2C wakeup enable vector" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x38++0x01 line.word 0x00 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set" bitfld.word 0x00 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "DMARX_ENABLE_SET_0,DMARX_ENABLE_SET_1" group.word 0x3C++0x01 line.word 0x00 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set" bitfld.word 0x00 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "DMATX_ENABLE_SET_0,DMATX_ENABLE_SET_1" group.word 0x40++0x01 line.word 0x00 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear" bitfld.word 0x00 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "DMARX_ENABLE_CLEAR_0,DMARX_ENABLE_CLEAR_1" group.word 0x44++0x01 line.word 0x00 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear" bitfld.word 0x00 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "DMATX_ENABLE_CLEAR_0,DMATX_ENABLE_CLEAR_1" group.word 0x48++0x01 line.word 0x00 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x4C++0x01 line.word 0x00 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable" bitfld.word 0x00 14. "XDR,Transmit Draining wakeup set" "XDR_0,XDR_1" bitfld.word 0x00 13. "RDR,Receive Draining wakeup set" "RDR_0,RDR_1" bitfld.word 0x00 11. "ROVR,Receive overrun wakeup set" "ROVR_0,ROVR_1" newline bitfld.word 0x00 10. "XUDF,Transmit underflow wakeup set" "XUDF_0,XUDF_1" bitfld.word 0x00 9. "AAS,Address as slave IRQ wakeup set" "AAS_0,AAS_1" bitfld.word 0x00 8. "BF,Bus Free IRQ wakeup set" "BF_0,BF_1" newline bitfld.word 0x00 6. "STC,Start Condition IRQ wakeup set" "STC_0,STC_1" bitfld.word 0x00 5. "GC,General call IRQ wakeup set" "GC_0,GC_1" bitfld.word 0x00 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "DRDY_0,DRDY_1" newline bitfld.word 0x00 2. "ARDY,Register access ready IRQ wakeup set" "ARDY_0,ARDY_1" bitfld.word 0x00 1. "NACK,No acknowledgment IRQ wakeup set" "NACK_0,NACK_1" bitfld.word 0x00 0. "AL,Arbitration lost IRQ wakeup set" "AL_0,AL_1" group.word 0x90++0x01 line.word 0x00 "I2C_SYSS,System Status register" bitfld.word 0x00 0. "RDONE,Reset done bit - rstcomp" "RDONE_0_r,RDONE_1_r" group.word 0x94++0x01 line.word 0x00 "I2C_BUF,Buffer Configuration register" bitfld.word 0x00 15. "RDMA_EN,Receive DMA channel enable - disable" "RDMA_EN_0,RDMA_EN_1" bitfld.word 0x00 14. "RXFIFO_CLR,Receive FIFO clear - nmode" "RXFIFO_CLR_0,RXFIFO_CLR_1" bitfld.word 0x00 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.word 0x00 7. "XDMA_EN,Transmit DMA channel enable - disable" "XDMA_EN_0,XDMA_EN_1" bitfld.word 0x00 6. "TXFIFO_CLR,Transmit FIFO clear - nmode" "TXFIFO_CLR_0,TXFIFO_CLR_1" bitfld.word 0x00 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0x98++0x01 line.word 0x00 "I2C_CNT,Data counter register" group.word 0x9C++0x01 line.word 0x00 "I2C_DATA,Data access register" hexmask.word.byte 0x00 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint" group.word 0xA4++0x01 line.word 0x00 "I2C_CON,I2C configuration register" bitfld.word 0x00 15. "I2C_EN,I2C module enable" "I2C_EN_0,I2C_EN_1" bitfld.word 0x00 12.--13. "OPMODE,Operation mode selection" "OPMODE_0,OPMODE_1,OPMODE_2,OPMODE_3" bitfld.word 0x00 11. "STB,Start byte mode (master mode only)" "STB_0,STB_1" newline bitfld.word 0x00 10. "MST,Master/slave mode" "MST_0,MST_1" bitfld.word 0x00 9. "TRX,Transmitter/Receiver mode (master mode only)" "TRX_0,TRX_1" bitfld.word 0x00 8. "XSA,Expand Slave address" "XSA_0,XSA_1" newline bitfld.word 0x00 7. "XOA0,Expand Own address 0" "XOA0_0,XOA0_1" bitfld.word 0x00 6. "XOA1,Expand Own address 1" "XOA1_0,XOA1_1" bitfld.word 0x00 5. "XOA2,Expand Own address 2" "XOA2_0,XOA2_1" newline bitfld.word 0x00 4. "XOA3,Expand Own address 3" "XOA3_0,XOA3_1" bitfld.word 0x00 1. "STP,Stop condition (master mode only)" "STP_0,STP_1" bitfld.word 0x00 0. "STT,Start condition (master mode only)" "STT_0,STT_1" group.word 0xA8++0x01 line.word 0x00 "I2C_OA,Own address register" bitfld.word 0x00 13.--15. "MCODE,Master Code" "MCODE_0,MCODE_1,MCODE_2,MCODE_3,MCODE_4,MCODE_5,MCODE_6,MCODE_7" hexmask.word 0x00 0.--9. 1. "OA,Own address" group.word 0xAC++0x01 line.word 0x00 "I2C_SA,Slave address register" hexmask.word 0x00 0.--9. 1. "SA,Slave address" group.word 0xB0++0x01 line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x00 0.--7. 1. "PSC,Fast/Standard mode prescale sampling clock divider value" group.word 0xB4++0x01 line.word 0x00 "I2C_SCLL,I2C SCL Low Time Register" hexmask.word.byte 0x00 8.--15. 1. "HSSCLL,High speed mode SCL low time - The value of the bit field is automatically increased by 7" hexmask.word.byte 0x00 0.--7. 1. "SCLL,Fast/standard mode SCL low time - The value of the bit field is automatically increased by 7" group.word 0xB8++0x01 line.word 0x00 "I2C_SCLH,I2C SCL High Time Register" hexmask.word.byte 0x00 8.--15. 1. "HSSCLH,High speed mode SCL high time - The value of the bit field is automatically increased by 5" hexmask.word.byte 0x00 0.--7. 1. "SCLH,Fast/standard mode SCL high time - The value of the bit field is automatically increased by 5" group.word 0xBC++0x01 line.word 0x00 "I2C_SYSTEST,I2C System Test Register" bitfld.word 0x00 15. "ST_EN,System test enable" "ST_EN_0,ST_EN_1" bitfld.word 0x00 14. "FREE,Free running mode (on breakpoint) - stop" "FREE_0,FREE_1" bitfld.word 0x00 12.--13. "TMODE,Test mode select" "TMODE_0,TMODE_1,TMODE_2,TMODE_3" newline bitfld.word 0x00 11. "SSB,Set status bits from 0 to 5" "SSB_0,SSB_1" rbitfld.word 0x00 8. "SCL_I_FUNC,SCL line input value (functional mode)" "SCL_I_FUNC_0_r,SCL_I_FUNC_1_r" rbitfld.word 0x00 7. "SCL_O_FUNC,SCL line output value (functional mode)" "SCL_O_FUNC_0_r,SCL_O_FUNC_1_r" newline rbitfld.word 0x00 6. "SDA_I_FUNC,SDA line input value (functional mode)" "SDA_I_FUNC_0_r,SDA_I_FUNC_1_r" rbitfld.word 0x00 5. "SDA_O_FUNC,SDA line output value (functional mode)" "SDA_O_FUNC_0_r,SDA_O_FUNC_1_r" rbitfld.word 0x00 3. "SCL_I,SCL line sense input value - sclih" "SCL_I_0_r,SCL_I_1_r" newline bitfld.word 0x00 2. "SCL_O,SCL line drive output value" "SCL_O_0,SCL_O_1" rbitfld.word 0x00 1. "SDA_I,SDA line sense input value" "SDA_I_0_r,SDA_I_1_r" bitfld.word 0x00 0. "SDA_O,SDA line drive output value" "SDA_O_0,SDA_O_1" rgroup.word 0xC0++0x01 line.word 0x00 "I2C_BUFSTAT,I2C Buffer Status Register" bitfld.word 0x00 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3" bitfld.word 0x00 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x00 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.word 0xC4++0x01 line.word 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x00 0.--9. 1. "OA1,Own address 1" group.word 0xC8++0x01 line.word 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x00 0.--9. 1. "OA2,Own address 2" group.word 0xCC++0x01 line.word 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x00 0.--9. 1. "OA3,Own address 3" rgroup.word 0xD0++0x01 line.word 0x00 "I2C_ACTOA,I2C Active Own Address Register" bitfld.word 0x00 3. "OA3_ACT,Own Address 3 active" "OA3_ACT_0_r,OA3_ACT_1_r" bitfld.word 0x00 2. "OA2_ACT,Own Address 2 active" "OA2_ACT_0_r,OA2_ACT_1_r" bitfld.word 0x00 1. "OA1_ACT,Own Address 1 active" "OA1_ACT_0_r,OA1_ACT_1_r" newline bitfld.word 0x00 0. "OA0_ACT,Own Address 0 active" "OA0_ACT_0_r,OA0_ACT_1_r" group.word 0xD4++0x01 line.word 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register" bitfld.word 0x00 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "OA3_EN_0,OA3_EN_1" bitfld.word 0x00 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "OA2_EN_0,OA2_EN_1" bitfld.word 0x00 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "OA1_EN_0,OA1_EN_1" newline bitfld.word 0x00 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "OA0_EN_0,OA0_EN_1" tree.end repeat.end tree.end tree.open "On_Chip_Memory_OCM_Subsystem" repeat 3. (list 1. 2. 3. )(list ad:0x48804000 ad:0x4880A000 ad:0x48810000 ) tree "OCMC_RAM$1" base $2 rgroup.long 0x00++0x0F line.long 0x00 "OCMC_ECC_PID," line.long 0x04 "OCMC_SYSCONFIG_PM," bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x08 "OCMC_SYSCONFIG_RST," bitfld.long 0x08 0. "SW_RST,Software reset of the OCM controller configuration and history logic (does not reset L4 interface) - NORMAL_OP" "SW_RST_0,SW_RST_1" line.long 0x0C "OCMC_MEM_SIZE_READ,This register provides the status of the OCM Controller configuration" bitfld.long 0x0C 9. "MEM_CBUF_ENABLE,Indicates whether CBUF is supported or not" "MEM_CBUF_ENABLE_0,MEM_CBUF_ENABLE_1" newline bitfld.long 0x0C 8. "MEM_ECC_ENABLE,Indicates whether ECC is supported or not" "MEM_ECC_ENABLE_0,MEM_ECC_ENABLE_1" newline bitfld.long 0x0C 0.--4. "MEM_SIZE_128K_CNT,This bit field indicates how many 128KiB memory blocks are present in the SRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40++0x13 line.long 0x00 "INTR0_STATUS_RAW_SET,This register contains the raw interrupt status" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" line.long 0x04 "INTR0_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive. 1=active)" bitfld.long 0x04 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x04 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x04 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x04 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x04 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x04 0. "SEC_ERR_FOUND," "0,1" line.long 0x08 "INTR0_ENABLE_SET,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will set the corresponding interrupt enable bit" bitfld.long 0x08 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x08 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x08 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x08 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x08 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x08 0. "SEC_ERR_FOUND," "0,1" line.long 0x0C "INTR0_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will clear interrupt enabled" bitfld.long 0x0C 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x0C 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x0C 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x0C 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x0C 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x0C 0. "SEC_ERR_FOUND," "0,1" line.long 0x10 "OCMC_INTR0_EOI,This register contains the EOI vector" bitfld.long 0x10 0. "EOI_VECTOR," "0,1" group.long 0x60++0x13 line.long 0x00 "INTR1_STATUS_RAW_SET,This register contains the raw interrupt status" bitfld.long 0x00 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x00 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x00 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x00 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x00 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x00 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x00 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x00 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x00 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x00 0. "SEC_ERR_FOUND," "0,1" line.long 0x04 "INTR1_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive. 1=active)" bitfld.long 0x04 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x04 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x04 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x04 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x04 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x04 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x04 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x04 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x04 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x04 0. "SEC_ERR_FOUND," "0,1" line.long 0x08 "INTR1_ENABLE_SET,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will set the corresponding interrupt enable bit" bitfld.long 0x08 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x08 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x08 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x08 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x08 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x08 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x08 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x08 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x08 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x08 0. "SEC_ERR_FOUND," "0,1" line.long 0x0C "INTR1_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled. 1=enabled) Writing 1 will clear interrupt enabled" bitfld.long 0x0C 14. "CBUF_SHORT_FRAME_DETECT_FOUND,CBUF detected short frame" "0,1" newline bitfld.long 0x0C 13. "CBUF_UNDERFLOW_ERR_FOUND," "0,1" newline bitfld.long 0x0C 12. "CBUF_OVERFLOW_WRAP_ERR_FOUND," "0,1" newline bitfld.long 0x0C 11. "CBUF_OVERFLOW_MID_ERR_FOUND," "0,1" newline bitfld.long 0x0C 10. "CBUF_READ_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 9. "CBUF_VBUF_READ_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 8. "CBUF_READ_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 7. "CBUF_WRITE_SEQUENCE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 6. "CBUF_VBUF_WRITE_START_ERR_FOUND," "0,1" newline bitfld.long 0x0C 5. "CBUF_WR_OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 4. "CBUF_VIRTUAL_ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 3. "OUT_OF_RANGE_ERR_FOUND," "0,1" newline bitfld.long 0x0C 2. "ADDR_ERR_FOUND," "0,1" newline bitfld.long 0x0C 1. "DED_ERR_FOUND," "0,1" newline bitfld.long 0x0C 0. "SEC_ERR_FOUND," "0,1" line.long 0x10 "OCMC_INTR1_EOI,This register contains the EOI vector" bitfld.long 0x10 0. "EOI_VECTOR," "0,1" group.long 0x80++0x1F line.long 0x00 "CFG_OCMC_ECC," bitfld.long 0x00 5. "CFG_ECC_OPT_NON_ECC_READ,Optimize read latency for non-ECC" "0,1" newline bitfld.long 0x00 4. "CFG_ECC_ERR_SRESP_EN,ECC non-correctable error SRESP enable" "0,1" newline bitfld.long 0x00 3. "CFG_ECC_SEC_AUTO_CORRECT,SEC error auto correction mode" "0,1" newline bitfld.long 0x00 0.--2. "CFG_OCMC_MODE,OCM Controller memory access modes" "0,1,2,3,4,5,6,7" line.long 0x04 "CFG_OCMC_ECC_MEM_BLK," hexmask.long.tbyte 0x04 0.--19. 1. "CFG_ECC_ENABLED_128K_BLK,ECC memory block enable bits" line.long 0x08 "CFG_OCMC_ECC_ERROR," bitfld.long 0x08 24. "CFG_DISCARD_DUP_ADDR,Do not save duplicate error address" "0,1" newline bitfld.long 0x08 20.--23. "CFG_ADDR_ERR_CNT_MAX,Number of ADDR errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 16.--19. "CFG_DED_CNT_MAX,Number of DED errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x08 0.--15. 1. "CFG_SEC_CNT_MAX,Number of SEC error to trigger an interrupt (The value configured must be > 0 to generate an interrupt)" line.long 0x0C "CFG_OCMC_ECC_CLEAR_HIST," bitfld.long 0x0C 3. "CLEAR_SEC_BIT_DISTR,Clear stored single error correction (SEC) bit distribution history" "0,1" newline bitfld.long 0x0C 2. "CLEAR_ADDR_ERR_CNT,Clear stored address error history" "0,1" newline bitfld.long 0x0C 1. "CLEAR_DED_ERR_CNT,Clear stored double error detection (DED) history" "0,1" newline bitfld.long 0x0C 0. "CLEAR_SEC_ERR_CNT,Clear stored single error correction history" "0,1" line.long 0x10 "STATUS_ERROR_CNT,OCM Controller error status" bitfld.long 0x10 20.--23. "ADDR_ERROR_CNT,Counter for the address errors found" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 16.--19. "DED_ERROR_CNT,Counter for the double error detections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x10 0.--15. 1. "SEC_ERROR_CNT,Counter for the single errors occured" line.long 0x14 "STATUS_SEC_ERROR_TRACE,SEC error 128-bit memory address" bitfld.long 0x14 18. "VALID,SEC FIFO valid addres indication" "VALID_0,VALID_1" newline hexmask.long.tbyte 0x14 0.--17. 1. "ADDRESS_128BIT,SEC error 128-bit memory address (Read from the SEC error address trace fifo)" line.long 0x18 "STATUS_DED_ERROR_TRACE,DED error 128-bit memory address" bitfld.long 0x18 18. "VALID,DED FIFO valid addres indication" "0,1" newline hexmask.long.tbyte 0x18 0.--17. 1. "ADDRESS_128BIT,DED error 128-bit memory address (Read from the DED error address trace fifo)" line.long 0x1C "STATUS_ADDR_TRANSLATION_ERROR_TRACE,ADDR error 128-bit memory address" bitfld.long 0x1C 18. "VALID,ADDRERR FIFO valid addres indication" "0,1" newline hexmask.long.tbyte 0x1C 0.--17. 1. "ADDRESS_128BIT,ADDR error 128-bit memory address (Read from the ADDR error address trace fifo)" rgroup.long 0xB0++0x03 line.long 0x00 "STATUS_SEC_ERROR_DISTR_4,SEC ecc code error bit distribution status [7:0]" hexmask.long.byte 0x00 0.--7. 1. "SEC_ECC_CODE_ERROR_FOUND,ECC Code (excluding the parity bit) error distribution [7:0]" group.long 0x200++0x33 line.long 0x00 "CFG_OCMC_CBUF_EN,CBUF mode enable register" bitfld.long 0x00 27. "CBUF_EN_11,CBUF 11 enable" "0,1" newline bitfld.long 0x00 26. "CBUF_EN_10,CBUF 10 enable" "0,1" newline bitfld.long 0x00 25. "CBUF_EN_9,CBUF 9 enable" "0,1" newline bitfld.long 0x00 24. "CBUF_EN_8,CBUF 8 enable" "0,1" newline bitfld.long 0x00 23. "CBUF_EN_7,CBUF 7 enable" "0,1" newline bitfld.long 0x00 22. "CBUF_EN_6,CBUF 6 enable" "0,1" newline bitfld.long 0x00 21. "CBUF_EN_5,CBUF 5 enable" "0,1" newline bitfld.long 0x00 20. "CBUF_EN_4,CBUF 4 enable" "0,1" newline bitfld.long 0x00 19. "CBUF_EN_3,CBUF 3 enable" "0,1" newline bitfld.long 0x00 18. "CBUF_EN_2,CBUF 2 enable" "0,1" newline bitfld.long 0x00 17. "CBUF_EN_1,CBUF 1 enable" "0,1" newline bitfld.long 0x00 16. "CBUF_EN_0,CBUF 0 enable" "0,1" newline bitfld.long 0x00 2. "NEW_FRAME_SEL,CBUF New Frame Event Definition Select" "0,1" newline bitfld.long 0x00 1. "CBUF_DEBUG_EN,CBUF Debug Enable Mode" "0,1" newline bitfld.long 0x00 0. "CBUF_MODE_EN,CBUF Mode Enable" "0,1" line.long 0x04 "CFG_OCMC_CBUF_RESET,Writing 1 to bit n will set a reset bit to clear the corresponding CBUF_n address translation logic" bitfld.long 0x04 11. "CBUF_RESET_11,cbuf_reset_11" "0,1" newline bitfld.long 0x04 10. "CBUF_RESET_10,cbuf_reset_10" "0,1" newline bitfld.long 0x04 9. "CBUF_RESET_9,cbuf_reset_9" "0,1" newline bitfld.long 0x04 8. "CBUF_RESET_8,cbuf_reset_8" "0,1" newline bitfld.long 0x04 7. "CBUF_RESET_7,cbuf_reset_7" "0,1" newline bitfld.long 0x04 6. "CBUF_RESET_6,cbuf_reset_6" "0,1" newline bitfld.long 0x04 5. "CBUF_RESET_5,cbuf_reset_5" "0,1" newline bitfld.long 0x04 4. "CBUF_RESET_4,cbuf_reset_4" "0,1" newline bitfld.long 0x04 3. "CBUF_RESET_3,cbuf_reset_3" "0,1" newline bitfld.long 0x04 2. "CBUF_RESET_2,cbuf_reset_2" "0,1" newline bitfld.long 0x04 1. "CBUF_RESET_1,cbuf_reset_1" "0,1" newline bitfld.long 0x04 0. "CBUF_RESET_0,cbuf_reset_0" "0,1" line.long 0x08 "CFG_OCMC_CBUF_ERR_HANDLER," bitfld.long 0x08 8. "UNDERFLOW_LAST_CBUF_SLICE_DISABLE," "0,1" newline bitfld.long 0x08 6.--7. "OVERFLOW_CHECK_REENABLE_SEL,Overflow check re-enable selection" "0,1,2,3" newline bitfld.long 0x08 4.--5. "OVERFLOW_WRITE_HANDLER_SEL,Overflow write handler selection" "0,1,2,3" newline bitfld.long 0x08 3. "UNDERFLOW_ERR_CHECK_EN,Underflow chek enable" "UNDERFLOW_ERR_CHECK_EN_0,UNDERFLOW_ERR_CHECK_EN_1" newline bitfld.long 0x08 2. "OVERFLOW_ERR_CHECK_EN,Overflow chek enable" "OVERFLOW_ERR_CHECK_EN_0,OVERFLOW_ERR_CHECK_EN_1" newline bitfld.long 0x08 1. "SHORT_FRAME_PREV_EOF_SEL," "0,1" newline bitfld.long 0x08 0. "SHORT_FRAME_DETECT_CHECK_EN,Short frame detection enable" "SHORT_FRAME_DETECT_CHECK_EN_0,SHORT_FRAME_DETECT_CHECK_EN_1" line.long 0x0C "STATUS_CBUF_WR_OUT_OF_RANGE_ERR," hexmask.long.word 0x0C 0.--11. 1. "CBUF_ERR,Indicates that the CBUF write address is out of the CBUF range" line.long 0x10 "STATUS_CBUF_WR_VBUF_START_ERR," hexmask.long.word 0x10 0.--11. 1. "CBUF_ERR,CBUF write is not to the base address at vbuf access start" line.long 0x14 "STATUS_CBUF_WR_ADDR_SEQ_ERROR," hexmask.long.word 0x14 0.--11. 1. "CBUF_ERR,CBUF address is not incrementing in raster scan order" line.long 0x18 "STATUS_CBUF_RD_OUT_OF_RANGE_ERROR," hexmask.long.word 0x18 0.--11. 1. "CBUF_ERR,Indicates that the CBUF read address is out of the CBUF range" line.long 0x1C "STATUS_CBUF_VBUF_RD_START_ERROR," hexmask.long.word 0x1C 0.--11. 1. "CBUF_ERR,CBUF read is not from the base address at VBUF access start" line.long 0x20 "STATUS_CBUF_RD_ADDR_SEQ_ERROR," hexmask.long.word 0x20 0.--11. 1. "CBUF_ERR,CBUF read address is not incrementing in raster scan order" line.long 0x24 "STATUS_CBUF_OVERFLOW_MID," hexmask.long.word 0x24 0.--11. 1. "CBUF_ERR,CBUF overflow condition detected in the middle of a frame" line.long 0x28 "STATUS_CBUF_OVERFLOW_WRAP," hexmask.long.word 0x28 0.--11. 1. "CBUF_ERR,CBUF overflow condition detected during buffer switching" line.long 0x2C "STATUS_CBUF_UNDERFLOW," hexmask.long.word 0x2C 0.--11. 1. "CBUF_ERR,CBUF underflow condition detected" line.long 0x30 "STATUS_CBUF_SHORT_FRAME_DETECT," hexmask.long.word 0x30 0.--11. 1. "CBUF_ERR,CBUF short frame detected" rgroup.long 0x360++0x03 line.long 0x00 "LAST_ILLEGAL_OCMC_ADDR," repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) rgroup.long ($2+0xA0)++0x03 line.long 0x00 "STATUS_SEC_ERROR_DISTR_$1,SEC data error bit distribution status [31:0]" repeat.end repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. ) tree "Channel_$1" group.long 0x24C++0x03 line.long 0x00 "CBUF_i_OCMC_BUF_SIZE_0," hexmask.long.word 0x00 4.--19. 1. "BUF_SIZE,SRAM size allocated for this CBUF - bits [19:4]" group.long 0x248++0x03 line.long 0x00 "CBUF_i_OCMC_START_ADDR_0," hexmask.long 0x00 4.--31. 1. "ADDR,SRAM start address for this CBUF - bits [30:4]" group.long 0x244++0x03 line.long 0x00 "CBUF_i_VBUF_END_ADDR_0," hexmask.long 0x00 4.--31. 1. "ADDR,Virtual frame end address for this CBUF - bits [30:4]" group.long 0x240++0x03 line.long 0x00 "CBUF_i_VBUF_START_ADDR_0," hexmask.long 0x00 4.--31. 1. "ADDR,Virtual frame start address for this CBUF - bits [30:4]" rgroup.long 0x304++0x03 line.long 0x00 "CBUF_k_LAST_RD_ADDR_0," rgroup.long 0x300++0x03 line.long 0x00 "CBUF_k_LAST_WR_ADDR_0," tree.end repeat.end tree.end repeat.end tree.end tree.open "PCIe_Controllers" tree "PCIe_SS1_EP_CFG_DBICS" base ad:0x51000000 group.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_DBICS_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline bitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x14 "PCIECTRL_EP_DBICS_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline bitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x18 "PCIECTRL_EP_DBICS_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x18 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x18 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline bitfld.long 0x18 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x18 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x18 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x1C "PCIECTRL_EP_DBICS_BAR3,Base Address Register 3 If BAR2.AS =" hexmask.long.word 0x1C 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x1C 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline bitfld.long 0x1C 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x1C 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x1C 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x20 "PCIECTRL_EP_DBICS_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.tbyte 0x20 12.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.byte 0x20 4.--11. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline bitfld.long 0x20 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x20 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x20 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x24 "PCIECTRL_EP_DBICS_BAR5,Base Address Register 5 If BAR4.AS =" hexmask.long.word 0x24 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x24 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline bitfld.long 0x24 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x24 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x24 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x28 "PCIECTRL_EP_DBICS_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_DBICS_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_DBICS_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_DBICS_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_DBICS_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" bitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PM_STATE,Power Management Control and Status Register" "PM_STATE_0,PM_STATE_1,PM_STATE_2,PM_STATE_3" group.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_DBICS_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_DBICS_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_DBICS_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline rbitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_DBICS_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "0,1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_DBICS_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS2_EP_CFG_DBICS" base ad:0x51800000 group.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_DBICS_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline bitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x14 "PCIECTRL_EP_DBICS_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline bitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x18 "PCIECTRL_EP_DBICS_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x18 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x18 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline bitfld.long 0x18 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x18 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x18 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x1C "PCIECTRL_EP_DBICS_BAR3,Base Address Register 3 If BAR2.AS =" hexmask.long.word 0x1C 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x1C 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline bitfld.long 0x1C 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x1C 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x1C 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x20 "PCIECTRL_EP_DBICS_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.tbyte 0x20 12.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.byte 0x20 4.--11. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline bitfld.long 0x20 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x20 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x20 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x24 "PCIECTRL_EP_DBICS_BAR5,Base Address Register 5 If BAR4.AS =" hexmask.long.word 0x24 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x24 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline bitfld.long 0x24 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x24 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x24 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x28 "PCIECTRL_EP_DBICS_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_DBICS_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_DBICS_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_DBICS_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_DBICS_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" bitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PM_STATE,Power Management Control and Status Register" "PM_STATE_0,PM_STATE_1,PM_STATE_2,PM_STATE_3" group.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_DBICS_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_DBICS_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_DBICS_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline rbitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" rbitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_DBICS_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "0,1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_DBICS_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS1_EP_CFG_DBICS2" base ad:0x51001000 group.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_DBICS2_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x10 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x10 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x14 "PCIECTRL_EP_DBICS2_BAR1_MASK,Base Address Register 1 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode. contains the upper bits of BAR0 mask" hexmask.long 0x14 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x14 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x18 "PCIECTRL_EP_DBICS2_BAR2_MASK,Base Address Register 2 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x18 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x18 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x1C "PCIECTRL_EP_DBICS2_BAR3_MASK,Base Address Register 3 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR2 is in 64-bit mode. contains the upper bits of BAR2 mask" hexmask.long 0x1C 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x1C 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x20 "PCIECTRL_EP_DBICS2_BAR4_MASK,Base Address Register 4 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x20 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x20 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x24 "PCIECTRL_EP_DBICS2_BAR5_MASK,Base Address Register 5 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR4 is in 64-bit mode. contains the upper bits of BAR4 mask" hexmask.long 0x24 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x24 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x28 "PCIECTRL_EP_DBICS2_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_DBICS2_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_DBICS2_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_DBICS2_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_DBICS2_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" bitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PWR_STATE,Device Power State" "PWR_STATE_0,PWR_STATE_1,PWR_STATE_2,PWR_STATE_3" group.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_DBICS2_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_DBICS2_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_DBICS2_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_DBICS2_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "0,1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_DBICS2_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS2_EP_CFG_DBICS2" base ad:0x51801000 group.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_DBICS2_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x10 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x10 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x14 "PCIECTRL_EP_DBICS2_BAR1_MASK,Base Address Register 1 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode. contains the upper bits of BAR0 mask" hexmask.long 0x14 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x14 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x18 "PCIECTRL_EP_DBICS2_BAR2_MASK,Base Address Register 2 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x18 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x18 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x1C "PCIECTRL_EP_DBICS2_BAR3_MASK,Base Address Register 3 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR2 is in 64-bit mode. contains the upper bits of BAR2 mask" hexmask.long 0x1C 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x1C 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x20 "PCIECTRL_EP_DBICS2_BAR4_MASK,Base Address Register 4 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" hexmask.long 0x20 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x20 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x24 "PCIECTRL_EP_DBICS2_BAR5_MASK,Base Address Register 5 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR4 is in 64-bit mode. contains the upper bits of BAR4 mask" hexmask.long 0x24 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x24 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x28 "PCIECTRL_EP_DBICS2_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_DBICS2_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_DBICS2_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_DBICS2_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_DBICS2_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" bitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PWR_STATE,Device Power State" "PWR_STATE_0,PWR_STATE_1,PWR_STATE_2,PWR_STATE_3" group.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_DBICS2_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_DBICS2_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_DBICS2_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_DBICS2_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "0,1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_DBICS2_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS1_EP_CFG_PCIe" base ad:0x20000000 rgroup.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_PCIEWIRE_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_PCIEWIRE_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline rbitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS)" "0,1,2,3" newline rbitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x14 "PCIECTRL_EP_PCIEWIRE_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline rbitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x18 "PCIECTRL_EP_PCIEWIRE_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x18 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x18 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline rbitfld.long 0x18 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x18 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x18 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x1C "PCIECTRL_EP_PCIEWIRE_BAR3,Base Address Register 3 If BAR2.AS =" hexmask.long.word 0x1C 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x1C 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline rbitfld.long 0x1C 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x1C 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x1C 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x20 "PCIECTRL_EP_PCIEWIRE_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.tbyte 0x20 12.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.byte 0x20 4.--11. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline rbitfld.long 0x20 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x20 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x20 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x24 "PCIECTRL_EP_PCIEWIRE_BAR5,Base Address Register 5 If BAR4.AS =" hexmask.long.word 0x24 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x24 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline rbitfld.long 0x24 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x24 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x24 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x28 "PCIECTRL_EP_PCIEWIRE_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_PCIEWIRE_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_PCIEWIRE_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (i.e. programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_PCIEWIRE_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_PCIEWIRE_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" rbitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PWR_STATE,Device Power State" "PWR_STATE_0,PWR_STATE_1,PWR_STATE_2,PWR_STATE_3" rgroup.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_PCIEWIRE_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline bitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline bitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline bitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_PCIEWIRE_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" rbitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline rbitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "0,1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_PCIEWIRE_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS2_EP_CFG_PCIe" base ad:0x30000000 rgroup.long 0x00++0x37 line.long 0x00 "PCIECTRL_EP_PCIEWIRE_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable" "0,1" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_EP_PCIEWIRE_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline rbitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS)" "0,1,2,3" newline rbitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x14 "PCIECTRL_EP_PCIEWIRE_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline rbitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x18 "PCIECTRL_EP_PCIEWIRE_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x18 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x18 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline rbitfld.long 0x18 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x18 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x18 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x1C "PCIECTRL_EP_PCIEWIRE_BAR3,Base Address Register 3 If BAR2.AS =" hexmask.long.word 0x1C 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x1C 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline rbitfld.long 0x1C 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x1C 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x1C 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x20 "PCIECTRL_EP_PCIEWIRE_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.tbyte 0x20 12.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.byte 0x20 4.--11. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline rbitfld.long 0x20 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x20 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x20 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x24 "PCIECTRL_EP_PCIEWIRE_BAR5,Base Address Register 5 If BAR4.AS =" hexmask.long.word 0x24 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x24 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline rbitfld.long 0x24 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" rbitfld.long 0x24 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline rbitfld.long 0x24 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS)" "0,1" line.long 0x28 "PCIECTRL_EP_PCIEWIRE_CARDBUS_CIS_POINTER," line.long 0x2C "PCIECTRL_EP_PCIEWIRE_SUBID_SUBVENDORID," hexmask.long.word 0x2C 16.--31. 1. "SUBSYS_DEV_ID_N,Subsystem ID (CS)" hexmask.long.word 0x2C 0.--15. 1. "SUBSYS_VENDOR_ID_N,Subsystem Vendor ID (CS)" line.long 0x30 "PCIECTRL_EP_PCIEWIRE_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x30 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (i.e. programmable)" rbitfld.long 0x30 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x30 0. "EXROM_EN,Expansion ROM Enable" "0,1" line.long 0x34 "PCIECTRL_EP_PCIEWIRE_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" group.long 0x3C++0x0B line.long 0x00 "PCIECTRL_EP_PCIEWIRE_INTERRUPT,Int Pin and line" hexmask.long.byte 0x00 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x00 0.--7. 1. "INT_LIN,Interrupt Line" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_PM_CAP,Power Management Capability structure header" bitfld.long 0x04 27.--31. "PME_SP,PME Support (CS); Power states from which PME messages can be sent (active hi one bit per state) Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 26. "D2_SP,D2 Support (CS)" "0,1" newline bitfld.long 0x04 25. "D1_SP,D1 Support (CS)" "0,1" bitfld.long 0x04 22.--24. "AUX_CUR,AUX Current (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 21. "DSI,Device Specific Initialization (CS)" "0,1" bitfld.long 0x04 19. "PME_CLK,PME Clock hardwired to 0 (CS)" "0,1" newline bitfld.long 0x04 16.--18. "PMC_VER,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 8.--15. 1. "PM_NX_PTR,Next Capability Pointer (CS)" newline hexmask.long.byte 0x04 0.--7. 1. "CAP_ID,Capability ID" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_PM_CSR,Power Management Control and Status Register" hexmask.long.byte 0x08 24.--31. 1. "DATA1,Data register for additional information(not supported)" rbitfld.long 0x08 23. "BP_CCE,Bus Power/Clock Control Enable hardwired to 0" "0,1" newline rbitfld.long 0x08 22. "B2B3_SP,B2/B3 Support hardwired to 0" "0,1" bitfld.long 0x08 15. "PME_STATUS,PME Status (Sticky bit)" "0,1" newline rbitfld.long 0x08 13.--14. "DATA_SCALE,Data Scale (not supported)" "0,1,2,3" rbitfld.long 0x08 9.--12. "DATA_SEL,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x08 8. "PME_EN,PME Enable (Sticky bit)" "PME_EN_0,PME_EN_1" rbitfld.long 0x08 3. "NSR,No Soft Reset (CS)" "0,1" newline bitfld.long 0x08 0.--1. "PWR_STATE,Device Power State" "PWR_STATE_0,PWR_STATE_1,PWR_STATE_2,PWR_STATE_3" rgroup.long 0x70++0x13 line.long 0x00 "PCIECTRL_EP_PCIEWIRE_PCIE_CAP,PCIE cap structure" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented Must be 0 for an endpoint" "0,1" newline bitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type Value depends on assigned type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 28. "FLR_EN,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value (CS)" "0,1,2,3" newline hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value (CS)" bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" newline bitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" newline bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable" "0,1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline bitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_EP_PCIEWIRE_LNK_CAS,PCIE Link Control and Status" rbitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" rbitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" rbitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration" "0,1" newline rbitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" rbitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline rbitfld.long 0x10 3. "RCB,Read Completion Boundary (CS)" "0,1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" rgroup.long 0x94++0x0F line.long 0x00 "PCIECTRL_EP_PCIEWIRE_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x00 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x00 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x00 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x00 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x00 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x00 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x00 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x00 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x00 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_EP_PCIEWIRE_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x04 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x04 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x04 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x04 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x04 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x04 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x04 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x04 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x04 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PCIECTRL_EP_PCIEWIRE_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x08 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x08 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x0C "PCIECTRL_EP_PCIEWIRE_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0C 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x0C 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x0C 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x0C 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x0C 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x0C 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x0C 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x0C 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0C 6. "SEL_DEEMP,Selectable De-emphasize" "0,1" rbitfld.long 0x0C 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x0C 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x0C 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS1_PL_CONF" base ad:0x51000700 group.long 0x00++0x27 line.long 0x00 "PCIECTRL_PL_LAT_REL_TIM,Ack Latency and Replay Timer Register" hexmask.long.word 0x00 16.--31. 1. "REPLAY_TIME_LIMIT,The replay timer expires when it reaches this limit; The core initiates a replay upon reception of a Nak or when the replay timer expires; The default value depends on number of bytes (NB) per cycle which is defined by the maximum core.." hexmask.long.word 0x00 0.--15. 1. "ACK_LATENCY_TIME_LIMIT,The Ack/Nak latency timer expires when it reaches this limit; The default value depends on number of bytes (NB) per cycle which is defined by the maximum core base frequency of the device PCIe core corresponding to 250 MHz for.." line.long 0x04 "PCIECTRL_PL_VENDOR_SPECIFIC_DLLP,Vendor Specific DLLP Register" line.long 0x08 "PCIECTRL_PL_PT_LNK_R,Port Force Link Register" hexmask.long.byte 0x08 24.--31. 1. "LOW_POWER_ENTR_CNT,The Power Management state will wait for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power; This register is intended for applications that do not let the core handle a completion for.." bitfld.long 0x08 16.--21. "FORCED_LINK_COMMAND,Link command transmitted by setting Force_Link (bit 15);" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 15. "FORCE_LINK,Forces the LTSSM state and the Link command specified in this register; Self-clearing - FORCE" "?,FORCE_LINK_1" bitfld.long 0x08 8.--11. "FORCED_LTSSM_STATE,LTSSM state forced by setting Force_Link (bit 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x08 0.--7. 1. "LINK_NUM,Link Number; Not used for Endpoint" line.long 0x0C "PCIECTRL_PL_ACK_FREQ_ASPM,Ack Frequency and L0-L1 ASPM Control Register (Sticky)" bitfld.long 0x0C 30. "L1_ENTR_WO_L0S,Enter ASPM L1 without receive in L0s; Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in L0s); When not set core goes to ASPM L1 only after idle period during which both receive and transmit are in L0s" "0,1" bitfld.long 0x0C 27.--29. "L1_ENTR_LAT,L1 Entrance Latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 24.--26. "L0S_ENTR_LAT,L0s Entrance Latency; Values correspond to" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 16.--23. 1. "COMMOM_CLK_N_FTS,Alternative N_FTS value for common clock mode" newline hexmask.long.byte 0x0C 8.--15. 1. "N_FTS,Number of Fast Training Sequence (FTS) ordered sets to be transmitted when exiting L0s to L0; The maximum that can be requested is 255; Value 0 is not supported and may cause LTSSM to go into Recovery upon L0s exit" hexmask.long.byte 0x0C 0.--7. 1. "ACK_FREQ,Ack Frequency; Number of pending ACKs accumulated before sending an ACK DLLP" line.long 0x10 "PCIECTRL_PL_PT_LNK_CTRL_R,Port Link Control Register (Sticky)" rbitfld.long 0x10 23. "CROSSLINK_ACT,Crosslink Active" "0,1" bitfld.long 0x10 22. "CROSSLINK_EN,Crosslink Enable" "0,1" newline bitfld.long 0x10 16.--21. "LINK_MODE,Link Mode Enable; Write 1 to bit N to enable (2**N)-lane mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 7. "FAST_LINK,Fast Link Mode" "0,1" newline bitfld.long 0x10 5. "DL_EN,DLL Link Enable" "0,1" bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert" "0,1" newline bitfld.long 0x10 2. "LB_EN,Loopback Enable" "0,1" bitfld.long 0x10 1. "SCRAMBLE_DIS,Scramble Disable" "0,1" newline bitfld.long 0x10 0. "VEN_DLLP_REQ,Vendor Specific DLLP transmit Request" "0,1" line.long 0x14 "PCIECTRL_PL_LN_SKW_R,Lane Skew Register (Sticky)" bitfld.long 0x14 31. "DIS_L2L_SKEW,Disable Lane-to-Lane Deskew" "0,1" bitfld.long 0x14 25. "ACKNAK_DIS,Ack/Nak Disable" "0,1" newline bitfld.long 0x14 24. "FC_DIS,Flow Control Disable" "0,1" hexmask.long.tbyte 0x14 0.--23. 1. "LANE_SKEW,Insert Lane Skew for Transmit" line.long 0x18 "PCIECTRL_PL_SYMB_N_R,Timer Control and Symbol Number Register (Sticky)" bitfld.long 0x18 19.--23. "ACK_LATENCY_INC,Timer Modifier for Ack/Nak Latency Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 14.--18. "REPLAY_ADJ,Timer Modifier for Replay Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC,Configuration Requests targeted at function numbers above this value will be returned with UR (unsupported request)" line.long 0x1C "PCIECTRL_PL_SYMB_T_R,Symbol Timer Register and Filter Mask Register 1 (Sticky)" hexmask.long.word 0x1C 16.--31. 1. "FLT_MSK_1,Mask RADM Filtering and Error Handling Rules: Mask 1" bitfld.long 0x1C 15. "DIS_FC_TIM,Disable FC Watchdog Timer" "0,1" newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT,SKP Interval Value minus one PIPE clock cycles" line.long 0x20 "PCIECTRL_PL_FL_MSK_R2,Filter Mask Register 2 (Sticky)" line.long 0x24 "PCIECTRL_PL_OBNP_SUBREQ_CTRL,AXI Multiple Outbound Decomposed NP SubRequests Control Register (Sticky)" bitfld.long 0x24 0. "EN_OBNP_SUBREQ,Enable AXI Multiple Outbound Decomposed NP Sub-Requests" "0,1" rgroup.long 0x30++0x23 line.long 0x00 "PCIECTRL_PL_TR_P_STS_R,Transmit Posted FC Credit Status Register (Sticky)" hexmask.long.byte 0x00 12.--19. 1. "PH_CRDT,Transmit Posted Header FC Credits" hexmask.long.word 0x00 0.--11. 1. "PD_CRDT,Transmit Posted Data FC Credits" line.long 0x04 "PCIECTRL_PL_TR_NP_STS_R,Transmit Non-Posted FC Credit Status Register (Sticky)" hexmask.long.byte 0x04 12.--19. 1. "NPH_CRDT,Transmit Non-Posted Header FC Credits" hexmask.long.word 0x04 0.--11. 1. "NPD_CRDT,Transmit Non-Posted Data FC Credits" line.long 0x08 "PCIECTRL_PL_TR_C_STS_R,Transmit Completion FC Credit Status Register (Sticky)" hexmask.long.byte 0x08 12.--19. 1. "CPLH_CRDT,Transmit Completion Header FC Credits" hexmask.long.word 0x08 0.--11. 1. "CPLD_CRDT,Transmit Completion Data FC Credits" line.long 0x0C "PCIECTRL_PL_Q_STS_R,Queue Status Register (Sticky)" bitfld.long 0x0C 31. "FC_LATENCY_OVR_EN,FC Latency Timer Override Enable" "0,1" hexmask.long.word 0x0C 16.--28. 1. "FC_LATENCY_OVR,FC Latency Timer Override Value" newline rbitfld.long 0x0C 2. "RCVQ_NOT_EMPTY,Received Queue Not Empty" "0,1" rbitfld.long 0x0C 1. "RTYB_NOT_EMPTY,Transmit Retry Buffer Not Empty" "0,1" newline rbitfld.long 0x0C 0. "CRDT_NOT_RTRN,Received TLP FC Credits Not Returned" "0,1" line.long 0x10 "PCIECTRL_PL_VC_TR_A_R1,VC Transmit Arbitration Register 1 (Sticky)" hexmask.long.byte 0x10 24.--31. 1. "WRR_VC3,WRR Weight for VC3" hexmask.long.byte 0x10 16.--23. 1. "WRR_VC2,WRR Weight for VC2" newline hexmask.long.byte 0x10 8.--15. 1. "WRR_VC1,WRR Weight for VC1" hexmask.long.byte 0x10 0.--7. 1. "WRR_VC0,WRR Weight for VC0" line.long 0x14 "PCIECTRL_PL_VC_TR_A_R2,VC Transmit Arbitration Register 2 (Sticky)" hexmask.long.byte 0x14 24.--31. 1. "WRR_VC7,WRR Weight for VC7" hexmask.long.byte 0x14 16.--23. 1. "WRR_VC6,WRR Weight for VC6" newline hexmask.long.byte 0x14 8.--15. 1. "WRR_VC5,WRR Weight for VC5" hexmask.long.byte 0x14 0.--7. 1. "WRR_VC4,WRR Weight for VC4" line.long 0x18 "PCIECTRL_PL_VC0_PR_Q_C,VC0 Posted Receive Queue Control (Sticky)" bitfld.long 0x18 31. "STRICT_VC_PRIORITY,VC Ordering for Receive Queues - ROUND_ROBIN" "STRICT_VC_PRIORITY_0,STRICT_VC_PRIORITY_1" bitfld.long 0x18 30. "ORDERING_RULES,VC0 TLP Type Ordering Rules - STRICT" "ORDERING_RULES_0,ORDERING_RULES_1" newline bitfld.long 0x18 21.--23. "P_QMODE,VC0 Poster TLP Queue Mode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 12.--19. 1. "P_HCRD,VC0 Posted Header Credits" newline hexmask.long.word 0x18 0.--11. 1. "P_DCRD,VC0 Posted Data Credits" line.long 0x1C "PCIECTRL_PL_VC0_NPR_Q_C,VC0 Non-Posted Receive Queue Control (Sticky)" bitfld.long 0x1C 21.--23. "NP_QMODE,VC0 Non-Poster TLP Queue Mode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 12.--19. 1. "NP_HCRD,VC0 Non-Posted Header Credits" newline hexmask.long.word 0x1C 0.--11. 1. "NP_DCRD,VC0 Non-Posted Data Credits" line.long 0x20 "PCIECTRL_PL_VC0_CR_Q_C,VC0 Completion Receive Queue Control (Sticky)" bitfld.long 0x20 21.--23. "CPL_QMODE,VC0 Completion TLP Queue Mode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 12.--19. 1. "CPL_HCRD,VC0 Completion Header Credits" newline hexmask.long.word 0x20 0.--11. 1. "CPL_DCRD,VC0 Completion Data Credits" group.long 0x10C++0x0B line.long 0x00 "PCIECTRL_PL_WIDTH_SPEED_CTL,Link Width and Speed Change Control Register (Sticky)" bitfld.long 0x00 20. "CFG_UP_SEL_DEEMPH,Used to set the de-emphasis level for Upstream Ports" "0,1" bitfld.long 0x00 19. "CFG_TX_COMPLIANCE_RCV,Config Tx Compliance Receive Bit" "0,1" newline bitfld.long 0x00 18. "CFG_PHY_TXSWING,Config PHY Tx Swing" "0,1" bitfld.long 0x00 17. "CFG_DIRECTED_SPEED_CHANGE,Directed Speed Change" "0,1" newline hexmask.long.word 0x00 8.--16. 1. "CFG_LANE_EN,Predetermined Number of Lanes" hexmask.long.byte 0x00 0.--7. 1. "CFG_GEN2_N_FTS,Number of Fast Training Sequences" line.long 0x04 "PCIECTRL_PL_PHY_STS_R,PHY Status Register (Sticky)" line.long 0x08 "PCIECTRL_PL_PHY_CTRL_R,PHY Control Register (Sticky)" group.long 0x120++0x07 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_ADDRESS,MSI Controller Address Register (RC-mode MSI receiver)" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS,MSI Controller Upper Address Register (RC-mode MSI receiver)" group.long 0x188++0x03 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_GPIO,MSI Controller General Purpose IO Register (RC-mode MSI receiver)" group.long 0x1B8++0x07 line.long 0x00 "PCIECTRL_PL_PIPE_LOOPBACK,PIPE loopback control register (Sticky)" bitfld.long 0x00 31. "LOOPBACK_EN,PIPE Loopback Enable" "0,1" line.long 0x04 "PCIECTRL_PL_DBI_RO_WR_EN,DBI Read-Only register Write Enable (Sticky)" bitfld.long 0x04 0. "CX_DBI_RO_WR_EN,Control the writability over DBI of certain configuration fields that are RO over the PCIe wire - WRDIS" "CX_DBI_RO_WR_EN_0,CX_DBI_RO_WR_EN_1" group.long 0x1D0++0x07 line.long 0x00 "PCIECTRL_PL_AXIS_SLV_ERR_RESP,AXI Slave Error Response Register (Sticky)" bitfld.long 0x00 3. "RESET_TIMEOUT_ERR_MAP,Graceful Reset and Link Timeout Slave Error Response Mapping" "0,1" bitfld.long 0x00 2. "NO_VID_ERR_MAP,Vendor ID Non-existent Slave Error Response Mapping" "0,1" newline bitfld.long 0x00 1. "DBI_ERR_MAP,DBI Slave Error Response Mapping" "0,1" bitfld.long 0x00 0. "SLAVE_ERR_MAP,Global Slave Error Response Mapping" "0,1" line.long 0x04 "PCIECTRL_PL_AXIS_SLV_TIMEOUT,Link Down AXI Slave Timeout Register (Sticky)" bitfld.long 0x04 8. "FLUSH_EN,Enable flush" "0,1" hexmask.long.byte 0x04 0.--7. 1. "TIMEOUT_VALUE,Timeout Value (ms)" group.long 0x200++0x23 line.long 0x00 "PCIECTRL_PL_IATU_INDEX,iATU Viewport Register: makes the registers of the corresponding iATU region accessible" bitfld.long 0x00 31. "REGION_DIRECTION,- OUTBOUND" "REGION_DIRECTION_0,REGION_DIRECTION_1" bitfld.long 0x00 0.--3. "REGION_INDEX,Outbound region from 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_PL_IATU_REG_CTRL_1,iATU Region Control 1 Register" bitfld.long 0x04 20.--24. "FUNCTION_NUMBER,Outbound: F.N; applied to outgoing TLP (RID) with matching addess Inbound: F.N.-match criteria for incoming TLP (if Function_Number_match_enable=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--17. "AT,Outbound: AT applied to outgoing TLP with matching addess Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)" "0,1,2,3" newline bitfld.long 0x04 9.--10. "ATTR,Outbound: ATTR applied to outgoing TLP with matching addess Inbound: ATTR-match criteria (if ATTR_match_enable=1)" "0,1,2,3" bitfld.long 0x04 8. "TD,Outbound: TD applied to outgoing TLP with matching addess Inbound: TD-match criteria (if TD_match_enable=1)" "0,1" newline bitfld.long 0x04 5.--7. "TC,Outbound: TC applied to outgoing TLP with matching addess Inbound: TC-match criteria (if TC_match_enable=1)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "TYPE,Outbound: TYPE applied to outgoing TLP with matching addess Inbound: TYPE-match criteria" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "PCIECTRL_PL_IATU_REG_CTRL_2,iATU Region Control 2 Register" bitfld.long 0x08 31. "REGION_ENABLE,Enable AT for this region" "0,1" bitfld.long 0x08 30. "MATCH_MODE,Sets inbound TLP match mode depending on TYPE - _0" "MATCH_MODE_0,MATCH_MODE_1" newline bitfld.long 0x08 29. "INVERT_MODE,Redefine match criteria as outside the defined range (instead of inside)" "0,1" bitfld.long 0x08 28. "CFG_SHIFT_MODE,Enable the shifting of CFG CID (BDF) incoming and outgoing TLP; CFG get mapped to a contiguous" "0,1" newline bitfld.long 0x08 27. "FUZZY_TYPE_MATCH_MODE,Outbound: DMA Bypass Mode Inbound: Relax matching on inbound TLP TYPE: CfgRd0 == CfgRd1 CfgWr0 == CfgWr1 MRd == MRdLk routing field of Msg/MsgD ignored" "0,1" bitfld.long 0x08 24.--25. "RESPONSE_CODE,Override HW-generated completion status when responding inbound TLP" "0,1,2,3" newline bitfld.long 0x08 21. "MESSAGE_CODE_MATCH_ENABLE,Enable MessageCode match criteria on inbound TLP" "0,1" bitfld.long 0x08 20. "VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE,VIRTUAL FUNCTIONS NOT IMPLEMENTED: NOT USED" "0,1" newline bitfld.long 0x08 19. "FUNCTION_NUMBER_MATCH_ENABLE,Outbound: Function Number Translation Bypass Inbound: Enable Function Number match criteria" "0,1" bitfld.long 0x08 18. "AT_MATCH_ENABLE,Enable AT match criteria on inbound TLP ATS NOT SUPPORTED: DO NOT USE" "0,1" newline bitfld.long 0x08 16. "ATTR_MATCH_ENABLE,Enable ATTR match criteria on inbound TLP" "0,1" bitfld.long 0x08 15. "TD_MATCH_ENABLE,Enable TD match criteria on inbound TLP" "0,1" newline bitfld.long 0x08 14. "TC_MATCH_ENABLE,Enable TC match criteria on inbound TLP" "0,1" bitfld.long 0x08 8.--10. "BAR_NUMBER,BAR number for mayching with incoming MEM I/O TLP (if Match_Mode = 1)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 0.--7. 1. "MESSAGECODE,Outbound: MessageCode applied to outgoing message TLP with matching addess Inbound: MessageCode-match criteria for infoming message TLP (if Message_Code_match_enable=1)" line.long 0x0C "PCIECTRL_PL_IATU_REG_LOWER_BASE,iATU Region Lower Base Address Register (2**12 = 4kbyte - aligned)" hexmask.long.tbyte 0x0C 12.--31. 1. "IATU_REG_LOWER_BASE," hexmask.long.word 0x0C 0.--11. 1. "ZERO," line.long 0x10 "PCIECTRL_PL_IATU_REG_UPPER_BASE,iATU Region Upper Base Address Register" line.long 0x14 "PCIECTRL_PL_IATU_REG_LIMIT,iATU Region Limit Address Register" hexmask.long.tbyte 0x14 12.--31. 1. "IATU_REG_LIMIT," hexmask.long.word 0x14 0.--11. 1. "ONES," line.long 0x18 "PCIECTRL_PL_IATU_REG_LOWER_TARGET,iATU Region Lower Target Address Register (2**12 = 4kbyte - aligned)" hexmask.long.tbyte 0x18 12.--31. 1. "IATU_REG_LOWER_TARGET," hexmask.long.word 0x18 0.--11. 1. "ZERO," line.long 0x1C "PCIECTRL_PL_IATU_REG_UPPER_TARGET,iATU Region Upper Target Address Register" line.long 0x20 "PCIECTRL_PL_IATU_REG_CTRL_3,iATU Region Control 3 Register; VIRTUAL FUNCTIONS NOT IMPLEMENTED: NOT USED" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" group.long 0x128++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_0,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_0,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_0,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end repeat.end tree.end tree "PCIe_SS2_PL_CONF" base ad:0x51800700 group.long 0x00++0x27 line.long 0x00 "PCIECTRL_PL_LAT_REL_TIM,Ack Latency and Replay Timer Register" hexmask.long.word 0x00 16.--31. 1. "REPLAY_TIME_LIMIT,The replay timer expires when it reaches this limit; The core initiates a replay upon reception of a Nak or when the replay timer expires; The default value depends on number of bytes (NB) per cycle which is defined by the maximum core.." hexmask.long.word 0x00 0.--15. 1. "ACK_LATENCY_TIME_LIMIT,The Ack/Nak latency timer expires when it reaches this limit; The default value depends on number of bytes (NB) per cycle which is defined by the maximum core base frequency of the device PCIe core corresponding to 250 MHz for.." line.long 0x04 "PCIECTRL_PL_VENDOR_SPECIFIC_DLLP,Vendor Specific DLLP Register" line.long 0x08 "PCIECTRL_PL_PT_LNK_R,Port Force Link Register" hexmask.long.byte 0x08 24.--31. 1. "LOW_POWER_ENTR_CNT,The Power Management state will wait for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power; This register is intended for applications that do not let the core handle a completion for.." bitfld.long 0x08 16.--21. "FORCED_LINK_COMMAND,Link command transmitted by setting Force_Link (bit 15);" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x08 15. "FORCE_LINK,Forces the LTSSM state and the Link command specified in this register; Self-clearing - FORCE" "?,FORCE_LINK_1" bitfld.long 0x08 8.--11. "FORCED_LTSSM_STATE,LTSSM state forced by setting Force_Link (bit 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x08 0.--7. 1. "LINK_NUM,Link Number; Not used for Endpoint" line.long 0x0C "PCIECTRL_PL_ACK_FREQ_ASPM,Ack Frequency and L0-L1 ASPM Control Register (Sticky)" bitfld.long 0x0C 30. "L1_ENTR_WO_L0S,Enter ASPM L1 without receive in L0s; Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in L0s); When not set core goes to ASPM L1 only after idle period during which both receive and transmit are in L0s" "0,1" bitfld.long 0x0C 27.--29. "L1_ENTR_LAT,L1 Entrance Latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 24.--26. "L0S_ENTR_LAT,L0s Entrance Latency; Values correspond to" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0C 16.--23. 1. "COMMOM_CLK_N_FTS,Alternative N_FTS value for common clock mode" newline hexmask.long.byte 0x0C 8.--15. 1. "N_FTS,Number of Fast Training Sequence (FTS) ordered sets to be transmitted when exiting L0s to L0; The maximum that can be requested is 255; Value 0 is not supported and may cause LTSSM to go into Recovery upon L0s exit" hexmask.long.byte 0x0C 0.--7. 1. "ACK_FREQ,Ack Frequency; Number of pending ACKs accumulated before sending an ACK DLLP" line.long 0x10 "PCIECTRL_PL_PT_LNK_CTRL_R,Port Link Control Register (Sticky)" rbitfld.long 0x10 23. "CROSSLINK_ACT,Crosslink Active" "0,1" bitfld.long 0x10 22. "CROSSLINK_EN,Crosslink Enable" "0,1" newline bitfld.long 0x10 16.--21. "LINK_MODE,Link Mode Enable; Write 1 to bit N to enable (2**N)-lane mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 7. "FAST_LINK,Fast Link Mode" "0,1" newline bitfld.long 0x10 5. "DL_EN,DLL Link Enable" "0,1" bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert" "0,1" newline bitfld.long 0x10 2. "LB_EN,Loopback Enable" "0,1" bitfld.long 0x10 1. "SCRAMBLE_DIS,Scramble Disable" "0,1" newline bitfld.long 0x10 0. "VEN_DLLP_REQ,Vendor Specific DLLP transmit Request" "0,1" line.long 0x14 "PCIECTRL_PL_LN_SKW_R,Lane Skew Register (Sticky)" bitfld.long 0x14 31. "DIS_L2L_SKEW,Disable Lane-to-Lane Deskew" "0,1" bitfld.long 0x14 25. "ACKNAK_DIS,Ack/Nak Disable" "0,1" newline bitfld.long 0x14 24. "FC_DIS,Flow Control Disable" "0,1" hexmask.long.tbyte 0x14 0.--23. 1. "LANE_SKEW,Insert Lane Skew for Transmit" line.long 0x18 "PCIECTRL_PL_SYMB_N_R,Timer Control and Symbol Number Register (Sticky)" bitfld.long 0x18 19.--23. "ACK_LATENCY_INC,Timer Modifier for Ack/Nak Latency Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 14.--18. "REPLAY_ADJ,Timer Modifier for Replay Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC,Configuration Requests targeted at function numbers above this value will be returned with UR (unsupported request)" line.long 0x1C "PCIECTRL_PL_SYMB_T_R,Symbol Timer Register and Filter Mask Register 1 (Sticky)" hexmask.long.word 0x1C 16.--31. 1. "FLT_MSK_1,Mask RADM Filtering and Error Handling Rules: Mask 1" bitfld.long 0x1C 15. "DIS_FC_TIM,Disable FC Watchdog Timer" "0,1" newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT,SKP Interval Value minus one PIPE clock cycles" line.long 0x20 "PCIECTRL_PL_FL_MSK_R2,Filter Mask Register 2 (Sticky)" line.long 0x24 "PCIECTRL_PL_OBNP_SUBREQ_CTRL,AXI Multiple Outbound Decomposed NP SubRequests Control Register (Sticky)" bitfld.long 0x24 0. "EN_OBNP_SUBREQ,Enable AXI Multiple Outbound Decomposed NP Sub-Requests" "0,1" rgroup.long 0x30++0x23 line.long 0x00 "PCIECTRL_PL_TR_P_STS_R,Transmit Posted FC Credit Status Register (Sticky)" hexmask.long.byte 0x00 12.--19. 1. "PH_CRDT,Transmit Posted Header FC Credits" hexmask.long.word 0x00 0.--11. 1. "PD_CRDT,Transmit Posted Data FC Credits" line.long 0x04 "PCIECTRL_PL_TR_NP_STS_R,Transmit Non-Posted FC Credit Status Register (Sticky)" hexmask.long.byte 0x04 12.--19. 1. "NPH_CRDT,Transmit Non-Posted Header FC Credits" hexmask.long.word 0x04 0.--11. 1. "NPD_CRDT,Transmit Non-Posted Data FC Credits" line.long 0x08 "PCIECTRL_PL_TR_C_STS_R,Transmit Completion FC Credit Status Register (Sticky)" hexmask.long.byte 0x08 12.--19. 1. "CPLH_CRDT,Transmit Completion Header FC Credits" hexmask.long.word 0x08 0.--11. 1. "CPLD_CRDT,Transmit Completion Data FC Credits" line.long 0x0C "PCIECTRL_PL_Q_STS_R,Queue Status Register (Sticky)" bitfld.long 0x0C 31. "FC_LATENCY_OVR_EN,FC Latency Timer Override Enable" "0,1" hexmask.long.word 0x0C 16.--28. 1. "FC_LATENCY_OVR,FC Latency Timer Override Value" newline rbitfld.long 0x0C 2. "RCVQ_NOT_EMPTY,Received Queue Not Empty" "0,1" rbitfld.long 0x0C 1. "RTYB_NOT_EMPTY,Transmit Retry Buffer Not Empty" "0,1" newline rbitfld.long 0x0C 0. "CRDT_NOT_RTRN,Received TLP FC Credits Not Returned" "0,1" line.long 0x10 "PCIECTRL_PL_VC_TR_A_R1,VC Transmit Arbitration Register 1 (Sticky)" hexmask.long.byte 0x10 24.--31. 1. "WRR_VC3,WRR Weight for VC3" hexmask.long.byte 0x10 16.--23. 1. "WRR_VC2,WRR Weight for VC2" newline hexmask.long.byte 0x10 8.--15. 1. "WRR_VC1,WRR Weight for VC1" hexmask.long.byte 0x10 0.--7. 1. "WRR_VC0,WRR Weight for VC0" line.long 0x14 "PCIECTRL_PL_VC_TR_A_R2,VC Transmit Arbitration Register 2 (Sticky)" hexmask.long.byte 0x14 24.--31. 1. "WRR_VC7,WRR Weight for VC7" hexmask.long.byte 0x14 16.--23. 1. "WRR_VC6,WRR Weight for VC6" newline hexmask.long.byte 0x14 8.--15. 1. "WRR_VC5,WRR Weight for VC5" hexmask.long.byte 0x14 0.--7. 1. "WRR_VC4,WRR Weight for VC4" line.long 0x18 "PCIECTRL_PL_VC0_PR_Q_C,VC0 Posted Receive Queue Control (Sticky)" bitfld.long 0x18 31. "STRICT_VC_PRIORITY,VC Ordering for Receive Queues - ROUND_ROBIN" "STRICT_VC_PRIORITY_0,STRICT_VC_PRIORITY_1" bitfld.long 0x18 30. "ORDERING_RULES,VC0 TLP Type Ordering Rules - STRICT" "ORDERING_RULES_0,ORDERING_RULES_1" newline bitfld.long 0x18 21.--23. "P_QMODE,VC0 Poster TLP Queue Mode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 12.--19. 1. "P_HCRD,VC0 Posted Header Credits" newline hexmask.long.word 0x18 0.--11. 1. "P_DCRD,VC0 Posted Data Credits" line.long 0x1C "PCIECTRL_PL_VC0_NPR_Q_C,VC0 Non-Posted Receive Queue Control (Sticky)" bitfld.long 0x1C 21.--23. "NP_QMODE,VC0 Non-Poster TLP Queue Mode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 12.--19. 1. "NP_HCRD,VC0 Non-Posted Header Credits" newline hexmask.long.word 0x1C 0.--11. 1. "NP_DCRD,VC0 Non-Posted Data Credits" line.long 0x20 "PCIECTRL_PL_VC0_CR_Q_C,VC0 Completion Receive Queue Control (Sticky)" bitfld.long 0x20 21.--23. "CPL_QMODE,VC0 Completion TLP Queue Mode" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 12.--19. 1. "CPL_HCRD,VC0 Completion Header Credits" newline hexmask.long.word 0x20 0.--11. 1. "CPL_DCRD,VC0 Completion Data Credits" group.long 0x10C++0x0B line.long 0x00 "PCIECTRL_PL_WIDTH_SPEED_CTL,Link Width and Speed Change Control Register (Sticky)" bitfld.long 0x00 20. "CFG_UP_SEL_DEEMPH,Used to set the de-emphasis level for Upstream Ports" "0,1" bitfld.long 0x00 19. "CFG_TX_COMPLIANCE_RCV,Config Tx Compliance Receive Bit" "0,1" newline bitfld.long 0x00 18. "CFG_PHY_TXSWING,Config PHY Tx Swing" "0,1" bitfld.long 0x00 17. "CFG_DIRECTED_SPEED_CHANGE,Directed Speed Change" "0,1" newline hexmask.long.word 0x00 8.--16. 1. "CFG_LANE_EN,Predetermined Number of Lanes" hexmask.long.byte 0x00 0.--7. 1. "CFG_GEN2_N_FTS,Number of Fast Training Sequences" line.long 0x04 "PCIECTRL_PL_PHY_STS_R,PHY Status Register (Sticky)" line.long 0x08 "PCIECTRL_PL_PHY_CTRL_R,PHY Control Register (Sticky)" group.long 0x120++0x07 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_ADDRESS,MSI Controller Address Register (RC-mode MSI receiver)" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS,MSI Controller Upper Address Register (RC-mode MSI receiver)" group.long 0x188++0x03 line.long 0x00 "PCIECTRL_PL_MSI_CTRL_GPIO,MSI Controller General Purpose IO Register (RC-mode MSI receiver)" group.long 0x1B8++0x07 line.long 0x00 "PCIECTRL_PL_PIPE_LOOPBACK,PIPE loopback control register (Sticky)" bitfld.long 0x00 31. "LOOPBACK_EN,PIPE Loopback Enable" "0,1" line.long 0x04 "PCIECTRL_PL_DBI_RO_WR_EN,DBI Read-Only register Write Enable (Sticky)" bitfld.long 0x04 0. "CX_DBI_RO_WR_EN,Control the writability over DBI of certain configuration fields that are RO over the PCIe wire - WRDIS" "CX_DBI_RO_WR_EN_0,CX_DBI_RO_WR_EN_1" group.long 0x1D0++0x07 line.long 0x00 "PCIECTRL_PL_AXIS_SLV_ERR_RESP,AXI Slave Error Response Register (Sticky)" bitfld.long 0x00 3. "RESET_TIMEOUT_ERR_MAP,Graceful Reset and Link Timeout Slave Error Response Mapping" "0,1" bitfld.long 0x00 2. "NO_VID_ERR_MAP,Vendor ID Non-existent Slave Error Response Mapping" "0,1" newline bitfld.long 0x00 1. "DBI_ERR_MAP,DBI Slave Error Response Mapping" "0,1" bitfld.long 0x00 0. "SLAVE_ERR_MAP,Global Slave Error Response Mapping" "0,1" line.long 0x04 "PCIECTRL_PL_AXIS_SLV_TIMEOUT,Link Down AXI Slave Timeout Register (Sticky)" bitfld.long 0x04 8. "FLUSH_EN,Enable flush" "0,1" hexmask.long.byte 0x04 0.--7. 1. "TIMEOUT_VALUE,Timeout Value (ms)" group.long 0x200++0x23 line.long 0x00 "PCIECTRL_PL_IATU_INDEX,iATU Viewport Register: makes the registers of the corresponding iATU region accessible" bitfld.long 0x00 31. "REGION_DIRECTION,- OUTBOUND" "REGION_DIRECTION_0,REGION_DIRECTION_1" bitfld.long 0x00 0.--3. "REGION_INDEX,Outbound region from 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_PL_IATU_REG_CTRL_1,iATU Region Control 1 Register" bitfld.long 0x04 20.--24. "FUNCTION_NUMBER,Outbound: F.N; applied to outgoing TLP (RID) with matching addess Inbound: F.N.-match criteria for incoming TLP (if Function_Number_match_enable=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--17. "AT,Outbound: AT applied to outgoing TLP with matching addess Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)" "0,1,2,3" newline bitfld.long 0x04 9.--10. "ATTR,Outbound: ATTR applied to outgoing TLP with matching addess Inbound: ATTR-match criteria (if ATTR_match_enable=1)" "0,1,2,3" bitfld.long 0x04 8. "TD,Outbound: TD applied to outgoing TLP with matching addess Inbound: TD-match criteria (if TD_match_enable=1)" "0,1" newline bitfld.long 0x04 5.--7. "TC,Outbound: TC applied to outgoing TLP with matching addess Inbound: TC-match criteria (if TC_match_enable=1)" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--4. "TYPE,Outbound: TYPE applied to outgoing TLP with matching addess Inbound: TYPE-match criteria" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "PCIECTRL_PL_IATU_REG_CTRL_2,iATU Region Control 2 Register" bitfld.long 0x08 31. "REGION_ENABLE,Enable AT for this region" "0,1" bitfld.long 0x08 30. "MATCH_MODE,Sets inbound TLP match mode depending on TYPE - _0" "MATCH_MODE_0,MATCH_MODE_1" newline bitfld.long 0x08 29. "INVERT_MODE,Redefine match criteria as outside the defined range (instead of inside)" "0,1" bitfld.long 0x08 28. "CFG_SHIFT_MODE,Enable the shifting of CFG CID (BDF) incoming and outgoing TLP; CFG get mapped to a contiguous" "0,1" newline bitfld.long 0x08 27. "FUZZY_TYPE_MATCH_MODE,Outbound: DMA Bypass Mode Inbound: Relax matching on inbound TLP TYPE: CfgRd0 == CfgRd1 CfgWr0 == CfgWr1 MRd == MRdLk routing field of Msg/MsgD ignored" "0,1" bitfld.long 0x08 24.--25. "RESPONSE_CODE,Override HW-generated completion status when responding inbound TLP" "0,1,2,3" newline bitfld.long 0x08 21. "MESSAGE_CODE_MATCH_ENABLE,Enable MessageCode match criteria on inbound TLP" "0,1" bitfld.long 0x08 20. "VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE,VIRTUAL FUNCTIONS NOT IMPLEMENTED: NOT USED" "0,1" newline bitfld.long 0x08 19. "FUNCTION_NUMBER_MATCH_ENABLE,Outbound: Function Number Translation Bypass Inbound: Enable Function Number match criteria" "0,1" bitfld.long 0x08 18. "AT_MATCH_ENABLE,Enable AT match criteria on inbound TLP ATS NOT SUPPORTED: DO NOT USE" "0,1" newline bitfld.long 0x08 16. "ATTR_MATCH_ENABLE,Enable ATTR match criteria on inbound TLP" "0,1" bitfld.long 0x08 15. "TD_MATCH_ENABLE,Enable TD match criteria on inbound TLP" "0,1" newline bitfld.long 0x08 14. "TC_MATCH_ENABLE,Enable TC match criteria on inbound TLP" "0,1" bitfld.long 0x08 8.--10. "BAR_NUMBER,BAR number for mayching with incoming MEM I/O TLP (if Match_Mode = 1)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x08 0.--7. 1. "MESSAGECODE,Outbound: MessageCode applied to outgoing message TLP with matching addess Inbound: MessageCode-match criteria for infoming message TLP (if Message_Code_match_enable=1)" line.long 0x0C "PCIECTRL_PL_IATU_REG_LOWER_BASE,iATU Region Lower Base Address Register (2**12 = 4kbyte - aligned)" hexmask.long.tbyte 0x0C 12.--31. 1. "IATU_REG_LOWER_BASE," hexmask.long.word 0x0C 0.--11. 1. "ZERO," line.long 0x10 "PCIECTRL_PL_IATU_REG_UPPER_BASE,iATU Region Upper Base Address Register" line.long 0x14 "PCIECTRL_PL_IATU_REG_LIMIT,iATU Region Limit Address Register" hexmask.long.tbyte 0x14 12.--31. 1. "IATU_REG_LIMIT," hexmask.long.word 0x14 0.--11. 1. "ONES," line.long 0x18 "PCIECTRL_PL_IATU_REG_LOWER_TARGET,iATU Region Lower Target Address Register (2**12 = 4kbyte - aligned)" hexmask.long.tbyte 0x18 12.--31. 1. "IATU_REG_LOWER_TARGET," hexmask.long.word 0x18 0.--11. 1. "ZERO," line.long 0x1C "PCIECTRL_PL_IATU_REG_UPPER_TARGET,iATU Region Upper Target Address Register" line.long 0x20 "PCIECTRL_PL_IATU_REG_CTRL_3,iATU Region Control 3 Register; VIRTUAL FUNCTIONS NOT IMPLEMENTED: NOT USED" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" group.long 0x128++0x0B line.long 0x00 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_0,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i. with i = MSI data [4:0]" line.long 0x04 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_0,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i. with i = MSI data [4:0]" line.long 0x08 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_0,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i. with i = MSI data [4:0]" tree.end repeat.end tree.end tree "PCIe_SS1_RC_CFG_DBICS" base ad:0x51000000 group.long 0x00++0x3F line.long 0x00 "PCIECTRL_RC_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable (BME)" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable (MSE)" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable (ISE)" "0,1" line.long 0x08 "PCIECTRL_RC_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_RC_DBICS_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type - TYPE0" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_RC_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline bitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LS Bit of I/O address" "0,1,2,3" newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS) - MEM" "SPACE_INDICATOR_0,SPACE_INDICATOR_1" line.long 0x14 "PCIECTRL_RC_DBICS_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline bitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS) - MEM" "SPACE_INDICATOR_0,SPACE_INDICATOR_1" line.long 0x18 "PCIECTRL_RC_DBICS_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer Not Applicable for PCI Express hence hardwired to 0" hexmask.long.byte 0x18 16.--23. 1. "SUBORD_BUS_NUM,Subordinate Bus Number" newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number" hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS_NUM,Primary Bus Number" line.long 0x1C "PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS,IO Base.Limit and Secondary Status Register" bitfld.long 0x1C 31. "DET_PAR_ERR,Detected Parity Error" "0,1" bitfld.long 0x1C 30. "RCVD_SYS_ERR,Received System Error" "0,1" newline bitfld.long 0x1C 29. "RCVD_MSTR_ABORT,Received Master Abort" "0,1" bitfld.long 0x1C 28. "RCVD_TRGT_ABORT,Received Target Error" "0,1" newline bitfld.long 0x1C 27. "SGNLD_TRGT_ABORT,Signaled Target Error" "0,1" rbitfld.long 0x1C 25.--26. "DEVSEL_TIMING,DEVSEL Timing Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" newline bitfld.long 0x1C 24. "MSTR_DATA_PRTY_ERR,Mastered Data Parity Error" "0,1" rbitfld.long 0x1C 23. "FAST_B2B_CAP,Fast Back to Back Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" newline rbitfld.long 0x1C 21. "C66MHZ_CAPA,66MHz Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" bitfld.long 0x1C 12.--15. "IO_SPACE_LIMIT,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 8. "IODECODE_32,32 or 16 Bit IO Space" "0,1" bitfld.long 0x1C 4.--7. "IO_SPACE_BASE,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 0. "IODECODE_32_0,32 or 16 Bit IO Space (CS)" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS_MEM_BASE_LIMIT,Memory Base and Limit Register" hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT_ADDR,Memory Limit Address" hexmask.long.word 0x20 4.--15. 1. "MEM_BASE_ADDR,Memory Base Address" line.long 0x24 "PCIECTRL_RC_DBICS_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory End Address" rbitfld.long 0x24 16. "MEMDECODE_64,64-Bit Memory Addressing" "0,1" newline hexmask.long.word 0x24 4.--15. 1. "UPPPREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory start Address" rbitfld.long 0x24 0. "MEMDECODE_64_0,64-Bit Memory Addressing" "0,1" line.long 0x28 "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" line.long 0x2C "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" line.long 0x30 "PCIECTRL_RC_DBICS_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x30 16.--31. 1. "UPP16_IOLIMIT,Upper 16 IO Limit Address" hexmask.long.word 0x30 0.--15. 1. "UPP16_IOBASE,Upper 16 IO Base Address" line.long 0x34 "PCIECTRL_RC_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" line.long 0x38 "PCIECTRL_RC_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x38 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x38 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x38 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1" line.long 0x3C "PCIECTRL_RC_DBICS_BRIDGE_INT,Bridge Control and Int Pin and line" rbitfld.long 0x3C 27. "DT_SERR_EN,Discard Timer SERR Enable Status" "0,1" rbitfld.long 0x3C 26. "DT_STS,Discard Timer Status" "0,1" newline rbitfld.long 0x3C 25. "SEC_DT,Secondary Discard Timer" "0,1" rbitfld.long 0x3C 24. "PRI_DT,Primary Discard Timer" "0,1" newline rbitfld.long 0x3C 23. "FAST_B2B_EN,Fast Back-to-Back Transactions Enable" "0,1" bitfld.long 0x3C 22. "SEC_BUS_RST,Secondary Bus Reset (initiate hot reset)" "0,1" newline rbitfld.long 0x3C 21. "MST_ABT_MOD,Master Abort Mode" "0,1" bitfld.long 0x3C 20. "VGA_16B_DEC,VGA 16-Bit Decode" "0,1" newline bitfld.long 0x3C 19. "VGA_EN,VGA Enable" "0,1" bitfld.long 0x3C 18. "ISA_EN,ISA Enable" "0,1" newline bitfld.long 0x3C 17. "SERR_EN,SERR Enable" "0,1" bitfld.long 0x3C 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1" newline hexmask.long.byte 0x3C 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x3C 0.--7. 1. "INT_LIN,Interrupt Line" group.long 0x70++0x33 line.long 0x00 "PCIECTRL_RC_DBICS_PCIE_CAP,PCI Express Capability structure header" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented (CS)" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type - RC" "?,?,?,?,DEV_TYPE_4_r,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID - PCIE" line.long 0x04 "PCIECTRL_RC_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value for Upstream Port Only (CS)" "0,1,2,3" hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value for Upstream Port Only (CS)" newline bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" newline bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS) - _256_BYTE" "?,MAX_PAYLOAD_SIZE_1_r,?,?,?,?,?,?" line.long 0x08 "PCIECTRL_RC_DBICS_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable (Sticky bit) - DIS" "AUXPM_EN_0,AUXPM_EN_1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_RC_DBICS_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_RC_DBICS_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" bitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration - ASYNC" "COM_CLK_CFG_0,COM_CLK_CFG_1" newline bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" bitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS) - _64_BYTE" "RCB_0,RCB_1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" line.long 0x14 "PCIECTRL_RC_DBICS_SLOT_CAP,Slot Capabilities Register" hexmask.long.word 0x14 19.--31. 1. "PSN,Physical Slot Number (CS)" bitfld.long 0x14 18. "NCCS,No Command Complete Support (CS)" "0,1" newline bitfld.long 0x14 17. "EIP,Electromechanical Interlock Present (CS)" "0,1" bitfld.long 0x14 15.--16. "SPLS,Slot Power Limit Scale (CS)" "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "SPLV,Slot Power Limit Value (CS)" bitfld.long 0x14 6. "HPC,Hot-Plug Capable (CS)" "0,1" newline bitfld.long 0x14 5. "HPS,Hot-Plug Surprise (CS)" "0,1" bitfld.long 0x14 4. "PIP,Power Indicator Present (CS)" "0,1" newline bitfld.long 0x14 3. "AIP,Attention Indicator Present (CS)" "0,1" bitfld.long 0x14 2. "MRLSP,MRL Sensor Present (CS)" "0,1" newline bitfld.long 0x14 1. "PCP,Power Controller Present (CS)" "0,1" bitfld.long 0x14 0. "ABP,Attention Button Present (CS)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x18 24. "DSC,Data Link Layer State Changed" "0,1" rbitfld.long 0x18 23. "EIS,Electromechanical Interlock Status" "0,1" newline rbitfld.long 0x18 22. "PDS,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" rbitfld.long 0x18 21. "MRLSS,MRL Sensor State" "0,1" newline bitfld.long 0x18 20. "CC,Command Completed" "0,1" bitfld.long 0x18 19. "PDC,Presence Detect Changed" "0,1" newline bitfld.long 0x18 18. "MRCSC,MRL Sensor Changed" "0,1" bitfld.long 0x18 17. "PFD,Power Fault Detected" "0,1" newline bitfld.long 0x18 16. "ABP,Attention Button Pressed" "0,1" bitfld.long 0x18 12. "DSC_EN,Data Link Layer State Changed Enable" "0,1" newline bitfld.long 0x18 11. "EIC,Electromechanical Interlock Control" "0,1" bitfld.long 0x18 10. "PCC,Power Controller Control" "0,1" newline bitfld.long 0x18 8.--9. "PIC,Power Indicator Control" "0,1,2,3" bitfld.long 0x18 6.--7. "AIC,Attention Indicator Control" "0,1,2,3" newline bitfld.long 0x18 5. "HPI_EN,Hot-Plug Interrupt Enable" "0,1" bitfld.long 0x18 4. "CCI_EN,Command Completed Interrupt Enable" "0,1" newline bitfld.long 0x18 3. "PDC_EN,Presence Detect Changed Enable" "0,1" bitfld.long 0x18 2. "MRLSC_EN,MRL Sensor Changed Enable" "0,1" newline bitfld.long 0x18 1. "PFD_EN,Power Fault Detected Enable" "0,1" bitfld.long 0x18 0. "ABP_EN,Attention Button Pressed Enable" "0,1" line.long 0x1C "PCIECTRL_RC_DBICS_ROOT_CAC,Root Control and Capability Register" rbitfld.long 0x1C 16. "CRSSV,CRS Software Visibility" "0,1" rbitfld.long 0x1C 4. "CRSSV_EN,CRS Software Visibility Enable" "0,1" newline bitfld.long 0x1C 3. "PMEI_EN,PME Interrupt Enable" "0,1" bitfld.long 0x1C 2. "SEFE_EN,System Error on Fatal Error Enable" "0,1" newline bitfld.long 0x1C 1. "SENE_EN,System Error on Non-fatal Error Enable" "0,1" bitfld.long 0x1C 0. "SECE_EN,System Error on Correctable Error Enable" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS_ROOT_STS,Root Status Register" rbitfld.long 0x20 17. "PME_PND,PME Pending" "0,1" bitfld.long 0x20 16. "PME_STS,PME Status (Sticky bit)" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PME_RID,PME Requester ID" line.long 0x24 "PCIECTRL_RC_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x24 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x24 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x24 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x24 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x24 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x24 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x24 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x24 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x24 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "PCIECTRL_RC_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x28 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x28 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x28 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x28 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x28 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x28 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x28 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x28 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x28 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "PCIECTRL_RC_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x2C 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x2C 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x30 "PCIECTRL_RC_DBICS_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x30 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x30 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x30 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x30 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x30 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x30 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x30 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6. "SEL_DEEMP,Selectable De-emphasis (CS)" "0,1" bitfld.long 0x30 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x30 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x30 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS2_RC_CFG_DBICS" base ad:0x51800000 group.long 0x00++0x3F line.long 0x00 "PCIECTRL_RC_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable (BME)" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable (MSE)" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable (ISE)" "0,1" line.long 0x08 "PCIECTRL_RC_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_RC_DBICS_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type - TYPE0" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_RC_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" hexmask.long.word 0x10 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x10 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR upper base address bits are in BAR above) Masked LSBs as set by BAR mask" newline bitfld.long 0x10 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x10 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LS Bit of I/O address" "0,1,2,3" newline bitfld.long 0x10 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS) - MEM" "SPACE_INDICATOR_0,SPACE_INDICATOR_1" line.long 0x14 "PCIECTRL_RC_DBICS_BAR1,Base Address Register 1 If BAR0.AS =" hexmask.long.word 0x14 20.--31. 1. "BASE_ADDR_RW,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Unmasked MSBs as set by BAR mask" hexmask.long.word 0x14 4.--19. 1. "BASE_ADDR_RO,Base address bits (for a 64-bit BAR lower base address bits are in BAR below) Masked LSBs as set by BAR mask" newline bitfld.long 0x14 3. "PREFETCHABLE,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" bitfld.long 0x14 1.--2. "AS,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0 bit 1 is LSBit of I/O address" "0,1,2,3" newline bitfld.long 0x14 0. "SPACE_INDICATOR,BAR I/O vs memory space indicator (CS) - MEM" "SPACE_INDICATOR_0,SPACE_INDICATOR_1" line.long 0x18 "PCIECTRL_RC_DBICS_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer Not Applicable for PCI Express hence hardwired to 0" hexmask.long.byte 0x18 16.--23. 1. "SUBORD_BUS_NUM,Subordinate Bus Number" newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number" hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS_NUM,Primary Bus Number" line.long 0x1C "PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS,IO Base.Limit and Secondary Status Register" bitfld.long 0x1C 31. "DET_PAR_ERR,Detected Parity Error" "0,1" bitfld.long 0x1C 30. "RCVD_SYS_ERR,Received System Error" "0,1" newline bitfld.long 0x1C 29. "RCVD_MSTR_ABORT,Received Master Abort" "0,1" bitfld.long 0x1C 28. "RCVD_TRGT_ABORT,Received Target Error" "0,1" newline bitfld.long 0x1C 27. "SGNLD_TRGT_ABORT,Signaled Target Error" "0,1" rbitfld.long 0x1C 25.--26. "DEVSEL_TIMING,DEVSEL Timing Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" newline bitfld.long 0x1C 24. "MSTR_DATA_PRTY_ERR,Mastered Data Parity Error" "0,1" rbitfld.long 0x1C 23. "FAST_B2B_CAP,Fast Back to Back Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" newline rbitfld.long 0x1C 21. "C66MHZ_CAPA,66MHz Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" bitfld.long 0x1C 12.--15. "IO_SPACE_LIMIT,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 8. "IODECODE_32,32 or 16 Bit IO Space" "0,1" bitfld.long 0x1C 4.--7. "IO_SPACE_BASE,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 0. "IODECODE_32_0,32 or 16 Bit IO Space (CS)" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS_MEM_BASE_LIMIT,Memory Base and Limit Register" hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT_ADDR,Memory Limit Address" hexmask.long.word 0x20 4.--15. 1. "MEM_BASE_ADDR,Memory Base Address" line.long 0x24 "PCIECTRL_RC_DBICS_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory End Address" rbitfld.long 0x24 16. "MEMDECODE_64,64-Bit Memory Addressing" "0,1" newline hexmask.long.word 0x24 4.--15. 1. "UPPPREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory start Address" rbitfld.long 0x24 0. "MEMDECODE_64_0,64-Bit Memory Addressing" "0,1" line.long 0x28 "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" line.long 0x2C "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" line.long 0x30 "PCIECTRL_RC_DBICS_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x30 16.--31. 1. "UPP16_IOLIMIT,Upper 16 IO Limit Address" hexmask.long.word 0x30 0.--15. 1. "UPP16_IOBASE,Upper 16 IO Base Address" line.long 0x34 "PCIECTRL_RC_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" line.long 0x38 "PCIECTRL_RC_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x38 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x38 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x38 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1" line.long 0x3C "PCIECTRL_RC_DBICS_BRIDGE_INT,Bridge Control and Int Pin and line" rbitfld.long 0x3C 27. "DT_SERR_EN,Discard Timer SERR Enable Status" "0,1" rbitfld.long 0x3C 26. "DT_STS,Discard Timer Status" "0,1" newline rbitfld.long 0x3C 25. "SEC_DT,Secondary Discard Timer" "0,1" rbitfld.long 0x3C 24. "PRI_DT,Primary Discard Timer" "0,1" newline rbitfld.long 0x3C 23. "FAST_B2B_EN,Fast Back-to-Back Transactions Enable" "0,1" bitfld.long 0x3C 22. "SEC_BUS_RST,Secondary Bus Reset (initiate hot reset)" "0,1" newline rbitfld.long 0x3C 21. "MST_ABT_MOD,Master Abort Mode" "0,1" bitfld.long 0x3C 20. "VGA_16B_DEC,VGA 16-Bit Decode" "0,1" newline bitfld.long 0x3C 19. "VGA_EN,VGA Enable" "0,1" bitfld.long 0x3C 18. "ISA_EN,ISA Enable" "0,1" newline bitfld.long 0x3C 17. "SERR_EN,SERR Enable" "0,1" bitfld.long 0x3C 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1" newline hexmask.long.byte 0x3C 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x3C 0.--7. 1. "INT_LIN,Interrupt Line" group.long 0x70++0x33 line.long 0x00 "PCIECTRL_RC_DBICS_PCIE_CAP,PCI Express Capability structure header" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented (CS)" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type - RC" "?,?,?,?,DEV_TYPE_4_r,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID - PCIE" line.long 0x04 "PCIECTRL_RC_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value for Upstream Port Only (CS)" "0,1,2,3" hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value for Upstream Port Only (CS)" newline bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" newline bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS) - _256_BYTE" "?,MAX_PAYLOAD_SIZE_1_r,?,?,?,?,?,?" line.long 0x08 "PCIECTRL_RC_DBICS_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable (Sticky bit) - DIS" "AUXPM_EN_0,AUXPM_EN_1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_RC_DBICS_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "L1_EXIT_LAT,L1 Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "L0S_EXIT_LAT,L0s Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_RC_DBICS_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" bitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration - ASYNC" "COM_CLK_CFG_0,COM_CLK_CFG_1" newline bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" bitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS) - _64_BYTE" "RCB_0,RCB_1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" line.long 0x14 "PCIECTRL_RC_DBICS_SLOT_CAP,Slot Capabilities Register" hexmask.long.word 0x14 19.--31. 1. "PSN,Physical Slot Number (CS)" bitfld.long 0x14 18. "NCCS,No Command Complete Support (CS)" "0,1" newline bitfld.long 0x14 17. "EIP,Electromechanical Interlock Present (CS)" "0,1" bitfld.long 0x14 15.--16. "SPLS,Slot Power Limit Scale (CS)" "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "SPLV,Slot Power Limit Value (CS)" bitfld.long 0x14 6. "HPC,Hot-Plug Capable (CS)" "0,1" newline bitfld.long 0x14 5. "HPS,Hot-Plug Surprise (CS)" "0,1" bitfld.long 0x14 4. "PIP,Power Indicator Present (CS)" "0,1" newline bitfld.long 0x14 3. "AIP,Attention Indicator Present (CS)" "0,1" bitfld.long 0x14 2. "MRLSP,MRL Sensor Present (CS)" "0,1" newline bitfld.long 0x14 1. "PCP,Power Controller Present (CS)" "0,1" bitfld.long 0x14 0. "ABP,Attention Button Present (CS)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x18 24. "DSC,Data Link Layer State Changed" "0,1" rbitfld.long 0x18 23. "EIS,Electromechanical Interlock Status" "0,1" newline rbitfld.long 0x18 22. "PDS,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" rbitfld.long 0x18 21. "MRLSS,MRL Sensor State" "0,1" newline bitfld.long 0x18 20. "CC,Command Completed" "0,1" bitfld.long 0x18 19. "PDC,Presence Detect Changed" "0,1" newline bitfld.long 0x18 18. "MRCSC,MRL Sensor Changed" "0,1" bitfld.long 0x18 17. "PFD,Power Fault Detected" "0,1" newline bitfld.long 0x18 16. "ABP,Attention Button Pressed" "0,1" bitfld.long 0x18 12. "DSC_EN,Data Link Layer State Changed Enable" "0,1" newline bitfld.long 0x18 11. "EIC,Electromechanical Interlock Control" "0,1" bitfld.long 0x18 10. "PCC,Power Controller Control" "0,1" newline bitfld.long 0x18 8.--9. "PIC,Power Indicator Control" "0,1,2,3" bitfld.long 0x18 6.--7. "AIC,Attention Indicator Control" "0,1,2,3" newline bitfld.long 0x18 5. "HPI_EN,Hot-Plug Interrupt Enable" "0,1" bitfld.long 0x18 4. "CCI_EN,Command Completed Interrupt Enable" "0,1" newline bitfld.long 0x18 3. "PDC_EN,Presence Detect Changed Enable" "0,1" bitfld.long 0x18 2. "MRLSC_EN,MRL Sensor Changed Enable" "0,1" newline bitfld.long 0x18 1. "PFD_EN,Power Fault Detected Enable" "0,1" bitfld.long 0x18 0. "ABP_EN,Attention Button Pressed Enable" "0,1" line.long 0x1C "PCIECTRL_RC_DBICS_ROOT_CAC,Root Control and Capability Register" rbitfld.long 0x1C 16. "CRSSV,CRS Software Visibility" "0,1" rbitfld.long 0x1C 4. "CRSSV_EN,CRS Software Visibility Enable" "0,1" newline bitfld.long 0x1C 3. "PMEI_EN,PME Interrupt Enable" "0,1" bitfld.long 0x1C 2. "SEFE_EN,System Error on Fatal Error Enable" "0,1" newline bitfld.long 0x1C 1. "SENE_EN,System Error on Non-fatal Error Enable" "0,1" bitfld.long 0x1C 0. "SECE_EN,System Error on Correctable Error Enable" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS_ROOT_STS,Root Status Register" rbitfld.long 0x20 17. "PME_PND,PME Pending" "0,1" bitfld.long 0x20 16. "PME_STS,PME Status (Sticky bit)" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PME_RID,PME Requester ID" line.long 0x24 "PCIECTRL_RC_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x24 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x24 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x24 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x24 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x24 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x24 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x24 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x24 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x24 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "PCIECTRL_RC_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x28 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x28 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x28 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x28 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x28 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x28 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x28 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x28 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x28 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "PCIECTRL_RC_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x2C 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x2C 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x30 "PCIECTRL_RC_DBICS_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x30 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x30 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x30 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x30 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x30 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x30 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x30 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6. "SEL_DEEMP,Selectable De-emphasis (CS)" "0,1" bitfld.long 0x30 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x30 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x30 0.--3. "TRGT_LINK_SPEED,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS1_RC_CFG_DBICS2" base ad:0x51001000 group.long 0x00++0x3F line.long 0x00 "PCIECTRL_RC_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_RC_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable (BME)" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable (MSE)" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable (ISE)" "0,1" line.long 0x08 "PCIECTRL_RC_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_RC_DBICS2_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type - TYPE0" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_RC_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR Reads like in CS mode" hexmask.long 0x10 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x10 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x14 "PCIECTRL_RC_DBICS2_BAR1_MASK,Base Address Register 1 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode. contains the upper bits of BAR0 mask Reads like in CS mode" hexmask.long 0x14 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x14 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS2_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer Not Applicable for PCI Express hence hardwired to 0" hexmask.long.byte 0x18 16.--23. 1. "SUBORD_BUS_NUM,Subordinate Bus Number" newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number" hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS_NUM,Primary Bus Number" line.long 0x1C "PCIECTRL_RC_DBICS2_IOBASE_LIMIT_SEC_STATUS,IO Base.Limit and Secondary Status Register" bitfld.long 0x1C 31. "DET_PAR_ERR,Detected Parity Error" "0,1" bitfld.long 0x1C 30. "RCVD_SYS_ERR,Received System Error" "0,1" newline bitfld.long 0x1C 29. "RCVD_MSTR_ABORT,Received Master Abort" "0,1" bitfld.long 0x1C 28. "RCVD_TRGT_ABORT,Received Target Error" "0,1" newline bitfld.long 0x1C 27. "SGNLD_TRGT_ABORT,Signaled Target Error" "0,1" rbitfld.long 0x1C 25.--26. "DEVSEL_TIMING,DEVSEL Timing Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" newline bitfld.long 0x1C 24. "MSTR_DATA_PRTY_ERR,Mastered Data Parity Error" "0,1" rbitfld.long 0x1C 23. "FAST_B2B_CAP,Fast Back to Back Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" newline rbitfld.long 0x1C 21. "C66MHZ_CAPA,66MHz Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" bitfld.long 0x1C 12.--15. "IO_SPACE_LIMIT,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 8. "IODECODE_32,32 or 16 Bit IO Space" "0,1" bitfld.long 0x1C 4.--7. "IO_SPACE_BASE,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 0. "IODECODE_32_0,32 or 16 Bit IO Space (CS)" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS2_MEM_BASE_LIMIT,Memory Base and Limit Register" hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT_ADDR,Memory Limit Address" hexmask.long.word 0x20 4.--15. 1. "MEM_BASE_ADDR,Memory Base Address" line.long 0x24 "PCIECTRL_RC_DBICS2_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory End Address" rbitfld.long 0x24 16. "MEMDECODE_64,64-Bit Memory Addressing" "0,1" newline hexmask.long.word 0x24 4.--15. 1. "UPPPREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory start Address" rbitfld.long 0x24 0. "MEMDECODE_64_0,64-Bit Memory Addressing" "0,1" line.long 0x28 "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" line.long 0x2C "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" line.long 0x30 "PCIECTRL_RC_DBICS2_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x30 16.--31. 1. "UPP16_IOLIMIT,Upper 16 IO Limit Address" hexmask.long.word 0x30 0.--15. 1. "UPP16_IOBASE,Upper 16 IO Base Address" line.long 0x34 "PCIECTRL_RC_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" line.long 0x38 "PCIECTRL_RC_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x38 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x38 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x38 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1" line.long 0x3C "PCIECTRL_RC_DBICS2_BRIDGE_INT,Bridge Control and Int Pin and line" rbitfld.long 0x3C 27. "DT_SERR_EN,Discard Timer SERR Enable Status" "0,1" rbitfld.long 0x3C 26. "DT_STS,Discard Timer Status" "0,1" newline rbitfld.long 0x3C 25. "SEC_DT,Secondary Discard Timer" "0,1" rbitfld.long 0x3C 24. "PRI_DT,Primary Discard Timer" "0,1" newline rbitfld.long 0x3C 23. "FAST_B2B_EN,Fast Back-to-Back Transactions Enable" "0,1" bitfld.long 0x3C 22. "SEC_BUS_RST,Secondary Bus Reset (initiate hot reset)" "0,1" newline rbitfld.long 0x3C 21. "MST_ABT_MOD,Master Abort Mode" "0,1" bitfld.long 0x3C 20. "VGA_16B_DEC,VGA 16-Bit Decode" "0,1" newline bitfld.long 0x3C 19. "VGA_EN,VGA Enable" "0,1" bitfld.long 0x3C 18. "ISA_EN,ISA Enable" "0,1" newline bitfld.long 0x3C 17. "SERR_EN,SERR Enable" "0,1" bitfld.long 0x3C 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1" newline hexmask.long.byte 0x3C 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x3C 0.--7. 1. "INT_LIN,Interrupt Line" group.long 0x70++0x33 line.long 0x00 "PCIECTRL_RC_DBICS2_PCIE_CAP,PCI Express Capability structure header" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented (CS)" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type - RC" "?,?,?,?,DEV_TYPE_4_r,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID - PCIE" line.long 0x04 "PCIECTRL_RC_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value for Upstream Port Only (CS)" "0,1,2,3" hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value for Upstream Port Only (CS)" newline bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" newline bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS) - _256_BYTE" "?,MAX_PAYLOAD_SIZE_1_r,?,?,?,?,?,?" line.long 0x08 "PCIECTRL_RC_DBICS2_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable (Sticky bit) - DIS" "AUXPM_EN_0,AUXPM_EN_1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_RC_DBICS2_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "COMM_L1_EXIT_LAT,Common-clock-mode L1 Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "COMM_L0S_EXIT_LAT,Common-clock-mode L0s Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_RC_DBICS2_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" bitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration - ASYNC" "COM_CLK_CFG_0,COM_CLK_CFG_1" newline bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" bitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS) - _64_BYTE" "RCB_0,RCB_1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" line.long 0x14 "PCIECTRL_RC_DBICS2_SLOT_CAP,Slot Capabilities Register" hexmask.long.word 0x14 19.--31. 1. "PSN,Physical Slot Number (CS)" bitfld.long 0x14 18. "NCCS,No Command Complete Support (CS)" "0,1" newline bitfld.long 0x14 17. "EIP,Electromechanical Interlock Present (CS)" "0,1" bitfld.long 0x14 15.--16. "SPLS,Slot Power Limit Scale (CS)" "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "SPLV,Slot Power Limit Value (CS)" bitfld.long 0x14 6. "HPC,Hot-Plug Capable (CS)" "0,1" newline bitfld.long 0x14 5. "HPS,Hot-Plug Surprise (CS)" "0,1" bitfld.long 0x14 4. "PIP,Power Indicator Present (CS)" "0,1" newline bitfld.long 0x14 3. "AIP,Attention Indicator Present (CS)" "0,1" bitfld.long 0x14 2. "MRLSP,MRL Sensor Present (CS)" "0,1" newline bitfld.long 0x14 1. "PCP,Power Controller Present (CS)" "0,1" bitfld.long 0x14 0. "ABP,Attention Button Present (CS)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS2_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x18 24. "DSC,Data Link Layer State Changed" "0,1" rbitfld.long 0x18 23. "EIS,Electromechanical Interlock Status" "0,1" newline rbitfld.long 0x18 22. "PDS,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" rbitfld.long 0x18 21. "MRLSS,MRL Sensor State" "0,1" newline bitfld.long 0x18 20. "CC,Command Completed" "0,1" bitfld.long 0x18 19. "PDC,Presence Detect Changed" "0,1" newline bitfld.long 0x18 18. "MRCSC,MRL Sensor Changed" "0,1" bitfld.long 0x18 17. "PFD,Power Fault Detected" "0,1" newline bitfld.long 0x18 16. "ABP,Attention Button Pressed" "0,1" bitfld.long 0x18 12. "DSC_EN,Data Link Layer State Changed Enable" "0,1" newline bitfld.long 0x18 11. "EIC,Electromechanical Interlock Control" "0,1" bitfld.long 0x18 10. "PCC,Power Controller Control" "0,1" newline bitfld.long 0x18 8.--9. "PIC,Power Indicator Control" "0,1,2,3" bitfld.long 0x18 6.--7. "AIC,Attention Indicator Control" "0,1,2,3" newline bitfld.long 0x18 5. "HPI_EN,Hot-Plug Interrupt Enable" "0,1" bitfld.long 0x18 4. "CCI_EN,Command Completed Interrupt Enable" "0,1" newline bitfld.long 0x18 3. "PDC_EN,Presence Detect Changed Enable" "0,1" bitfld.long 0x18 2. "MRLSC_EN,MRL Sensor Changed Enable" "0,1" newline bitfld.long 0x18 1. "PFD_EN,Power Fault Detected Enable" "0,1" bitfld.long 0x18 0. "ABP_EN,Attention Button Pressed Enable" "0,1" line.long 0x1C "PCIECTRL_RC_DBICS2_ROOT_CAC,Root Control and Capability Register" rbitfld.long 0x1C 16. "CRSSV,CRS Software Visibility" "0,1" rbitfld.long 0x1C 4. "CRSSV_EN,CRS Software Visibility Enable" "0,1" newline bitfld.long 0x1C 3. "PMEI_EN,PME Interrupt Enable" "0,1" bitfld.long 0x1C 2. "SEFE_EN,System Error on Fatal Error Enable" "0,1" newline bitfld.long 0x1C 1. "SENE_EN,System Error on Non-fatal Error Enable" "0,1" bitfld.long 0x1C 0. "SECE_EN,System Error on Correctable Error Enable" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS2_ROOT_STS,Root Status Register" rbitfld.long 0x20 17. "PME_PND,PME Pending" "0,1" bitfld.long 0x20 16. "PME_STS,PME Status (Sticky bit)" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PME_RID,PME Requester ID" line.long 0x24 "PCIECTRL_RC_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x24 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x24 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x24 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x24 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x24 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x24 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x24 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x24 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x24 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "PCIECTRL_RC_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x28 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x28 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x28 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x28 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x28 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x28 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x28 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x28 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x28 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "PCIECTRL_RC_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x2C 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x2C 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x30 "PCIECTRL_RC_DBICS2_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x30 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x30 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x30 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x30 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x30 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x30 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x30 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6. "SEL_DEEMP,Selectable De-emphasis (CS)" "0,1" bitfld.long 0x30 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x30 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x30 0.--3. "TRGT_LINK_SPEED,Target Link Speed: Read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS2_RC_CFG_DBICS2" base ad:0x51801000 group.long 0x00++0x3F line.long 0x00 "PCIECTRL_RC_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x00 16.--31. 1. "DEVICEID,Device ID (CS)" hexmask.long.word 0x00 0.--15. 1. "VENDORID,Vendor ID (CS)" line.long 0x04 "PCIECTRL_RC_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x04 31. "DETECT_PARERR,Detected Parity Error" "0,1" bitfld.long 0x04 30. "SIGNAL_SYSERR,Signaled System Error" "0,1" newline bitfld.long 0x04 29. "RCVD_MASTERABORT,Received Master Abort" "0,1" bitfld.long 0x04 28. "RCVD_TRGTABORT,Received Target Abort" "0,1" newline bitfld.long 0x04 27. "SIGNAL_TRGTABORT,Signaled Target Abort" "0,1" rbitfld.long 0x04 25.--26. "DEVSEL_TIME,DevSel Timing Harsdwired to 0 for PCIExpress" "0,1,2,3" newline bitfld.long 0x04 24. "MASTERDATA_PARERR,Master Data Parity Error" "0,1" rbitfld.long 0x04 23. "FAST_B2B,Back to Back Capable Harsdwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 21. "C66MHZ_CAP,66MHz Capable Harsdwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 20. "CAP_LIST,Capabilities List Hardwired to 1" "0,1" newline rbitfld.long 0x04 19. "INTX_STATUS,INTx Status" "0,1" bitfld.long 0x04 10. "INTX_ASSER_DIS,INTx Assertion Disable" "0,1" newline rbitfld.long 0x04 9. "FAST_BBEN,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 8. "SERR_EN,SERR Enable" "0,1" newline rbitfld.long 0x04 7. "IDSEL_CTRL,Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 6. "PARITYERRRESP,Parity Error Response" "0,1" newline rbitfld.long 0x04 5. "VGA_SNOOP,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" rbitfld.long 0x04 4. "MEMWR_INVA,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" newline rbitfld.long 0x04 3. "SPEC_CYCLE_EN,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x04 2. "BUSMASTER_EN,Bus Master Enable (BME)" "0,1" newline bitfld.long 0x04 1. "MEM_SPACE_EN,Memory Space Enable (MSE)" "0,1" bitfld.long 0x04 0. "IO_SPACE_EN,IO Space Enable (ISE)" "0,1" line.long 0x08 "PCIECTRL_RC_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x08 24.--31. 1. "BASE_CLS_CD,Base Class Code (CS)" hexmask.long.byte 0x08 16.--23. 1. "SUBCLS_CD,Sub Class Code (CS)" newline hexmask.long.byte 0x08 8.--15. 1. "PROG_IF_CODE,Programming Interface Code (CS)" hexmask.long.byte 0x08 0.--7. 1. "REVID,Revision ID (CS)" line.long 0x0C "PCIECTRL_RC_DBICS2_BIST_HEAD_LAT_CACH,BIST. Header Type. Latency Timer. Cache Line Size" hexmask.long.byte 0x0C 24.--31. 1. "BIST,BIST" rbitfld.long 0x0C 23. "MFD,MultiFunction Device" "0,1" newline hexmask.long.byte 0x0C 16.--22. 1. "HEAD_TYP,Header Type - TYPE0" hexmask.long.byte 0x0C 8.--15. 1. "MSTR_LAT_TIM,Master Latency Timer Not Applicable for PCIe hence hardwired to 0" newline hexmask.long.byte 0x0C 0.--7. 1. "CACH_LN_SZE,Cache Line Size No impact on write write is allowed only for legacy purpose" line.long 0x10 "PCIECTRL_RC_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR Reads like in CS mode" hexmask.long 0x10 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x10 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x14 "PCIECTRL_RC_DBICS2_BAR1_MASK,Base Address Register 1 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode. contains the upper bits of BAR0 mask Reads like in CS mode" hexmask.long 0x14 1.--31. 1. "BAR_MASK,Write 1 to unmask / 0 to mask the BAR address bit (CS2 only)" bitfld.long 0x14 0. "BAR_ENABLED,BAR enabled (CS2 only)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS2_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer Not Applicable for PCI Express hence hardwired to 0" hexmask.long.byte 0x18 16.--23. 1. "SUBORD_BUS_NUM,Subordinate Bus Number" newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS_NUM,Secondary Bus Number" hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS_NUM,Primary Bus Number" line.long 0x1C "PCIECTRL_RC_DBICS2_IOBASE_LIMIT_SEC_STATUS,IO Base.Limit and Secondary Status Register" bitfld.long 0x1C 31. "DET_PAR_ERR,Detected Parity Error" "0,1" bitfld.long 0x1C 30. "RCVD_SYS_ERR,Received System Error" "0,1" newline bitfld.long 0x1C 29. "RCVD_MSTR_ABORT,Received Master Abort" "0,1" bitfld.long 0x1C 28. "RCVD_TRGT_ABORT,Received Target Error" "0,1" newline bitfld.long 0x1C 27. "SGNLD_TRGT_ABORT,Signaled Target Error" "0,1" rbitfld.long 0x1C 25.--26. "DEVSEL_TIMING,DEVSEL Timing Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" newline bitfld.long 0x1C 24. "MSTR_DATA_PRTY_ERR,Mastered Data Parity Error" "0,1" rbitfld.long 0x1C 23. "FAST_B2B_CAP,Fast Back to Back Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" newline rbitfld.long 0x1C 21. "C66MHZ_CAPA,66MHz Capable Not Applicable for PCI Express hence hardwired to 0" "0,1" bitfld.long 0x1C 12.--15. "IO_SPACE_LIMIT,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 8. "IODECODE_32,32 or 16 Bit IO Space" "0,1" bitfld.long 0x1C 4.--7. "IO_SPACE_BASE,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 0. "IODECODE_32_0,32 or 16 Bit IO Space (CS)" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS2_MEM_BASE_LIMIT,Memory Base and Limit Register" hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT_ADDR,Memory Limit Address" hexmask.long.word 0x20 4.--15. 1. "MEM_BASE_ADDR,Memory Base Address" line.long 0x24 "PCIECTRL_RC_DBICS2_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory End Address" rbitfld.long 0x24 16. "MEMDECODE_64,64-Bit Memory Addressing" "0,1" newline hexmask.long.word 0x24 4.--15. 1. "UPPPREF_MEM_ADDR,Upper 12 bits of 32-bit Prefetchable Memory start Address" rbitfld.long 0x24 0. "MEMDECODE_64_0,64-Bit Memory Addressing" "0,1" line.long 0x28 "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" line.long 0x2C "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" line.long 0x30 "PCIECTRL_RC_DBICS2_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x30 16.--31. 1. "UPP16_IOLIMIT,Upper 16 IO Limit Address" hexmask.long.word 0x30 0.--15. 1. "UPP16_IOBASE,Upper 16 IO Base Address" line.long 0x34 "PCIECTRL_RC_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x34 0.--7. 1. "CAPTR,First Capability Pointer (CS)" line.long 0x38 "PCIECTRL_RC_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" hexmask.long.word 0x38 16.--31. 1. "EXROM_ADDRESS,Expansion ROM address unmasked (ie programmable)" rbitfld.long 0x38 11.--15. "EXROM_ADDRESS_RO,Expansion ROM address masked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x38 0. "EXP_ROM_EN,Expansion ROM Enable" "0,1" line.long 0x3C "PCIECTRL_RC_DBICS2_BRIDGE_INT,Bridge Control and Int Pin and line" rbitfld.long 0x3C 27. "DT_SERR_EN,Discard Timer SERR Enable Status" "0,1" rbitfld.long 0x3C 26. "DT_STS,Discard Timer Status" "0,1" newline rbitfld.long 0x3C 25. "SEC_DT,Secondary Discard Timer" "0,1" rbitfld.long 0x3C 24. "PRI_DT,Primary Discard Timer" "0,1" newline rbitfld.long 0x3C 23. "FAST_B2B_EN,Fast Back-to-Back Transactions Enable" "0,1" bitfld.long 0x3C 22. "SEC_BUS_RST,Secondary Bus Reset (initiate hot reset)" "0,1" newline rbitfld.long 0x3C 21. "MST_ABT_MOD,Master Abort Mode" "0,1" bitfld.long 0x3C 20. "VGA_16B_DEC,VGA 16-Bit Decode" "0,1" newline bitfld.long 0x3C 19. "VGA_EN,VGA Enable" "0,1" bitfld.long 0x3C 18. "ISA_EN,ISA Enable" "0,1" newline bitfld.long 0x3C 17. "SERR_EN,SERR Enable" "0,1" bitfld.long 0x3C 16. "PERR_RESP_EN,Parity Error Response Enable" "0,1" newline hexmask.long.byte 0x3C 8.--15. 1. "INT_PIN,Interrupt Pin (CS)" hexmask.long.byte 0x3C 0.--7. 1. "INT_LIN,Interrupt Line" group.long 0x70++0x33 line.long 0x00 "PCIECTRL_RC_DBICS2_PCIE_CAP,PCI Express Capability structure header" bitfld.long 0x00 25.--29. "IM_NUM,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24. "SLOT,Slot Implemented (CS)" "0,1" newline rbitfld.long 0x00 20.--23. "DEV_TYPE,Device/Port Type - RC" "?,?,?,?,DEV_TYPE_4_r,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 16.--19. "PCIE_VER,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. "PCIE_NX_PTR,Next Capability Pointer (CS)" hexmask.long.byte 0x00 0.--7. 1. "CAP_ID,Capability ID - PCIE" line.long 0x04 "PCIECTRL_RC_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x04 26.--27. "CAPT_SLOW_PWRLIMIT_SCALE,Captured Slow Power Scale Value for Upstream Port Only (CS)" "0,1,2,3" hexmask.long.byte 0x04 18.--25. 1. "CAPT_SLOW_PWRLIMIT_VALUE,Captured Slow Power Limit Value for Upstream Port Only (CS)" newline bitfld.long 0x04 15. "ROLEBASED_ERRRPT,Role Based Error Reporting (CS)" "0,1" rbitfld.long 0x04 12.--14. "UNDEFINED,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x04 9.--11. "DEFAULT_EP_L1_ACCPT_LATENCY,Endpoint L1 Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" rbitfld.long 0x04 6.--8. "DEFAULT_EP_L0S_ACCPT_LATENCY,Endpoint L0s Acceptable Latency; Must be 0 for RC" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 5. "EXTTAGFIELD_SUPPORT,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x04 3.--4. "PHANTOMFUNC,Phantom Function Support NOT SUPPORTED (CS)" "0,1,2,3" newline bitfld.long 0x04 0.--2. "MAX_PAYLOAD_SIZE,Maximum Payload Size (CS) - _256_BYTE" "?,MAX_PAYLOAD_SIZE_1_r,?,?,?,?,?,?" line.long 0x08 "PCIECTRL_RC_DBICS2_DEV_CAS,PCIE Device Control and Status" rbitfld.long 0x08 21. "TRANS_PEND,Transaction Pending" "0,1" rbitfld.long 0x08 20. "AUXP_DET,Aux Power Detected" "0,1" newline bitfld.long 0x08 19. "UR_DET,Unsupported Request Detected" "0,1" bitfld.long 0x08 18. "FT_DET,Fatal Error Detected" "0,1" newline bitfld.long 0x08 17. "NFT_DET,Non-Fatal Error Detected" "0,1" bitfld.long 0x08 16. "COR_DET,Correctable Error Detected" "0,1" newline rbitfld.long 0x08 15. "INIT_FLR,Reserved" "0,1" bitfld.long 0x08 12.--14. "MRRS,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 11. "NOSNP_EN,Enable No Snoop" "0,1" bitfld.long 0x08 10. "AUXPM_EN,AUX Power PM Enable (Sticky bit) - DIS" "AUXPM_EN_0,AUXPM_EN_1" newline bitfld.long 0x08 9. "PHFUN_EN,Phantom Function Enable" "0,1" bitfld.long 0x08 8. "EXTAG_EN,Extended Tag Field Enable" "0,1" newline bitfld.long 0x08 5.--7. "MPS,Max_Payload_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4. "EN_RO,Enable Relaxed Ordering" "0,1" newline bitfld.long 0x08 3. "UR_RE,Unsupported Request Reporting Enable" "0,1" bitfld.long 0x08 2. "FT_RE,Fatal Error Reporting Enable" "0,1" newline bitfld.long 0x08 1. "NFT_RE,Non-Fatal Error Reporting Enable" "0,1" bitfld.long 0x08 0. "COR_RE,Correctable Error Reporting Enable" "0,1" line.long 0x0C "PCIECTRL_RC_DBICS2_LNK_CAP,PCIE Link Capabilities" hexmask.long.byte 0x0C 24.--31. 1. "PORT_NUM,Port Number (CS)" bitfld.long 0x0C 22. "ASPM_OPT_COMP,ASPM Optionality Compliance (CS)" "0,1" newline bitfld.long 0x0C 21. "LNK_BW_NOT_CAP,Link Bandwidth Notification Capability (CS)" "0,1" rbitfld.long 0x0C 20. "DLL_ACTRPT_CAP,Data Link Layer Active Reporting Capable" "0,1" newline rbitfld.long 0x0C 19. "UNSUP,Unsupported Surprise Down Error Reporting Capable Hardwired to 0" "0,1" bitfld.long 0x0C 18. "CLK_PWR_MGMT,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" newline bitfld.long 0x0C 15.--17. "COMM_L1_EXIT_LAT,Common-clock-mode L1 Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 12.--14. "COMM_L0S_EXIT_LAT,Common-clock-mode L0s Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 10.--11. "AS_LINK_PM_SUPPORT,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0C 4.--9. "MAX_LINK_WIDTH,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 0.--3. "MAX_LINK_SPEEDS,Supported Max Link Speed (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "PCIECTRL_RC_DBICS2_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x10 31. "LAB_STATUS,Link Autonomous Bandwidth Status" "0,1" bitfld.long 0x10 30. "LBW_STATUS,Link Bandwidth Management Status" "0,1" newline rbitfld.long 0x10 29. "DLL_ACT,Data Link Layer Active" "0,1" bitfld.long 0x10 28. "SLOT_CLK_CONFIG,Slot Clock Configuration (CS)" "0,1" newline rbitfld.long 0x10 27. "LINK_TRAIN,LINK training" "0,1" rbitfld.long 0x10 26. "UNDEF,Undefined" "0,1" newline rbitfld.long 0x10 20.--25. "NEG_LW,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x10 16.--19. "LINK_SPEED,Link Speed; UNDEFINED UNTIL LINK IS UP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 11. "LABIE,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x10 10. "LBMIE,Link Bandwidth Management Interrupt Enable" "0,1" newline rbitfld.long 0x10 9. "HAWD,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x10 8. "EN_CPM,Enable Clock Power Management" "0,1" newline bitfld.long 0x10 7. "EXT_SYN,Extended Synch" "0,1" bitfld.long 0x10 6. "COM_CLK_CFG,Common Clock Configuration - ASYNC" "COM_CLK_CFG_0,COM_CLK_CFG_1" newline bitfld.long 0x10 5. "RETRAIN_LINK,Retrain Link" "0,1" bitfld.long 0x10 4. "LINK_DIS,Link Disable" "0,1" newline bitfld.long 0x10 3. "RCB,Read Completion Boundary (CS) - _64_BYTE" "RCB_0,RCB_1" bitfld.long 0x10 0.--1. "ASPM_CTRL,Active State Link PM Control" "0,1,2,3" line.long 0x14 "PCIECTRL_RC_DBICS2_SLOT_CAP,Slot Capabilities Register" hexmask.long.word 0x14 19.--31. 1. "PSN,Physical Slot Number (CS)" bitfld.long 0x14 18. "NCCS,No Command Complete Support (CS)" "0,1" newline bitfld.long 0x14 17. "EIP,Electromechanical Interlock Present (CS)" "0,1" bitfld.long 0x14 15.--16. "SPLS,Slot Power Limit Scale (CS)" "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "SPLV,Slot Power Limit Value (CS)" bitfld.long 0x14 6. "HPC,Hot-Plug Capable (CS)" "0,1" newline bitfld.long 0x14 5. "HPS,Hot-Plug Surprise (CS)" "0,1" bitfld.long 0x14 4. "PIP,Power Indicator Present (CS)" "0,1" newline bitfld.long 0x14 3. "AIP,Attention Indicator Present (CS)" "0,1" bitfld.long 0x14 2. "MRLSP,MRL Sensor Present (CS)" "0,1" newline bitfld.long 0x14 1. "PCP,Power Controller Present (CS)" "0,1" bitfld.long 0x14 0. "ABP,Attention Button Present (CS)" "0,1" line.long 0x18 "PCIECTRL_RC_DBICS2_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x18 24. "DSC,Data Link Layer State Changed" "0,1" rbitfld.long 0x18 23. "EIS,Electromechanical Interlock Status" "0,1" newline rbitfld.long 0x18 22. "PDS,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" rbitfld.long 0x18 21. "MRLSS,MRL Sensor State" "0,1" newline bitfld.long 0x18 20. "CC,Command Completed" "0,1" bitfld.long 0x18 19. "PDC,Presence Detect Changed" "0,1" newline bitfld.long 0x18 18. "MRCSC,MRL Sensor Changed" "0,1" bitfld.long 0x18 17. "PFD,Power Fault Detected" "0,1" newline bitfld.long 0x18 16. "ABP,Attention Button Pressed" "0,1" bitfld.long 0x18 12. "DSC_EN,Data Link Layer State Changed Enable" "0,1" newline bitfld.long 0x18 11. "EIC,Electromechanical Interlock Control" "0,1" bitfld.long 0x18 10. "PCC,Power Controller Control" "0,1" newline bitfld.long 0x18 8.--9. "PIC,Power Indicator Control" "0,1,2,3" bitfld.long 0x18 6.--7. "AIC,Attention Indicator Control" "0,1,2,3" newline bitfld.long 0x18 5. "HPI_EN,Hot-Plug Interrupt Enable" "0,1" bitfld.long 0x18 4. "CCI_EN,Command Completed Interrupt Enable" "0,1" newline bitfld.long 0x18 3. "PDC_EN,Presence Detect Changed Enable" "0,1" bitfld.long 0x18 2. "MRLSC_EN,MRL Sensor Changed Enable" "0,1" newline bitfld.long 0x18 1. "PFD_EN,Power Fault Detected Enable" "0,1" bitfld.long 0x18 0. "ABP_EN,Attention Button Pressed Enable" "0,1" line.long 0x1C "PCIECTRL_RC_DBICS2_ROOT_CAC,Root Control and Capability Register" rbitfld.long 0x1C 16. "CRSSV,CRS Software Visibility" "0,1" rbitfld.long 0x1C 4. "CRSSV_EN,CRS Software Visibility Enable" "0,1" newline bitfld.long 0x1C 3. "PMEI_EN,PME Interrupt Enable" "0,1" bitfld.long 0x1C 2. "SEFE_EN,System Error on Fatal Error Enable" "0,1" newline bitfld.long 0x1C 1. "SENE_EN,System Error on Non-fatal Error Enable" "0,1" bitfld.long 0x1C 0. "SECE_EN,System Error on Correctable Error Enable" "0,1" line.long 0x20 "PCIECTRL_RC_DBICS2_ROOT_STS,Root Status Register" rbitfld.long 0x20 17. "PME_PND,PME Pending" "0,1" bitfld.long 0x20 16. "PME_STS,PME Status (Sticky bit)" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "PME_RID,PME Requester ID" line.long 0x24 "PCIECTRL_RC_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x24 12.--13. "TPHC_SP,TPH Completer Supported" "0,1,2,3" bitfld.long 0x24 10. "NOROPR,No RO-enabled PR-PR Passing" "0,1" newline bitfld.long 0x24 9. "CASC128_SP,128-bit CAS Completer Supported" "0,1" bitfld.long 0x24 8. "AOC64_SP,64-bit AtomicOp Completer Supported" "0,1" newline bitfld.long 0x24 7. "AOC32_SP,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x24 6. "AOR_SP,AtomicOp Routing Supported" "0,1" newline bitfld.long 0x24 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x24 4. "CPL_TIMEOUT_DIS_SUPPORTED,Completion Timeout Disable Supported" "0,1" newline bitfld.long 0x24 0.--3. "CPL_TIMEOUT_RNG_SUPPORTED,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "PCIECTRL_RC_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x28 13.--14. "OBFF_EN,OBFF Enable" "0,1,2,3" bitfld.long 0x28 10. "LTR_EN,LTR Mechanism Enable" "0,1" newline bitfld.long 0x28 9. "IDO_CPL_EN,IDO Completion Enable" "0,1" bitfld.long 0x28 8. "IDO_REQ_EN,IDO Request Enable" "0,1" newline bitfld.long 0x28 7. "AOP_EG_BLK,AtomicOp Egress Blocking" "0,1" bitfld.long 0x28 6. "AOP_REQ_EN,AtomicOp Requester Enable" "0,1" newline bitfld.long 0x28 5. "ARI_FWD_SP,ARI Forwarding Supported" "0,1" bitfld.long 0x28 4. "CPL_TIMEOUT_DIS,Completion Timeout Disable" "0,1" newline bitfld.long 0x28 0.--3. "CPL_TIMEOUT_VALUE,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "PCIECTRL_RC_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x2C 8. "CROSSLINK_SP,Crosslink Supported" "0,1" hexmask.long.byte 0x2C 1.--7. 1. "SP_LS_VEC,Supported Link Speeds Vector" line.long 0x30 "PCIECTRL_RC_DBICS2_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x30 21. "LINK_EQ_REQ,Link Equilization Request" "0,1" rbitfld.long 0x30 20. "EQ_PH3,Equalization Ph3 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 19. "EQ_PH2,Equalization Ph2 Success Gen3 Only" "0,1" rbitfld.long 0x30 18. "EQ_PH1,Equalization Ph1 Success Gen3 Only" "0,1" newline rbitfld.long 0x30 17. "EQ_COMPLETE,Equalization Complete Gen3 Only" "0,1" rbitfld.long 0x30 16. "DEEMPH_LEVEL,Current De-emphasis Level" "0,1" newline bitfld.long 0x30 12.--15. "COMPL_PRST_DEEPH,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x30 11. "COMPL_SOS,Compliance SOS" "0,1" newline bitfld.long 0x30 10. "ENT_MOD_COMPL,Enter Modified Compliance" "0,1" bitfld.long 0x30 7.--9. "TX_MARGIN,Transmit Margin" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6. "SEL_DEEMP,Selectable De-emphasis (CS)" "0,1" bitfld.long 0x30 5. "HW_AUTO_SP_DIS,Hardware Autonomous Speed Disable" "0,1" newline bitfld.long 0x30 4. "ENTR_COMPL,Enter Compliance" "0,1" bitfld.long 0x30 0.--3. "TRGT_LINK_SPEED,Target Link Speed: Read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe_SS1_TI_CONF" base ad:0x51002000 rgroup.long 0x00++0x03 line.long 0x00 "PCIECTRL_TI_CONF_REVISION,IP Revision Identifier" group.long 0x10++0x03 line.long 0x00 "PCIECTRL_TI_CONF_SYSCONFIG,Controls various parameters of the master and slave interfaces" bitfld.long 0x00 16. "MCOHERENT_EN,Allows the no-snoop (NS) attribute of inbound PCIe TLPs to be passed to SoC system bus (AXI) master as a 'coherent' inband flag" "MCOHERENT_EN_0,MCOHERENT_EN_1" bitfld.long 0x00 4.--5. "STANDBYMODE,PM mode of local initiator (master); Initiator may generate read/write transaction as long as it is out of STANDBY state" "0,1,2,3" bitfld.long 0x00 2.--3. "IDLEMODE,PM mode of local target (slave); Target shall be capable of handling read/write transaction as long as it is out of IDLE state" "0,1,2,3" group.long 0x18++0x03 line.long 0x00 "PCIECTRL_TI_CONF_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0.--3. "LINE_NUMBER,Write the IRQ line number to apply SW EOI to it" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x1F line.long 0x00 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN,Raw status of 'main' interrupt requests; Set even if event is not enabled" bitfld.long 0x00 14. "CFG_MSE_EVT,CFG 'Memory Space Enable' change IRQ status" "0,1" bitfld.long 0x00 13. "CFG_BME_EVT,CFG 'Bus Master Enable' change IRQ status" "0,1" bitfld.long 0x00 12. "LINK_UP_EVT,Link-up state change IRQ status" "0,1" newline bitfld.long 0x00 11. "LINK_REQ_RST,Link Request Reset IRQ status" "0,1" bitfld.long 0x00 10. "PM_PME,PM Power Management Event message received IRQ status" "0,1" bitfld.long 0x00 9. "PME_TO_ACK,Power Management Event Turn-Off Ack message received IRQ status" "0,1" newline bitfld.long 0x00 8. "PME_TURN_OFF,Power Management Event Turn-Off message received IRQ status" "0,1" bitfld.long 0x00 5. "ERR_ECRC,ECRC Error IRQ status" "0,1" bitfld.long 0x00 4. "ERR_AXI,AXI tag lookup fatal Error IRQ status" "0,1" newline bitfld.long 0x00 3. "ERR_COR,Correctable Error message received IRQ status" "0,1" bitfld.long 0x00 2. "ERR_NONFATAL,Non-Fatal Error message received IRQ status" "0,1" bitfld.long 0x00 1. "ERR_FATAL,Fatal Error message received IRQ status" "0,1" newline bitfld.long 0x00 0. "ERR_SYS,System Error IRQ status" "0,1" line.long 0x04 "PCIECTRL_TI_CONF_IRQSTATUS_MAIN,Regular status of 'main' interrupt requests; Set only when enabled" bitfld.long 0x04 14. "CFG_MSE_EVT,CFG 'Memory Space Enable' change IRQ status" "0,1" bitfld.long 0x04 13. "CFG_BME_EVT,CFG 'Bus Master Enable' change IRQ status" "0,1" bitfld.long 0x04 12. "LINK_UP_EVT,Link-up state change IRQ status" "0,1" newline bitfld.long 0x04 11. "LINK_REQ_RST,Link Request Reset IRQ status" "0,1" bitfld.long 0x04 10. "PM_PME,PM Power Management Event message received IRQ status" "0,1" bitfld.long 0x04 9. "PME_TO_ACK,Power Management Event Turn-Off Ack message received IRQ status" "0,1" newline bitfld.long 0x04 8. "PME_TURN_OFF,Power Management Event Turn-Off message received IRQ status" "0,1" bitfld.long 0x04 5. "ERR_ECRC,ECRC Error IRQ status" "0,1" bitfld.long 0x04 4. "ERR_AXI,AXI tag lookup fatal Error IRQ status" "0,1" newline bitfld.long 0x04 3. "ERR_COR,Correctable Error message received IRQ status" "0,1" bitfld.long 0x04 2. "ERR_NONFATAL,Non-Fatal Error message received IRQ status" "0,1" bitfld.long 0x04 1. "ERR_FATAL,Fatal Error message received IRQ status" "0,1" newline bitfld.long 0x04 0. "ERR_SYS,System Error IRQ status" "0,1" line.long 0x08 "PCIECTRL_TI_CONF_IRQENABLE_SET_MAIN,Enable of 'main' interrupt requests; Write 1 to set (ie to enable interrupt)" bitfld.long 0x08 14. "CFG_MSE_EVT_EN,CFG 'Memory Space Enable' change IRQ enable" "0,1" bitfld.long 0x08 13. "CFG_BME_EVT_EN,CFG 'Bus Master Enable' change IRQ enable" "0,1" bitfld.long 0x08 12. "LINK_UP_EVT_EN,Link-up state change IRQ enable" "0,1" newline bitfld.long 0x08 11. "LINK_REQ_RST_EN,Link Request Reset IRQ enable" "0,1" bitfld.long 0x08 10. "PM_PME_EN,PM Power Management Event message received IRQ enable" "0,1" bitfld.long 0x08 9. "PME_TO_ACK_EN,Power Management Event Turn-Off Ack message received IRQ enable" "0,1" newline bitfld.long 0x08 8. "PME_TURN_OFF_EN,Power Management Event Turn-Off message received IRQ enable" "0,1" bitfld.long 0x08 5. "ERR_ECRC_EN,ECRC Error IRQ enable" "0,1" bitfld.long 0x08 4. "ERR_AXI_EN,AXI tag lookup fatal Error IRQ enable" "0,1" newline bitfld.long 0x08 3. "ERR_COR_EN,Correctable Error message received IRQ enable" "0,1" bitfld.long 0x08 2. "ERR_NONFATAL_EN,Non-Fatal Error message received IRQ enable" "0,1" bitfld.long 0x08 1. "ERR_FATAL_EN,Fatal Error message received IRQ enable" "0,1" newline bitfld.long 0x08 0. "ERR_SYS_EN,System Error IRQ enable" "0,1" line.long 0x0C "PCIECTRL_TI_CONF_IRQENABLE_CLR_MAIN,Enable of 'main' interrupt requests; Write 1 to clear (ie to disable interrupt)" bitfld.long 0x0C 14. "CFG_MSE_EVT_EN,CFG 'Memory Space Enable' change IRQ enable" "0,1" bitfld.long 0x0C 13. "CFG_BME_EVT_EN,CFG 'Bus Master Enable' change IRQ enable" "0,1" bitfld.long 0x0C 12. "LINK_UP_EVT_EN,Link-up state change IRQ enable" "0,1" newline bitfld.long 0x0C 11. "LINK_REQ_RST_EN,Link Request Reset IRQ enable" "0,1" bitfld.long 0x0C 10. "PM_PME_EN,PM Power Management Event message received IRQ enable" "0,1" bitfld.long 0x0C 9. "PME_TO_ACK_EN,Power Management Event Turn-Off Ack message received IRQ enable" "0,1" newline bitfld.long 0x0C 8. "PME_TURN_OFF_EN,Power Management Event Turn-Off message received IRQ enable" "0,1" bitfld.long 0x0C 5. "ERR_ECRC_EN,ECRC Error IRQ enable" "0,1" bitfld.long 0x0C 4. "ERR_AXI_EN,AXI tag lookup fatal Error IRQ enable" "0,1" newline bitfld.long 0x0C 3. "ERR_COR_EN,Correctable Error message received IRQ enable" "0,1" bitfld.long 0x0C 2. "ERR_NONFATAL_EN,Non-Fatal Error message received IRQ enable" "0,1" bitfld.long 0x0C 1. "ERR_FATAL_EN,Fatal Error message received IRQ enable" "0,1" newline bitfld.long 0x0C 0. "ERR_SYS_EN,System Error IRQ enable" "0,1" line.long 0x10 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MSI,Raw status of legacy and MSI interrupt requests; Set even if event is not enabled" bitfld.long 0x10 4. "MSI,Message Signaled Interrupt IRQ status" "0,1" bitfld.long 0x10 3. "INTD,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only" "0,1" bitfld.long 0x10 2. "INTC,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only" "0,1" newline bitfld.long 0x10 1. "INTB,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only" "0,1" bitfld.long 0x10 0. "INTA,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only" "0,1" line.long 0x14 "PCIECTRL_TI_CONF_IRQSTATUS_MSI,Regular status of legacy and MSI interrupt requests; Set only when enabled" bitfld.long 0x14 4. "MSI,Message Signaled Interrupt IRQ status" "0,1" bitfld.long 0x14 3. "INTD,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only" "0,1" bitfld.long 0x14 2. "INTC,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only" "0,1" newline bitfld.long 0x14 1. "INTB,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only" "0,1" bitfld.long 0x14 0. "INTA,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only" "0,1" line.long 0x18 "PCIECTRL_TI_CONF_IRQENABLE_SET_MSI,Enable of legacy and MSI interrupt requests; Write 1 to set (ie to enable interrupt)" bitfld.long 0x18 4. "MSI_EN,Message Signaled Interrupt IRQ enable" "0,1" bitfld.long 0x18 3. "INTD_EN,INTD IRQ enable" "0,1" bitfld.long 0x18 2. "INTC_EN,INTC IRQ enable" "0,1" newline bitfld.long 0x18 1. "INTB_EN,INTB IRQ enable" "0,1" bitfld.long 0x18 0. "INTA_EN,INTA IRQ enable" "0,1" line.long 0x1C "PCIECTRL_TI_CONF_IRQENABLE_CLR_MSI,Enable of legacy and MSI interrupt requests; Write 1 to clear (ie to disable interrupt)" bitfld.long 0x1C 4. "MSI_EN,Message Signaled Interrupt IRQ enable" "0,1" bitfld.long 0x1C 3. "INTD_EN,INTD IRQ enable" "0,1" bitfld.long 0x1C 2. "INTC_EN,INTC IRQ enable" "0,1" newline bitfld.long 0x1C 1. "INTB_EN,INTB IRQ enable" "0,1" bitfld.long 0x1C 0. "INTA_EN,INTA IRQ enable" "0,1" group.long 0x100++0x0F line.long 0x00 "PCIECTRL_TI_CONF_DEVICE_TYPE,Sets the Dual-Mode device's type" bitfld.long 0x00 0.--3. "TYPE,PCIe device type including the contents of the PCI config space (Type-0 for EP Type-1 for RC); Apply fundamental reset after change; Do not change during core operation;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_TI_CONF_DEVICE_CMD,Device command (startup control and status); WARNING: cleared by all reset conditions. including fundamental reset" hexmask.long.byte 0x04 21.--28. 1. "BUS_NUM,PCIe bus number" rbitfld.long 0x04 16.--20. "DEV_NUM,PCIe device number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 2.--7. "LTSSM_STATE,LTSSM state / substate implementation-specific for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 1. "APP_REQ_RETRY_EN,Application Request Retry Enable (This bit is CLEARED BY FUNDAMENTAL RESET) - DISABLED" "APP_REQ_RETRY_EN_0,APP_REQ_RETRY_EN_1" bitfld.long 0x04 0. "LTSSM_EN,LTSSM enable: start the PCI link (This bit is CLEARED BY FUNDAMENTAL RESET) - DISABLED" "LTSSM_EN_0,LTSSM_EN_1" line.long 0x08 "PCIECTRL_TI_CONF_PM_CTRL,Power Management Control" bitfld.long 0x08 11. "AUX_PWR_DET,Auxilliary Power Detection; Status of Vaux detection for the PCIe controller; Determines transition to L2 vs L3 upon Vmain turn-off" "AUX_PWR_DET_0,AUX_PWR_DET_1" bitfld.long 0x08 10. "REQ_EXIT_L1,Request to exit L1 state (to L0) - INACTIVE" "REQ_EXIT_L1_0,REQ_EXIT_L1_1" bitfld.long 0x08 9. "REQ_ENTR_L1,Request to transition to L1 state - INACTIVE" "REQ_ENTR_L1_0,REQ_ENTR_L1_1" newline bitfld.long 0x08 8. "L23_READY,Indicates system readiness for the link to enter L2/L3 ready state (EP mode only); Allows the transmission of PM_Enter_L23 following PM_Turn_OFF / PME_TO_Ack handshake" "L23_READY_0,L23_READY_1" bitfld.long 0x08 1. "PM_PME,Transmits PM_PME wakeup message (EP mode only) - NOACTION" "PM_PME_0,PM_PME_1" bitfld.long 0x08 0. "PME_TURN_OFF,Transmits PME_Turn_Off message downstream (RC mode only); Eventually sends all links of hierarchy domain to L2L/3_ready - NOACTION" "PME_TURN_OFF_0,PME_TURN_OFF_1" line.long 0x0C "PCIECTRL_TI_CONF_PHY_CS,Physical Layer Control and Status" rbitfld.long 0x0C 16. "LINK_UP,Link status from LTSSM - DOWN" "LINK_UP_0,LINK_UP_1" bitfld.long 0x0C 0. "REVERSE_LANES,Manual lane reversal control allowing lane 0 and lane 1 to be swapped by default; Both Tx and Rx are reversed; Polarity of the individual lane is unchanged - STRAIGHT" "REVERSE_LANES_0,REVERSE_LANES_1" group.long 0x124++0x0B line.long 0x00 "PCIECTRL_TI_CONF_INTX_ASSERT,Legacy INTx ASSERT message control. with 'x' in (A.B.C.D) set by the 'Interrupt Pin' field" bitfld.long 0x00 0. "ASSERT_F0,INTx ASSERT for function 0" "0,1" line.long 0x04 "PCIECTRL_TI_CONF_INTX_DEASSERT,Legacy INTx DEASSERT message control. with 'x' in (A.B.C.D) set by the 'Interrupt Pin' field" bitfld.long 0x04 0. "DEASSERT_F0,INTx DEASSERT for function 0" "0,1" line.long 0x08 "PCIECTRL_TI_CONF_MSI_XMT,MSI transmitter (EP mode); Specifies parameters of MSI. together with MSI capability descriptor already configured by remote RC" bitfld.long 0x08 7.--11. "MSI_VECTOR,Vector number for transmitted MSI (as allowed by RC at enumeration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--6. "MSI_TC,Traffic class (TC) for transmitted MSI" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. "MSI_FUNC_NUM,Function number for transmitted MSI; Always 0 for single-function EP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0. "MSI_REQ_GRANT,MSI transmit request (and grant status)" "0,1" group.long 0x140++0x0B line.long 0x00 "PCIECTRL_TI_CONF_DEBUG_CFG,Configuration of debug_data output and register (observability)" bitfld.long 0x00 0.--5. "SEL,Debug_data mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PCIECTRL_TI_CONF_DEBUG_DATA,Debug data vector. depending on DEBUG_CFG.sel value" line.long 0x08 "PCIECTRL_TI_CONF_DIAG_CTRL,Diagnostic control" bitfld.long 0x08 1. "INV_ECRC,Corrupt LSB of ECRC in the next packet then self-clears" "0,1" bitfld.long 0x08 0. "INV_LCRC,Corrupts LSB of LCRC in the next packet then self-clears" "0,1" tree.end tree "PCIe_SS2_TI_CONF" base ad:0x51802000 rgroup.long 0x00++0x03 line.long 0x00 "PCIECTRL_TI_CONF_REVISION,IP Revision Identifier" group.long 0x10++0x03 line.long 0x00 "PCIECTRL_TI_CONF_SYSCONFIG,Controls various parameters of the master and slave interfaces" bitfld.long 0x00 16. "MCOHERENT_EN,Allows the no-snoop (NS) attribute of inbound PCIe TLPs to be passed to SoC system bus (AXI) master as a 'coherent' inband flag" "MCOHERENT_EN_0,MCOHERENT_EN_1" bitfld.long 0x00 4.--5. "STANDBYMODE,PM mode of local initiator (master); Initiator may generate read/write transaction as long as it is out of STANDBY state" "0,1,2,3" bitfld.long 0x00 2.--3. "IDLEMODE,PM mode of local target (slave); Target shall be capable of handling read/write transaction as long as it is out of IDLE state" "0,1,2,3" group.long 0x18++0x03 line.long 0x00 "PCIECTRL_TI_CONF_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0.--3. "LINE_NUMBER,Write the IRQ line number to apply SW EOI to it" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x1F line.long 0x00 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN,Raw status of 'main' interrupt requests; Set even if event is not enabled" bitfld.long 0x00 14. "CFG_MSE_EVT,CFG 'Memory Space Enable' change IRQ status" "0,1" bitfld.long 0x00 13. "CFG_BME_EVT,CFG 'Bus Master Enable' change IRQ status" "0,1" bitfld.long 0x00 12. "LINK_UP_EVT,Link-up state change IRQ status" "0,1" newline bitfld.long 0x00 11. "LINK_REQ_RST,Link Request Reset IRQ status" "0,1" bitfld.long 0x00 10. "PM_PME,PM Power Management Event message received IRQ status" "0,1" bitfld.long 0x00 9. "PME_TO_ACK,Power Management Event Turn-Off Ack message received IRQ status" "0,1" newline bitfld.long 0x00 8. "PME_TURN_OFF,Power Management Event Turn-Off message received IRQ status" "0,1" bitfld.long 0x00 5. "ERR_ECRC,ECRC Error IRQ status" "0,1" bitfld.long 0x00 4. "ERR_AXI,AXI tag lookup fatal Error IRQ status" "0,1" newline bitfld.long 0x00 3. "ERR_COR,Correctable Error message received IRQ status" "0,1" bitfld.long 0x00 2. "ERR_NONFATAL,Non-Fatal Error message received IRQ status" "0,1" bitfld.long 0x00 1. "ERR_FATAL,Fatal Error message received IRQ status" "0,1" newline bitfld.long 0x00 0. "ERR_SYS,System Error IRQ status" "0,1" line.long 0x04 "PCIECTRL_TI_CONF_IRQSTATUS_MAIN,Regular status of 'main' interrupt requests; Set only when enabled" bitfld.long 0x04 14. "CFG_MSE_EVT,CFG 'Memory Space Enable' change IRQ status" "0,1" bitfld.long 0x04 13. "CFG_BME_EVT,CFG 'Bus Master Enable' change IRQ status" "0,1" bitfld.long 0x04 12. "LINK_UP_EVT,Link-up state change IRQ status" "0,1" newline bitfld.long 0x04 11. "LINK_REQ_RST,Link Request Reset IRQ status" "0,1" bitfld.long 0x04 10. "PM_PME,PM Power Management Event message received IRQ status" "0,1" bitfld.long 0x04 9. "PME_TO_ACK,Power Management Event Turn-Off Ack message received IRQ status" "0,1" newline bitfld.long 0x04 8. "PME_TURN_OFF,Power Management Event Turn-Off message received IRQ status" "0,1" bitfld.long 0x04 5. "ERR_ECRC,ECRC Error IRQ status" "0,1" bitfld.long 0x04 4. "ERR_AXI,AXI tag lookup fatal Error IRQ status" "0,1" newline bitfld.long 0x04 3. "ERR_COR,Correctable Error message received IRQ status" "0,1" bitfld.long 0x04 2. "ERR_NONFATAL,Non-Fatal Error message received IRQ status" "0,1" bitfld.long 0x04 1. "ERR_FATAL,Fatal Error message received IRQ status" "0,1" newline bitfld.long 0x04 0. "ERR_SYS,System Error IRQ status" "0,1" line.long 0x08 "PCIECTRL_TI_CONF_IRQENABLE_SET_MAIN,Enable of 'main' interrupt requests; Write 1 to set (ie to enable interrupt)" bitfld.long 0x08 14. "CFG_MSE_EVT_EN,CFG 'Memory Space Enable' change IRQ enable" "0,1" bitfld.long 0x08 13. "CFG_BME_EVT_EN,CFG 'Bus Master Enable' change IRQ enable" "0,1" bitfld.long 0x08 12. "LINK_UP_EVT_EN,Link-up state change IRQ enable" "0,1" newline bitfld.long 0x08 11. "LINK_REQ_RST_EN,Link Request Reset IRQ enable" "0,1" bitfld.long 0x08 10. "PM_PME_EN,PM Power Management Event message received IRQ enable" "0,1" bitfld.long 0x08 9. "PME_TO_ACK_EN,Power Management Event Turn-Off Ack message received IRQ enable" "0,1" newline bitfld.long 0x08 8. "PME_TURN_OFF_EN,Power Management Event Turn-Off message received IRQ enable" "0,1" bitfld.long 0x08 5. "ERR_ECRC_EN,ECRC Error IRQ enable" "0,1" bitfld.long 0x08 4. "ERR_AXI_EN,AXI tag lookup fatal Error IRQ enable" "0,1" newline bitfld.long 0x08 3. "ERR_COR_EN,Correctable Error message received IRQ enable" "0,1" bitfld.long 0x08 2. "ERR_NONFATAL_EN,Non-Fatal Error message received IRQ enable" "0,1" bitfld.long 0x08 1. "ERR_FATAL_EN,Fatal Error message received IRQ enable" "0,1" newline bitfld.long 0x08 0. "ERR_SYS_EN,System Error IRQ enable" "0,1" line.long 0x0C "PCIECTRL_TI_CONF_IRQENABLE_CLR_MAIN,Enable of 'main' interrupt requests; Write 1 to clear (ie to disable interrupt)" bitfld.long 0x0C 14. "CFG_MSE_EVT_EN,CFG 'Memory Space Enable' change IRQ enable" "0,1" bitfld.long 0x0C 13. "CFG_BME_EVT_EN,CFG 'Bus Master Enable' change IRQ enable" "0,1" bitfld.long 0x0C 12. "LINK_UP_EVT_EN,Link-up state change IRQ enable" "0,1" newline bitfld.long 0x0C 11. "LINK_REQ_RST_EN,Link Request Reset IRQ enable" "0,1" bitfld.long 0x0C 10. "PM_PME_EN,PM Power Management Event message received IRQ enable" "0,1" bitfld.long 0x0C 9. "PME_TO_ACK_EN,Power Management Event Turn-Off Ack message received IRQ enable" "0,1" newline bitfld.long 0x0C 8. "PME_TURN_OFF_EN,Power Management Event Turn-Off message received IRQ enable" "0,1" bitfld.long 0x0C 5. "ERR_ECRC_EN,ECRC Error IRQ enable" "0,1" bitfld.long 0x0C 4. "ERR_AXI_EN,AXI tag lookup fatal Error IRQ enable" "0,1" newline bitfld.long 0x0C 3. "ERR_COR_EN,Correctable Error message received IRQ enable" "0,1" bitfld.long 0x0C 2. "ERR_NONFATAL_EN,Non-Fatal Error message received IRQ enable" "0,1" bitfld.long 0x0C 1. "ERR_FATAL_EN,Fatal Error message received IRQ enable" "0,1" newline bitfld.long 0x0C 0. "ERR_SYS_EN,System Error IRQ enable" "0,1" line.long 0x10 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MSI,Raw status of legacy and MSI interrupt requests; Set even if event is not enabled" bitfld.long 0x10 4. "MSI,Message Signaled Interrupt IRQ status" "0,1" bitfld.long 0x10 3. "INTD,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only" "0,1" bitfld.long 0x10 2. "INTC,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only" "0,1" newline bitfld.long 0x10 1. "INTB,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only" "0,1" bitfld.long 0x10 0. "INTA,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only" "0,1" line.long 0x14 "PCIECTRL_TI_CONF_IRQSTATUS_MSI,Regular status of legacy and MSI interrupt requests; Set only when enabled" bitfld.long 0x14 4. "MSI,Message Signaled Interrupt IRQ status" "0,1" bitfld.long 0x14 3. "INTD,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only" "0,1" bitfld.long 0x14 2. "INTC,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only" "0,1" newline bitfld.long 0x14 1. "INTB,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only" "0,1" bitfld.long 0x14 0. "INTA,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only" "0,1" line.long 0x18 "PCIECTRL_TI_CONF_IRQENABLE_SET_MSI,Enable of legacy and MSI interrupt requests; Write 1 to set (ie to enable interrupt)" bitfld.long 0x18 4. "MSI_EN,Message Signaled Interrupt IRQ enable" "0,1" bitfld.long 0x18 3. "INTD_EN,INTD IRQ enable" "0,1" bitfld.long 0x18 2. "INTC_EN,INTC IRQ enable" "0,1" newline bitfld.long 0x18 1. "INTB_EN,INTB IRQ enable" "0,1" bitfld.long 0x18 0. "INTA_EN,INTA IRQ enable" "0,1" line.long 0x1C "PCIECTRL_TI_CONF_IRQENABLE_CLR_MSI,Enable of legacy and MSI interrupt requests; Write 1 to clear (ie to disable interrupt)" bitfld.long 0x1C 4. "MSI_EN,Message Signaled Interrupt IRQ enable" "0,1" bitfld.long 0x1C 3. "INTD_EN,INTD IRQ enable" "0,1" bitfld.long 0x1C 2. "INTC_EN,INTC IRQ enable" "0,1" newline bitfld.long 0x1C 1. "INTB_EN,INTB IRQ enable" "0,1" bitfld.long 0x1C 0. "INTA_EN,INTA IRQ enable" "0,1" group.long 0x100++0x0F line.long 0x00 "PCIECTRL_TI_CONF_DEVICE_TYPE,Sets the Dual-Mode device's type" bitfld.long 0x00 0.--3. "TYPE,PCIe device type including the contents of the PCI config space (Type-0 for EP Type-1 for RC); Apply fundamental reset after change; Do not change during core operation;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PCIECTRL_TI_CONF_DEVICE_CMD,Device command (startup control and status); WARNING: cleared by all reset conditions. including fundamental reset" hexmask.long.byte 0x04 21.--28. 1. "BUS_NUM,PCIe bus number" rbitfld.long 0x04 16.--20. "DEV_NUM,PCIe device number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x04 2.--7. "LTSSM_STATE,LTSSM state / substate implementation-specific for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 1. "APP_REQ_RETRY_EN,Application Request Retry Enable (This bit is CLEARED BY FUNDAMENTAL RESET) - DISABLED" "APP_REQ_RETRY_EN_0,APP_REQ_RETRY_EN_1" bitfld.long 0x04 0. "LTSSM_EN,LTSSM enable: start the PCI link (This bit is CLEARED BY FUNDAMENTAL RESET) - DISABLED" "LTSSM_EN_0,LTSSM_EN_1" line.long 0x08 "PCIECTRL_TI_CONF_PM_CTRL,Power Management Control" bitfld.long 0x08 11. "AUX_PWR_DET,Auxilliary Power Detection; Status of Vaux detection for the PCIe controller; Determines transition to L2 vs L3 upon Vmain turn-off" "AUX_PWR_DET_0,AUX_PWR_DET_1" bitfld.long 0x08 10. "REQ_EXIT_L1,Request to exit L1 state (to L0) - INACTIVE" "REQ_EXIT_L1_0,REQ_EXIT_L1_1" bitfld.long 0x08 9. "REQ_ENTR_L1,Request to transition to L1 state - INACTIVE" "REQ_ENTR_L1_0,REQ_ENTR_L1_1" newline bitfld.long 0x08 8. "L23_READY,Indicates system readiness for the link to enter L2/L3 ready state (EP mode only); Allows the transmission of PM_Enter_L23 following PM_Turn_OFF / PME_TO_Ack handshake" "L23_READY_0,L23_READY_1" bitfld.long 0x08 1. "PM_PME,Transmits PM_PME wakeup message (EP mode only) - NOACTION" "PM_PME_0,PM_PME_1" bitfld.long 0x08 0. "PME_TURN_OFF,Transmits PME_Turn_Off message downstream (RC mode only); Eventually sends all links of hierarchy domain to L2L/3_ready - NOACTION" "PME_TURN_OFF_0,PME_TURN_OFF_1" line.long 0x0C "PCIECTRL_TI_CONF_PHY_CS,Physical Layer Control and Status" rbitfld.long 0x0C 16. "LINK_UP,Link status from LTSSM - DOWN" "LINK_UP_0,LINK_UP_1" bitfld.long 0x0C 0. "REVERSE_LANES,Manual lane reversal control allowing lane 0 and lane 1 to be swapped by default; Both Tx and Rx are reversed; Polarity of the individual lane is unchanged - STRAIGHT" "REVERSE_LANES_0,REVERSE_LANES_1" group.long 0x124++0x0B line.long 0x00 "PCIECTRL_TI_CONF_INTX_ASSERT,Legacy INTx ASSERT message control. with 'x' in (A.B.C.D) set by the 'Interrupt Pin' field" bitfld.long 0x00 0. "ASSERT_F0,INTx ASSERT for function 0" "0,1" line.long 0x04 "PCIECTRL_TI_CONF_INTX_DEASSERT,Legacy INTx DEASSERT message control. with 'x' in (A.B.C.D) set by the 'Interrupt Pin' field" bitfld.long 0x04 0. "DEASSERT_F0,INTx DEASSERT for function 0" "0,1" line.long 0x08 "PCIECTRL_TI_CONF_MSI_XMT,MSI transmitter (EP mode); Specifies parameters of MSI. together with MSI capability descriptor already configured by remote RC" bitfld.long 0x08 7.--11. "MSI_VECTOR,Vector number for transmitted MSI (as allowed by RC at enumeration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 4.--6. "MSI_TC,Traffic class (TC) for transmitted MSI" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. "MSI_FUNC_NUM,Function number for transmitted MSI; Always 0 for single-function EP" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 0. "MSI_REQ_GRANT,MSI transmit request (and grant status)" "0,1" group.long 0x140++0x0B line.long 0x00 "PCIECTRL_TI_CONF_DEBUG_CFG,Configuration of debug_data output and register (observability)" bitfld.long 0x00 0.--5. "SEL,Debug_data mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "PCIECTRL_TI_CONF_DEBUG_DATA,Debug data vector. depending on DEBUG_CFG.sel value" line.long 0x08 "PCIECTRL_TI_CONF_DIAG_CTRL,Diagnostic control" bitfld.long 0x08 1. "INV_ECRC,Corrupt LSB of ECRC in the next packet then self-clears" "0,1" bitfld.long 0x08 0. "INV_LCRC,Corrupts LSB of LCRC in the next packet then self-clears" "0,1" tree.end tree.end tree.open "PCIe_Shared_PHY_Subsystem" tree "OCP2SCP3" base ad:0x4A090000 rgroup.long 0x00++0x03 line.long 0x00 "OCP2SCP_REVISION,IP Revision Identifier (X.Y.R)" bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function: Indicates a software compatible module family" bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "MAJOR,ajor Revision This field changes when there is a major feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. "MINOR,inor Revision This field changes when features are scaled up or down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x0B line.long 0x00 "OCP2SCP_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 3.--4. "IDLEMODE,- ForceIdle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software Reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,OCP interface clock gating control" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "OCP2SCP_SYSSTATUS,System Status register" bitfld.long 0x04 0. "RESETDONE,- Complete" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "OCP2SCP_TIMING,Interrupt Status Register (legacy) for first line of interrupt" bitfld.long 0x08 7.--9. "DIVISIONRATIO,Division Ration of the SCP clock in relation to OCP input clock" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "SYNC1,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--3. "SYNC2,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "PCIe1_PHY_RX" base ad:0x4A094000 group.long 0x0C++0x03 line.long 0x00 "PCIEPHYRX_ANA_PROGRAMMABILITY_REG1,Some programmability for different analog circuits in the IP" hexmask.long.tbyte 0x00 8.--31. 1. "MEM_ANATESTMODE,Programmability for Analog circuits in the IP" bitfld.long 0x00 5.--6. "MEM_PLLDIV,This is a test mode" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "PCIEPHYRX_TRIM_REG4,The IP requires some values to be remembered in EFUSE" bitfld.long 0x00 30.--31. "MEM_DLL_TRIM_SEL,Determines which of the 4 EFUSE registers EFUSE_dll_rateN_coarsetrim should be used as the trim code by the DLL" "0,1,2,3" group.long 0x24++0x07 line.long 0x00 "PCIEPHYRX_DLL_REG1,This register is used to program DLL settings" bitfld.long 0x00 30.--31. "MEM_DLL_PHINT_RATE,Programs the DLL and the Phase Interpolator analog circuits to work with different clock frequencies" "0,1,2,3" line.long 0x04 "PCIEPHYRX_DIGITAL_MODES_REG1,This register contains control bits which affect different circuits in digital section of the IP" bitfld.long 0x04 31. "MEM_INV_RXPN_PAIR,If '1' interchanges RXP and RXN effectively by inverting the received data samples" "0,1" bitfld.long 0x04 30. "MEM_OVRD_INV_RXPN_PAIR,Pin override control" "0,1" bitfld.long 0x04 27.--28. "MEM_HS_RATE,Determines the ratio of pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) frequency and the output data rate" "0,1,2,3" bitfld.long 0x04 26. "MEM_OVRD_HS_RATE,Pin override control" "0,1" newline bitfld.long 0x04 23. "MEM_CDR_FASTLOCK,'1' to reduce lock time of CDR (clock-data-recovery circuit)" "0,1" bitfld.long 0x04 21.--22. "MEM_CDR_LBW,CDR band-width control" "0,1,2,3" bitfld.long 0x04 19.--20. "MEM_CDR_STEPCNT,CDR 2nd order setting" "0,1,2,3" bitfld.long 0x04 16.--18. "MEM_CDR_STL,CDR settling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 13.--15. "MEM_CDR_THR,CDR 1st order threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12. "MEM_CDR_THR_MODE,CDR 1st order threshold" "0,1" bitfld.long 0x04 11. "MEM_CDR_2NDO_SDM_MODE,If '1' the 2nd Order CDR block uses a 1st order Sigma Delta Modulator to accomplish frequency offset If '0' a simple rate transformer is used for the same purpose" "0,1" group.long 0x38++0x03 line.long 0x00 "PCIEPHYRX_EQUALIZER_REG1,The IP has an Equalizer (with analog and digital parts) which addresses Inter Symbol Interference (ISI)" hexmask.long.word 0x00 16.--31. 1. "MEM_EQLEV,Equalizer level control" bitfld.long 0x00 11.--15. "MEM_EQFTC,Equalizer zero freq control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7.--10. "MEM_EQCTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. "MEM_OVRD_EQLEV,Continuosly forces the Equalizer output with the eqlev[15:0]" "0,1" newline bitfld.long 0x00 1. "MEM_OVRD_EQFTC,Continuosly forces the Equalizer output with the eqftc[4:0]" "0,1" tree.end tree "PCIe2_PHY_RX" base ad:0x4A095000 group.long 0x0C++0x03 line.long 0x00 "PCIEPHYRX_ANA_PROGRAMMABILITY_REG1,Some programmability for different analog circuits in the IP" hexmask.long.tbyte 0x00 8.--31. 1. "MEM_ANATESTMODE,Programmability for Analog circuits in the IP" bitfld.long 0x00 5.--6. "MEM_PLLDIV,This is a test mode" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "PCIEPHYRX_TRIM_REG4,The IP requires some values to be remembered in EFUSE" bitfld.long 0x00 30.--31. "MEM_DLL_TRIM_SEL,Determines which of the 4 EFUSE registers EFUSE_dll_rateN_coarsetrim should be used as the trim code by the DLL" "0,1,2,3" group.long 0x24++0x07 line.long 0x00 "PCIEPHYRX_DLL_REG1,This register is used to program DLL settings" bitfld.long 0x00 30.--31. "MEM_DLL_PHINT_RATE,Programs the DLL and the Phase Interpolator analog circuits to work with different clock frequencies" "0,1,2,3" line.long 0x04 "PCIEPHYRX_DIGITAL_MODES_REG1,This register contains control bits which affect different circuits in digital section of the IP" bitfld.long 0x04 31. "MEM_INV_RXPN_PAIR,If '1' interchanges RXP and RXN effectively by inverting the received data samples" "0,1" bitfld.long 0x04 30. "MEM_OVRD_INV_RXPN_PAIR,Pin override control" "0,1" bitfld.long 0x04 27.--28. "MEM_HS_RATE,Determines the ratio of pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) frequency and the output data rate" "0,1,2,3" bitfld.long 0x04 26. "MEM_OVRD_HS_RATE,Pin override control" "0,1" newline bitfld.long 0x04 23. "MEM_CDR_FASTLOCK,'1' to reduce lock time of CDR (clock-data-recovery circuit)" "0,1" bitfld.long 0x04 21.--22. "MEM_CDR_LBW,CDR band-width control" "0,1,2,3" bitfld.long 0x04 19.--20. "MEM_CDR_STEPCNT,CDR 2nd order setting" "0,1,2,3" bitfld.long 0x04 16.--18. "MEM_CDR_STL,CDR settling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 13.--15. "MEM_CDR_THR,CDR 1st order threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12. "MEM_CDR_THR_MODE,CDR 1st order threshold" "0,1" bitfld.long 0x04 11. "MEM_CDR_2NDO_SDM_MODE,If '1' the 2nd Order CDR block uses a 1st order Sigma Delta Modulator to accomplish frequency offset If '0' a simple rate transformer is used for the same purpose" "0,1" group.long 0x38++0x03 line.long 0x00 "PCIEPHYRX_EQUALIZER_REG1,The IP has an Equalizer (with analog and digital parts) which addresses Inter Symbol Interference (ISI)" hexmask.long.word 0x00 16.--31. 1. "MEM_EQLEV,Equalizer level control" bitfld.long 0x00 11.--15. "MEM_EQFTC,Equalizer zero freq control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7.--10. "MEM_EQCTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. "MEM_OVRD_EQLEV,Continuosly forces the Equalizer output with the eqlev[15:0]" "0,1" newline bitfld.long 0x00 1. "MEM_OVRD_EQFTC,Continuosly forces the Equalizer output with the eqftc[4:0]" "0,1" tree.end tree "PCIe1_PHY_TX" base ad:0x4A094400 group.long 0x0C++0x07 line.long 0x00 "PCIEPHYTX_FUNC_CONFIG_REG,Functional Configuration registers" bitfld.long 0x00 31. "MEM_INVPAIR,Invert polarity of TXP/TXN" "0,1" line.long 0x04 "PCIEPHYTX_DRIVER_DATA_CONFIG1,Configures the Driver data pattern -details TBD" hexmask.long.byte 0x04 25.--31. 1. "MEM_EVEN_OUT_CONFIG0,Overriding the even TX data driver - to AFE - details TBD" hexmask.long.byte 0x04 18.--24. 1. "MEM_ODD_OUT_CONFIG0,Overriding the odd TX data driver - to AFE - details TBD" hexmask.long.byte 0x04 11.--17. 1. "MEM_EVEN_OUT_CONFIG1,Overriding the even TX data driver - to AFE - details TBD" newline hexmask.long.byte 0x04 4.--10. 1. "MEM_ODD_OUT_CONFIG1,Overriding the odd TX data driver - to AFE - details TBD" bitfld.long 0x04 2.--3. "MEM_HS_RATE_ANA_OVERRIDE,Override for the HS rate signal going to the AFE" "0,1,2,3" bitfld.long 0x04 1. "MEM_OVRD_HS_RATE_ANA_OVERRIDE,Pin override for the hs_rate_ana_override" "0,1" group.long 0x2C++0x07 line.long 0x00 "PCIEPHYTX_TEST_CONFIG_REG,Test related configuration registers" bitfld.long 0x00 30. "MEM_EN_LPBK,Loopback enable for test" "0,1" bitfld.long 0x00 29. "MEM_ENTXPATT,Enable Test pattern to input of the serializer instead of TD" "0,1" bitfld.long 0x00 26.--28. "MEM_TESTPATT,Select the LFSR mode to generate the required pattern" "0,1,2,3,4,5,6,7" line.long 0x04 "PCIEPHYTX_PATTGEN_PRELOAD,Pattern generator (31 bit) LFSR Seed or preload value" hexmask.long 0x04 1.--31. 1. "MEM_PATTGEN_PRELOAD_VAL,Preload value to the LFSR pattern generator" tree.end tree "PCIe2_PHY_TX" base ad:0x4A095400 group.long 0x0C++0x07 line.long 0x00 "PCIEPHYTX_FUNC_CONFIG_REG,Functional Configuration registers" bitfld.long 0x00 31. "MEM_INVPAIR,Invert polarity of TXP/TXN" "0,1" line.long 0x04 "PCIEPHYTX_DRIVER_DATA_CONFIG1,Configures the Driver data pattern -details TBD" hexmask.long.byte 0x04 25.--31. 1. "MEM_EVEN_OUT_CONFIG0,Overriding the even TX data driver - to AFE - details TBD" hexmask.long.byte 0x04 18.--24. 1. "MEM_ODD_OUT_CONFIG0,Overriding the odd TX data driver - to AFE - details TBD" hexmask.long.byte 0x04 11.--17. 1. "MEM_EVEN_OUT_CONFIG1,Overriding the even TX data driver - to AFE - details TBD" newline hexmask.long.byte 0x04 4.--10. 1. "MEM_ODD_OUT_CONFIG1,Overriding the odd TX data driver - to AFE - details TBD" bitfld.long 0x04 2.--3. "MEM_HS_RATE_ANA_OVERRIDE,Override for the HS rate signal going to the AFE" "0,1,2,3" bitfld.long 0x04 1. "MEM_OVRD_HS_RATE_ANA_OVERRIDE,Pin override for the hs_rate_ana_override" "0,1" group.long 0x2C++0x07 line.long 0x00 "PCIEPHYTX_TEST_CONFIG_REG,Test related configuration registers" bitfld.long 0x00 30. "MEM_EN_LPBK,Loopback enable for test" "0,1" bitfld.long 0x00 29. "MEM_ENTXPATT,Enable Test pattern to input of the serializer instead of TD" "0,1" bitfld.long 0x00 26.--28. "MEM_TESTPATT,Select the LFSR mode to generate the required pattern" "0,1,2,3,4,5,6,7" line.long 0x04 "PCIEPHYTX_PATTGEN_PRELOAD,Pattern generator (31 bit) LFSR Seed or preload value" hexmask.long 0x04 1.--31. 1. "MEM_PATTGEN_PRELOAD_VAL,Preload value to the LFSR pattern generator" tree.end tree.end tree.open "PRCM" tree "CAM_PRM" base ad:0x4AE07000 group.long 0x00++0x07 line.long 0x00 "PM_CAM_PWRSTCTRL,This register controls the CAM power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "VIP_BANK_ONSTATE,VIP_BANK memory state when domain is ON" "?,?,?,VIP_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CAM_PWRSTST,This register provides a status on the current CAM power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 4.--5. "VIP_BANK_STATEST,VIP_BANK memory state status - MEM_OFF" "VIP_BANK_STATEST_0,VIP_BANK_STATEST_1,VIP_BANK_STATEST_2,VIP_BANK_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x17 line.long 0x00 "PM_CAM_VIP1_WKDEP,This register controls wakeup dependency based on VIP1 service requests" bitfld.long 0x00 7. "WKUPDEP_VIP1_EVE2,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_EVE2_0,WKUPDEP_VIP1_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_VIP1_EVE1,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_EVE1_0,WKUPDEP_VIP1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_VIP1_DSP2,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_DSP2_0,WKUPDEP_VIP1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_VIP1_IPU1,Wakeup dependency from VIP1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_IPU1_0,WKUPDEP_VIP1_IPU1_1" bitfld.long 0x00 2. "WKUPDEP_VIP1_DSP1,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_DSP1_0,WKUPDEP_VIP1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_VIP1_IPU2,Wakeup dependency from vip1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_IPU2_0,WKUPDEP_VIP1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_VIP1_MPU,Wakeup dependency from VIP1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP1_MPU_0,WKUPDEP_VIP1_MPU_1" line.long 0x04 "RM_CAM_VIP1_CONTEXT,This register contains dedicated VIP1 context statuses" bitfld.long 0x04 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_CAM_VIP2_WKDEP,This register controls wakeup dependency based on VIP2 service requests" bitfld.long 0x08 7. "WKUPDEP_VIP2_EVE2,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_EVE2_0,WKUPDEP_VIP2_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_VIP2_EVE1,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_EVE1_0,WKUPDEP_VIP2_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_VIP2_DSP2,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_DSP2_0,WKUPDEP_VIP2_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_VIP2_IPU1,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_IPU1_0,WKUPDEP_VIP2_IPU1_1" bitfld.long 0x08 2. "WKUPDEP_VIP2_DSP1,Wakeup dependency from VIP2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_DSP1_0,WKUPDEP_VIP2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_VIP2_IPU2,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_IPU2_0,WKUPDEP_VIP2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_VIP2_MPU,Wakeup dependency from VIP2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP2_MPU_0,WKUPDEP_VIP2_MPU_1" line.long 0x0C "RM_CAM_VIP2_CONTEXT,This register contains dedicated VIP2 context statuses" bitfld.long 0x0C 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_CAM_VIP3_WKDEP,This register controls wakeup dependency based on VIP3 service requests" bitfld.long 0x10 7. "WKUPDEP_VIP3_EVE2,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_EVE2_0,WKUPDEP_VIP3_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_VIP3_EVE1,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_EVE1_0,WKUPDEP_VIP3_EVE1_1" bitfld.long 0x10 5. "WKUPDEP_VIP3_DSP2,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_DSP2_0,WKUPDEP_VIP3_DSP2_1" newline bitfld.long 0x10 4. "WKUPDEP_VIP3_IPU1,Wakeup dependency from VIP3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_IPU1_0,WKUPDEP_VIP3_IPU1_1" bitfld.long 0x10 2. "WKUPDEP_VIP3_DSP1,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_DSP1_0,WKUPDEP_VIP3_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_VIP3_IPU2,Wakeup dependency from vip3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_IPU2_0,WKUPDEP_VIP3_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_VIP3_MPU,Wakeup dependency from VIP3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VIP3_MPU_0,WKUPDEP_VIP3_MPU_1" line.long 0x14 "RM_CAM_VIP3_CONTEXT,This register contains dedicated VIP3 context statuses" bitfld.long 0x14 8. "LOSTMEM_VIP_BANK,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VIP_BANK_0,LOSTMEM_VIP_BANK_1" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "CKGEN_PRM" base ad:0x4AE06100 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_SYSCLK1,Select the SYS CLK for SYSCLK1_32K_CLK" bitfld.long 0x00 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_6" "CLKSEL_0,CLKSEL_1" group.long 0x08++0x33 line.long 0x00 "CM_CLKSEL_WKUPAON,Control the functional clock source of WKUPAON. PRM and Smart Reflex functional clock" bitfld.long 0x00 0. "CLKSEL,Select the clock source for WKUPAON_ICLK clock - SEL_SYS_CLK" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_ABE_PLL_REF,Control the source of the reference clock for DPLL_ABE" bitfld.long 0x04 0. "CLKSEL,Select the source for the DPLL_ABE reference clock" "CLKSEL_0,CLKSEL_1" line.long 0x08 "CM_CLKSEL_SYS,Software sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK" bitfld.long 0x08 0.--2. "SYS_CLKSEL,System clock input selection" "SYS_CLKSEL_0,SYS_CLKSEL_1,SYS_CLKSEL_2,SYS_CLKSEL_3,SYS_CLKSEL_4,SYS_CLKSEL_5,SYS_CLKSEL_6,SYS_CLKSEL_7" line.long 0x0C "CM_CLKSEL_ABE_PLL_BYPAS,Control the source of the bypass clock for DPLL_ABE" bitfld.long 0x0C 0. "CLKSEL,Control the source of the bypass clock for DPLL_ABE - SEL_SYS_CLK" "CLKSEL_0,CLKSEL_1" line.long 0x10 "CM_CLKSEL_ABE_PLL_SYS,Control the source of the SYS clock for DPLL_ABE" bitfld.long 0x10 0. "CLKSEL,Select the SYS clock for the DPLL_ABE reference and bypass clock" "CLKSEL_0,CLKSEL_1" line.long 0x14 "CM_CLKSEL_ABE_24M,Select the ABE_24M_FCLK for TIMERS subsystems" bitfld.long 0x14 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_8" "CLKSEL_0,CLKSEL_1" line.long 0x18 "CM_CLKSEL_ABE_SYS,Select the SYS CLK for IPU subsystems" bitfld.long 0x18 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_1" "CLKSEL_0,CLKSEL_1" line.long 0x1C "CM_CLKSEL_HDMI_MCASP_AUX,Select the HDMI_CLK for MCASP subsystems" bitfld.long 0x1C 0.--2. "CLKSEL,Selects the divider value - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x20 "CM_CLKSEL_HDMI_TIMER,Select the HDMI_CLK for TIMER subsystems" bitfld.long 0x20 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_32" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x24 "CM_CLKSEL_MCASP_SYS,Select the SYS CLK for ABE_24M_FCLK" bitfld.long 0x24 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_8" "CLKSEL_0,CLKSEL_1" line.long 0x28 "CM_CLKSEL_MLBP_MCASP,Select the MLBP_CLK for MCASP subsystems" bitfld.long 0x28 0.--2. "CLKSEL,Selects the divider value - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x2C "CM_CLKSEL_MLB_MCASP,Select the MLB_CLK for MCASP subsystems" bitfld.long 0x2C 0.--2. "CLKSEL,Selects the divider value - RESEREVD1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x30 "CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,Select the PER_ABE_X1_GFCLK_CLK for MCASP subsystems" bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" group.long 0x40++0x17 line.long 0x00 "CM_CLKSEL_SYS_CLK1_32K,Control the source of the SYS clock for GPIO. WD _TIMER.KBD" bitfld.long 0x00 0. "CLKSEL,Select the SYS clock for the DPLL_ABE reference and bypass clock" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_TIMER_SYS,Select the SYS CLK for TIMERS subsystems" bitfld.long 0x04 0. "CLKSEL,Selects the divider value - SYSCLK_DIV_1" "CLKSEL_0,CLKSEL_1" line.long 0x08 "CM_CLKSEL_VIDEO1_MCASP_AUX,Select the VIDEO1_CLK for MCASP subsystems" bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_VIDEO1_TIMER,Select the VIDEO1_CLK for TIMER subsystems" bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_32" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_VIDEO2_MCASP_AUX,Select the VIDEO2_CLK for MCASP subsystems" bitfld.long 0x10 0.--2. "CLKSEL,Selects the divider value - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x14 "CM_CLKSEL_VIDEO2_TIMER,Select the VIDEO2_CLK for TIMER subsystems" bitfld.long 0x14 0.--2. "CLKSEL,Selects the divider value - CLK_DIV_32" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" group.long 0x64++0x17 line.long 0x00 "CM_CLKSEL_HDMI_PLL_SYS,Control the source of the SYS clock for DPLL_HDMI" bitfld.long 0x00 0. "CLKSEL,Select the SYS clock for the DPLL_HDMI - SEL_SYS_CLK1" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_VIDEO1_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" bitfld.long 0x04 0. "CLKSEL,Select the SYS clock for the DPLL_VIDEO1" "CLKSEL_0,CLKSEL_1" line.long 0x08 "CM_CLKSEL_VIDEO2_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" bitfld.long 0x08 0. "CLKSEL,Select the SYS clock for the DPLL_VIDEO2" "CLKSEL_0,CLKSEL_1" line.long 0x0C "CM_CLKSEL_ABE_CLK_DIV,Select the ABE_CLK" bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_ABE_GICLK_DIV,Select the ABE_GICLK" bitfld.long 0x10 0. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1" line.long 0x14 "CM_CLKSEL_AESS_FCLK_DIV,Select the AESS_FCLK" bitfld.long 0x14 0. "CLKSEL,Selects the divider value - CLK_DIV_1" "CLKSEL_0,CLKSEL_1" group.long 0x80++0x43 line.long 0x00 "CM_CLKSEL_EVE_CLK,Control the source of the EVE_CLK for EVE1. EVE2" bitfld.long 0x00 0. "CLKSEL,Select the EVE_CLK for EVE1 EVE2 - SEL_EVE_GFCLK" "CLKSEL_0,CLKSEL_1" line.long 0x04 "CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX,Select the USB_OTG_CLK" bitfld.long 0x04 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x08 "CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX,Select the CORE_DPLL_OUT_CLK" bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_DSP_GFCLK_CLKOUTMUX,Select the DSP_GFCLK" bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,Select the EMIF_PHY_GCLK" bitfld.long 0x10 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x14 "CM_CLKSEL_EMU_CLK_CLKOUTMUX,Select the EMU_CLK" bitfld.long 0x14 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x18 "CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX,Select the FUNC_96M_AON_CLK" bitfld.long 0x18 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x1C "CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,Select the GMAC_250M_CLK" bitfld.long 0x1C 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x20 "CM_CLKSEL_GPU_GCLK_CLKOUTMUX,Select the GPU_GCLK" bitfld.long 0x20 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x24 "CM_CLKSEL_HDMI_CLK_CLKOUTMUX,Select the HDMI_CLK" bitfld.long 0x24 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x28 "CM_CLKSEL_IVA_GCLK_CLKOUTMUX,Select the IVA_GCLK" bitfld.long 0x28 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x2C "CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,Select the L3INIT_480M_GFCLK" bitfld.long 0x2C 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x30 "CM_CLKSEL_MPU_GCLK_CLKOUTMUX,Select the MPU_GCLK" bitfld.long 0x30 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x34 "CM_CLKSEL_PCIE1_CLK_CLKOUTMUX,Select the PCIE1_CLK" bitfld.long 0x34 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x38 "CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,Select the PCIE2_CLK" bitfld.long 0x38 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x3C "CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX,Select the PER_ABE_X1_CLK" bitfld.long 0x3C 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x40 "CM_CLKSEL_SATA_CLK_CLKOUTMUX,Select the SATA_CLK" bitfld.long 0x40 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" group.long 0xC8++0x13 line.long 0x00 "CM_CLKSEL_SYS_CLK1_CLKOUTMUX,Select the SYS_CLK1" bitfld.long 0x00 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x04 "CM_CLKSEL_SYS_CLK2_CLKOUTMUX,Select the SYS_CLK2" bitfld.long 0x04 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x08 "CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX,Select the VIDEO1_CLK" bitfld.long 0x08 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x0C "CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX,Select the VIDEO2_CLK" bitfld.long 0x0C 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" line.long 0x10 "CM_CLKSEL_ABE_LP_CLK,Select the ABE_LP_CLK" bitfld.long 0x10 0. "CLKSEL,Selects the divider value - CLK_DIV_16" "CLKSEL_0,CLKSEL_1" group.long 0xE0++0x03 line.long 0x00 "CM_CLKSEL_EVE_GFCLK_CLKOUTMUX,Select the EVE_GFCLK" bitfld.long 0x00 0.--2. "CLKSEL,Selects the divider value - RESERVED" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7" repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 ) group.long ($2+0x58)++0x03 line.long 0x00 "CM_CLKSEL_CLKOUTMUX$1,Control the source of the CLKOUTMUX0" bitfld.long 0x00 0.--4. "CLKSEL,Select the SYS clock for the DPLL_ABE reference and bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15,CLKSEL_16,CLKSEL_17,CLKSEL_18,CLKSEL_19,CLKSEL_20,CLKSEL_21,CLKSEL_22,CLKSEL_23,CLKSEL_24,CLKSEL_25,CLKSEL_26,CLKSEL_27,CLKSEL_28,CLKSEL_29,CLKSEL_30,CLKSEL_31" repeat.end tree.end tree "CM_CORE__CAM" base ad:0x4A009000 group.long 0x00++0x07 line.long 0x00 "CM_CAM_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 10. "CLKACTIVITY_VIP3_GCLK,This field indicates the state of the VIP3_GCLK clock input of the domain" "CLKACTIVITY_VIP3_GCLK_0,CLKACTIVITY_VIP3_GCLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_VIP2_GCLK,This field indicates the state of the VIP2_GCLK clock input of the domain" "CLKACTIVITY_VIP2_GCLK_0,CLKACTIVITY_VIP2_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_VIP1_GCLK,This field indicates the state of the VIP1_GCLK clock input of the domain" "CLKACTIVITY_VIP1_GCLK_0,CLKACTIVITY_VIP1_GCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the CAM clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_CAM_STATICDEP,This register controls the static domain depedencies from CAM domain towards 'target' domains" bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,?" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_CAM_VIP1_CLKCTRL,This register manages the VIP1 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK - SEL_L3_ICLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_CAM_VIP2_CLKCTRL,This register manages the VIP2 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK - SEL_L3_ICLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_CAM_VIP3_CLKCTRL,This register manages the VIP3 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK - SEL_L3_ICLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE__CKGEN" base ad:0x4A008100 group.long 0x04++0x03 line.long 0x00 "CM_CLKSEL_USB_60MHZ,Selects the configuration of the divider generating 60MHz clock for USB from the DPLL_USB o/p" bitfld.long 0x00 0. "CLKSEL,Select the configuration of the divider - SEL_DIV_1" "CLKSEL_0,CLKSEL_1" group.long 0x40++0x13 line.long 0x00 "CM_CLKMODE_DPLL_PER,This register allows controlling the DPLL modes" bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "DPLL_RELOCK_RAMP_EN_0,DPLL_RELOCK_RAMP_EN_1" bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x00 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x00 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_PER,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_PER,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_FR_BYP" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_PER,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "DPLL_BYP_CLKSEL_0,DPLL_BYP_CLKSEL_1" rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_PER,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 11. "CLKX2ST,DPLL CLKOUTX2 status - CLK_GATED" "CLKX2ST_0,CLKX2ST_1" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" newline bitfld.long 0x10 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x58++0x17 line.long 0x00 "CM_DIV_H11_DPLL_PER,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1" rbitfld.long 0x00 9. "CLKST,HSDIVIDER1 CLKOUT1 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x00 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "CM_DIV_H12_DPLL_PER,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1" rbitfld.long 0x04 9. "CLKST,HSDIVIDER1 CLKOUT2 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x04 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x08 "CM_DIV_H13_DPLL_PER,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1" rbitfld.long 0x08 9. "CLKST,HSDIVIDER1 CLKOUT3 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x08 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x0C "CM_DIV_H14_DPLL_PER,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1" rbitfld.long 0x0C 9. "CLKST,HSDIVIDER1 CLKOUT4 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x0C 0.--5. "DIVHS,DPLL (H14+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x10 "CM_SSC_DELTAMSTEP_DPLL_PER,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x10 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x14 "CM_SSC_MODFREQDIV_DPLL_PER,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x14 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "MODFREQDIV_EXPONENT_0,MODFREQDIV_EXPONENT_1,MODFREQDIV_EXPONENT_2,MODFREQDIV_EXPONENT_3,MODFREQDIV_EXPONENT_4,MODFREQDIV_EXPONENT_5,MODFREQDIV_EXPONENT_6,MODFREQDIV_EXPONENT_7" hexmask.long.byte 0x14 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0x80++0x13 line.long 0x00 "CM_CLKMODE_DPLL_USB,This register allows controlling the DPLL modes" bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_USB,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_USB,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - RESERVED6" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_USB,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "DPLL_SD_DIV,Sigma-Delta divider select (2-255)" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "DPLL_BYP_CLKSEL_0,DPLL_BYP_CLKSEL_1" newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" bitfld.long 0x0C 21. "DPLL_SELFREQDCO,select DCO output according to required frequency" "DPLL_SELFREQDCO_0,DPLL_SELFREQDCO_1" newline hexmask.long.word 0x0C 8.--19. 1. "DPLL_MULT,DPLL multiplier factor (2 to 4095)" hexmask.long.byte 0x0C 0.--7. 1. "DPLL_DIV,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_USB,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" hexmask.long.byte 0x10 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" group.long 0xA8++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_USB,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x00 0.--20. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_USB,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "MODFREQDIV_EXPONENT_0,MODFREQDIV_EXPONENT_1,MODFREQDIV_EXPONENT_2,MODFREQDIV_EXPONENT_3,MODFREQDIV_EXPONENT_4,MODFREQDIV_EXPONENT_5,MODFREQDIV_EXPONENT_6,MODFREQDIV_EXPONENT_7" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" rgroup.long 0xB4++0x03 line.long 0x00 "CM_CLKDCOLDO_DPLL_USB,This register provides status over CLKDCOLDO output of the DPLL" bitfld.long 0x00 9. "ST_DPLL_CLKDCOLDO,DPLL CLKDCOLDO status - CLK_GATED" "ST_DPLL_CLKDCOLDO_0,ST_DPLL_CLKDCOLDO_1" group.long 0x100++0x2B line.long 0x00 "CM_CLKMODE_DPLL_PCIE_REF,This register allows controlling the DPLL modes" bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_PCIE_REF,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_PCIE_REF,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - RESERVED6" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_PCIE_REF,This register provides controls over the DPLL" hexmask.long.byte 0x0C 24.--31. 1. "DPLL_SD_DIV,Sigma-Delta divider select (2-255)" rbitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "0,1" newline rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" bitfld.long 0x0C 21. "DPLL_SELFREQDCO,select DCO output according to required frequency" "DPLL_SELFREQDCO_0,DPLL_SELFREQDCO_1" newline hexmask.long.word 0x0C 8.--19. 1. "DPLL_MULT,DPLL multiplier factor (2 to 4095)" hexmask.long.byte 0x0C 0.--7. 1. "DPLL_DIV,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_PCIE_REF,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 10. "CLKLDOST,DPLL CLKOUTLDO status - CLK_GATED" "CLKLDOST_0,CLKLDOST_1" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" newline hexmask.long.byte 0x10 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" line.long 0x14 "CM_SSC_DELTAMSTEP_DPLL_PCIE_REF,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x14 0.--20. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x18 "CM_SSC_MODFREQDIV_DPLL_PCIE_REF,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x18 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x1C "CM_CLKMODE_APLL_PCIE,This register allows controlling the APLL modes" bitfld.long 0x1C 8. "CLKDIV_BYPASS,- PCIEDIVBY2_BYPASS_0" "CLKDIV_BYPASS_0,CLKDIV_BYPASS_1" bitfld.long 0x1C 7. "REFSEL,Select source of reference input clock - CLKREF_ADPLL" "REFSEL_0,REFSEL_1" newline rbitfld.long 0x1C 3.--5. "INPSEL,Reference clock is 100MHz" "0,1,2,3,4,5,6,7" rbitfld.long 0x1C 2. "MODE,APLLPCIE Mode Status - PCIE" "MODE_0,?" newline bitfld.long 0x1C 0.--1. "MODE_SELECT,Control APLL mode" "MODE_SELECT_0,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3" line.long 0x20 "CM_IDLEST_APLL_PCIE,This register allows monitoring APLL activity" bitfld.long 0x20 0. "ST_APLL_CLK,APLL lock status - APLL_UNLOCKED" "ST_APLL_CLK_0,ST_APLL_CLK_1" line.long 0x24 "CM_DIV_M2_APLL_PCIE,This register provides controls over the M2 divider of the DPLL" bitfld.long 0x24 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" hexmask.long.byte 0x24 0.--6. 1. "DIVHS,DPLL M2 post-divider factor (1 to 127)" line.long 0x28 "CM_CLKVCOLDO_APLL_PCIE,This register provides status over CLKVCOLDO and CLKVCOLDO_DIV outputs of the APLL" bitfld.long 0x28 10. "CLK_DIVST,APLL CLKVCOLDO_DIV status - CLK_GATED" "CLK_DIVST_0,CLK_DIVST_1" bitfld.long 0x28 9. "CLKST,APLL CLKVCOLDO status - CLK_GATED" "CLKST_0,CLKST_1" tree.end tree "CM_CORE__CORE" base ad:0x4A008700 group.long 0x00++0x03 line.long 0x00 "CM_L3MAIN1_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 9. "CLKACTIVITY_L3MAIN1_L4_GICLK,This field indicates the state of the L3MAIN1_L4_GICLK clock in the domain" "CLKACTIVITY_L3MAIN1_L4_GICLK_0,CLKACTIVITY_L3MAIN1_L4_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L3MAIN1_L3_GICLK,This field indicates the state of the L3MAIN1_L3_GICLK clock in the domain" "CLKACTIVITY_L3MAIN1_L3_GICLK_0,CLKACTIVITY_L3MAIN1_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3MAIN1 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x08++0x03 line.long 0x00 "CM_L3MAIN1_DYNAMICDEP,This register controls the dynamic domain depedencies from L3MAIN1 domain towards 'target' domains" rbitfld.long 0x00 29. "EVE2_DYNDEP,Dynamic dependency towards EVE2 clock domain - ENABLED" "?,EVE2_DYNDEP_1" newline rbitfld.long 0x00 28. "EVE1_DYNDEP,Dynamic dependency towards EVE1 clock domain - ENABLED" "?,EVE1_DYNDEP_1" newline bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 23. "L4PER3_DYNDEP,Dynamic dependency towards L4PER3 clock domain - ENABLED" "?,L4PER3_DYNDEP_1" newline rbitfld.long 0x00 22. "L4PER2_DYNDEP,Dynamic dependency towards L4PER2 clock domain - ENABLED" "?,L4PER2_DYNDEP_1" newline rbitfld.long 0x00 21. "PCIE_DYNDEP,Dynamic dependency towards PCIE clock domain - ENABLED" "?,PCIE_DYNDEP_1" newline rbitfld.long 0x00 20. "DSP2_DYNDEP,Dynamic dependency towards DSP2 clock domain - ENABLED" "?,DSP2_DYNDEP_1" newline rbitfld.long 0x00 18. "IPU1_DYNDEP,Dynamic dependency towards IPU1 clock domain - ENABLED" "?,IPU1_DYNDEP_1" newline rbitfld.long 0x00 15. "WKUPAON_DYNDEP,Dynamic dependency towards WKUPAON clock domain - ENABLED" "?,WKUPAON_DYNDEP_1" newline rbitfld.long 0x00 14. "L4SEC_DYNDEP,Dynamic dependency towards L4SEC clock domain - ENABLED" "?,L4SEC_DYNDEP_1" newline rbitfld.long 0x00 13. "L4PER_DYNDEP,Dynamic dependency towards L4PER1 clock domain - ENABLED" "?,L4PER_DYNDEP_1" newline rbitfld.long 0x00 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain - ENABLED" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x00 10. "GPU_DYNDEP,Dynamic dependency towards GPU clock domain - ENABLED" "?,GPU_DYNDEP_1" newline rbitfld.long 0x00 8. "DSS_DYNDEP,Dynamic dependency towards DSS clock domain - ENABLED" "?,DSS_DYNDEP_1" newline rbitfld.long 0x00 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain - ENABLED" "?,EMIF_DYNDEP_1" newline rbitfld.long 0x00 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain - ENABLED" "?,IPU_DYNDEP_1" newline rbitfld.long 0x00 2. "IVA_DYNDEP,Dynamic dependency towards IVA clock domain - ENABLED" "?,IVA_DYNDEP_1" newline rbitfld.long 0x00 1. "DSP1_DYNDEP,Dynamic dependency towards DSP1 clock domain - ENABLED" "?,DSP1_DYNDEP_1" newline rbitfld.long 0x00 0. "IPU2_DYNDEP,Dynamic dependency towards IPU2 clock domain - ENABLED" "?,IPU2_DYNDEP_1" rgroup.long 0x20++0x03 line.long 0x00 "CM_L3MAIN1_L3_MAIN_1_CLKCTRL,This register manages the L3_MAIN_1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x28++0x03 line.long 0x00 "CM_L3MAIN1_GPMC_CLKCTRL,This register manages the GPMC clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x30++0x03 line.long 0x00 "CM_L3MAIN1_MMU_EDMA_CLKCTRL,This register manages the MMU_L4_EDMA clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x48++0x03 line.long 0x00 "CM_L3MAIN1_MMU_PCIESS_CLKCTRL,This register manages the MMU_L4_PCIESS clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x50++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM1_CLKCTRL,This register manages the OCMC_RAM1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x58++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM2_CLKCTRL,This register manages the OCMC_RAM2 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x60++0x03 line.long 0x00 "CM_L3MAIN1_OCMC_RAM3_CLKCTRL,This register manages the OCMC_RAM3 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x70++0x03 line.long 0x00 "CM_L3MAIN1_TPCC_CLKCTRL,This register manages the TPCC clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x78++0x03 line.long 0x00 "CM_L3MAIN1_TPTC1_CLKCTRL,This register manages the TPTC1 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_L3MAIN1_TPTC2_CLKCTRL,This register manages the TPTC2 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x88++0x03 line.long 0x00 "CM_L3MAIN1_VCP1_CLKCTRL,This register manages the VCP1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x90++0x03 line.long 0x00 "CM_L3MAIN1_VCP2_CLKCTRL,This register manages the VCP2 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x200++0x0B line.long 0x00 "CM_IPU2_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_IPU2_GFCLK,This field indicates the state of the BELLNI1_GCLK clock in the domain" "CLKACTIVITY_IPU2_GFCLK_0,CLKACTIVITY_IPU2_GFCLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the BELLINI1 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IPU2_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains" bitfld.long 0x04 30. "ATL_STATDEP,Static dependency towards ATL clock domain - DISABLED" "ATL_STATDEP_0,ATL_STATDEP_1" newline bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards DMA clock domain - DISABLED" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" line.long 0x08 "CM_IPU2_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x08 9. "CAM_DYNDEP,Dynamic dependency towards CAM clock domain - DISABLED" "CAM_DYNDEP_0,?" newline rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" group.long 0x220++0x03 line.long 0x00 "CM_IPU2_IPU2_CLKCTRL,This register manages the IPU2 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x300++0x0B line.long 0x00 "CM_DMA_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_DMA_L3_GICLK,This field indicates the state of the DMA_L3_GICLK clock in the domain" "CLKACTIVITY_DMA_L3_GICLK_0,CLKACTIVITY_DMA_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DMA clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DMA_STATICDEP,This register controls the static domain depedencies from DMA domain towards 'target' domains" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,?" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain - DISABLED" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DMA_DYNAMICDEP,This register controls the dynamic domain depedencies from SDMA domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" rgroup.long 0x320++0x03 line.long 0x00 "CM_DMA_DMA_SYSTEM_CLKCTRL,This register manages the DMA_SYSTEM clocks" bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x400++0x03 line.long 0x00 "CM_EMIF_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 10. "CLKACTIVITY_EMIF_PHY_GCLK,This field indicates the state of the EMIF_PHY_GCLK clock in the domain" "CLKACTIVITY_EMIF_PHY_GCLK_0,CLKACTIVITY_EMIF_PHY_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_EMIF_DLL_GCLK,This field indicates the state of the DLL_GCLK clock in the domain" "CLKACTIVITY_EMIF_DLL_GCLK_0,CLKACTIVITY_EMIF_DLL_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_EMIF_L3_GICLK,This field indicates the state of the EMIF_L3_GICLK clock in the domain" "CLKACTIVITY_EMIF_L3_GICLK_0,CLKACTIVITY_EMIF_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the EMIF clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x420++0x03 line.long 0x00 "CM_EMIF_DMM_CLKCTRL,This register manages the DMM clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x428++0x03 line.long 0x00 "CM_EMIF_EMIF_OCP_FW_CLKCTRL,This register manages the EMIF_OCP_FW clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x430++0x03 line.long 0x00 "CM_EMIF_EMIF1_CLKCTRL,This register manages the EMIF1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x438++0x03 line.long 0x00 "CM_EMIF_EMIF2_CLKCTRL,This register manages the EMIF2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x440++0x03 line.long 0x00 "CM_EMIF_EMIF_DLL_CLKCTRL,This register manages the DLL clock" bitfld.long 0x00 8. "OPTFCLKEN_DLL_CLK,Optional functional clock control" "OPTFCLKEN_DLL_CLK_0,OPTFCLKEN_DLL_CLK_1" group.long 0x500++0x03 line.long 0x00 "CM_ATL_ATL_CLKCTRL,This register manages the ATL clocks" bitfld.long 0x00 26.--27. "CLKSEL_SOURCE2,Selects source for ATL clock - SEL_L3_ICLK" "CLKSEL_SOURCE2_0,CLKSEL_SOURCE2_1,CLKSEL_SOURCE2_2,CLKSEL_SOURCE2_3" newline bitfld.long 0x00 24.--25. "CLKSEL_SOURCE1,Selects source for ATL clock - SEL_FUNC_32K_CLK" "CLKSEL_SOURCE1_0,CLKSEL_SOURCE1_1,CLKSEL_SOURCE1_2,CLKSEL_SOURCE1_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x520++0x03 line.long 0x00 "CM_ATL_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 9. "CLKACTIVITY_ATL_GFCLK,This field indicates the state of the ATL_GFCLK clock in the domain" "CLKACTIVITY_ATL_GFCLK_0,CLKACTIVITY_ATL_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_ATL_L3_GICLK,This field indicates the state of the ATL_L3_GICLK clock in the domain" "CLKACTIVITY_ATL_L3_GICLK_0,CLKACTIVITY_ATL_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the C2C clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x600++0x03 line.long 0x00 "CM_L4CFG_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 9. "CLKACTIVITY_L4CFG_L3_GICLK,This field indicates the state of the L4CFG_L3_GICLK clock in the domain" "CLKACTIVITY_L4CFG_L3_GICLK_0,CLKACTIVITY_L4CFG_L3_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L4CFG_L4_GICLK,This field indicates the state of the L4CFG_L4_GICLK clock in the domain" "CLKACTIVITY_L4CFG_L4_GICLK_0,CLKACTIVITY_L4CFG_L4_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4CFG clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x608++0x03 line.long 0x00 "CM_L4CFG_DYNAMICDEP,This register controls the dynamic domain depedencies from L4CFG domain towards 'target' domains" bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "WINDOWSIZE_0,WINDOWSIZE_1,WINDOWSIZE_2,WINDOWSIZE_3,WINDOWSIZE_4,WINDOWSIZE_5,WINDOWSIZE_6,WINDOWSIZE_7,WINDOWSIZE_8,WINDOWSIZE_9,WINDOWSIZE_10,WINDOWSIZE_11,WINDOWSIZE_12,WINDOWSIZE_13,WINDOWSIZE_14,WINDOWSIZE_15" newline rbitfld.long 0x00 19. "MPU_DYNDEP,Dynamic dependency towards MPU clock domain - ENABLED" "?,MPU_DYNDEP_1" newline rbitfld.long 0x00 17. "CUSTEFUSE_DYNDEP,Dynamic dependency towards CUSTEFUSE clock domain - ENABLED" "?,CUSTEFUSE_DYNDEP_1" newline rbitfld.long 0x00 16. "COREAON_DYNDEP,Dynamic dependency towards COREAON clock domain - ENABLED" "?,COREAON_DYNDEP_1" newline rbitfld.long 0x00 11. "SDMA_DYNDEP,Dynamic dependency towards DMA clock domain - ENABLED" "?,SDMA_DYNDEP_1" newline rbitfld.long 0x00 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain - ENABLED" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x00 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x00 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain - ENABLED" "?,EMIF_DYNDEP_1" rgroup.long 0x620++0x03 line.long 0x00 "CM_L4CFG_L4_CFG_CLKCTRL,This register manages the L4_CFG clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x628++0x03 line.long 0x00 "CM_L4CFG_SPINLOCK_CLKCTRL,This register manages the SPINLOCK clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x630++0x03 line.long 0x00 "CM_L4CFG_MAILBOX1_CLKCTRL,This register manages the MAILBOX1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x638++0x03 line.long 0x00 "CM_L4CFG_SAR_ROM_CLKCTRL,This register manages the SAR_ROM clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x640++0x03 line.long 0x00 "CM_L4CFG_OCP2SCP2_CLKCTRL,This register manages the OCP2SCP2 clocks and the optional clock of USB PHY" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x648++0x03 line.long 0x00 "CM_L4CFG_MAILBOX2_CLKCTRL,This register manages the MAILBOX2 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x650++0x03 line.long 0x00 "CM_L4CFG_MAILBOX3_CLKCTRL,This register manages the MAILBOX3 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x658++0x03 line.long 0x00 "CM_L4CFG_MAILBOX4_CLKCTRL,This register manages the MAILBOX4 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x660++0x03 line.long 0x00 "CM_L4CFG_MAILBOX5_CLKCTRL,This register manages the MAILBOX5 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x668++0x03 line.long 0x00 "CM_L4CFG_MAILBOX6_CLKCTRL,This register manages the MAILBOX6 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x670++0x03 line.long 0x00 "CM_L4CFG_MAILBOX7_CLKCTRL,This register manages the MAILBOX7 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x678++0x03 line.long 0x00 "CM_L4CFG_MAILBOX8_CLKCTRL,This register manages the MAILBOX8 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x680++0x03 line.long 0x00 "CM_L4CFG_MAILBOX9_CLKCTRL,This register manages the MAILBOX9 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x688++0x03 line.long 0x00 "CM_L4CFG_MAILBOX10_CLKCTRL,This register manages the MAILBOX10 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x690++0x03 line.long 0x00 "CM_L4CFG_MAILBOX11_CLKCTRL,This register manages the MAILBOX11 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x698++0x03 line.long 0x00 "CM_L4CFG_MAILBOX12_CLKCTRL,This register manages the MAILBOX12 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x6A0++0x03 line.long 0x00 "CM_L4CFG_MAILBOX13_CLKCTRL,This register manages the MAILBOX13 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x700++0x03 line.long 0x00 "CM_L3INSTR_CLKSTCTRL,This register enables the domain power state transition" bitfld.long 0x00 10. "CLKACTIVITY_L3INSTR_TS_GCLK,This field indicates the state of the L3INSTR_TS_GCLK clock in the domain" "CLKACTIVITY_L3INSTR_TS_GCLK_0,CLKACTIVITY_L3INSTR_TS_GCLK_1" newline bitfld.long 0x00 9. "CLKACTIVITY_L3INSTR_DLL_AGING_GCLK,This field indicates the state of the L3INSTR_DLL_AGING_GCLK clock in the domain" "CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_0,CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_1" newline bitfld.long 0x00 8. "CLKACTIVITY_L3INSTR_L3_GICLK,This field indicates the state of the L3INSTR_L3_GICLK clock in the domain" "CLKACTIVITY_L3INSTR_L3_GICLK_0,CLKACTIVITY_L3INSTR_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INSTR clock domain" "?,?,?,CLKTRCTRL_3" group.long 0x720++0x03 line.long 0x00 "CM_L3INSTR_L3_MAIN_2_CLKCTRL,This register manages the L3_MAIN_2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x728++0x03 line.long 0x00 "CM_L3INSTR_L3_INSTR_CLKCTRL,This register manages the L3 INSTRUMENTATION clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x740++0x03 line.long 0x00 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL,This register manages the OCP_WP_NOC clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x748++0x03 line.long 0x00 "CM_L3INSTR_DLL_AGING_CLKCTRL,This register manages the DLL_AGING clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x750++0x03 line.long 0x00 "CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,This register manages the CTRL_MODULE_BANDGAP clock" bitfld.long 0x00 24.--25. "CLKSEL,Selects the divider value for generating the Thermal Sensor clock from WKUPAON_ICLK source" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline rbitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" tree.end tree "CM_CORE__COREAON" base ad:0x4A008600 group.long 0x00++0x03 line.long 0x00 "CM_COREAON_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 16. "CLKACTIVITY_ABE_GICLK,This field indicates the state of the ABE_GICLK clock input of the domain" "CLKACTIVITY_ABE_GICLK_0,CLKACTIVITY_ABE_GICLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_SR_IVAHD_SYS_GFCLK,This field indicates the state of the SR_IVAHD_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_IVAHD_SYS_GFCLK_0,CLKACTIVITY_SR_IVAHD_SYS_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_SR_DSPEVE_SYS_GFCLK,This field indicates the state of the SR_DSPEVE_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_0,CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_COREAON_32K_GFCLK,This field indicates the state of the COREAON_32K_GFCLK clock in the domain" "CLKACTIVITY_COREAON_32K_GFCLK_0,CLKACTIVITY_COREAON_32K_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_SR_CORE_SYS_GFCLK,This field indicates the state of the SR_CORE_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_CORE_SYS_GFCLK_0,CLKACTIVITY_SR_CORE_SYS_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_SR_GPU_SYS_GFCLK,This field indicates the state of the SR_GPU_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_GPU_SYS_GFCLK_0,CLKACTIVITY_SR_GPU_SYS_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_SR_MPU_SYS_GFCLK,This field indicates the state of the SR_MPU_SYS_GFCLK clock input of the domain" "CLKACTIVITY_SR_MPU_SYS_GFCLK_0,CLKACTIVITY_SR_MPU_SYS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_COREAON_L4_GICLK,This field indicates the state of the COREAON_L4_GICLK clock of the domain" "CLKACTIVITY_COREAON_L4_GICLK_0,CLKACTIVITY_COREAON_L4_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the COREAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x28++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,This register manages the SR_MPU clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,This register manages the SR_CORE clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_COREAON_USB_PHY1_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" group.long 0x58++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_GPU_CLKCTRL,This register manages the SR_GPU clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL,This register manages the SR_DSPEVE clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL,This register manages the SR_IVAHD clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_COREAON_USB_PHY2_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" group.long 0x98++0x03 line.long 0x00 "CM_COREAON_USB_PHY3_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,Optional functional clock control" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" tree.end tree "CM_CORE__CUSTEFUSE" base ad:0x4A009600 group.long 0x00++0x03 line.long 0x00 "CM_CUSTEFUSE_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 9. "CLKACTIVITY_CUSTEFUSE_SYS_GFCLK,This field indicates the state of the CUSTEFUSE_SYS_CLK clock input of the domain" "CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_0,CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_CUSTEFUSE_L4_GICLK,This field indicates the state of the L4_CUSTEFUSE_GICLK clock input of the domain" "CLKACTIVITY_CUSTEFUSE_L4_GICLK_0,CLKACTIVITY_CUSTEFUSE_L4_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the CUSTEFUSE clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x20++0x03 line.long 0x00 "CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL,This register manages the CUSTEFUSE clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE__DSS" base ad:0x4A009100 group.long 0x00++0x0B line.long 0x00 "CM_DSS_CLKSTCTRL,This register enables the DSS domain power state transition" rbitfld.long 0x00 18. "CLKACTIVITY_HDMI_PHY_GFCLK,This field indicates the state of the HDMI_PHY_GFCLK clock in the domain" "CLKACTIVITY_HDMI_PHY_GFCLK_0,CLKACTIVITY_HDMI_PHY_GFCLK_1" rbitfld.long 0x00 17. "CLKACTIVITY_HDMI_CEC_GFCLK,This field indicates the state of the HDMI_CEC_GFCLK clock in the domain" "CLKACTIVITY_HDMI_CEC_GFCLK_0,CLKACTIVITY_HDMI_CEC_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_DSS_L4_GICLK,This field indicates the state of the DSS_L4_GICLK clock in the domain" "CLKACTIVITY_DSS_L4_GICLK_0,CLKACTIVITY_DSS_L4_GICLK_1" rbitfld.long 0x00 13. "CLKACTIVITY_BB2D_GFCLK,This field indicates the state of the BB2D_GFCLK clock in the domain" "CLKACTIVITY_BB2D_GFCLK_0,CLKACTIVITY_BB2D_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_VIDEO2_DPLL_CLK,This field indicates the state of the VIDEO2_DPLL_CLK clock in the domain" "CLKACTIVITY_VIDEO2_DPLL_CLK_0,CLKACTIVITY_VIDEO2_DPLL_CLK_1" rbitfld.long 0x00 11. "CLKACTIVITY_HDMI_DPLL_CLK,This field indicates the state of the HDMI_DPLL_CLK clock in the domain" "CLKACTIVITY_HDMI_DPLL_CLK_0,CLKACTIVITY_HDMI_DPLL_CLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_VIDEO1_DPLL_CLK,This field indicates the state of the VIDEO1_DPLL_CLK clock in the domain" "CLKACTIVITY_VIDEO1_DPLL_CLK_0,CLKACTIVITY_VIDEO1_DPLL_CLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_DSS_GFCLK,This field indicates the state of the DSS_GFCLK clock in the domain" "CLKACTIVITY_DSS_GFCLK_0,CLKACTIVITY_DSS_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_DSS_L3_GICLK,This field indicates the state of the DSS_L3_GICLK clock in the domain" "CLKACTIVITY_DSS_L3_GICLK_0,CLKACTIVITY_DSS_L3_GICLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSS clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSS_STATICDEP,This register controls the static domain depedencies from DSS domain towards 'target' domains" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" line.long 0x08 "CM_DSS_DYNAMICDEP,This register controls the dynamic domain depedencies from DSS domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x20++0x03 line.long 0x00 "CM_DSS_DSS_CLKCTRL,This register manages the DSS clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 13. "OPTFCLKEN_VIDEO2_CLK,Optional functional clock control" "OPTFCLKEN_VIDEO2_CLK_0,OPTFCLKEN_VIDEO2_CLK_1" bitfld.long 0x00 12. "OPTFCLKEN_VIDEO1_CLK,Optional functional clock control" "OPTFCLKEN_VIDEO1_CLK_0,OPTFCLKEN_VIDEO1_CLK_1" newline bitfld.long 0x00 11. "OPTFCLKEN_32KHZ_CLK,Optional functional clock control" "OPTFCLKEN_32KHZ_CLK_0,OPTFCLKEN_32KHZ_CLK_1" bitfld.long 0x00 10. "OPTFCLKEN_HDMI_CLK,Optional functional clock control" "OPTFCLKEN_HDMI_CLK_0,OPTFCLKEN_HDMI_CLK_1" newline bitfld.long 0x00 9. "OPTFCLKEN_48MHZ_CLK,Optional functional clock control" "OPTFCLKEN_48MHZ_CLK_0,OPTFCLKEN_48MHZ_CLK_1" bitfld.long 0x00 8. "OPTFCLKEN_DSSCLK,Optional functional clock control" "OPTFCLKEN_DSSCLK_0,OPTFCLKEN_DSSCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_DSS_BB2D_CLKCTRL,This register manages the BB2D clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE__GPU" base ad:0x4A009200 group.long 0x00++0x0B line.long 0x00 "CM_GPU_CLKSTCTRL,This register enables the GPU domain power state transition" rbitfld.long 0x00 10. "CLKACTIVITY_GPU_HYD_GCLK,This field indicates the state of the GPU_HYD_GCLK clock in the domain" "CLKACTIVITY_GPU_HYD_GCLK_0,CLKACTIVITY_GPU_HYD_GCLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_GPU_CORE_GCLK,This field indicates the state of the GPU_CORE_GCLK clock in the domain" "CLKACTIVITY_GPU_CORE_GCLK_0,CLKACTIVITY_GPU_CORE_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_GPU_L3_GICLK,This field indicates the state of the GPU_L3_GICLK clock in the domain" "CLKACTIVITY_GPU_L3_GICLK_0,CLKACTIVITY_GPU_L3_GICLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the GPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_GPU_STATICDEP,This register controls the static domain depedencies from GPU domain towards 'target' domains" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" line.long 0x08 "CM_GPU_DYNAMICDEP,This register controls the dynamic domain depedencies from GPU domain towards 'target' domains" bitfld.long 0x08 6. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x20++0x03 line.long 0x00 "CM_GPU_GPU_CLKCTRL,This register manages the GPU clocks" bitfld.long 0x00 26.--27. "CLKSEL_HYD_CLK,Select the source of the functional clock - SEL_CORE_GPU_CLK" "CLKSEL_HYD_CLK_0,CLKSEL_HYD_CLK_1,CLKSEL_HYD_CLK_2,CLKSEL_HYD_CLK_3" bitfld.long 0x00 24.--25. "CLKSEL_CORE_CLK,Select the source of the functional clock - SEL_CORE_GPU_CLK" "CLKSEL_CORE_CLK_0,CLKSEL_CORE_CLK_1,CLKSEL_CORE_CLK_2,CLKSEL_CORE_CLK_3" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE__IVA" base ad:0x4A008F00 group.long 0x00++0x0B line.long 0x00 "CM_IVA_CLKSTCTRL,This register enables the IVA domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_IVA_GCLK,This field indicates the state of the IVA_ROOT_CLK clock input of the domain" "CLKACTIVITY_IVA_GCLK_0,CLKACTIVITY_IVA_GCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the IVA clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IVA_STATICDEP,This register controls the static domain depedencies from IVA domain towards 'target' domains" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" line.long 0x08 "CM_IVA_DYNAMICDEP,This register controls the dynamic domain depedencies from IVA domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x20++0x03 line.long 0x00 "CM_IVA_IVA_CLKCTRL,This register manages the IVA clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x28++0x03 line.long 0x00 "CM_IVA_SL2_CLKCTRL,This register manages the SL2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE__L3INIT" base ad:0x4A009300 group.long 0x00++0x0B line.long 0x00 "CM_L3INIT_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 24. "CLKACTIVITY_SATA_REF_GFCLK,This field indicates the state of the SATA_REF_GFCLK clock in the domain" "CLKACTIVITY_SATA_REF_GFCLK_0,CLKACTIVITY_SATA_REF_GFCLK_1" newline rbitfld.long 0x00 23. "CLKACTIVITY_L3INIT_32K_GFCLK,This field indicates the state of the L3INIT_32K_FCLK clock in the domain" "CLKACTIVITY_L3INIT_32K_GFCLK_0,CLKACTIVITY_L3INIT_32K_GFCLK_1" newline rbitfld.long 0x00 22. "CLKACTIVITY_L3INIT_960M_GFCLK,This field indicates the state of the L3INIT_960M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_960M_GFCLK_0,CLKACTIVITY_L3INIT_960M_GFCLK_1" newline rbitfld.long 0x00 21. "CLKACTIVITY_L3INIT_480M_GFCLK,This field indicates the state of the L3INIT_480M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_480M_GFCLK_0,CLKACTIVITY_L3INIT_480M_GFCLK_1" newline rbitfld.long 0x00 20. "CLKACTIVITY_USB_OTG_SS_REF_CLK,This field indicates the state of the USB_OTG_SS_REF_CLK clock in the domain" "CLKACTIVITY_USB_OTG_SS_REF_CLK_0,CLKACTIVITY_USB_OTG_SS_REF_CLK_1" newline rbitfld.long 0x00 19. "CLKACTIVITY_MLB_SYS_L3_GFCLK,This field indicates the state of the MLB_SYS_L3_GFCLK clock in the domain" "CLKACTIVITY_MLB_SYS_L3_GFCLK_0,CLKACTIVITY_MLB_SYS_L3_GFCLK_1" newline rbitfld.long 0x00 18. "CLKACTIVITY_MLB_SPB_L4_GICLK,This field indicates the state of the MLB_SPB_L4_GICLK clock in the domain" "CLKACTIVITY_MLB_SPB_L4_GICLK_0,CLKACTIVITY_MLB_SPB_L4_GICLK_1" newline rbitfld.long 0x00 17. "CLKACTIVITY_MLB_SHB_L3_GICLK,This field indicates the state of the MLB_SHB_L3_GICLK clock in the domain" "CLKACTIVITY_MLB_SHB_L3_GICLK_0,CLKACTIVITY_MLB_SHB_L3_GICLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_MMC2_GFCLK,This field indicates the state of the MMC2 clock in the domain" "CLKACTIVITY_MMC2_GFCLK_0,CLKACTIVITY_MMC2_GFCLK_1" newline rbitfld.long 0x00 15. "CLKACTIVITY_MMC1_GFCLK,This field indicates the state of the MMC1_GFCLK clock in the domain" "CLKACTIVITY_MMC1_GFCLK_0,CLKACTIVITY_MMC1_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_USB_DPLL_HS_CLK,This field indicates the state of the USB_DPLL_HS_CLK clock in the domain" "CLKACTIVITY_USB_DPLL_HS_CLK_0,CLKACTIVITY_USB_DPLL_HS_CLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_USB_DPLL_CLK,This field indicates the state of the USB_DPLL_CLK clock in the domain" "CLKACTIVITY_USB_DPLL_CLK_0,CLKACTIVITY_USB_DPLL_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_L3INIT_48M_GFCLK,This field indicates the state of the INIT_48M_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_48M_GFCLK_0,CLKACTIVITY_L3INIT_48M_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK,This field indicates the state of the L3INIT_USB_LFPS_TX_GFCLK clock in the domain" "CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_0,CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_L3INIT_L4_GICLK,This field indicates the state of the L3INIT_L4_GICLK clock in the domain" "CLKACTIVITY_L3INIT_L4_GICLK_0,CLKACTIVITY_L3INIT_L4_GICLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L3INIT_L3_GICLK,This field indicates the state of the L3INIT_L3_GICLK clock in the domain" "CLKACTIVITY_L3INIT_L3_GICLK_0,CLKACTIVITY_L3INIT_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INIT clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_L3INIT_STATICDEP,This register controls the static domain depedencies from L3INIT domain towards 'target' domains" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" line.long 0x08 "CM_L3INIT_DYNAMICDEP,This register controls the dynamic domain depedencies from L3INIT domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x28++0x03 line.long 0x00 "CM_L3INIT_MMC1_CLKCTRL,This register manages the MMC1 clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,MMC1 clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK - FCLK_DIS" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_L3INIT_MMC2_CLKCTRL,This register manages the MMC2 clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,MMC2 clock divide ratio - DIV1" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" newline bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK - FCLK_DIS" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS2_CLKCTRL,This register manages the USB_OTG_SS2 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_REFCLK960M,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock) - FCLK_DIS" "OPTFCLKEN_REFCLK960M_0,OPTFCLKEN_REFCLK960M_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x48++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS3_CLKCTRL,This register manages the USB_OTG_SS3 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x50++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS4_CLKCTRL,This register manages the USB_OTG_SS4 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x58++0x03 line.long 0x00 "CM_L3INIT_MLB_SS_CLKCTRL,This register manages the MLBSS clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x78++0x03 line.long 0x00 "CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,This register manages the IEE1500_2_OCP clocks" bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x88++0x03 line.long 0x00 "CM_L3INIT_SATA_CLKCTRL,This register manages the SATA clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_REF_CLK,SATA optional clock control: REF_CLK (from SYS_CLK clock) - FCLK_DIS" "OPTFCLKEN_REF_CLK_0,OPTFCLKEN_REF_CLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x07 line.long 0x00 "CM_PCIE_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 13. "CLKACTIVITY_PCIE_32K_GFCLK,This field indicates the state of the PCIE_32K_GFCLK clock in the domain" "CLKACTIVITY_PCIE_32K_GFCLK_0,CLKACTIVITY_PCIE_32K_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_PCIE_SYS_GFCLK,This field indicates the state of the PCIE_SYS_GFCLK clock in the domain" "CLKACTIVITY_PCIE_SYS_GFCLK_0,CLKACTIVITY_PCIE_SYS_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_PCIE_REF_GFCLK,This field indicates the state of the PCIE_REF_GFCLK clock in the domain" "CLKACTIVITY_PCIE_REF_GFCLK_0,CLKACTIVITY_PCIE_REF_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_PCIE_PHY_DIV_GCLK,This field indicates the state of the PCIE_PHY_DIV_GCLK clock in the domain" "CLKACTIVITY_PCIE_PHY_DIV_GCLK_0,CLKACTIVITY_PCIE_PHY_DIV_GCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_PCIE_PHY_GCLK,This field indicates the state of the PCIE_PHY_GCLK clock in the domain" "CLKACTIVITY_PCIE_PHY_GCLK_0,CLKACTIVITY_PCIE_PHY_GCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_PCIE_L3_GICLK,This field indicates the state of the PCIE_L3_GICLK clock in the domain" "CLKACTIVITY_PCIE_L3_GICLK_0,CLKACTIVITY_PCIE_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L3INIT clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_PCIE_STATICDEP,This register controls the static domain depedencies from PCIE domain towards 'target' domains" bitfld.long 0x04 30. "ATL_STATDEP,Static dependency towards ATL clock domain - DISABLED" "ATL_STATDEP_0,ATL_STATDEP_1" newline bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards SDMA clock domain - DISABLED" "SDMA_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,CAM_STATDEP_1" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" group.long 0xB0++0x03 line.long 0x00 "CM_PCIE_PCIESS1_CLKCTRL,This register manages the PCESS1 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 10. "OPTFCLKEN_PCIEPHY_CLK_DIV,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_PCIEPHY_CLK_DIV_0,OPTFCLKEN_PCIEPHY_CLK_DIV_1" newline bitfld.long 0x00 9. "OPTFCLKEN_PCIEPHY_CLK,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_PCIEPHY_CLK_0,OPTFCLKEN_PCIEPHY_CLK_1" newline bitfld.long 0x00 8. "OPTFCLKEN_32KHZ,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_32KHZ_0,OPTFCLKEN_32KHZ_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB8++0x03 line.long 0x00 "CM_PCIE_PCIESS2_CLKCTRL,This register manages the PCESS2 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 10. "OPTFCLKEN_PCIEPHY_CLK_DIV,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_PCIEPHY_CLK_DIV_0,OPTFCLKEN_PCIEPHY_CLK_DIV_1" newline bitfld.long 0x00 9. "OPTFCLKEN_PCIEPHY_CLK,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_PCIEPHY_CLK_0,OPTFCLKEN_PCIEPHY_CLK_1" newline bitfld.long 0x00 8. "OPTFCLKEN_32KHZ,PCIE PHY optional clock control - FCLK_DIS" "OPTFCLKEN_32KHZ_0,OPTFCLKEN_32KHZ_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xC0++0x0B line.long 0x00 "CM_GMAC_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 12. "CLKACTIVITY_GMAC_MAIN_CLK,This field indicates the state of the GMAC_MAIN_CLK clock in the domain" "CLKACTIVITY_GMAC_MAIN_CLK_0,CLKACTIVITY_GMAC_MAIN_CLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_GMAC_RFT_CLK,This field indicates the state of the GMAC_RFT_CLK clock in the domain" "CLKACTIVITY_GMAC_RFT_CLK_0,CLKACTIVITY_GMAC_RFT_CLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_RMII_50MHZ_CLK,This field indicates the state of the RMII_50MHZ_CLK clock in the domain" "CLKACTIVITY_RMII_50MHZ_CLK_0,CLKACTIVITY_RMII_50MHZ_CLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_RGMII_5MHZ_CLK,This field indicates the state of the RGMII_5MHZ_CLK clock in the domain" "CLKACTIVITY_RGMII_5MHZ_CLK_0,CLKACTIVITY_RGMII_5MHZ_CLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_GMII_250MHZ_CLK,This field indicates the state of the GMII_250MHZ_CLK clock in the domain" "CLKACTIVITY_GMII_250MHZ_CLK_0,CLKACTIVITY_GMII_250MHZ_CLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the GMAC clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_GMAC_STATICDEP,This register controls the static domain depedencies from GMAC domain towards 'target' domains" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" line.long 0x08 "CM_GMAC_DYNAMICDEP,This register controls the dynamic domain depedencies from GMAC domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0xD0++0x03 line.long 0x00 "CM_GMAC_GMAC_CLKCTRL,This register manages the GMAC clocks" bitfld.long 0x00 25.--27. "CLKSEL_RFT,Selects the source of the CPTS_RFT_CLK" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 24. "CLKSEL_REF,Selects the source of the functional clock" "CLKSEL_REF_0,CLKSEL_REF_1" newline rbitfld.long 0x00 18. "STBYST,odule standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,odule idle status" "0,1,2,3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "0,1,2,3" group.long 0xE0++0x03 line.long 0x00 "CM_L3INIT_OCP2SCP1_CLKCTRL,This register manages the OCP2SCP1 clocks and the optional clock of USB PHY" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xE8++0x03 line.long 0x00 "CM_L3INIT_OCP2SCP3_CLKCTRL,This register manages the OCP2SCP3 clocks and the optional clock of USB PHY" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_L3INIT_USB_OTG_SS1_CLKCTRL,This register manages the USB_OTG_SS1 clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 8. "OPTFCLKEN_REFCLK960M,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock) - FCLK_DIS" "OPTFCLKEN_REFCLK960M_0,OPTFCLKEN_REFCLK960M_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE__L4PER" base ad:0x4A009700 group.long 0x00++0x03 line.long 0x00 "CM_L4PER_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 27. "CLKACTIVITY_L4PER_32K_GFCLK,This field indicates the state of the L4PER_32K_FCLK clock in the domain" "CLKACTIVITY_L4PER_32K_GFCLK_0,CLKACTIVITY_L4PER_32K_GFCLK_1" rbitfld.long 0x00 26. "CLKACTIVITY_UART5_GFCLK,This field indicates the state of the UART5_GFCLK clock in the domain" "CLKACTIVITY_UART5_GFCLK_0,CLKACTIVITY_UART5_GFCLK_1" newline rbitfld.long 0x00 24. "CLKACTIVITY_GPIO_GFCLK,This field indicates the state of the GPIO_GFCLK clock in the domain" "CLKACTIVITY_GPIO_GFCLK_0,CLKACTIVITY_GPIO_GFCLK_1" rbitfld.long 0x00 23. "CLKACTIVITY_MMC4_GFCLK,This field indicates the state of the MMC4_GFCLK clock in the domain" "CLKACTIVITY_MMC4_GFCLK_0,CLKACTIVITY_MMC4_GFCLK_1" newline rbitfld.long 0x00 22. "CLKACTIVITY_MMC3_GFCLK,This field indicates the state of the MMC3_GFCLK clock in the domain" "CLKACTIVITY_MMC3_GFCLK_0,CLKACTIVITY_MMC3_GFCLK_1" rbitfld.long 0x00 21. "CLKACTIVITY_PER_96M_GFCLK,This field indicates the state of the PER_96M_GFCLK clock in the domain" "CLKACTIVITY_PER_96M_GFCLK_0,CLKACTIVITY_PER_96M_GFCLK_1" newline rbitfld.long 0x00 20. "CLKACTIVITY_PER_48M_GFCLK,This field indicates the state of the PER_48M_GFCLK clock in the domain" "CLKACTIVITY_PER_48M_GFCLK_0,CLKACTIVITY_PER_48M_GFCLK_1" rbitfld.long 0x00 19. "CLKACTIVITY_PER_12M_GFCLK,This field indicates the state of the PER_12M_GFCLK clock in the domain" "CLKACTIVITY_PER_12M_GFCLK_0,CLKACTIVITY_PER_12M_GFCLK_1" newline rbitfld.long 0x00 18. "CLKACTIVITY_UART4_GFCLK,This field indicates the state of the UART4_GFCLK clock in the domain" "CLKACTIVITY_UART4_GFCLK_0,CLKACTIVITY_UART4_GFCLK_1" rbitfld.long 0x00 17. "CLKACTIVITY_UART3_GFCLK,This field indicates the state of the UART3_GFCLK clock in the domain" "CLKACTIVITY_UART3_GFCLK_0,CLKACTIVITY_UART3_GFCLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_UART2_GFCLK,This field indicates the state of the UART2_GFCLK clock in the domain" "CLKACTIVITY_UART2_GFCLK_0,CLKACTIVITY_UART2_GFCLK_1" rbitfld.long 0x00 15. "CLKACTIVITY_UART1_GFCLK,This field indicates the state of the UART1_GFCLK clock in the domain" "CLKACTIVITY_UART1_GFCLK_0,CLKACTIVITY_UART1_GFCLK_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_TIMER9_GFCLK,This field indicates the state of the DMT9_GFCLK clock in the domain" "CLKACTIVITY_TIMER9_GFCLK_0,CLKACTIVITY_TIMER9_GFCLK_1" rbitfld.long 0x00 13. "CLKACTIVITY_TIMER4_GFCLK,This field indicates the state of the DMT4_GFCLK clock in the domain" "CLKACTIVITY_TIMER4_GFCLK_0,CLKACTIVITY_TIMER4_GFCLK_1" newline rbitfld.long 0x00 12. "CLKACTIVITY_TIMER3_GFCLK,This field indicates the state of the DMT3_GFCLK clock in the domain" "CLKACTIVITY_TIMER3_GFCLK_0,CLKACTIVITY_TIMER3_GFCLK_1" rbitfld.long 0x00 11. "CLKACTIVITY_TIMER2_GFCLK,This field indicates the state of the DMT2_GFCLK clock in the domain" "CLKACTIVITY_TIMER2_GFCLK_0,CLKACTIVITY_TIMER2_GFCLK_1" newline rbitfld.long 0x00 10. "CLKACTIVITY_TIMER11_GFCLK,This field indicates the state of the DMT11_GFCLK clock in the domain" "CLKACTIVITY_TIMER11_GFCLK_0,CLKACTIVITY_TIMER11_GFCLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_TIMER10_GFCLK,This field indicates the state of the DMT10_GFCLK clock in the domain" "CLKACTIVITY_TIMER10_GFCLK_0,CLKACTIVITY_TIMER10_GFCLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_L4PER_L3_GICLK,This field indicates the state of the L4PER_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER_L3_GICLK_0,CLKACTIVITY_L4PER_L3_GICLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x08++0x07 line.long 0x00 "CM_L4PER_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER domain towards 'target' domains" bitfld.long 0x00 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "WINDOWSIZE_0,WINDOWSIZE_1,WINDOWSIZE_2,WINDOWSIZE_3,WINDOWSIZE_4,WINDOWSIZE_5,WINDOWSIZE_6,WINDOWSIZE_7,WINDOWSIZE_8,WINDOWSIZE_9,WINDOWSIZE_10,WINDOWSIZE_11,WINDOWSIZE_12,WINDOWSIZE_13,WINDOWSIZE_14,WINDOWSIZE_15" rbitfld.long 0x00 14. "L4SEC_DYNDEP,Dynamic dependency towards L4SEC clock domain - ENABLED" "?,L4SEC_DYNDEP_1" newline rbitfld.long 0x00 8. "DSS_DYNDEP,Dynamic dependency towards DSS clock domain - ENABLED" "?,DSS_DYNDEP_1" rbitfld.long 0x00 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain - ENABLED" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x00 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain - ENABLED" "?,IPU_DYNDEP_1" line.long 0x04 "CM_L4PER2_L4_PER2_CLKCTRL,This register manages the L4_PER2 clocks" bitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x14++0x03 line.long 0x00 "CM_L4PER3_L4_PER3_CLKCTRL,This register manages the L4_PER3 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x28++0x03 line.long 0x00 "CM_L4PER_TIMER10_CLKCTRL,This register manages the TIMER10 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x30++0x03 line.long 0x00 "CM_L4PER_TIMER11_CLKCTRL,This register manages the TIMER11 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_L4PER_TIMER2_CLKCTRL,This register manages the TIMER2 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_L4PER_TIMER3_CLKCTRL,This register manages the TIMER3 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x48++0x03 line.long 0x00 "CM_L4PER_TIMER4_CLKCTRL,This register manages the TIMER4 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x50++0x03 line.long 0x00 "CM_L4PER_TIMER9_CLKCTRL,This register manages the TIMER9 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x58++0x03 line.long 0x00 "CM_L4PER_ELM_CLKCTRL,This register manages the ELM clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x60++0x03 line.long 0x00 "CM_L4PER_GPIO2_CLKCTRL,This register manages the GPIO2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_L4PER_GPIO3_CLKCTRL,This register manages the GPIO3 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x70++0x03 line.long 0x00 "CM_L4PER_GPIO4_CLKCTRL,This register manages the GPIO4 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_L4PER_GPIO5_CLKCTRL,This register manages the GPIO5 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_L4PER_GPIO6_CLKCTRL,This register manages the GPIO6 clocks" rbitfld.long 0x00 16.--17. "IDLEST,odule idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_L4PER_HDQ1W_CLKCTRL,This register manages the HDQ1W clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x90++0x03 line.long 0x00 "CM_L4PER2_PWMSS2_CLKCTRL,This register manages the PWMSS1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x98++0x03 line.long 0x00 "CM_L4PER2_PWMSS3_CLKCTRL,This register manages the PWMSS2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA0++0x03 line.long 0x00 "CM_L4PER_I2C1_CLKCTRL,This register manages the I2C1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xA8++0x03 line.long 0x00 "CM_L4PER_I2C2_CLKCTRL,This register manages the I2C2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB0++0x03 line.long 0x00 "CM_L4PER_I2C3_CLKCTRL,This register manages the I2C3 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xB8++0x03 line.long 0x00 "CM_L4PER_I2C4_CLKCTRL,This register manages the I2C4 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xC0++0x0B line.long 0x00 "CM_L4PER_L4_PER1_CLKCTRL,This register manages the L4_PER1 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x04 "CM_L4PER2_PWMSS1_CLKCTRL,This register manages the PWMSS0 clocks" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x08 "CM_L4PER3_TIMER13_CLKCTRL,This register manages the TIMER13 clocks" bitfld.long 0x08 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x08 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x08 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xD0++0x03 line.long 0x00 "CM_L4PER3_TIMER14_CLKCTRL,This register manages the TIMER14 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xD8++0x03 line.long 0x00 "CM_L4PER3_TIMER15_CLKCTRL,This register manages the TIMER15 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_L4PER_MCSPI1_CLKCTRL,This register manages the MCSPI1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF8++0x03 line.long 0x00 "CM_L4PER_MCSPI2_CLKCTRL,This register manages the MCSPI2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x100++0x03 line.long 0x00 "CM_L4PER_MCSPI3_CLKCTRL,This register manages the MCSPI3 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x108++0x03 line.long 0x00 "CM_L4PER_MCSPI4_CLKCTRL,This register manages the MCSPI4 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x110++0x03 line.long 0x00 "CM_L4PER_GPIO7_CLKCTRL,This register manages the GPIO7 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x118++0x03 line.long 0x00 "CM_L4PER_GPIO8_CLKCTRL,This register manages the GPIO8 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x120++0x03 line.long 0x00 "CM_L4PER_MMC3_CLKCTRL,This register manages the MMC3 clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,Selects the divider value - MMCCLK_DIV_1" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" bitfld.long 0x00 24. "CLKSEL_MUX,Select the clock for the MMC from DPLL_PER" "CLKSEL_MUX_0,CLKSEL_MUX_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK - FCLK_DIS" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x128++0x03 line.long 0x00 "CM_L4PER_MMC4_CLKCTRL,This register manages the MMC4 clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,Selects the divider value - MMCCLK_DIV_1" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" bitfld.long 0x00 24. "CLKSEL_MUX,Select the clock for the MMC from DPLL_PER" "CLKSEL_MUX_0,CLKSEL_MUX_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_CLK32K,MMC optional clock control: 32K CLK - FCLK_DIS" "OPTFCLKEN_CLK32K_0,OPTFCLKEN_CLK32K_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x130++0x03 line.long 0x00 "CM_L4PER3_TIMER16_CLKCTRL,This register manages the TIMER16 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x138++0x03 line.long 0x00 "CM_L4PER2_QSPI_CLKCTRL,This register manages the QSPI clocks" bitfld.long 0x00 25.--26. "CLKSEL_DIV,QSPI clock divide ratio" "CLKSEL_DIV_0,CLKSEL_DIV_1,CLKSEL_DIV_2,CLKSEL_DIV_3" bitfld.long 0x00 24. "CLKSEL_SOURCE,Selects the source of the functional clock" "CLKSEL_SOURCE_0,CLKSEL_SOURCE_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x140++0x03 line.long 0x00 "CM_L4PER_UART1_CLKCTRL,This register manages the UART1 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x148++0x03 line.long 0x00 "CM_L4PER_UART2_CLKCTRL,This register manages the UART2 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x150++0x03 line.long 0x00 "CM_L4PER_UART3_CLKCTRL,This register manages the UART3 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x158++0x03 line.long 0x00 "CM_L4PER_UART4_CLKCTRL,This register manages the UART4 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x160++0x03 line.long 0x00 "CM_L4PER2_MCASP2_CLKCTRL,This register manages the MCASP2 clocks" bitfld.long 0x00 28.--31. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR - SEL_MLBP_CLK" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_MLBP_CLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x168++0x03 line.long 0x00 "CM_L4PER2_MCASP3_CLKCTRL,This register manages the MCASP3 clocks" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_MLBP_CLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x170++0x03 line.long 0x00 "CM_L4PER_UART5_CLKCTRL,This register manages the UART5 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x178++0x03 line.long 0x00 "CM_L4PER2_MCASP5_CLKCTRL,This register manages the MCASP5 clocks" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_MLBP_CLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x180++0x0B line.long 0x00 "CM_L4SEC_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_L4SEC_L3_GICLK,This field indicates the state of the L3_SECURE_GICLK clock in the domain" "CLKACTIVITY_L4SEC_L3_GICLK_0,CLKACTIVITY_L4SEC_L3_GICLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_L4SEC_STATICDEP,This register controls the static domain depedencies from L4SEC domain towards 'target' domains" bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" line.long 0x08 "CM_L4SEC_DYNAMICDEP,This register controls the dynamic domain depedencies from L4SEC domain towards 'target' domains" bitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_DYNDEP_0,?" group.long 0x190++0x03 line.long 0x00 "CM_L4PER2_MCASP8_CLKCTRL,This register manages the MCASP8 clocks" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_MLBP_CLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x198++0x03 line.long 0x00 "CM_L4PER2_MCASP4_CLKCTRL,This register manages the MCASP4 clocks" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_MLBP_CLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1A0++0x03 line.long 0x00 "CM_L4SEC_AES1_CLKCTRL,This register manages the AES1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1A8++0x03 line.long 0x00 "CM_L4SEC_AES2_CLKCTRL,This register manages the AES2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1B0++0x03 line.long 0x00 "CM_L4SEC_DES3DES_CLKCTRL,This register manages the DES3DES clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1B8++0x03 line.long 0x00 "CM_L4SEC_FPKA_CLKCTRL,This register manages the FPKA clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1C0++0x03 line.long 0x00 "CM_L4SEC_RNG_CLKCTRL,This register manages the RNG clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1C8++0x03 line.long 0x00 "CM_L4SEC_SHA2MD51_CLKCTRL,This register manages the SHA2MD51 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1D0++0x03 line.long 0x00 "CM_L4PER2_UART7_CLKCTRL,This register manages the UART7 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x1D8++0x03 line.long 0x00 "CM_L4SEC_DMA_CRYPTO_CLKCTRL,This register manages the DMA_CRYPTO clocks" bitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x1E0++0x03 line.long 0x00 "CM_L4PER2_UART8_CLKCTRL,This register manages the UART8 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1E8++0x03 line.long 0x00 "CM_L4PER2_UART9_CLKCTRL,This register manages the UART9 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1F0++0x03 line.long 0x00 "CM_L4PER2_DCAN2_CLKCTRL,This register manages the DCAN2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x1F8++0x1F line.long 0x00 "CM_L4SEC_SHA2MD52_CLKCTRL,This register manages the SHA2MD52 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x04 "CM_L4PER2_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x04 31. "CLKACTIVITY_MCASP8_AUX_GFCLK,This field indicates the state of the MCASP8_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP8_AUX_GFCLK_0,CLKACTIVITY_MCASP8_AUX_GFCLK_1" rbitfld.long 0x04 30. "CLKACTIVITY_MCASP8_AHCLKX,This field indicates the state of the MCASP8_AHCLKX clock in the domain" "CLKACTIVITY_MCASP8_AHCLKX_0,CLKACTIVITY_MCASP8_AHCLKX_1" newline rbitfld.long 0x04 29. "CLKACTIVITY_MCASP7_AUX_GFCLK,This field indicates the state of the MCASP7_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP7_AUX_GFCLK_0,CLKACTIVITY_MCASP7_AUX_GFCLK_1" rbitfld.long 0x04 28. "CLKACTIVITY_MCASP7_AHCLKX,This field indicates the state of the MCASP7_AHCLKX clock in the domain" "CLKACTIVITY_MCASP7_AHCLKX_0,CLKACTIVITY_MCASP7_AHCLKX_1" newline rbitfld.long 0x04 27. "CLKACTIVITY_MCASP6_AUX_GFCLK,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP6_AUX_GFCLK_0,CLKACTIVITY_MCASP6_AUX_GFCLK_1" rbitfld.long 0x04 26. "CLKACTIVITY_MCASP6_AHCLKX,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP6_AHCLKX_0,CLKACTIVITY_MCASP6_AHCLKX_1" newline rbitfld.long 0x04 25. "CLKACTIVITY_MCASP5_AHCLKX,This field indicates the state of the MCASP5_AHCLKX clock in the domain" "CLKACTIVITY_MCASP5_AHCLKX_0,CLKACTIVITY_MCASP5_AHCLKX_1" rbitfld.long 0x04 24. "CLKACTIVITY_MCASP5_AUX_GFCLK,This field indicates the state of the MCASP5_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP5_AUX_GFCLK_0,CLKACTIVITY_MCASP5_AUX_GFCLK_1" newline rbitfld.long 0x04 23. "CLKACTIVITY_MCASP4_AUX_GFCLK,This field indicates the state of the MCASP4_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP4_AUX_GFCLK_0,CLKACTIVITY_MCASP4_AUX_GFCLK_1" rbitfld.long 0x04 22. "CLKACTIVITY_MCASP4_AHCLKX,This field indicates the state of the MCASP4_AHCLKX clock in the domain" "CLKACTIVITY_MCASP4_AHCLKX_0,CLKACTIVITY_MCASP4_AHCLKX_1" newline rbitfld.long 0x04 21. "CLKACTIVITY_MCASP3_AUX_GFCLK,This field indicates the state of the MCASP3_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP3_AUX_GFCLK_0,CLKACTIVITY_MCASP3_AUX_GFCLK_1" rbitfld.long 0x04 20. "CLKACTIVITY_MCASP3_AHCLKX,This field indicates the state of the MCASP3_AHCLKX clock in the domain" "CLKACTIVITY_MCASP3_AHCLKX_0,CLKACTIVITY_MCASP3_AHCLKX_1" newline rbitfld.long 0x04 19. "CLKACTIVITY_MCASP2_AUX_GFCLK,This field indicates the state of the MCASP2_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP2_AUX_GFCLK_0,CLKACTIVITY_MCASP2_AUX_GFCLK_1" rbitfld.long 0x04 18. "CLKACTIVITY_MCASP2_AHCLKR,This field indicates the state of the MCASP2_AHCLKR clock in the domain" "CLKACTIVITY_MCASP2_AHCLKR_0,CLKACTIVITY_MCASP2_AHCLKR_1" newline rbitfld.long 0x04 17. "CLKACTIVITY_MCASP2_AHCLKX,This field indicates the state of the MCASP2_AHCLKX clock in the domain" "CLKACTIVITY_MCASP2_AHCLKX_0,CLKACTIVITY_MCASP2_AHCLKX_1" rbitfld.long 0x04 16. "CLKACTIVITY_L4PER2_L3_GICLK,This field indicates the state of the L4PER2_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER2_L3_GICLK_0,CLKACTIVITY_L4PER2_L3_GICLK_1" newline rbitfld.long 0x04 15. "CLKACTIVITY_DCAN2_SYS_CLK,This field indicates the state of the DCAN2_SYS_CLK clock in the domain" "CLKACTIVITY_DCAN2_SYS_CLK_0,CLKACTIVITY_DCAN2_SYS_CLK_1" rbitfld.long 0x04 14. "CLKACTIVITY_ICSS_IEP_CLK,This field indicates the state of the ICSS_IEP_CLK clock in the domain" "CLKACTIVITY_ICSS_IEP_CLK_0,CLKACTIVITY_ICSS_IEP_CLK_1" newline rbitfld.long 0x04 13. "CLKACTIVITY_PER_192M_GFCLK,This field indicates the state of the PER_192M_GFCLK clock in the domain" "CLKACTIVITY_PER_192M_GFCLK_0,CLKACTIVITY_PER_192M_GFCLK_1" rbitfld.long 0x04 12. "CLKACTIVITY_QSPI_GFCLK,This field indicates the state of the QSPI_GFCLK clock in the domain" "CLKACTIVITY_QSPI_GFCLK_0,CLKACTIVITY_QSPI_GFCLK_1" newline rbitfld.long 0x04 11. "CLKACTIVITY_UART9_GFCLK,This field indicates the state of the UART9_GFCLK clock in the domain" "CLKACTIVITY_UART9_GFCLK_0,CLKACTIVITY_UART9_GFCLK_1" rbitfld.long 0x04 10. "CLKACTIVITY_UART8_GFCLK,This field indicates the state of the UART8_GFCLK clock in the domain" "CLKACTIVITY_UART8_GFCLK_0,CLKACTIVITY_UART8_GFCLK_1" newline rbitfld.long 0x04 9. "CLKACTIVITY_UART7_GFCLK,This field indicates the state of the UART7_GFCLK clock in the domain" "CLKACTIVITY_UART7_GFCLK_0,CLKACTIVITY_UART7_GFCLK_1" rbitfld.long 0x04 8. "CLKACTIVITY_ICSS_CLK,This field indicates the state of the ICSS_CLK clock in the domain" "CLKACTIVITY_ICSS_CLK_0,CLKACTIVITY_ICSS_CLK_1" newline bitfld.long 0x04 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x08 "CM_L4PER2_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER2 domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 22. "GMAC_DYNDEP,Dynamic dependency towards GMAC clock domain - ENABLED" "?,GMAC_DYNDEP_1" newline rbitfld.long 0x08 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain - ENABLED" "?,L4CFG_DYNDEP_1" rbitfld.long 0x08 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain - ENABLED" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x08 6. "ATL_DYNDEP,Dynamic dependency towards ATL clock domain - ENABLED" "?,ATL_DYNDEP_1" rbitfld.long 0x08 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain - ENABLED" "?,IPU_DYNDEP_1" line.long 0x0C "CM_L4PER2_MCASP6_CLKCTRL,This register manages the MCASP6 clocks" bitfld.long 0x0C 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_MLBP_CLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x0C 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x0C 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x0C 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x10 "CM_L4PER2_MCASP7_CLKCTRL,This register manages the MCASP7 clocks" bitfld.long 0x10 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_MLBP_CLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" bitfld.long 0x10 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" newline rbitfld.long 0x10 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x10 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x14 "CM_L4PER2_STATICDEP,This register controls the static domain depedencies from L4PER2 domain towards 'target' domains" bitfld.long 0x14 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x14 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x14 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x14 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline bitfld.long 0x14 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain - DISABLED" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x18 "CM_L4PER3_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x18 12. "CLKACTIVITY_TIMER16_GFCLK,This field indicates the state of the DMT16_GFCLK clock in the domain" "CLKACTIVITY_TIMER16_GFCLK_0,CLKACTIVITY_TIMER16_GFCLK_1" rbitfld.long 0x18 11. "CLKACTIVITY_TIMER15_GFCLK,This field indicates the state of the DMT15_GFCLK clock in the domain" "CLKACTIVITY_TIMER15_GFCLK_0,CLKACTIVITY_TIMER15_GFCLK_1" newline rbitfld.long 0x18 10. "CLKACTIVITY_TIMER14_GFCLK,This field indicates the state of the DMT14_GFCLK clock in the domain" "CLKACTIVITY_TIMER14_GFCLK_0,CLKACTIVITY_TIMER14_GFCLK_1" rbitfld.long 0x18 9. "CLKACTIVITY_TIMER13_GFCLK,This field indicates the state of the DMT13_GFCLK clock in the domain" "CLKACTIVITY_TIMER13_GFCLK_0,CLKACTIVITY_TIMER13_GFCLK_1" newline rbitfld.long 0x18 8. "CLKACTIVITY_L4PER3_L3_GICLK,This field indicates the state of the L4PER2_L3_GICLK clock in the domain" "CLKACTIVITY_L4PER3_L3_GICLK_0,CLKACTIVITY_L4PER3_L3_GICLK_1" bitfld.long 0x18 0.--1. "CLKTRCTRL,Controls the clock state transition of the L4PER clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x1C "CM_L4PER3_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER3 domain towards 'target' domains" rbitfld.long 0x1C 31. "VPE_DYNDEP,Dynamic dependency towards VPE clock domain - ENABLED" "?,VPE_DYNDEP_1" bitfld.long 0x1C 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x1C 23. "RTC_DYNDEP,Dynamic dependency towards RTC clock domain - ENABLED" "?,RTC_DYNDEP_1" rbitfld.long 0x1C 12. "L4CFG_DYNDEP,Dynamic dependency towards L4CFG clock domain - ENABLED" "?,L4CFG_DYNDEP_1" newline rbitfld.long 0x1C 9. "CAM_DYNDEP,Dynamic dependency towards CAM clock domain - ENABLED" "?,CAM_DYNDEP_1" rbitfld.long 0x1C 7. "L3INIT_DYNDEP,Dynamic dependency towards L3INIT clock domain - ENABLED" "?,L3INIT_DYNDEP_1" newline rbitfld.long 0x1C 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" rbitfld.long 0x1C 3. "IPU_DYNDEP,Dynamic dependency towards IPU clock domain - ENABLED" "?,IPU_DYNDEP_1" tree.end tree "CM_CORE__OCP_SOCKET" base ad:0x4A008000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_CM_CORE,This register contains the IP revision code for the CM_CORE part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "SCHEME_0,SCHEME_1,?,?" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R) maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X) maintained by IP specification owner" "X_MAJOR_0,X_MAJOR_1,X_MAJOR_2,X_MAJOR_3,X_MAJOR_4,?,?,?" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y) maintained by IP specification owner" "Y_MINOR_0,Y_MINOR_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x40++0x03 line.long 0x00 "CM_CM_CORE_PROFILING_CLKCTRL,This register manages the CM_CORE_PROFILING clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0xF0++0x03 line.long 0x00 "CM_CORE_DEBUG_CFG,This register is used to configure the CM_CORE's 32-bit debug output" hexmask.long.byte 0x00 24.--31. 1. "SEL3,Internal signal block select for debug word byte-3" hexmask.long.byte 0x00 16.--23. 1. "SEL2,Internal signal block select for debug word byte-2" hexmask.long.byte 0x00 8.--15. 1. "SEL1,Internal signal block select for debug word byte-1" hexmask.long.byte 0x00 0.--7. 1. "SEL0,Internal signal block select for debug word byte-0" tree.end tree "CM_CORE__RESTORE" base ad:0x4A009E00 group.long 0x18++0x03 line.long 0x00 "CM_L3MAIN1_CLKSTCTRL_RESTORE,Second address map for register" group.long 0x20++0x03 line.long 0x00 "CM_L4CFG_CLKSTCTRL_RESTORE,Second address map for register" group.long 0x28++0x17 line.long 0x00 "CM_L4PER_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x04 "CM_L3INIT_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x08 "CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE,Second address map for register" line.long 0x0C "CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,Second address map for register" line.long 0x10 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE,Second address map for register" line.long 0x14 "CM_CM_CORE_PROFILING_CLKCTRL_RESTORE,Second address map for register" group.long 0x48++0x03 line.long 0x00 "CM_L3MAIN1_DYNAMICDEP_RESTORE,Second address map for register" group.long 0x58++0x07 line.long 0x00 "CM_L4CFG_DYNAMICDEP_RESTORE,Second address map for register" line.long 0x04 "CM_L4PER_DYNAMICDEP_RESTORE,Second address map for register" group.long 0x6C++0x03 line.long 0x00 "CM_DMA_STATICDEP_RESTORE,Second address map for register" tree.end tree "CM_CORE_AON__CKGEN" base ad:0x4A005100 group.long 0x00++0x03 line.long 0x00 "CM_CLKSEL_CORE,CORE module clock selection" rbitfld.long 0x00 8. "CLKSEL_L4,Selects L4 interconnect clock (L4_clk) - L3_CLK_DIV_1" "CLKSEL_L4_0,CLKSEL_L4_1" bitfld.long 0x00 4. "CLKSEL_L3,Selects L3 interconnect clock (L3_clk) - CORE_CLK_DIV_1" "CLKSEL_L3_0,CLKSEL_L3_1" group.long 0x08++0x03 line.long 0x00 "CM_CLKSEL_ABE,ABE module clock selection" bitfld.long 0x00 10. "SLIMBUS1_CLK_GATE,Gating control for SLIMBUS_CLK clock tree in ABE" "SLIMBUS1_CLK_GATE_0,SLIMBUS1_CLK_GATE_1" bitfld.long 0x00 8. "PAD_CLKS_GATE,Gating control for PAD_CLKS clock tree in ABE - GATED" "PAD_CLKS_GATE_0,PAD_CLKS_GATE_1" newline bitfld.long 0x00 0.--1. "CLKSEL_OPP,Selects the OPP divider ABE domain - DIV_1" "CLKSEL_OPP_0,CLKSEL_OPP_1,CLKSEL_OPP_2,CLKSEL_OPP_3" group.long 0x10++0x03 line.long 0x00 "CM_DLL_CTRL,Special register for DLL control" bitfld.long 0x00 0. "DLL_OVERRIDE,Control if DLL lock and code outputs are overriden or not - NO_OVR" "DLL_OVERRIDE_0,DLL_OVERRIDE_1" group.long 0x20++0x13 line.long 0x00 "CM_CLKMODE_DPLL_CORE,This register allows controlling the DPLL modes" bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "DPLL_RELOCK_RAMP_EN_0,DPLL_RELOCK_RAMP_EN_1" bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x00 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x00 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_CORE,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_CORE,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_CORE,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "DPLL_BYP_CLKSEL_0,DPLL_BYP_CLKSEL_1" rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline bitfld.long 0x0C 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" newline hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_CORE,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x10 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x3C++0x13 line.long 0x00 "CM_DIV_H12_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1" rbitfld.long 0x00 9. "CLKST,HSDIVIDER1 CLKOUT2 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x00 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "CM_DIV_H13_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1" rbitfld.long 0x04 9. "CLKST,HSDIVIDER1 CLKOUT3 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x04 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x08 "CM_DIV_H14_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1" rbitfld.long 0x08 9. "CLKST,HSDIVIDER1 CLKOUT4 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x08 0.--5. "DIVHS,DPLL (H14+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x0C "CM_SSC_DELTAMSTEP_DPLL_CORE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x0C 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x10 "CM_SSC_MODFREQDIV_DPLL_CORE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x10 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "MODFREQDIV_EXPONENT_0,MODFREQDIV_EXPONENT_1,MODFREQDIV_EXPONENT_2,MODFREQDIV_EXPONENT_3,MODFREQDIV_EXPONENT_4,MODFREQDIV_EXPONENT_5,MODFREQDIV_EXPONENT_6,MODFREQDIV_EXPONENT_7" hexmask.long.byte 0x10 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0x54++0x1F line.long 0x00 "CM_DIV_H22_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the 2nd HSDIVIDER" rbitfld.long 0x00 9. "CLKST,HSDIVIDER2 CLKOUT2 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x00 0.--5. "DIVHS,DPLL (H22+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "CM_DIV_H23_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the 2nd HSDIVIDER" rbitfld.long 0x04 9. "CLKST,HSDIVIDER2 CLKOUT3 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x04 0.--5. "DIVHS,DPLL (H23+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x08 "CM_DIV_H24_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the 2nd HSDIVIDER" rbitfld.long 0x08 9. "CLKST,HSDIVIDER2 CLKOUT4 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x08 0.--5. "DIVHS,DPLL (H24+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x0C "CM_CLKMODE_DPLL_MPU,This register allows controlling the DPLL modes" bitfld.long 0x0C 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x0C 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x0C 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x0C 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x0C 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x0C 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x0C 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "DPLL_RELOCK_RAMP_EN_0,DPLL_RELOCK_RAMP_EN_1" bitfld.long 0x0C 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x0C 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x0C 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x0C 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x10 "CM_IDLEST_DPLL_MPU,This register allows monitoring DPLL activity" bitfld.long 0x10 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x10 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x10 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x14 "CM_AUTOIDLE_DPLL_MPU,This register provides automatic control over the DPLL activity" bitfld.long 0x14 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_FR_BYP" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x18 "CM_CLKSEL_DPLL_MPU,This register provides controls over the DPLL" rbitfld.long 0x18 23. "DPLL_BYP_CLKSEL,Only CLKINPULOW bypass clock supported for this PLL" "DPLL_BYP_CLKSEL_0,DPLL_BYP_CLKSEL_1" bitfld.long 0x18 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,DCC_EN_1" newline hexmask.long.word 0x18 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x18 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x1C "CM_DIV_M2_DPLL_MPU,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x1C 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x1C 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x88++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_MPU,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_MPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "MODFREQDIV_EXPONENT_0,MODFREQDIV_EXPONENT_1,MODFREQDIV_EXPONENT_2,MODFREQDIV_EXPONENT_3,MODFREQDIV_EXPONENT_4,MODFREQDIV_EXPONENT_5,MODFREQDIV_EXPONENT_6,MODFREQDIV_EXPONENT_7" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0x9C++0x17 line.long 0x00 "CM_BYPCLK_DPLL_MPU,Control MPU PLL BYPASS clock" bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL MPU bypass clock" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_IVA,This register allows controlling the DPLL modes" bitfld.long 0x04 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x04 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x04 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x04 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x04 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "DPLL_RELOCK_RAMP_EN_0,DPLL_RELOCK_RAMP_EN_1" bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x04 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x04 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_IVA,This register allows monitoring DPLL activity" bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose) - DPLL_NOTINIT" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_IVA,This register provides automatic control over the DPLL activity" bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_FR_BYP" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_IVA,This register provides controls over the DPLL" bitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "DPLL_BYP_CLKSEL_0,DPLL_BYP_CLKSEL_1" rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_IVA,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x14 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xC8++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_IVA,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_IVA,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "MODFREQDIV_EXPONENT_0,MODFREQDIV_EXPONENT_1,MODFREQDIV_EXPONENT_2,MODFREQDIV_EXPONENT_3,MODFREQDIV_EXPONENT_4,MODFREQDIV_EXPONENT_5,MODFREQDIV_EXPONENT_6,MODFREQDIV_EXPONENT_7" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" group.long 0xDC++0x1B line.long 0x00 "CM_BYPCLK_DPLL_IVA,Control IVA PLL BYPASS clock" bitfld.long 0x00 0.--1. "CLKSEL,Select the DPLL IVA bypass clock - CORE_X2_CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" line.long 0x04 "CM_CLKMODE_DPLL_ABE,This register allows controlling the DPLL modes" bitfld.long 0x04 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x04 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x04 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x04 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline bitfld.long 0x04 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,DPLL_REGM4XEN_1" bitfld.long 0x04 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x04 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "DPLL_RELOCK_RAMP_EN_0,DPLL_RELOCK_RAMP_EN_1" bitfld.long 0x04 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x04 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x04 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x04 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x08 "CM_IDLEST_DPLL_ABE,This register allows monitoring DPLL activity" bitfld.long 0x08 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x08 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x08 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x0C "CM_AUTOIDLE_DPLL_ABE,This register provides automatic control over the DPLL activity" bitfld.long 0x0C 0.--2. "AUTO_DPLL_MODE,DPLL automatic control;" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x10 "CM_CLKSEL_DPLL_ABE,This register provides controls over the DPLL" rbitfld.long 0x10 23. "DPLL_BYP_CLKSEL,Only CLKINPULOW bypass clock supported for this PLL" "DPLL_BYP_CLKSEL_0,DPLL_BYP_CLKSEL_1" rbitfld.long 0x10 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x10 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x10 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x14 "CM_DIV_M2_DPLL_ABE,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x14 11. "CLKX2ST,DPLL CLKOUTX2 status - CLK_GATED" "CLKX2ST_0,CLKX2ST_1" rbitfld.long 0x14 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" newline bitfld.long 0x14 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x18 "CM_DIV_M3_DPLL_ABE,This register provides controls over the M3 divider of the DPLL" rbitfld.long 0x18 9. "CLKST,DPLL CLKOUTHIF status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x18 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x108++0x1B line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_ABE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_ABE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "MODFREQDIV_EXPONENT_0,MODFREQDIV_EXPONENT_1,MODFREQDIV_EXPONENT_2,MODFREQDIV_EXPONENT_3,MODFREQDIV_EXPONENT_4,MODFREQDIV_EXPONENT_5,MODFREQDIV_EXPONENT_6,MODFREQDIV_EXPONENT_7" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKMODE_DPLL_DDR,This register allows controlling the DPLL modes" bitfld.long 0x08 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x08 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x08 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x08 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x08 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x08 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x08 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" bitfld.long 0x08 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x08 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x08 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x08 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x0C "CM_IDLEST_DPLL_DDR,This register allows monitoring DPLL activity" bitfld.long 0x0C 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x0C 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x0C 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x10 "CM_AUTOIDLE_DPLL_DDR,This register provides automatic control over the DPLL activity" bitfld.long 0x10 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_FR_BYP" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x14 "CM_CLKSEL_DPLL_DDR,This register provides controls over the DPLL" bitfld.long 0x14 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "0,1" bitfld.long 0x14 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,DCC_EN_1" newline hexmask.long.word 0x14 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x14 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x18 "CM_DIV_M2_DPLL_DDR,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x18 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x18 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x128++0x2F line.long 0x00 "CM_DIV_H11_DPLL_DDR,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1" rbitfld.long 0x00 9. "CLKST,HSDIVIDER1 CLKOUT1 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x00 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "CM_SSC_DELTAMSTEP_DPLL_DDR,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x04 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x08 "CM_SSC_MODFREQDIV_DPLL_DDR,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x08 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x0C "CM_CLKMODE_DPLL_DSP,This register allows controlling the DPLL modes" bitfld.long 0x0C 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x0C 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x0C 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x0C 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x0C 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x0C 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x0C 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" bitfld.long 0x0C 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x0C 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x0C 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x0C 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x10 "CM_IDLEST_DPLL_DSP,This register allows monitoring DPLL activity" bitfld.long 0x10 4. "ST_DPLL_INIT,DPLL init status (for debug purpose) - DPLL_NOTINIT" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x10 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x10 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x14 "CM_AUTOIDLE_DPLL_DSP,This register provides automatic control over the DPLL activity" bitfld.long 0x14 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_FR_BYP" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x18 "CM_CLKSEL_DPLL_DSP,This register provides controls over the DPLL" bitfld.long 0x18 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "0,1" rbitfld.long 0x18 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x18 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x18 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x1C "CM_DIV_M2_DPLL_DSP,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x1C 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x1C 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_DIV_M3_DPLL_DSP,This register provides controls over the M3 divider of the DPLL" rbitfld.long 0x20 9. "CLKST,DPLL CLKOUTHIF status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x20 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_SSC_DELTAMSTEP_DPLL_DSP,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x24 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x28 "CM_SSC_MODFREQDIV_DPLL_DSP,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x28 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x2C "CM_BYPCLK_DPLL_DSP,Control IVA PLL BYPASS clock" bitfld.long 0x2C 0.--1. "CLKSEL,Select the DPLL IVA bypass clock - CORE_X2_CLK_DIV_1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3" group.long 0x160++0x07 line.long 0x00 "CM_SHADOW_FREQ_CONFIG1,Shadow register to program new DPLL configuration affecting EMIF and GPMC (L3 clock) functional frequency during DVFS" bitfld.long 0x00 16.--18. "DPLL_DDR_DPLL_EN,Shadow register forCM_CLKMODE_DPLL_DDR.DPLL_EN" "DPLL_DDR_DPLL_EN_0,DPLL_DDR_DPLL_EN_1,DPLL_DDR_DPLL_EN_2,DPLL_DDR_DPLL_EN_3,DPLL_DDR_DPLL_EN_4,DPLL_DDR_DPLL_EN_5,DPLL_DDR_DPLL_EN_6,DPLL_DDR_DPLL_EN_7" bitfld.long 0x00 11.--15. "DPLL_DDR_M2_DIV,Shadow register forCM_DIV_M2_DPLL_DDR.DIVHS" "DPLL_DDR_M2_DIV_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 3. "DLL_RESET,Specify if DLL should be reset or not during the frequency change hardware sequence" "DLL_RESET_0,DLL_RESET_1" bitfld.long 0x00 2. "DLL_OVERRIDE,Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to '1'" "DLL_OVERRIDE_0,DLL_OVERRIDE_1" newline bitfld.long 0x00 0. "FREQ_UPDATE,Writing '1' indicates that a new configuration is available" "FREQ_UPDATE_0,FREQ_UPDATE_1" line.long 0x04 "CM_SHADOW_FREQ_CONFIG2,Shadow register to program new DPLL configuration affecting GPMC (L3 clock) functional frequency during DVFS" bitfld.long 0x04 2.--7. "DPLL_CORE_H12_DIV,Shadow register forCM_DIV_H12_DPLL_CORE.DIVHS" "DPLL_CORE_H12_DIV_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x04 1. "CLKSEL_L3,Shadow register forCM_CLKSEL_CORE.CLKSEL_L3" "CLKSEL_L3_0,CLKSEL_L3_1" newline bitfld.long 0x04 0. "GPMC_FREQ_UPDATE,Controls whether or not GPMC has to be put automatically into idle during the frequency change operation" "GPMC_FREQ_UPDATE_0,GPMC_FREQ_UPDATE_1" group.long 0x170++0x03 line.long 0x00 "CM_DYN_DEP_PRESCAL,Control the time unit of the sliding window for dynamic dependencies (auto-sleep feature)" bitfld.long 0x00 0.--5. "PRESCAL,Time unit is equal to (PRESCAL + 1) L4 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x184++0x13 line.long 0x00 "CM_CLKMODE_DPLL_EVE,This register allows controlling the DPLL modes" bitfld.long 0x00 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x00 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x00 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x00 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x00 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x00 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x00 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" bitfld.long 0x00 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x00 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x00 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x00 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x04 "CM_IDLEST_DPLL_EVE,This register allows monitoring DPLL activity" bitfld.long 0x04 4. "ST_DPLL_INIT,DPLL init status (for debug purpose) - DPLL_NOTINIT" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x04 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x04 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x08 "CM_AUTOIDLE_DPLL_EVE,This register provides automatic control over the DPLL activity" bitfld.long 0x08 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_FR_BYP" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x0C "CM_CLKSEL_DPLL_EVE,This register provides controls over the DPLL" bitfld.long 0x0C 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "0,1" rbitfld.long 0x0C 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline hexmask.long.word 0x0C 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" hexmask.long.byte 0x0C 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x10 "CM_DIV_M2_DPLL_EVE,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x10 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x10 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x19C++0x2F line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_EVE,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_EVE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_BYPCLK_DPLL_EVE,Control IVA PLL BYPASS clock" bitfld.long 0x08 0.--1. "CLKSEL,Select the DPLL IVA bypass clock" "0,1,2,3" line.long 0x0C "CM_CLKMODE_DPLL_GMAC,This register allows controlling the DPLL modes" bitfld.long 0x0C 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x0C 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x0C 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x0C 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x0C 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x0C 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x0C 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" bitfld.long 0x0C 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x0C 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x0C 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x0C 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x10 "CM_IDLEST_DPLL_GMAC,This register allows monitoring DPLL activity" bitfld.long 0x10 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x10 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "ST_DPLL_MODE_0,ST_DPLL_MODE_1,ST_DPLL_MODE_2,ST_DPLL_MODE_3,ST_DPLL_MODE_4,ST_DPLL_MODE_5,ST_DPLL_MODE_6,ST_DPLL_MODE_7" newline bitfld.long 0x10 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x14 "CM_AUTOIDLE_DPLL_GMAC,This register provides automatic control over the DPLL activity" bitfld.long 0x14 0.--2. "AUTO_DPLL_MODE,DPLL automatic control; - AUTO_FR_BYP" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x18 "CM_CLKSEL_DPLL_GMAC,This register provides controls over the DPLL" bitfld.long 0x18 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "0,1" bitfld.long 0x18 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,DCC_EN_1" newline bitfld.long 0x18 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" hexmask.long.word 0x18 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" newline hexmask.long.byte 0x18 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x1C "CM_DIV_M2_DPLL_GMAC,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x1C 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x1C 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x20 "CM_DIV_M3_DPLL_GMAC,This register provides controls over the M3 divider of the DPLL" rbitfld.long 0x20 9. "CLKST,DPLL CLKOUTHIF status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x20 0.--4. "DIVHS,DPLL M3 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x24 "CM_DIV_H11_DPLL_GMAC,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1" rbitfld.long 0x24 9. "CLKST,HSDIVIDER1 CLKOUT1 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x24 0.--5. "DIVHS,DPLL (H11+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x28 "CM_DIV_H12_DPLL_GMAC,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1" rbitfld.long 0x28 9. "CLKST,HSDIVIDER1 CLKOUT2 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x28 0.--5. "DIVHS,DPLL (H12+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x2C "CM_DIV_H13_DPLL_GMAC,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1" rbitfld.long 0x2C 9. "CLKST,HSDIVIDER1 CLKOUT3 status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x2C 0.--5. "DIVHS,DPLL (H13+1) post-divider factor (1 to 63)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x1D0++0x1B line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_GMAC,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_GMAC,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKMODE_DPLL_GPU,This register allows controlling the DPLL modes" bitfld.long 0x08 15. "DPLL_SSC_TYPE,Select between Triangular and SquareWave Spread Spectrum Clocking - TRIANGULAR" "DPLL_SSC_TYPE_0,DPLL_SSC_TYPE_1" bitfld.long 0x08 14. "DPLL_SSC_DOWNSPREAD,Control if only low frequency spread is required - FULL_SPREAD" "DPLL_SSC_DOWNSPREAD_0,DPLL_SSC_DOWNSPREAD_1" newline rbitfld.long 0x08 13. "DPLL_SSC_ACK,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature - DISABLED" "DPLL_SSC_ACK_0,DPLL_SSC_ACK_1" bitfld.long 0x08 12. "DPLL_SSC_EN,Enable or disable Spread Spectrum Clocking - DISABLED" "DPLL_SSC_EN_0,DPLL_SSC_EN_1" newline rbitfld.long 0x08 11. "DPLL_REGM4XEN,Enable the REGM4XEN mode of the DPLL" "DPLL_REGM4XEN_0,?" bitfld.long 0x08 10. "DPLL_LPMODE_EN,Set the DPLL in Low Power mode" "DPLL_LPMODE_EN_0,DPLL_LPMODE_EN_1" newline bitfld.long 0x08 9. "DPLL_RELOCK_RAMP_EN,If enabled the clock ramping feature is used applied during the lock process as well as the relock process" "0,1" bitfld.long 0x08 8. "DPLL_DRIFTGUARD_EN,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "DPLL_DRIFTGUARD_EN_0,DPLL_DRIFTGUARD_EN_1" newline bitfld.long 0x08 5.--7. "DPLL_RAMP_RATE,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process - REFCLKX128" "DPLL_RAMP_RATE_0,DPLL_RAMP_RATE_1,DPLL_RAMP_RATE_2,DPLL_RAMP_RATE_3,DPLL_RAMP_RATE_4,DPLL_RAMP_RATE_5,DPLL_RAMP_RATE_6,DPLL_RAMP_RATE_7" bitfld.long 0x08 3.--4. "DPLL_RAMP_LEVEL,The DPLL provides an output clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "DPLL_RAMP_LEVEL_0,DPLL_RAMP_LEVEL_1,DPLL_RAMP_LEVEL_2,DPLL_RAMP_LEVEL_3" newline bitfld.long 0x08 0.--2. "DPLL_EN,DPLL control" "DPLL_EN_0,DPLL_EN_1,DPLL_EN_2,DPLL_EN_3,DPLL_EN_4,DPLL_EN_5,DPLL_EN_6,DPLL_EN_7" line.long 0x0C "CM_IDLEST_DPLL_GPU,This register allows monitoring DPLL activity" bitfld.long 0x0C 4. "ST_DPLL_INIT,DPLL init status (for debug purpose)" "ST_DPLL_INIT_0,ST_DPLL_INIT_1" bitfld.long 0x0C 1.--3. "ST_DPLL_MODE,DPLL mode status (for debug purpose)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 0. "ST_DPLL_CLK,DPLL lock status - DPLL_UNLOCKED" "ST_DPLL_CLK_0,ST_DPLL_CLK_1" line.long 0x10 "CM_AUTOIDLE_DPLL_GPU,This register provides automatic control over the DPLL activity" bitfld.long 0x10 0.--2. "AUTO_DPLL_MODE,DPLL automatic control" "AUTO_DPLL_MODE_0,AUTO_DPLL_MODE_1,AUTO_DPLL_MODE_2,AUTO_DPLL_MODE_3,AUTO_DPLL_MODE_4,AUTO_DPLL_MODE_5,AUTO_DPLL_MODE_6,AUTO_DPLL_MODE_7" line.long 0x14 "CM_CLKSEL_DPLL_GPU,This register provides controls over the DPLL" bitfld.long 0x14 23. "DPLL_BYP_CLKSEL,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER" "0,1" rbitfld.long 0x14 22. "DCC_EN,Duty-cycle corrector for high frequency clock - DISABLED" "DCC_EN_0,?" newline bitfld.long 0x14 20. "DPLL_CLKOUTHIF_CLKSEL,Selects the source of the DPLL CLKOUTHIF clock" "DPLL_CLKOUTHIF_CLKSEL_0,DPLL_CLKOUTHIF_CLKSEL_1" hexmask.long.word 0x14 8.--18. 1. "DPLL_MULT,DPLL multiplier factor (2 to 2047)" newline hexmask.long.byte 0x14 0.--6. 1. "DPLL_DIV,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)" line.long 0x18 "CM_DIV_M2_DPLL_GPU,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x18 9. "CLKST,DPLL CLKOUT status - CLK_GATED" "CLKST_0,CLKST_1" bitfld.long 0x18 0.--4. "DIVHS,DPLL M2 post-divider factor (1 to 31)" "DIVHS_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x1F0++0x07 line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_GPU,Control the DeltaMStep parameter for Spread Spectrum Clocking" hexmask.long.tbyte 0x00 0.--19. 1. "DELTAMSTEP,DeltaMStep is split into fractional and integer part" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_GPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking" bitfld.long 0x04 8.--10. "MODFREQDIV_EXPONENT,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--6. 1. "MODFREQDIV_MANTISSA,Set the Mantissa component of MODFREQDIV factor" tree.end tree "CM_CORE_AON__DSP1" base ad:0x4A005400 group.long 0x00++0x0B line.long 0x00 "CM_DSP1_CLKSTCTRL,This register enables the DSP domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_DSP1_GFCLK,This field indicates the state of the DSP_ROOT_CLK clock in the domain" "CLKACTIVITY_DSP1_GFCLK_0,CLKACTIVITY_DSP1_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSP1_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains" bitfld.long 0x04 30. "ATL_STATDEP,Static dependency towards L3INIT Clock Domain - DISABLED" "ATL_STATDEP_0,ATL_STATDEP_1" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE Clock Domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE Clock Domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 Clock Domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 Clock Domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC Clock Domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU Clock Domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 Clock Domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 Clock Domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 Clock Domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 Clock Domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE Clock Domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" newline rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON Clock Domain - DISABLED" "COREAON_STATDEP_0,?" bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON Clock Domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" newline bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC Clock Domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 Clock Domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" newline rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG Clock Domain - DISABLED" "L4CFG_STATDEP_0,?" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU Clock Domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM Clock Domain - DISABLED" "CAM_STATDEP_0,CAM_STATDEP_1" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS Clock Domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT Clock Domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 Clock Domain - ENABLED" "?,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF Clock Domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA Clock Domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 Clock Domain - DISABLED" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DSP1_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_DSP1_DSP1_CLKCTRL,This register manages the DSP clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE_AON__DSP2" base ad:0x4A005600 group.long 0x00++0x0B line.long 0x00 "CM_DSP2_CLKSTCTRL,This register enables the DSP domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_DSP2_GFCLK,This field indicates the state of the DSP_ROOT_CLK clock in the domain" "CLKACTIVITY_DSP2_GFCLK_0,CLKACTIVITY_DSP2_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_DSP2_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains" bitfld.long 0x04 30. "ATL_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "ATL_STATDEP_0,ATL_STATDEP_1" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE cLOCK dOMAIN - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE Clock Domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 Clock Domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 Clock Domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC Clock Domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPUClock Domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" newline bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2CLOCK dOMAIN - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 CLOCK dOMAIN - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC Clock Domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" rbitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,?" newline bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU Clock Domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,CAM_STATDEP_1" newline bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" newline rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" newline bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain - DISABLED" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_DSP2_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_DSP2_DSP2_CLKCTRL,This register manages the DSP clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE_AON__EVE1" base ad:0x4A005640 group.long 0x00++0x07 line.long 0x00 "CM_EVE1_CLKSTCTRL,This register enables the EVE domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_EVE1_GFCLK,This field indicates the state of the EVE1_GFCLK clock in the domain" "CLKACTIVITY_EVE1_GFCLK_0,CLKACTIVITY_EVE1_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE1_STATICDEP,This register controls the static domain depedencies from EVE1 domain towards 'target' domains" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_EVE1_EVE1_CLKCTRL,This register manages the EVE clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE_AON__EVE2" base ad:0x4A005680 group.long 0x00++0x07 line.long 0x00 "CM_EVE2_CLKSTCTRL,This register enables the EVE domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_EVE2_GFCLK,This field indicates the state of the EVE2_GFCLK clock in the domain" "CLKACTIVITY_EVE2_GFCLK_0,CLKACTIVITY_EVE2_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EVE2_STATICDEP,This register controls the static domain depedencies from EVE2 domain towards 'target' domains" bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" rbitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" newline bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_EVE2_EVE2_CLKCTRL,This register manages the EVE clocks" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE_AON__INSTR" base ad:0x4A005F00 rgroup.long 0x00++0x03 line.long 0x00 "CMI_IDENTICATION,CM profiling identification register" bitfld.long 0x00 30.--31. "SCHEME,Highlander 0.8 value: 0b01" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates a software compatible module family" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "MAJOR,Major revision" "MAJOR_0,MAJOR_1,MAJOR_2,MAJOR_3,MAJOR_4,MAJOR_5,MAJOR_6,MAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x07 line.long 0x00 "CMI_SYS_CONFIG,CM profiling system configuartion register" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local tartget state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" line.long 0x04 "CMI_STATUS,CM profiling status register" bitfld.long 0x04 8. "FIFOEMPTY,PM Profiling buffer empty" "FIFOEMPTY_0,FIFOEMPTY_1" group.long 0x24++0x0F line.long 0x00 "CMI_CONFIGURATION,CM profiling configuration register" bitfld.long 0x00 30.--31. "CLAIM_3,Ownership" "CLAIM_3_0,CLAIM_3_1,CLAIM_3_2,CLAIM_3_3" bitfld.long 0x00 29. "CLAIM_2,Debugger override qualifier" "CLAIM_2_0,CLAIM_2_1" rbitfld.long 0x00 28. "CLAIM_1,Current owner" "CLAIM_1_0,CLAIM_1_1" newline bitfld.long 0x00 15. "MOD_ACT_EN,When HIGH the CM Module Activity collection is enabled" "MOD_ACT_EN_0,MOD_ACT_EN_1" bitfld.long 0x00 7. "EVT_CAPT_EN,When HIGH the CM events capture is enabled" "EVT_CAPT_EN_0,EVT_CAPT_EN_1" line.long 0x04 "CMI_CLASS_FILTERING,CM profiling class filtering register" bitfld.long 0x04 31. "SNAP_CAPT_EN_1F,Snapshot capture enable - Class-ID = 0x1F" "SNAP_CAPT_EN_1F_0,SNAP_CAPT_EN_1F_1" bitfld.long 0x04 30. "SNAP_CAPT_EN_1E," "SNAP_CAPT_EN_1E_0,SNAP_CAPT_EN_1E_1" bitfld.long 0x04 29. "SNAP_CAPT_EN_1D," "SNAP_CAPT_EN_1D_0,SNAP_CAPT_EN_1D_1" newline bitfld.long 0x04 28. "SNAP_CAPT_EN_1C," "SNAP_CAPT_EN_1C_0,SNAP_CAPT_EN_1C_1" bitfld.long 0x04 27. "SNAP_CAPT_EN_1B," "SNAP_CAPT_EN_1B_0,SNAP_CAPT_EN_1B_1" bitfld.long 0x04 26. "SNAP_CAPT_EN_1A," "SNAP_CAPT_EN_1A_0,SNAP_CAPT_EN_1A_1" newline bitfld.long 0x04 25. "SNAP_CAPT_EN_19," "SNAP_CAPT_EN_19_0,SNAP_CAPT_EN_19_1" bitfld.long 0x04 24. "SNAP_CAPT_EN_18," "SNAP_CAPT_EN_18_0,SNAP_CAPT_EN_18_1" bitfld.long 0x04 23. "SNAP_CAPT_EN_17," "SNAP_CAPT_EN_17_0,SNAP_CAPT_EN_17_1" newline bitfld.long 0x04 22. "SNAP_CAPT_EN_16," "SNAP_CAPT_EN_16_0,SNAP_CAPT_EN_16_1" bitfld.long 0x04 21. "SNAP_CAPT_EN_15," "SNAP_CAPT_EN_15_0,SNAP_CAPT_EN_15_1" bitfld.long 0x04 20. "SNAP_CAPT_EN_14," "SNAP_CAPT_EN_14_0,SNAP_CAPT_EN_14_1" newline bitfld.long 0x04 19. "SNAP_CAPT_EN_13," "SNAP_CAPT_EN_13_0,SNAP_CAPT_EN_13_1" bitfld.long 0x04 18. "SNAP_CAPT_EN_12," "SNAP_CAPT_EN_12_0,SNAP_CAPT_EN_12_1" bitfld.long 0x04 17. "SNAP_CAPT_EN_11," "SNAP_CAPT_EN_11_0,SNAP_CAPT_EN_11_1" newline bitfld.long 0x04 16. "SNAP_CAPT_EN_10,Snapshot capture enable - Class-ID = 0x10" "SNAP_CAPT_EN_10_0,SNAP_CAPT_EN_10_1" bitfld.long 0x04 3. "SNAP_CAPT_EN_03,Snapshot capture enable - Class-ID = 0x03 [0x23]" "SNAP_CAPT_EN_03_0,SNAP_CAPT_EN_03_1" bitfld.long 0x04 2. "SNAP_CAPT_EN_02,Snapshot capture enable - Class-ID = 0x02 [0x22]" "SNAP_CAPT_EN_02_0,SNAP_CAPT_EN_02_1" newline bitfld.long 0x04 1. "SNAP_CAPT_EN_01,Snapshot capture enable - Class-ID = 0x01 [0x21]" "SNAP_CAPT_EN_01_0,SNAP_CAPT_EN_01_1" bitfld.long 0x04 0. "SNAP_CAPT_EN_00,Snapshot capture enable - Class-ID = 0x00 [0x20]" "SNAP_CAPT_EN_00_0,SNAP_CAPT_EN_00_1" line.long 0x08 "CMI_TRIGGERING,CM profiling triggering control register" bitfld.long 0x08 1. "TRIG_STOP_EN,Enable stop capturing CM events from external trigger detection" "TRIG_STOP_EN_0,TRIG_STOP_EN_1" bitfld.long 0x08 0. "TRIG_START_EN,Enable start capturing CM events from external trigger detection" "TRIG_START_EN_0,TRIG_START_EN_1" line.long 0x0C "CMI_SAMPLING,CM profiling sampling window register" bitfld.long 0x0C 16.--19. "FCLK_DIV_FACOR,FunClk divide factor ranging from 1 to 16" "FCLK_DIV_FACOR_0,FCLK_DIV_FACOR_1,FCLK_DIV_FACOR_2,FCLK_DIV_FACOR_3,FCLK_DIV_FACOR_4,FCLK_DIV_FACOR_5,FCLK_DIV_FACOR_6,FCLK_DIV_FACOR_7,FCLK_DIV_FACOR_8,FCLK_DIV_FACOR_9,FCLK_DIV_FACOR_10,FCLK_DIV_FACOR_11,FCLK_DIV_FACOR_12,FCLK_DIV_FACOR_13,FCLK_DIV_FACOR_14,FCLK_DIV_FACOR_15" hexmask.long.byte 0x0C 0.--7. 1. "SAMP_WIND_SIZE,CM events sampling window size" tree.end tree "CM_CORE_AON__IPU" base ad:0x4A005500 group.long 0x00++0x0B line.long 0x00 "CM_IPU1_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_IPU1_GFCLK,This field indicates the state of the IPU1_GFCLK clock in the domain" "CLKACTIVITY_IPU1_GFCLK_0,CLKACTIVITY_IPU1_GFCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the BELLINI0 clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_IPU1_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains" bitfld.long 0x04 30. "ATL_STATDEP,Static dependency towards ATL clock domain - DISABLED" "ATL_STATDEP_0,ATL_STATDEP_1" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" newline bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" newline bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" newline bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER1 clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards DMA clock domain - DISABLED" "SDMA_STATDEP_0,?" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline rbitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,?" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - DISABLED" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain - DISABLED" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_IPU1_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_IPU1_IPU1_CLKCTRL,This register manages the IPU1 clocks" bitfld.long 0x00 24. "CLKSEL,Selects the timer functional clock - SEL_DPLL_ABE_X2_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" newline rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_IPU_CLKSTCTRL,This register enables the ABE domain power state transition" rbitfld.long 0x00 18. "CLKACTIVITY_MCASP1_AHCLKR,This field indicates the state of the MCASP1_AHCLKR clock in the domain" "CLKACTIVITY_MCASP1_AHCLKR_0,CLKACTIVITY_MCASP1_AHCLKR_1" rbitfld.long 0x00 17. "CLKACTIVITY_MCASP1_AHCLKX,This field indicates the state of the MCASP1_AHCLKX clock in the domain" "CLKACTIVITY_MCASP1_AHCLKX_0,CLKACTIVITY_MCASP1_AHCLKX_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_MCASP1_AUX_GFCLK,This field indicates the state of the MCASP1_AUX_GFCLK clock in the domain" "CLKACTIVITY_MCASP1_AUX_GFCLK_0,CLKACTIVITY_MCASP1_AUX_GFCLK_1" rbitfld.long 0x00 14. "CLKACTIVITY_UART6_GFCLK,This field indicates the state of the UART6_GFCLK clock in the domain" "CLKACTIVITY_UART6_GFCLK_0,CLKACTIVITY_UART6_GFCLK_1" newline rbitfld.long 0x00 13. "CLKACTIVITY_IPU_96M_GFCLK,This field indicates the state of the IPU_96M_GFCLK clock in the domain" "CLKACTIVITY_IPU_96M_GFCLK_0,CLKACTIVITY_IPU_96M_GFCLK_1" rbitfld.long 0x00 12. "CLKACTIVITY_TIMER8_GFCLK,This field indicates the state of the TIMER8_GFCLK clock in the domain" "CLKACTIVITY_TIMER8_GFCLK_0,CLKACTIVITY_TIMER8_GFCLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_TIMER7_GFCLK,This field indicates the state of the TIMER7_GFCLK clock in the domain" "CLKACTIVITY_TIMER7_GFCLK_0,CLKACTIVITY_TIMER7_GFCLK_1" rbitfld.long 0x00 10. "CLKACTIVITY_TIMER6_GFCLK,This field indicates the state of the TIMER6_GFCLK clock in the domain" "CLKACTIVITY_TIMER6_GFCLK_0,CLKACTIVITY_TIMER6_GFCLK_1" newline rbitfld.long 0x00 9. "CLKACTIVITY_TIMER5_GFCLK,This field indicates the state of the TIMER5_GFCLK functional clock in the domain" "CLKACTIVITY_TIMER5_GFCLK_0,CLKACTIVITY_TIMER5_GFCLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_IPU_L3_GICLK,This field indicates the state of the IPU_L3_GICLK interface clock in the domain" "CLKACTIVITY_IPU_L3_GICLK_0,CLKACTIVITY_IPU_L3_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the ABE clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" group.long 0x50++0x03 line.long 0x00 "CM_IPU_MCASP1_CLKCTRL,This register manages the MCASP clocks" bitfld.long 0x00 28.--31. "CLKSEL_AHCLKR,Selects reference clock for AHCLKR - SEL_MLBP_CLK" "CLKSEL_AHCLKR_0,CLKSEL_AHCLKR_1,CLKSEL_AHCLKR_2,CLKSEL_AHCLKR_3,CLKSEL_AHCLKR_4,CLKSEL_AHCLKR_5,CLKSEL_AHCLKR_6,CLKSEL_AHCLKR_7,CLKSEL_AHCLKR_8,CLKSEL_AHCLKR_9,CLKSEL_AHCLKR_10,CLKSEL_AHCLKR_11,CLKSEL_AHCLKR_12,CLKSEL_AHCLKR_13,CLKSEL_AHCLKR_14,CLKSEL_AHCLKR_15" bitfld.long 0x00 24.--27. "CLKSEL_AHCLKX,Selects reference clock for AHCLKX - SEL_MLBP_CLK" "CLKSEL_AHCLKX_0,CLKSEL_AHCLKX_1,CLKSEL_AHCLKX_2,CLKSEL_AHCLKX_3,CLKSEL_AHCLKX_4,CLKSEL_AHCLKX_5,CLKSEL_AHCLKX_6,CLKSEL_AHCLKX_7,CLKSEL_AHCLKX_8,CLKSEL_AHCLKX_9,CLKSEL_AHCLKX_10,CLKSEL_AHCLKX_11,CLKSEL_AHCLKX_12,CLKSEL_AHCLKX_13,CLKSEL_AHCLKX_14,CLKSEL_AHCLKX_15" newline bitfld.long 0x00 22.--23. "CLKSEL_AUX_CLK,Selects the source of the AUX clock - SEL_PER_ABE_X1_GFCLK" "CLKSEL_AUX_CLK_0,CLKSEL_AUX_CLK_1,CLKSEL_AUX_CLK_2,CLKSEL_AUX_CLK_3" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x58++0x03 line.long 0x00 "CM_IPU_TIMER5_CLKCTRL,This register manages the TIMER5 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Selects the timer functional clock - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x60++0x03 line.long 0x00 "CM_IPU_TIMER6_CLKCTRL,This register manages the TIMER6 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Selects the timer functional clock - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x68++0x03 line.long 0x00 "CM_IPU_TIMER7_CLKCTRL,This register manages the TIMER7 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Selects the timer functional clock - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x70++0x03 line.long 0x00 "CM_IPU_TIMER8_CLKCTRL,This register manages the TIMER8 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Selects the timer functional clock - RESERVED1" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x78++0x03 line.long 0x00 "CM_IPU_I2C5_CLKCTRL,This register manages the I2C5 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_IPU_UART6_CLKCTRL,This register manages the UART6 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE_AON__MPU" base ad:0x4A005300 group.long 0x00++0x0B line.long 0x00 "CM_MPU_CLKSTCTRL,This register enables the MPU domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_MPU_GCLK,This field indicates the state of the MPU_DPLL_CLK clock in the domain" "CLKACTIVITY_MPU_GCLK_0,CLKACTIVITY_MPU_GCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the MPU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_MPU_STATICDEP,This register controls the static domain depedencies from MPU domain towards 'target' domains" bitfld.long 0x04 29. "PCIE_STATDEP,Static dependency towards PCIE clock domain - DISABLED" "PCIE_STATDEP_0,PCIE_STATDEP_1" bitfld.long 0x04 28. "VPE_STATDEP,Static dependency towards VPE clock domain - DISABLED" "VPE_STATDEP_0,VPE_STATDEP_1" newline bitfld.long 0x04 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" bitfld.long 0x04 26. "L4PER2_STATDEP,Static dependency towards L4PER2 clock domain - DISABLED" "L4PER2_STATDEP_0,L4PER2_STATDEP_1" newline bitfld.long 0x04 25. "GMAC_STATDEP,Static dependency towards GMAC clock domain - DISABLED" "GMAC_STATDEP_0,GMAC_STATDEP_1" bitfld.long 0x04 24. "IPU_STATDEP,Static dependency towards IPU clock domain - DISABLED" "IPU_STATDEP_0,IPU_STATDEP_1" newline bitfld.long 0x04 23. "IPU1_STATDEP,Static dependency towards IPU1 clock domain - DISABLED" "IPU1_STATDEP_0,IPU1_STATDEP_1" bitfld.long 0x04 20. "EVE2_STATDEP,Static dependency towards EVE2 clock domain - DISABLED" "EVE2_STATDEP_0,EVE2_STATDEP_1" newline bitfld.long 0x04 19. "EVE1_STATDEP,Static dependency towards EVE1 clock domain - DISABLED" "EVE1_STATDEP_0,EVE1_STATDEP_1" bitfld.long 0x04 18. "DSP2_STATDEP,Static dependency towards DSP2 clock domain - DISABLED" "DSP2_STATDEP_0,DSP2_STATDEP_1" newline rbitfld.long 0x04 17. "CUSTEFUSE_STATDEP,Static dependency towards CUSTEFUSE clock domain - DISABLED" "CUSTEFUSE_STATDEP_0,?" rbitfld.long 0x04 16. "COREAON_STATDEP,Static dependency towards COREAON clock domain - DISABLED" "COREAON_STATDEP_0,?" newline bitfld.long 0x04 15. "WKUPAON_STATDEP,Static dependency towards WKUPAON clock domain - DISABLED" "WKUPAON_STATDEP_0,WKUPAON_STATDEP_1" bitfld.long 0x04 14. "L4SEC_STATDEP,Static dependency towards L4SEC clock domain - DISABLED" "L4SEC_STATDEP_0,L4SEC_STATDEP_1" newline bitfld.long 0x04 13. "L4PER_STATDEP,Static dependency towards L4PER clock domain - DISABLED" "L4PER_STATDEP_0,L4PER_STATDEP_1" bitfld.long 0x04 12. "L4CFG_STATDEP,Static dependency towards L4CFG clock domain - DISABLED" "L4CFG_STATDEP_0,L4CFG_STATDEP_1" newline rbitfld.long 0x04 11. "SDMA_STATDEP,Static dependency towards SDMA clock domain - DISABLED" "SDMA_STATDEP_0,?" bitfld.long 0x04 10. "GPU_STATDEP,Static dependency towards GPU clock domain - DISABLED" "GPU_STATDEP_0,GPU_STATDEP_1" newline bitfld.long 0x04 9. "CAM_STATDEP,Static dependency towards CAM clock domain - DISABLED" "CAM_STATDEP_0,CAM_STATDEP_1" bitfld.long 0x04 8. "DSS_STATDEP,Static dependency towards DSS clock domain - DISABLED" "DSS_STATDEP_0,DSS_STATDEP_1" newline bitfld.long 0x04 7. "L3INIT_STATDEP,Static dependency towards L3INIT clock domain - DISABLED" "L3INIT_STATDEP_0,L3INIT_STATDEP_1" bitfld.long 0x04 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN clock domain - DISABLED" "L3MAIN1_STATDEP_0,L3MAIN1_STATDEP_1" newline bitfld.long 0x04 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" bitfld.long 0x04 2. "IVA_STATDEP,Static dependency towards IVA clock domain - DISABLED" "IVA_STATDEP_0,IVA_STATDEP_1" newline bitfld.long 0x04 1. "DSP1_STATDEP,Static dependency towards DSP1 clock domain - DISABLED" "DSP1_STATDEP_0,DSP1_STATDEP_1" bitfld.long 0x04 0. "IPU2_STATDEP,Static dependency towards IPU2 clock domain - DISABLED" "IPU2_STATDEP_0,IPU2_STATDEP_1" line.long 0x08 "CM_MPU_DYNAMICDEP,This register controls the dynamic domain depedencies from MPU domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "WINDOWSIZE_0,WINDOWSIZE_1,WINDOWSIZE_2,WINDOWSIZE_3,WINDOWSIZE_4,WINDOWSIZE_5,WINDOWSIZE_6,WINDOWSIZE_7,WINDOWSIZE_8,WINDOWSIZE_9,WINDOWSIZE_10,WINDOWSIZE_11,WINDOWSIZE_12,WINDOWSIZE_13,WINDOWSIZE_14,WINDOWSIZE_15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" newline rbitfld.long 0x08 4. "EMIF_DYNDEP,Dynamic dependency towards EMIF clock domain - ENABLED" "?,EMIF_DYNDEP_1" group.long 0x20++0x03 line.long 0x00 "CM_MPU_MPU_CLKCTRL,This register manages the MPU clocks" bitfld.long 0x00 26. "CLKSEL_ABE_DIV_MODE,Selects the ratio for MPU - ABE async bridge versus MPU DPLL clock - DIV8" "CLKSEL_ABE_DIV_MODE_0,CLKSEL_ABE_DIV_MODE_1" bitfld.long 0x00 24.--25. "CLKSEL_EMIF_DIV_MODE,Selects the ratio for MPU - L3 async bridge versus MPU DPLL clock - DIV4A" "CLKSEL_EMIF_DIV_MODE_0,CLKSEL_EMIF_DIV_MODE_1,CLKSEL_EMIF_DIV_MODE_2,CLKSEL_EMIF_DIV_MODE_3" newline rbitfld.long 0x00 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline rbitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x28++0x03 line.long 0x00 "CM_MPU_MPU_MPU_DBG_CLKCTRL,This register manages the MPU_MPU_DBG clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" tree.end tree "CM_CORE_AON__OCP_SOCKET" base ad:0x4A005000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_CM_CORE_AON,This register contains the IP revision code for the CM_CORE_AON part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "SCHEME_0,SCHEME_1,?,?" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R) maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X) maintained by IP specification owner" "X_MAJOR_0,X_MAJOR_1,X_MAJOR_2,X_MAJOR_3,X_MAJOR_4,?,?,?" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" newline bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y) maintained by IP specification owner" "Y_MINOR_0,Y_MINOR_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x40++0x03 line.long 0x00 "CM_CM_CORE_AON_PROFILING_CLKCTRL,This register manages the CM_CORE_AON_PROFILING clock" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0xEC++0x03 line.long 0x00 "CM_CORE_AON_DEBUG_OUT,This register is used to monitor the CM_COREAON's 32 bit HEDEBUG BUS [warm reset insensitive]" repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0xF0)++0x03 line.long 0x00 "CM_CORE_AON_DEBUG_CFG$1,This register is used to configure the CM_CORE_AON's 32-bit debug output" hexmask.long.word 0x00 0.--9. 1. "SEL0,Internal signal block select for debug word byte-0" repeat.end tree.end tree "CM_CORE_AON__RESTORE" base ad:0x4A005E00 group.long 0x00++0x07 line.long 0x00 "CM_CLKSEL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_DIV_M2_DPLL_CORE_RESTORE,Second address map for register" group.long 0x10++0x0B line.long 0x00 "CM_DIV_H12_DPLL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_DIV_H13_DPLL_CORE_RESTORE,Second address map for register" line.long 0x08 "CM_DIV_H14_DPLL_CORE_RESTORE,Second address map for register" group.long 0x20++0x33 line.long 0x00 "CM_DIV_H22_DPLL_CORE_RESTORE,Second address map for register" line.long 0x04 "CM_DIV_H23_DPLL_CORE_RESTORE,Second address map for register" line.long 0x08 "CM_DIV_H24_DPLL_CORE_RESTORE,Second address map for register" line.long 0x0C "CM_CLKSEL_DPLL_CORE_RESTORE,Second address map for register" line.long 0x10 "CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,Second address map for register" line.long 0x14 "CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,Second address map for register" line.long 0x18 "CM_CLKMODE_DPLL_CORE_RESTORE,Second address map for register" line.long 0x1C "CM_SHADOW_FREQ_CONFIG2_RESTORE,Second address map for register" line.long 0x20 "CM_SHADOW_FREQ_CONFIG1_RESTORE,Second address map for register" line.long 0x24 "CM_AUTOIDLE_DPLL_CORE_RESTORE,Second address map for register" line.long 0x28 "CM_MPU_CLKSTCTRL_RESTORE,Second address map for register" line.long 0x2C "CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE,Second address map for register" line.long 0x30 "CM_DYN_DEP_PRESCAL_RESTORE,Second address map for register" tree.end tree "CM_CORE_AON__RTC" base ad:0x4A005740 group.long 0x00++0x07 line.long 0x00 "CM_RTC_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 10. "CLKACTIVITY_RTC_AUX_CLK,This field indicates the state of the RTC_AUX_CLK in the domain" "CLKACTIVITY_RTC_AUX_CLK_0,CLKACTIVITY_RTC_AUX_CLK_1" rbitfld.long 0x00 8. "CLKACTIVITY_RTC_L4_GICLK,This field indicates the state of the RTC_L4_GICLK clock in the domain" "CLKACTIVITY_RTC_L4_GICLK_0,CLKACTIVITY_RTC_L4_GICLK_1" newline bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the WKUPAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_RTC_RTCSS_CLKCTRL,This register manages the RTC clocks" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "CM_CORE_AON__VPE" base ad:0x4A005760 group.long 0x00++0x0B line.long 0x00 "CM_VPE_CLKSTCTRL,This register enables the VPE domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_VPE_GCLK,This field indicates the state of the VPE_GCLK clock in the domain" "CLKACTIVITY_VPE_GCLK_0,CLKACTIVITY_VPE_GCLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the DSP clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_VPE_VPE_CLKCTRL,This register manages the VPE clocks" rbitfld.long 0x04 18. "STBYST,Module standby status" "STBYST_0,STBYST_1" rbitfld.long 0x04 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x08 "CM_VPE_STATICDEP,This register controls the static domain depedencies from VPE domain towards 'target' domains" bitfld.long 0x08 27. "L4PER3_STATDEP,Static dependency towards L4PER3 clock domain - DISABLED" "L4PER3_STATDEP_0,L4PER3_STATDEP_1" rbitfld.long 0x08 5. "L3MAIN1_STATDEP,Static dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_STATDEP_1" bitfld.long 0x08 4. "EMIF_STATDEP,Static dependency towards EMIF clock domain - DISABLED" "EMIF_STATDEP_0,EMIF_STATDEP_1" tree.end tree "CORE_PRM" base ad:0x4AE06700 group.long 0x00++0x07 line.long 0x00 "PM_CORE_PWRSTCTRL,This register controls the CORE power state to reach upon a domain sleep transition" rbitfld.long 0x00 24.--25. "OCP_NRET_BANK_ONSTATE,OCP_WP bank and DMM bank2 state when domain is ON" "?,?,?,OCP_NRET_BANK_ONSTATE_3" rbitfld.long 0x00 22.--23. "IPU_UNICACHE_ONSTATE,IPU UNICACHE bank state when domain is ON" "?,?,?,IPU_UNICACHE_ONSTATE_3" newline rbitfld.long 0x00 20.--21. "IPU_L2RAM_ONSTATE,IPU L2 bank state when domain is ON" "?,?,?,IPU_L2RAM_ONSTATE_3" rbitfld.long 0x00 18.--19. "CORE_OCMRAM_ONSTATE,OCMRAM bank state when domain is ON" "?,?,?,CORE_OCMRAM_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "CORE_OTHER_BANK_ONSTATE,DMA/ICR bank and DMM bank1 state when domain is ON" "?,?,?,CORE_OTHER_BANK_ONSTATE_3" rbitfld.long 0x00 12. "OCP_NRET_BANK_RETSTATE,OCP_WP bank and DMM bank2 state when domain is RETENTION" "OCP_NRET_BANK_RETSTATE_0,?" newline bitfld.long 0x00 11. "IPU_UNICACHE_RETSTATE,IPU UNICACHE bank state when domain is RETENTION" "IPU_UNICACHE_RETSTATE_0,IPU_UNICACHE_RETSTATE_1" bitfld.long 0x00 10. "IPU_L2RAM_RETSTATE,IPU L2 bank state when domain is RETENTION" "IPU_L2RAM_RETSTATE_0,IPU_L2RAM_RETSTATE_1" newline rbitfld.long 0x00 9. "CORE_OCMRAM_RETSTATE,OCMRAM bank state when domain is RETENTION" "?,CORE_OCMRAM_RETSTATE_1" rbitfld.long 0x00 8. "CORE_OTHER_BANK_RETSTATE,DMA/ICR bank and DMM bank1 state when domain is RETENTION" "?,CORE_OTHER_BANK_RETSTATE_1" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - RESERVED" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CORE_PWRSTST,This register provides a status on the current CORE power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 12.--13. "OCP_NRET_BANK_STATEST,OCP_WP bank and DMM bank2 state status - MEM_OFF" "OCP_NRET_BANK_STATEST_0,OCP_NRET_BANK_STATEST_1,OCP_NRET_BANK_STATEST_2,OCP_NRET_BANK_STATEST_3" rbitfld.long 0x04 10.--11. "IPU_UNICACHE_STATEST,IPU UNICACHE bank state status - MEM_OFF" "IPU_UNICACHE_STATEST_0,IPU_UNICACHE_STATEST_1,IPU_UNICACHE_STATEST_2,IPU_UNICACHE_STATEST_3" newline rbitfld.long 0x04 8.--9. "IPU_L2RAM_STATEST,IPU L2 bank state status - MEM_OFF" "IPU_L2RAM_STATEST_0,IPU_L2RAM_STATEST_1,IPU_L2RAM_STATEST_2,IPU_L2RAM_STATEST_3" rbitfld.long 0x04 6.--7. "CORE_OCMRAM_STATEST,OCMRAM bank state status - MEM_OFF" "CORE_OCMRAM_STATEST_0,CORE_OCMRAM_STATEST_1,CORE_OCMRAM_STATEST_2,CORE_OCMRAM_STATEST_3" newline rbitfld.long 0x04 4.--5. "CORE_OTHER_BANK_STATEST,DMA/ICR bank and DMM bank1 state status - MEM_OFF" "CORE_OTHER_BANK_STATEST_0,CORE_OTHER_BANK_STATEST_1,CORE_OTHER_BANK_STATEST_2,CORE_OTHER_BANK_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - RESERVED" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_L3MAIN1_L3_MAIN_1_CONTEXT,This register contains dedicated L3_MAIN_1 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x2C++0x03 line.long 0x00 "RM_L3MAIN1_GPMC_CONTEXT,This register contains dedicated GPMC context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x34++0x03 line.long 0x00 "RM_L3MAIN1_MMU_EDMA_CONTEXT,This register contains dedicated MMU context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x4C++0x1B line.long 0x00 "RM_L3MAIN1_MMU_PCIESS_CONTEXT,This register contains dedicated MMU context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x04 "PM_L3MAIN1_OCMC_RAM1_WKDEP,This register controls wakeup dependency based on OCMC_RAM1 service requests" bitfld.long 0x04 7. "WKUPDEP_OCMC_RAM1_EVE2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_EVE2_0,WKUPDEP_OCMC_RAM1_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_OCMC_RAM1_EVE1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_EVE1_0,WKUPDEP_OCMC_RAM1_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_OCMC_RAM1_DSP2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_DSP2_0,WKUPDEP_OCMC_RAM1_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_OCMC_RAM1_IPU1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_IPU1_0,WKUPDEP_OCMC_RAM1_IPU1_1" newline bitfld.long 0x04 2. "WKUPDEP_OCMC_RAM1_DSP1,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_DSP1_0,WKUPDEP_OCMC_RAM1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_OCMC_RAM1_IPU2,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_IPU2_0,WKUPDEP_OCMC_RAM1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_OCMC_RAM1_MPU,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM1_MPU_0,WKUPDEP_OCMC_RAM1_MPU_1" line.long 0x08 "RM_L3MAIN1_OCMC_RAM1_CONTEXT,This register contains dedicated OCMC_RAM context statuses" bitfld.long 0x08 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" bitfld.long 0x08 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x0C "PM_L3MAIN1_OCMC_RAM2_WKDEP,This register controls wakeup dependency based on OCMC_RAM2 service requests" bitfld.long 0x0C 7. "WKUPDEP_OCMC_RAM2_EVE2,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_EVE2_0,WKUPDEP_OCMC_RAM2_EVE2_1" bitfld.long 0x0C 6. "WKUPDEP_OCMC_RAM2_EVE1,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_EVE1_0,WKUPDEP_OCMC_RAM2_EVE1_1" newline bitfld.long 0x0C 5. "WKUPDEP_OCMC_RAM2_DSP2,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_DSP2_0,WKUPDEP_OCMC_RAM2_DSP2_1" bitfld.long 0x0C 4. "WKUPDEP_OCMC_RAM2_IPU1,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_IPU1_0,WKUPDEP_OCMC_RAM2_IPU1_1" newline bitfld.long 0x0C 2. "WKUPDEP_OCMC_RAM2_DSP1,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_DSP1_0,WKUPDEP_OCMC_RAM2_DSP1_1" bitfld.long 0x0C 1. "WKUPDEP_OCMC_RAM2_IPU2,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_IPU2_0,WKUPDEP_OCMC_RAM2_IPU2_1" newline bitfld.long 0x0C 0. "WKUPDEP_OCMC_RAM2_MPU,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM2_MPU_0,WKUPDEP_OCMC_RAM2_MPU_1" line.long 0x10 "RM_L3MAIN1_OCMC_RAM2_CONTEXT,This register contains dedicated OCMC_RAM2 context statuses" bitfld.long 0x10 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L3MAIN1_OCMC_RAM3_WKDEP,This register controls wakeup dependency based on OCMC_RAM3 service requests" bitfld.long 0x14 7. "WKUPDEP_OCMC_RAM3_EVE2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_EVE2_0,WKUPDEP_OCMC_RAM3_EVE2_1" bitfld.long 0x14 6. "WKUPDEP_OCMC_RAM3_EVE1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_EVE1_0,WKUPDEP_OCMC_RAM3_EVE1_1" newline bitfld.long 0x14 5. "WKUPDEP_OCMC_RAM3_DSP2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_DSP2_0,WKUPDEP_OCMC_RAM3_DSP2_1" bitfld.long 0x14 4. "WKUPDEP_OCMC_RAM3_IPU1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_IPU1_0,WKUPDEP_OCMC_RAM3_IPU1_1" newline bitfld.long 0x14 2. "WKUPDEP_OCMC_RAM3_DSP1,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_DSP1_0,WKUPDEP_OCMC_RAM3_DSP1_1" bitfld.long 0x14 1. "WKUPDEP_OCMC_RAM3_IPU2,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_IPU2_0,WKUPDEP_OCMC_RAM3_IPU2_1" newline bitfld.long 0x14 0. "WKUPDEP_OCMC_RAM3_MPU,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_OCMC_RAM3_MPU_0,WKUPDEP_OCMC_RAM3_MPU_1" line.long 0x18 "RM_L3MAIN1_OCMC_RAM3_CONTEXT,This register contains dedicated OCMC_RAM3 context statuses" bitfld.long 0x18 8. "LOSTMEM_CORE_OCMRAM,Specify if memory-based context in CORE_OCMRAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_CORE_OCMRAM_0,LOSTMEM_CORE_OCMRAM_1" bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x70++0x17 line.long 0x00 "PM_L3MAIN1_TPCC_WKDEP,This register controls wakeup dependency based on TPCC service requests" bitfld.long 0x00 7. "WKUPDEP_TPCC_EVE2,Wakeup dependency from TPCC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_EVE2_0,WKUPDEP_TPCC_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_TPCC_EVE1,Wakeup dependency from TPCC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_EVE1_0,WKUPDEP_TPCC_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_TPCC_DSP2,Wakeup dependency from TPCC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_DSP2_0,WKUPDEP_TPCC_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_TPCC_IPU1,Wakeup dependency from TPCC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_IPU1_0,WKUPDEP_TPCC_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_TPCC_DSP1,Wakeup dependency from TPCC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_DSP1_0,WKUPDEP_TPCC_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_TPCC_IPU2,Wakeup dependency from TPCC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_IPU2_0,WKUPDEP_TPCC_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_TPCC_MPU,Wakeup dependency from TPCC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPCC_MPU_0,WKUPDEP_TPCC_MPU_1" line.long 0x04 "RM_L3MAIN1_TPCC_CONTEXT,This register contains dedicated TPCC context statuses" bitfld.long 0x04 8. "LOSTMEM_TPCC_BANK,Specify if memory-based context in TPCC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPCC_BANK_0,LOSTMEM_TPCC_BANK_1" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x08 "PM_L3MAIN1_TPTC1_WKDEP,This register controls wakeup dependency based on TPTC service requests" bitfld.long 0x08 7. "WKUPDEP_TPTC1_EVE2,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_EVE2_0,WKUPDEP_TPTC1_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_TPTC1_EVE1,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_EVE1_0,WKUPDEP_TPTC1_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_TPTC1_DSP2,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_DSP2_0,WKUPDEP_TPTC1_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_TPTC1_IPU1,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_IPU1_0,WKUPDEP_TPTC1_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_TPTC1_DSP1,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_DSP1_0,WKUPDEP_TPTC1_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_TPTC1_IPU2,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_IPU2_0,WKUPDEP_TPTC1_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_TPTC1_MPU,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC1_MPU_0,WKUPDEP_TPTC1_MPU_1" line.long 0x0C "RM_L3MAIN1_TPTC1_CONTEXT,This register contains dedicated TPTC1 context statuses" bitfld.long 0x0C 8. "LOSTMEM_TPTC_BANK,Specify if memory-based context in TPTC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPTC_BANK_0,LOSTMEM_TPTC_BANK_1" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x10 "PM_L3MAIN1_TPTC2_WKDEP,This register controls wakeup dependency based on TPTC service requests" bitfld.long 0x10 7. "WKUPDEP_TPTC2_EVE2,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_EVE2_0,WKUPDEP_TPTC2_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_TPTC2_EVE1,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_EVE1_0,WKUPDEP_TPTC2_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_TPTC2_DSP2,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_DSP2_0,WKUPDEP_TPTC2_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_TPTC2_IPU1,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_IPU1_0,WKUPDEP_TPTC2_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_TPTC2_DSP1,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_DSP1_0,WKUPDEP_TPTC2_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TPTC2_IPU2,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_IPU2_0,WKUPDEP_TPTC2_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TPTC2_MPU,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TPTC2_MPU_0,WKUPDEP_TPTC2_MPU_1" line.long 0x14 "RM_L3MAIN1_TPTC2_CONTEXT,This register contains dedicated TPTC2 context statuses" bitfld.long 0x14 8. "LOSTMEM_TPTC_BANK,Specify if memory-based context in TPTC_MEM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_TPTC_BANK_0,LOSTMEM_TPTC_BANK_1" bitfld.long 0x14 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x8C++0x03 line.long 0x00 "RM_L3MAIN1_VCP1_CONTEXT,This register contains dedicated VCP1 context statuses" bitfld.long 0x00 8. "LOSTMEM_VCP_BANK,Specify if memory-based context in VCP memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VCP_BANK_0,LOSTMEM_VCP_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x94++0x03 line.long 0x00 "RM_L3MAIN1_VCP2_CONTEXT,This register contains dedicated VCP2 context statuses" bitfld.long 0x00 8. "LOSTMEM_VCP_BANK,Specify if memory-based context in VCP memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VCP_BANK_0,LOSTMEM_VCP_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x210++0x07 line.long 0x00 "RM_IPU2_RSTCTRL,This register controls the release of the IPU2 sub-system resets" bitfld.long 0x00 2. "RST_IPU,IPU system reset control" "RST_IPU_0,RST_IPU_1" bitfld.long 0x00 1. "RST_CPU1,IPU Cortex M3 CPU1 reset control - CLEAR" "RST_CPU1_0,RST_CPU1_1" newline bitfld.long 0x00 0. "RST_CPU0,IPU Cortex M3 CPU0 reset control" "RST_CPU0_0,RST_CPU0_1" line.long 0x04 "RM_IPU2_RSTST,This register logs the different reset sources of the IPU2 SS" bitfld.long 0x04 6. "RST_ICECRUSHER_CPU1,Cortex M3 CPU1 has been reset due to IPU ICECRUSHER1 reset source - RESET_NO" "RST_ICECRUSHER_CPU1_0,RST_ICECRUSHER_CPU1_1" bitfld.long 0x04 5. "RST_ICECRUSHER_CPU0,Cortex M3 CPU0 has been reset due to IPU ICECRUSHER0 reset source - RESET_NO" "RST_ICECRUSHER_CPU0_0,RST_ICECRUSHER_CPU0_1" newline bitfld.long 0x04 4. "RST_EMULATION_CPU1,Cortex M3 CPU1 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU1_0,RST_EMULATION_CPU1_1" bitfld.long 0x04 3. "RST_EMULATION_CPU0,Cortex M3 CPU0 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU0_0,RST_EMULATION_CPU0_1" newline bitfld.long 0x04 2. "RST_IPU,IPU system SW reset status - RESET_NO" "RST_IPU_0,RST_IPU_1" bitfld.long 0x04 1. "RST_CPU1,IPU Cortex-M3 CPU1 SW reset status - RESET_NO" "RST_CPU1_0,RST_CPU1_1" newline bitfld.long 0x04 0. "RST_CPU0,IPU Cortex-M3 CPU0 SW reset status - RESET_NO" "RST_CPU0_0,RST_CPU0_1" group.long 0x224++0x03 line.long 0x00 "RM_IPU2_IPU2_CONTEXT,This register contains dedicated IPU2 context statuses" bitfld.long 0x00 9. "LOSTMEM_IPU_L2RAM,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_L2RAM_0,LOSTMEM_IPU_L2RAM_1" bitfld.long 0x00 8. "LOSTMEM_IPU_UNICACHE,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_UNICACHE_0,LOSTMEM_IPU_UNICACHE_1" newline bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x324++0x03 line.long 0x00 "RM_DMA_DMA_SYSTEM_CONTEXT,This register contains dedicated SDMA context statuses" bitfld.long 0x00 8. "LOSTMEM_CORE_OTHER_BANK,Specify if memory-based context in CORE_OTHER_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CORE_OTHER_BANK_0,LOSTMEM_CORE_OTHER_BANK_1" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x424++0x03 line.long 0x00 "RM_EMIF_DMM_CONTEXT,This register contains dedicated DMM context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x42C++0x03 line.long 0x00 "RM_EMIF_EMIF_OCP_FW_CONTEXT,This register contains dedicated EMIF_OCP_FW context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x434++0x03 line.long 0x00 "RM_EMIF_EMIF1_CONTEXT,This register contains dedicated EMIF_1 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x43C++0x03 line.long 0x00 "RM_EMIF_EMIF2_CONTEXT,This register contains dedicated EMIF_2 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x444++0x03 line.long 0x00 "RM_EMIF_EMIF_DLL_CONTEXT,This register contains dedicated DLL context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x524++0x03 line.long 0x00 "RM_ATL_ATL_CONTEXT,This register contains dedicated ATL context statuses" bitfld.long 0x00 8. "LOSTMEM_ATL_BANK,Specify if memory-based context in ATL_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_ATL_BANK_0,LOSTMEM_ATL_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x624++0x03 line.long 0x00 "RM_L4CFG_L4_CFG_CONTEXT,This register contains dedicated L4_CFG context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x62C++0x03 line.long 0x00 "RM_L4CFG_SPINLOCK_CONTEXT,This register contains dedicated HW_SEM context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x634++0x03 line.long 0x00 "RM_L4CFG_MAILBOX1_CONTEXT,This register contains dedicated MAILBOX1 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x63C++0x03 line.long 0x00 "RM_L4CFG_SAR_ROM_CONTEXT,This register contains dedicated SAR_ROM context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x644++0x03 line.long 0x00 "RM_L4CFG_OCP2SCP2_CONTEXT,This register contains dedicated OCP2SCP2 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x64C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX2_CONTEXT,This register contains dedicated MAILBOX2 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x654++0x03 line.long 0x00 "RM_L4CFG_MAILBOX3_CONTEXT,This register contains dedicated MAILBOX3 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x65C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX4_CONTEXT,This register contains dedicated MAILBOX4 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x664++0x03 line.long 0x00 "RM_L4CFG_MAILBOX5_CONTEXT,This register contains dedicated MAILBOX5 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x66C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX6_CONTEXT,This register contains dedicated MAILBOX6 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x674++0x03 line.long 0x00 "RM_L4CFG_MAILBOX7_CONTEXT,This register contains dedicated MAILBOX7 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x67C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX8_CONTEXT,This register contains dedicated MAILBOX8 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x684++0x03 line.long 0x00 "RM_L4CFG_MAILBOX9_CONTEXT,This register contains dedicated MAILBOX9 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x68C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX10_CONTEXT,This register contains dedicated MAILBOX10 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x694++0x03 line.long 0x00 "RM_L4CFG_MAILBOX11_CONTEXT,This register contains dedicated MAILBOX11 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x69C++0x03 line.long 0x00 "RM_L4CFG_MAILBOX12_CONTEXT,This register contains dedicated MAILBOX12 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x6A4++0x03 line.long 0x00 "RM_L4CFG_MAILBOX13_CONTEXT,This register contains dedicated MAILBOX13 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x724++0x03 line.long 0x00 "RM_L3INSTR_L3_MAIN_2_CONTEXT,This register contains dedicated L3_3 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x72C++0x03 line.long 0x00 "RM_L3INSTR_L3_INSTR_CONTEXT,This register contains dedicated L3_INSTR context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x744++0x03 line.long 0x00 "RM_L3INSTR_OCP_WP_NOC_CONTEXT,This register contains dedicated OCP_WP1 context statuses" bitfld.long 0x00 8. "LOSTMEM_CORE_NRET_BANK,Specify if memory-based context in CORE_NRET_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_CORE_NRET_BANK_0,LOSTMEM_CORE_NRET_BANK_1" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "COREAON_PRM" base ad:0x4AE06600 group.long 0x28++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_MPU_WKDEP,This register controls wakeup dependency based on SR_MPU service requests" bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_MPU_EVE2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_MPU_EVE2_0,WKUPDEP_SMARTREFLEX_MPU_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_MPU_EVE1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_MPU_EVE1_0,WKUPDEP_SMARTREFLEX_MPU_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_MPU_DSP2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_MPU_DSP2_0,WKUPDEP_SMARTREFLEX_MPU_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_MPU_IPU1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_MPU_IPU1_0,WKUPDEP_SMARTREFLEX_MPU_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_MPU_DSP1,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_MPU_DSP1_0,WKUPDEP_SMARTREFLEX_MPU_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_MPU_IPU2,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_MPU_IPU2_0,WKUPDEP_SMARTREFLEX_MPU_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_MPU_MPU,Wakeup dependency from SMARTREFLEX_MPU module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_MPU_MPU_0,WKUPDEP_SMARTREFLEX_MPU_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_MPU_CONTEXT,This register contains dedicated SR_MPU context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x38++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_CORE_WKDEP,This register controls wakeup dependency based on SR_CORE service requests" bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_CORE_EVE2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_CORE_EVE2_0,WKUPDEP_SMARTREFLEX_CORE_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_CORE_EVE1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_CORE_EVE1_0,WKUPDEP_SMARTREFLEX_CORE_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_CORE_DSP2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_CORE_DSP2_0,WKUPDEP_SMARTREFLEX_CORE_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_CORE_IPU1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_CORE_IPU1_0,WKUPDEP_SMARTREFLEX_CORE_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_CORE_DSP1,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_CORE_DSP1_0,WKUPDEP_SMARTREFLEX_CORE_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_CORE_IPU2,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_CORE_IPU2_0,WKUPDEP_SMARTREFLEX_CORE_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_CORE_MPU,Wakeup dependency from SMARTREFLEX_CORE module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_CORE_MPU_0,WKUPDEP_SMARTREFLEX_CORE_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_CORE_CONTEXT,This register contains dedicated SR_CORE context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x58++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_GPU_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_GPU service requests" bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_GPU_EVE2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_GPU_EVE2_0,WKUPDEP_SMARTREFLEX_GPU_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_GPU_EVE1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_GPU_EVE1_0,WKUPDEP_SMARTREFLEX_GPU_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_GPU_DSP2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_GPU_DSP2_0,WKUPDEP_SMARTREFLEX_GPU_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_GPU_IPU1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_GPU_IPU1_0,WKUPDEP_SMARTREFLEX_GPU_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_GPU_DSP1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_GPU_DSP1_0,WKUPDEP_SMARTREFLEX_GPU_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_GPU_IPU2,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_GPU_IPU2_0,WKUPDEP_SMARTREFLEX_GPU_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_GPU_MPU,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_GPU_MPU_0,WKUPDEP_SMARTREFLEX_GPU_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_GPU_CONTEXT,This register contains dedicated SR_GPU context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x68++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_DSPEVE service requests" bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_DSPEVE_EVE1,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_0,WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_DSPEVE_DSP2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_0,WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_DSPEVE_IPU1,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_0,WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_SMARTREFLEX_DSPEVE_SDMA,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_0,WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_DSPEVE_DSP1,Wakeup dependency from SMARTREFLEX_GPU module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_0,WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_DSPEVE_IPU2,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_0,WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_DSPEVE_MPU,Wakeup dependency from SMARTREFLEX_DSPEVE module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_DSPEVE_MPU_0,WKUPDEP_SMARTREFLEX_DSPEVE_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT,This register contains dedicated SR_DSPEVE context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x78++0x07 line.long 0x00 "PM_COREAON_SMARTREFLEX_IVAHD_WKDEP,This register controls wakeup dependency based on SMARTREFLEX_IVAHD service requests" bitfld.long 0x00 7. "WKUPDEP_SMARTREFLEX_IVAHD_EVE2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_IVAHD_EVE2_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_SMARTREFLEX_IVAHD_EVE1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_IVAHD_EVE1_0,WKUPDEP_SMARTREFLEX_IVAHD_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SMARTREFLEX_IVAHD_DSP2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_IVAHD_DSP2_0,WKUPDEP_SMARTREFLEX_IVAHD_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_SMARTREFLEX_IVAHD_IPU1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_IVAHD_IPU1_0,WKUPDEP_SMARTREFLEX_IVAHD_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_SMARTREFLEX_IVAHD_DSP1,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_IVAHD_DSP1_0,WKUPDEP_SMARTREFLEX_IVAHD_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_SMARTREFLEX_IVAHD_IPU2,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_IVAHD_IPU2_0,WKUPDEP_SMARTREFLEX_IVAHD_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SMARTREFLEX_IVAHD_MPU,Wakeup dependency from SMARTREFLEX_IVAHD module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SMARTREFLEX_IVAHD_MPU_0,WKUPDEP_SMARTREFLEX_IVAHD_MPU_1" line.long 0x04 "RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT,This register contains dedicated SR_IVA context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "CUSTEFUSE_PRM" base ad:0x4AE07600 group.long 0x00++0x07 line.long 0x00 "PM_CUSTEFUSE_PWRSTCTRL,This register controls the CUSTEFUSE power state to reach upon a domain sleep transition" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_CUSTEFUSE_PWRSTST,This register provides a status on the current CUSTEFUSE power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,This register contains dedicated CUSTEFUSE module context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "DEVICE_PRM" base ad:0x4AE07D00 group.long 0x00++0x0F line.long 0x00 "PRM_RSTCTRL,Global software cold and warm reset control" bitfld.long 0x00 1. "RST_GLOBAL_COLD_SW,Global COLD software reset control" "RST_GLOBAL_COLD_SW_0,RST_GLOBAL_COLD_SW_1" bitfld.long 0x00 0. "RST_GLOBAL_WARM_SW,Global WARM software reset control" "RST_GLOBAL_WARM_SW_0,RST_GLOBAL_WARM_SW_1" line.long 0x04 "PRM_RSTST,This register logs the global reset sources" bitfld.long 0x04 16. "TSHUT_IVA_RST,TSHUT_IVA warm reset event" "TSHUT_IVA_RST_0,TSHUT_IVA_RST_1" bitfld.long 0x04 15. "TSHUT_DSPEVE_RST,TSHUT_DSPEVE warm reset event" "TSHUT_DSPEVE_RST_0,TSHUT_DSPEVE_RST_1" newline bitfld.long 0x04 13. "TSHUT_CORE_RST,TSHUT_CORE warm reset event" "TSHUT_CORE_RST_0,TSHUT_CORE_RST_1" bitfld.long 0x04 12. "TSHUT_MM_RST,TSHUT_GPU warm reset event" "TSHUT_MM_RST_0,TSHUT_MM_RST_1" newline bitfld.long 0x04 11. "TSHUT_MPU_RST,TSHUT_MPU warm reset event" "TSHUT_MPU_RST_0,TSHUT_MPU_RST_1" bitfld.long 0x04 9. "ICEPICK_RST,IcePick reset event" "ICEPICK_RST_0,ICEPICK_RST_1" newline bitfld.long 0x04 5. "EXTERNAL_WARM_RST,External warm reset event - _0X0" "EXTERNAL_WARM_RST_0,EXTERNAL_WARM_RST_1" bitfld.long 0x04 3. "MPU_WDT_RST,MPU Watchdog timer reset event" "MPU_WDT_RST_0,MPU_WDT_RST_1" newline bitfld.long 0x04 1. "GLOBAL_WARM_SW_RST,Global warm software reset event - _0X0" "GLOBAL_WARM_SW_RST_0,GLOBAL_WARM_SW_RST_1" bitfld.long 0x04 0. "GLOBAL_COLD_RST,Power-on (cold) reset event - _0X0" "GLOBAL_COLD_RST_0,GLOBAL_COLD_RST_1" line.long 0x08 "PRM_RSTTIME,Reset duration control" bitfld.long 0x08 10.--14. "RSTTIME2,Power domain reset duration 2 in number of RM.SYSCLK clock cycles" "RSTTIME2_0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" hexmask.long.word 0x08 0.--9. 1. "RSTTIME1,Global reset duration 1 in number of Func_32k_clk clock cycles" line.long 0x0C "PRM_CLKREQCTRL,This register allows controlling the CLKREQ signal towards SCRM" bitfld.long 0x0C 0.--2. "CLKREQ_COND,Control upon which condition CLKREQ signal is de-asserted" "CLKREQ_COND_0,CLKREQ_COND_1,CLKREQ_COND_2,CLKREQ_COND_3,CLKREQ_COND_4,CLKREQ_COND_5,CLKREQ_COND_6,CLKREQ_COND_7" group.long 0x18++0x0B line.long 0x00 "PRM_PSCON_COUNT,This register allows controlling 2 parameters for power state controller" hexmask.long.byte 0x00 16.--23. 1. "HG_PONOUT_2_PGOODIN_TIME,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS" hexmask.long.byte 0x00 8.--15. 1. "PONOUT_2_PGOODIN_TIME,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS" newline hexmask.long.byte 0x00 0.--7. 1. "PCHARGE_TIME,Number of system clock cycles for the SRAM pre-charge duration" line.long 0x04 "PRM_IO_COUNT,This register allows controlling LPDDR2 IO isolation removal setup" hexmask.long.byte 0x04 0.--7. 1. "ISO_2_ON_TIME,Determines the setup time of the LPDDR2 IOs going out of isolation" line.long 0x08 "PRM_IO_PMCTRL,This register allows controlling power management features of the IOs" bitfld.long 0x08 16. "GLOBAL_WUEN,Global IO wakeup enable" "GLOBAL_WUEN_0,GLOBAL_WUEN_1" rbitfld.long 0x08 9. "WUCLK_STATUS,Gives value of WUCLKOUT signal coming back from IO pad ring" "WUCLK_STATUS_0,WUCLK_STATUS_1" newline bitfld.long 0x08 8. "WUCLK_CTRL,Direct control on WUCLKIN signal to IO pad ring" "WUCLK_CTRL_0,WUCLK_CTRL_1" rbitfld.long 0x08 5. "IO_ON_STATUS,Gives the functional status of the IO ring" "IO_ON_STATUS_0,IO_ON_STATUS_1" newline bitfld.long 0x08 4. "ISOOVR_EXTEND,Control non-EMIF IO isolation extension upon a device wakeup from OFF mode" "ISOOVR_EXTEND_0,ISOOVR_EXTEND_1" rbitfld.long 0x08 1. "ISOCLK_STATUS,Gives value of ISOCLKOUT signal coming back from IO pad ring" "ISOCLK_STATUS_0,ISOCLK_STATUS_1" newline bitfld.long 0x08 0. "ISOCLK_OVERRIDE,Override control on ISOCLKIN signal to IO pad ring" "ISOCLK_OVERRIDE_0,ISOCLK_OVERRIDE_1" group.long 0xBC++0x03 line.long 0x00 "PRM_SRAM_COUNT,Common setup for SRAM LDO transition counters" hexmask.long.byte 0x00 24.--31. 1. "STARTUP_COUNT,Determines the start-up duration of SRAM and ABB LDO" hexmask.long.byte 0x00 16.--23. 1. "SLPCNT_VALUE,Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high" newline hexmask.long.byte 0x00 8.--15. 1. "VSETUPCNT_VALUE,SRAM LDO rampup time from retention to active mode" bitfld.long 0x00 0.--5. "PCHARGECNT_VALUE,Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC4++0x3F line.long 0x00 "PRM_SLDO_CORE_SETUP,Setup of the SRAM LDO for CORE voltage domain" bitfld.long 0x00 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x00 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x00 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x00 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x00 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x00 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x00 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x00 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x00 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x04 "PRM_SLDO_CORE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" bitfld.long 0x04 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" bitfld.long 0x04 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x04 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,?" line.long 0x08 "PRM_SLDO_MPU_SETUP,Setup of the SRAM LDO for MPU voltage domain" bitfld.long 0x08 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x08 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x08 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x08 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x08 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x08 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x08 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x08 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x08 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x0C "PRM_SLDO_MPU_CTRL,Control and status of the SRAM LDO for MPU voltage domain" rbitfld.long 0x0C 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" rbitfld.long 0x0C 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x0C 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x10 "PRM_SLDO_GPU_SETUP,Setup of the SRAM LDO for GPU voltage domain" bitfld.long 0x10 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x10 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x10 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x10 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x10 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x10 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x10 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x10 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x10 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x14 "PRM_SLDO_GPU_CTRL,Control and status of the SRAM LDO for GPU voltage domain" rbitfld.long 0x14 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" rbitfld.long 0x14 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x14 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x18 "PRM_ABBLDO_MPU_SETUP,Selects the MPU_ABB LDO mode" hexmask.long.byte 0x18 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" bitfld.long 0x18 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline bitfld.long 0x18 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" bitfld.long 0x18 0. "SR2EN,Enable ABB power management - BYPASS" "SR2EN_0,SR2EN_1" line.long 0x1C "PRM_ABBLDO_MPU_CTRL,Control and Status of ABB on MPU voltage domain" rbitfld.long 0x1C 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" rbitfld.long 0x1C 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status - BYPASS" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x1C 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x1C 0.--1. "OPP_SEL,Selects the OPP at which the MPU voltage domain is operating - DEFAULT_NOMINAL" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0x20 "PRM_ABBLDO_GPU_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.byte 0x20 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" bitfld.long 0x20 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline bitfld.long 0x20 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" bitfld.long 0x20 0. "SR2EN,Enable ABB power management - BYPASS" "SR2EN_0,SR2EN_1" line.long 0x24 "PRM_ABBLDO_GPU_CTRL,Control and Status of ABB on GPU voltage domain" rbitfld.long 0x24 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" rbitfld.long 0x24 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status - BYPASS" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x24 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x24 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP) - DEFAULT_NOMINAL" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0x28 "PRM_BANDGAP_SETUP,Setup of the bandgap" hexmask.long.byte 0x28 0.--7. 1. "STARTUP_COUNT,Determines the start-up duration of BANDGAP" line.long 0x2C "PRM_DEVICE_OFF_CTRL,This register is used to control device OFF transition" bitfld.long 0x2C 9. "EMIF2_OFFWKUP_DISABLE,Controls the EMIF2_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF1 upon a device wakeup from OFF mode" "EMIF2_OFFWKUP_DISABLE_0,EMIF2_OFFWKUP_DISABLE_1" bitfld.long 0x2C 8. "EMIF1_OFFWKUP_DISABLE,Controls the EMIF1_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF2 upon a device wakeup from OFF mode" "EMIF1_OFFWKUP_DISABLE_0,EMIF1_OFFWKUP_DISABLE_1" newline bitfld.long 0x2C 0. "DEVICE_OFF_ENABLE,Controls transition to device OFF mode" "DEVICE_OFF_ENABLE_0,DEVICE_OFF_ENABLE_1" line.long 0x30 "PRM_PHASE1_CNDP,This register stores the start descriptor address of automatic restore phase1" line.long 0x34 "PRM_PHASE2A_CNDP,This register stores the start descriptor address of automatic restore phase2A" line.long 0x38 "PRM_PHASE2B_CNDP,This register stores the start descriptor address of automatic restore phase2B" line.long 0x3C "PRM_MODEM_IF_CTRL,This register is used to control dedicated interfaces between on-chip modem and APE" bitfld.long 0x3C 9. "MODEM_SHUTDOWN_IRQ,Controls an interrupt signal to shutdown modem" "MODEM_SHUTDOWN_IRQ_0,MODEM_SHUTDOWN_IRQ_1" bitfld.long 0x3C 8. "MODEM_WAKE_IRQ,Controls an interrupt signal to wakeup modem" "MODEM_WAKE_IRQ_0,MODEM_WAKE_IRQ_1" group.long 0x118++0x1F line.long 0x00 "PRM_SLDO_DSPEVE_SETUP,Setup of the SRAM LDO for DSPEVE voltage domain" bitfld.long 0x00 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x00 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x00 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x00 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x00 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x00 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x00 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x00 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x00 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x04 "PRM_SLDO_IVA_SETUP,Setup of the SRAM LDO for IVA voltage domain" bitfld.long 0x04 8. "AIPOFF,Override on AIPOFF input of SRAM LDO" "AIPOFF_0,AIPOFF_1" bitfld.long 0x04 7. "ENFUNC5,ENFUNC5 input of SRAM LDO" "ENFUNC5_0,ENFUNC5_1" newline bitfld.long 0x04 6. "ENFUNC4,ENFUNC4 input of SRAM LDO" "ENFUNC4_0,ENFUNC4_1" bitfld.long 0x04 5. "ENFUNC3,ENFUNC3 input of SRAM LDO" "ENFUNC3_0,ENFUNC3_1" newline bitfld.long 0x04 4. "ENFUNC2,ENFUNC2 input of SRAM LDO" "ENFUNC2_0,ENFUNC2_1" bitfld.long 0x04 3. "ENFUNC1,ENFUNC1 input of SRAM LDO" "ENFUNC1_0,ENFUNC1_1" newline bitfld.long 0x04 2. "ABBOFF_SLEEP,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "ABBOFF_SLEEP_0,ABBOFF_SLEEP_1" bitfld.long 0x04 1. "ABBOFF_ACT,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "ABBOFF_ACT_0,ABBOFF_ACT_1" newline bitfld.long 0x04 0. "ENABLE_RTA,Control for HD memory RTA feature" "ENABLE_RTA_0,ENABLE_RTA_1" line.long 0x08 "PRM_ABBLDO_DSPEVE_CTRL,Control and Status of ABB on DSPEVE voltage domain" rbitfld.long 0x08 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" rbitfld.long 0x08 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status - BYPASS" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x08 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x08 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP) - DEFAULT_NOMINAL" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0x0C "PRM_ABBLDO_IVA_CTRL,Control and Status of ABB on IVA voltage domain" rbitfld.long 0x0C 6. "SR2_IN_TRANSITION,Indicates VBBLDO_CON is or is not in transition state" "SR2_IN_TRANSITION_0,SR2_IN_TRANSITION_1" rbitfld.long 0x0C 3.--4. "SR2_STATUS,Indicate ABB LDO current operation status - BYPASS" "SR2_STATUS_0,SR2_STATUS_1,SR2_STATUS_2,SR2_STATUS_3" newline bitfld.long 0x0C 2. "OPP_CHANGE,When OPP_CHANGE is set to 1 VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge" "0,1" bitfld.long 0x0C 0.--1. "OPP_SEL,Selects the OPP at which the MM voltage domain is operating (Fast OPP Nominal OPP or Slow OPP) - DEFAULT_NOMINAL" "OPP_SEL_0,OPP_SEL_1,OPP_SEL_2,OPP_SEL_3" line.long 0x10 "PRM_SLDO_DSPEVE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" rbitfld.long 0x10 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" rbitfld.long 0x10 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x10 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x14 "PRM_SLDO_IVA_CTRL,Control and status of the SRAM LDO for CORE voltage domain" rbitfld.long 0x14 9. "SRAM_IN_TRANSITION,Status indicating SRAM LDO state machine state" "SRAM_IN_TRANSITION_0,SRAM_IN_TRANSITION_1" rbitfld.long 0x14 8. "SRAMLDO_STATUS,SRAMLDO status - ACTIVE" "SRAMLDO_STATUS_0,SRAMLDO_STATUS_1" newline bitfld.long 0x14 0. "RETMODE_ENABLE,Control if the SRAM LDO retention mode is used or not" "RETMODE_ENABLE_0,RETMODE_ENABLE_1" line.long 0x18 "PRM_ABBLDO_DSPEVE_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.byte 0x18 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" bitfld.long 0x18 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline bitfld.long 0x18 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" bitfld.long 0x18 0. "SR2EN,Enable ABB power management - BYPASS" "SR2EN_0,SR2EN_1" line.long 0x1C "PRM_ABBLDO_IVA_SETUP,Selects the GPU_ABB LDO mode" hexmask.long.byte 0x1C 8.--15. 1. "SR2_WTCNT_VALUE,LDO settling time for active-mode OPP change" bitfld.long 0x1C 4. "NOCAP,Defines whether ABB LDO is cap-less or not" "NOCAP_0,NOCAP_1" newline bitfld.long 0x1C 2. "ACTIVE_FBB_SEL,Defines ABB LDO mode when voltage is in slow fast OPP" "ACTIVE_FBB_SEL_0,ACTIVE_FBB_SEL_1" bitfld.long 0x1C 0. "SR2EN,Enable ABB power management - BYPASS" "SR2EN_0,SR2EN_1" tree.end tree "DSP1_PRM" base ad:0x4AE06400 group.long 0x00++0x07 line.long 0x00 "PM_DSP1_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" rbitfld.long 0x00 20.--21. "DSP1_EDMA_ONSTATE,DSP_EDMA state when domain is ON" "?,?,?,DSP1_EDMA_ONSTATE_3" rbitfld.long 0x00 18.--19. "DSP1_L2_ONSTATE,DSP_L2 state when domain is ON" "?,?,?,DSP1_L2_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "DSP1_L1_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,DSP1_L1_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSP1_PWRSTST,This register provides a status on the DSP domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 8.--9. "DSP1_EDMA_STATEST,DSP_EDMA memory state status - MEM_OFF" "DSP1_EDMA_STATEST_0,DSP1_EDMA_STATEST_1,DSP1_EDMA_STATEST_2,DSP1_EDMA_STATEST_3" rbitfld.long 0x04 6.--7. "DSP1_L2_STATEST,DSP_L2 memory state status - MEM_OFF" "DSP1_L2_STATEST_0,DSP1_L2_STATEST_1,DSP1_L2_STATEST_2,DSP1_L2_STATEST_3" newline rbitfld.long 0x04 4.--5. "DSP1_L1_STATEST,DSP_L1 memory state status - MEM_OFF" "DSP1_L1_STATEST_0,DSP1_L1_STATEST_1,DSP1_L1_STATEST_2,DSP1_L1_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_DSP1_RSTCTRL,This register controls the release of the DSP sub-system resets" bitfld.long 0x00 1. "RST_DSP1,DSP reset control - CLEAR" "RST_DSP1_0,RST_DSP1_1" bitfld.long 0x00 0. "RST_DSP1_LRST,DSP Local reset control - CLEAR" "RST_DSP1_LRST_0,RST_DSP1_LRST_1" line.long 0x04 "RM_DSP1_RSTST,This register logs the different reset sources of the DSP domain" bitfld.long 0x04 3. "RST_DSP1_EMU_REQ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS - RESET_NO" "RST_DSP1_EMU_REQ_0,RST_DSP1_EMU_REQ_1" bitfld.long 0x04 2. "RST_DSP1_EMU,DSP domain has been reset due to emulation reset source e.g" "RST_DSP1_EMU_0,RST_DSP1_EMU_1" newline bitfld.long 0x04 1. "RST_DSP1,DSP SW reset status - RESET_NO" "RST_DSP1_0,RST_DSP1_1" bitfld.long 0x04 0. "RST_DSP1_LRST,DSP Local SW reset - RESET_NO" "RST_DSP1_LRST_0,RST_DSP1_LRST_1" group.long 0x24++0x03 line.long 0x00 "RM_DSP1_DSP1_CONTEXT,This register contains dedicated DSP context statuses" bitfld.long 0x00 10. "LOSTMEM_DSP_EDMA,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_EDMA_0,LOSTMEM_DSP_EDMA_1" bitfld.long 0x00 9. "LOSTMEM_DSP_L2,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L2_0,LOSTMEM_DSP_L2_1" newline bitfld.long 0x00 8. "LOSTMEM_DSP_L1,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L1_0,LOSTMEM_DSP_L1_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "DSP2_PRM" base ad:0x4AE07B00 group.long 0x00++0x07 line.long 0x00 "PM_DSP2_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" rbitfld.long 0x00 20.--21. "DSP2_EDMA_ONSTATE,DSP_EDMA state when domain is ON" "?,?,?,DSP2_EDMA_ONSTATE_3" rbitfld.long 0x00 18.--19. "DSP2_L2_ONSTATE,DSP_L2 state when domain is ON" "?,?,?,DSP2_L2_ONSTATE_3" newline rbitfld.long 0x00 16.--17. "DSP2_L1_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,DSP2_L1_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSP2_PWRSTST,This register provides a status on the DSP domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 8.--9. "DSP2_EDMA_STATEST,RSERVED - MEM_OFF" "DSP2_EDMA_STATEST_0,DSP2_EDMA_STATEST_1,DSP2_EDMA_STATEST_2,DSP2_EDMA_STATEST_3" rbitfld.long 0x04 6.--7. "DSP2_L2_STATEST,DSP_L2 memory state status - MEM_OFF" "DSP2_L2_STATEST_0,DSP2_L2_STATEST_1,DSP2_L2_STATEST_2,DSP2_L2_STATEST_3" newline rbitfld.long 0x04 4.--5. "DSP2_L1_STATEST,DSP_L1 memory state status - MEM_OFF" "DSP2_L1_STATEST_0,DSP2_L1_STATEST_1,DSP2_L1_STATEST_2,DSP2_L1_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_DSP2_RSTCTRL,This register controls the release of the DSP sub-system resets" bitfld.long 0x00 1. "RST_DSP2,DSP SW reset control - CLEAR" "RST_DSP2_0,RST_DSP2_1" bitfld.long 0x00 0. "RST_DSP2_LRST,DSP Local reset control - CLEAR" "RST_DSP2_LRST_0,RST_DSP2_LRST_1" line.long 0x04 "RM_DSP2_RSTST,This register logs the different reset sources of the DSP domain" bitfld.long 0x04 3. "RST_DSP2_EMU_REQ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS - RESET_NO" "RST_DSP2_EMU_REQ_0,RST_DSP2_EMU_REQ_1" bitfld.long 0x04 2. "RST_DSP2_EMU,DSP domain has been reset due to emulation reset source e.g" "RST_DSP2_EMU_0,RST_DSP2_EMU_1" newline bitfld.long 0x04 1. "RST_DSP2,DSP SW reset status - RESET_NO" "RST_DSP2_0,RST_DSP2_1" bitfld.long 0x04 0. "RST_DSP2_LRST,DSP Local SW reset - RESET_NO" "RST_DSP2_LRST_0,RST_DSP2_LRST_1" group.long 0x24++0x03 line.long 0x00 "RM_DSP2_DSP2_CONTEXT,This register contains dedicated DSP context statuses" bitfld.long 0x00 10. "LOSTMEM_DSP_EDMA,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_EDMA_0,LOSTMEM_DSP_EDMA_1" bitfld.long 0x00 9. "LOSTMEM_DSP_L2,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L2_0,LOSTMEM_DSP_L2_1" newline bitfld.long 0x00 8. "LOSTMEM_DSP_L1,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSP_L1_0,LOSTMEM_DSP_L1_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "DSS_PRM" base ad:0x4AE07100 group.long 0x00++0x07 line.long 0x00 "PM_DSS_PWRSTCTRL,This register controls the DSS power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "DSS_MEM_ONSTATE,DSS_MEM state when domain is ON" "?,?,?,DSS_MEM_ONSTATE_3" rbitfld.long 0x00 8. "DSS_MEM_RETSTATE,DSS_MEM state when domain is RETENTION" "DSS_MEM_RETSTATE_0,?" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_DSS_PWRSTST,This register provides a status on the current DSS power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 4.--5. "DSS_MEM_STATEST,DSS_MEM state status - MEM_OFF" "DSS_MEM_STATEST_0,DSS_MEM_STATEST_1,DSS_MEM_STATEST_2,DSS_MEM_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x0B line.long 0x00 "PM_DSS_DSS_WKDEP,This register controls wakeup dependency based on DSS service requests" bitfld.long 0x00 27. "WKUPDEP_DSI1_B_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_EVE2_0,WKUPDEP_DSI1_B_EVE2_1" bitfld.long 0x00 26. "WKUPDEP_DSI1_B_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_EVE1_0,WKUPDEP_DSI1_B_EVE1_1" newline bitfld.long 0x00 25. "WKUPDEP_DSI1_B_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_DSP2_0,WKUPDEP_DSI1_B_DSP2_1" bitfld.long 0x00 24. "WKUPDEP_DSI1_B_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_IPU1_0,WKUPDEP_DSI1_B_IPU1_1" newline bitfld.long 0x00 23. "WKUPDEP_DSI1_B_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_SDMA_0,WKUPDEP_DSI1_B_SDMA_1" bitfld.long 0x00 22. "WKUPDEP_DSI1_B_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_DSP1_0,WKUPDEP_DSI1_B_DSP1_1" newline bitfld.long 0x00 21. "WKUPDEP_DSI1_B_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_IPU2_0,WKUPDEP_DSI1_B_IPU2_1" bitfld.long 0x00 20. "WKUPDEP_DSI1_B_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_B_MPU_0,WKUPDEP_DSI1_B_MPU_1" newline bitfld.long 0x00 17. "WKUPDEP_DSI1_A_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_EVE2_0,WKUPDEP_DSI1_A_EVE2_1" bitfld.long 0x00 16. "WKUPDEP_DSI1_A_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_EVE1_0,WKUPDEP_DSI1_A_EVE1_1" newline bitfld.long 0x00 15. "WKUPDEP_DSI1_A_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_DSP2_0,WKUPDEP_DSI1_A_DSP2_1" bitfld.long 0x00 14. "WKUPDEP_DSI1_A_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_IPU1_0,WKUPDEP_DSI1_A_IPU1_1" newline bitfld.long 0x00 13. "WKUPDEP_DSI1_A_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_SDMA_0,WKUPDEP_DSI1_A_SDMA_1" bitfld.long 0x00 12. "WKUPDEP_DSI1_A_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_DSP1_0,WKUPDEP_DSI1_A_DSP1_1" newline bitfld.long 0x00 11. "WKUPDEP_DSI1_A_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_IPU2_0,WKUPDEP_DSI1_A_IPU2_1" bitfld.long 0x00 10. "WKUPDEP_DSI1_A_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_A_MPU_0,WKUPDEP_DSI1_A_MPU_1" newline bitfld.long 0x00 7. "WKUPDEP_DISPC_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_EVE2_0,WKUPDEP_DISPC_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_DISPC_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_EVE1_0,WKUPDEP_DISPC_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_DISPC_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_DSP2_0,WKUPDEP_DISPC_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_DISPC_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_IPU1_0,WKUPDEP_DISPC_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_DISPC_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_SDMA_0,WKUPDEP_DISPC_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_DISPC_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_DSP1_0,WKUPDEP_DISPC_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_DISPC_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_IPU2_0,WKUPDEP_DISPC_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_DISPC_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DISPC_MPU_0,WKUPDEP_DISPC_MPU_1" line.long 0x04 "RM_DSS_DSS_CONTEXT,This register contains dedicated DSS context statuses" bitfld.long 0x04 8. "LOSTMEM_DSS_MEM,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSS_MEM_0,LOSTMEM_DSS_MEM_1" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_DSS_DSS2_WKDEP,This register controls wakeup dependency based on DSS service requests" bitfld.long 0x08 25. "WKUPDEP_HDMIDMA_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIDMA_DSP2_0,WKUPDEP_HDMIDMA_DSP2_1" bitfld.long 0x08 23. "WKUPDEP_HDMIDMA_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIDMA_SDMA_0,WKUPDEP_HDMIDMA_SDMA_1" newline bitfld.long 0x08 22. "WKUPDEP_HDMIDMA_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIDMA_DSP1_0,WKUPDEP_HDMIDMA_DSP1_1" bitfld.long 0x08 17. "WKUPDEP_DSI1_C_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_EVE2_0,WKUPDEP_DSI1_C_EVE2_1" newline bitfld.long 0x08 16. "WKUPDEP_DSI1_C_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_EVE1_0,WKUPDEP_DSI1_C_EVE1_1" bitfld.long 0x08 15. "WKUPDEP_DSI1_C_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_DSP2_0,WKUPDEP_DSI1_C_DSP2_1" newline bitfld.long 0x08 14. "WKUPDEP_DSI1_C_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_IPU1_0,WKUPDEP_DSI1_C_IPU1_1" bitfld.long 0x08 13. "WKUPDEP_DSI1_C_SDMA,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_SDMA_0,WKUPDEP_DSI1_C_SDMA_1" newline bitfld.long 0x08 12. "WKUPDEP_DSI1_C_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_DSP1_0,WKUPDEP_DSI1_C_DSP1_1" bitfld.long 0x08 11. "WKUPDEP_DSI1_C_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_IPU2_0,WKUPDEP_DSI1_C_IPU2_1" newline bitfld.long 0x08 10. "WKUPDEP_DSI1_C_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DSI1_C_MPU_0,WKUPDEP_DSI1_C_MPU_1" bitfld.long 0x08 7. "WKUPDEP_HDMIIRQ_EVE2,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_EVE2_0,WKUPDEP_HDMIIRQ_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_HDMIIRQ_EVE1,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_EVE1_0,WKUPDEP_HDMIIRQ_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_HDMIIRQ_DSP2,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_DSP2_0,WKUPDEP_HDMIIRQ_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_HDMIIRQ_IPU1,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_IPU1_0,WKUPDEP_HDMIIRQ_IPU1_1" bitfld.long 0x08 2. "WKUPDEP_HDMIIRQ_DSP1,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_DSP1_0,WKUPDEP_HDMIIRQ_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_HDMIIRQ_IPU2,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_IPU2_0,WKUPDEP_HDMIIRQ_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_HDMIIRQ_MPU,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_HDMIIRQ_MPU_0,WKUPDEP_HDMIIRQ_MPU_1" group.long 0x34++0x03 line.long 0x00 "RM_DSS_BB2D_CONTEXT,This register contains dedicated BB2B context statuses" bitfld.long 0x00 8. "LOSTMEM_DSS_MEM,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DSS_MEM_0,LOSTMEM_DSS_MEM_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "EMU_CM" base ad:0x4AE07A00 group.long 0x00++0x0F line.long 0x00 "CM_EMU_CLKSTCTRL,This register enables the EMU domain power state transition" rbitfld.long 0x00 8. "CLKACTIVITY_EMU_SYS_CLK,This field indicates the state of the EMU_SYS_CLK clock in the domain" "CLKACTIVITY_EMU_SYS_CLK_0,CLKACTIVITY_EMU_SYS_CLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the EMU clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" line.long 0x04 "CM_EMU_DEBUGSS_CLKCTRL,This register manages the DEBUGSS clocks" bitfld.long 0x04 18. "STBYST,Module standby status - FUNC" "STBYST_0,STBYST_1" bitfld.long 0x04 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x04 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" line.long 0x08 "CM_EMU_DYNAMICDEP,This register controls the dynamic domain depedencies from EMU domain towards 'target' domains" bitfld.long 0x08 24.--27. "WINDOWSIZE,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature" "WINDOWSIZE_0,WINDOWSIZE_1,WINDOWSIZE_2,WINDOWSIZE_3,WINDOWSIZE_4,WINDOWSIZE_5,WINDOWSIZE_6,WINDOWSIZE_7,WINDOWSIZE_8,WINDOWSIZE_9,WINDOWSIZE_10,WINDOWSIZE_11,WINDOWSIZE_12,WINDOWSIZE_13,WINDOWSIZE_14,WINDOWSIZE_15" rbitfld.long 0x08 5. "L3MAIN1_DYNDEP,Dynamic dependency towards L3MAIN1 clock domain - ENABLED" "?,L3MAIN1_DYNDEP_1" line.long 0x0C "CM_EMU_MPU_EMU_DBG_CLKCTRL,This register manages the MPU_EMU_DBG clocks" bitfld.long 0x0C 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x0C 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" tree.end tree "EMU_PRM" base ad:0x4AE07900 rgroup.long 0x00++0x07 line.long 0x00 "PM_EMU_PWRSTCTRL,This register controls the EMU power state to reach upon a domain sleep transition" bitfld.long 0x00 16.--17. "EMU_BANK_ONSTATE,EMU memory state when domain is ON" "?,?,?,EMU_BANK_ONSTATE_3" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,?,?,?" line.long 0x04 "PM_EMU_PWRSTST,This register provides a status on the EMU domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 4.--5. "EMU_BANK_STATEST,EMU memory bank state status - MEM_OFF" "EMU_BANK_STATEST_0,EMU_BANK_STATEST_1,EMU_BANK_STATEST_2,EMU_BANK_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,?,?,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_EMU_DEBUGSS_CONTEXT,This register contains dedicated DEBUGSS context statuses" bitfld.long 0x00 8. "LOSTMEM_EMU_BANK,Specify if memory-based context in EMU_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EMU_BANK_0,LOSTMEM_EMU_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "EVE1_PRM" base ad:0x4AE07B40 group.long 0x00++0x07 line.long 0x00 "PM_EVE1_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "EVE1_BANK_ONSTATE,EVE1 state when domain is ON" "?,?,?,EVE1_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE1_PWRSTST,This register provides a status on the EVE domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 4.--5. "EVE1_BANK_STATEST,EVE0 memory state status - MEM_OFF" "EVE1_BANK_STATEST_0,EVE1_BANK_STATEST_1,EVE1_BANK_STATEST_2,EVE1_BANK_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE1_RSTCTRL,This register controls the release of the EVE sub-system resets" bitfld.long 0x00 1. "RST_EVE1,EVE reset control - CLEAR" "RST_EVE1_0,RST_EVE1_1" bitfld.long 0x00 0. "RST_EVE1_LRST,EVE Local reset control - CLEAR" "RST_EVE1_LRST_0,RST_EVE1_LRST_1" line.long 0x04 "RM_EVE1_RSTST,This register logs the different reset sources of the EVE domain" bitfld.long 0x04 3. "RST_EVE1_EMU_REQ,EVE1 processor has been reset due to EVE emulation reset request driven from EVE1-SS - RESET_NO" "RST_EVE1_EMU_REQ_0,RST_EVE1_EMU_REQ_1" bitfld.long 0x04 2. "RST_EVE1_EMU,EVE1 domain has been reset due to emulation reset source e.g" "RST_EVE1_EMU_0,RST_EVE1_EMU_1" newline bitfld.long 0x04 1. "RST_EVE1,EVE0 SW reset status - RESET_NO" "RST_EVE1_0,RST_EVE1_1" bitfld.long 0x04 0. "RST_EVE1_LRST,EVE0 Local SW reset - RESET_NO" "RST_EVE1_LRST_0,RST_EVE1_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE1_EVE1_WKDEP,This register controls wakeup dependency based on EVE1 service requests" bitfld.long 0x00 7. "WKUPDEP_EVE1_EVE2,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_EVE2_0,WKUPDEP_EVE1_EVE2_1" bitfld.long 0x00 5. "WKUPDEP_EVE1_DSP2,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_DSP2_0,WKUPDEP_EVE1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE1_IPU1,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_IPU1_0,WKUPDEP_EVE1_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE1_SDMA,Wakeup dependency from EVE1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_SDMA_0,WKUPDEP_EVE1_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE1_DSP1,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_DSP1_0,WKUPDEP_EVE1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE1_IPU2,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_IPU2_0,WKUPDEP_EVE1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE1_MPU,Wakeup dependency from EVE1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE1_MPU_0,WKUPDEP_EVE1_MPU_1" line.long 0x04 "RM_EVE1_EVE1_CONTEXT,This register contains dedicated EVE context statuses" bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "EVE2_PRM" base ad:0x4AE07B80 group.long 0x00++0x07 line.long 0x00 "PM_EVE2_PWRSTCTRL,This register controls the EVE power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "EVE2_BANK_ONSTATE,EVE2 state when domain is ON" "?,?,?,EVE2_BANK_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_EVE2_PWRSTST,This register provides a status on the EVE domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 4.--5. "EVE2_BANK_STATEST,EVE2 memory state status - MEM_OFF" "EVE2_BANK_STATEST_0,EVE2_BANK_STATEST_1,EVE2_BANK_STATEST_2,EVE2_BANK_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_EVE2_RSTCTRL,This register controls the release of the EVE sub-system resets" bitfld.long 0x00 1. "RST_EVE2,EVE SW reset control - CLEAR" "RST_EVE2_0,RST_EVE2_1" bitfld.long 0x00 0. "RST_EVE2_LRST,EVE Local reset control - CLEAR" "RST_EVE2_LRST_0,RST_EVE2_LRST_1" line.long 0x04 "RM_EVE2_RSTST,This register logs the different reset sources of the EVE domain" bitfld.long 0x04 3. "RST_EVE2_EMU_REQ,EVE2 processor has been reset due to EVE emulation reset request driven from EVE2-SS - RESET_NO" "RST_EVE2_EMU_REQ_0,RST_EVE2_EMU_REQ_1" bitfld.long 0x04 2. "RST_EVE2_EMU,EVE2 domain has been reset due to emulation reset source e.g" "RST_EVE2_EMU_0,RST_EVE2_EMU_1" newline bitfld.long 0x04 1. "RST_EVE2,EVE SW reset status - RESET_NO" "RST_EVE2_0,RST_EVE2_1" bitfld.long 0x04 0. "RST_EVE2_LRST,EVE Local SW reset - RESET_NO" "RST_EVE2_LRST_0,RST_EVE2_LRST_1" group.long 0x20++0x07 line.long 0x00 "PM_EVE2_EVE2_WKDEP,This register controls wakeup dependency based on EVE2 service requests" bitfld.long 0x00 6. "WKUPDEP_EVE2_EVE1,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_EVE1_0,WKUPDEP_EVE2_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_EVE2_DSP2,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_DSP2_0,WKUPDEP_EVE2_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_EVE2_IPU1,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_IPU1_0,WKUPDEP_EVE2_IPU1_1" bitfld.long 0x00 3. "WKUPDEP_EVE2_SDMA,Wakeup dependency from EVE2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_SDMA_0,WKUPDEP_EVE2_SDMA_1" newline bitfld.long 0x00 2. "WKUPDEP_EVE2_DSP1,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_DSP1_0,WKUPDEP_EVE2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_EVE2_IPU2,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_IPU2_0,WKUPDEP_EVE2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_EVE2_MPU,Wakeup dependency from EVE2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_EVE2_MPU_0,WKUPDEP_EVE2_MPU_1" line.long 0x04 "RM_EVE2_EVE2_CONTEXT,This register contains dedicated EVE context statuses" bitfld.long 0x04 8. "LOSTMEM_EVE_BANK,Specify if memory-based context in EVE2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_EVE_BANK_0,LOSTMEM_EVE_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "GPU_PRM" base ad:0x4AE07200 group.long 0x00++0x07 line.long 0x00 "PM_GPU_PWRSTCTRL,This register controls the GPU power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "GPU_MEM_ONSTATE,GPU_MEM memory bank state when domain is ON" "?,?,?,GPU_MEM_ONSTATE_3" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_GPU_PWRSTST,This register provides a status on the current GPU power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 4.--5. "GPU_MEM_STATEST,GPU_MEM memory bank state status - MEM_OFF" "GPU_MEM_STATEST_0,GPU_MEM_STATEST_1,GPU_MEM_STATEST_2,GPU_MEM_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_GPU_GPU_CONTEXT,This register contains dedicated GPU context statuses" bitfld.long 0x00 8. "LOSTMEM_GPU_MEM,Specify if memory-based context in GPU_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_GPU_MEM_0,LOSTMEM_GPU_MEM_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "INSTR_PRM" base ad:0x4AE07F00 rgroup.long 0x00++0x03 line.long 0x00 "PMI_IDENTICATION,PM profiling identification register" bitfld.long 0x00 30.--31. "SCHEME,Highlander 0.8 value: 0b01" "SCHEME_0,SCHEME_1,SCHEME_2,SCHEME_3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates a software compatible module family" bitfld.long 0x00 11.--15. "RTL,RTL version" "RTL_0,RTL_1,RTL_2,RTL_3,RTL_4,RTL_5,RTL_6,RTL_7,RTL_8,RTL_9,RTL_10,RTL_11,RTL_12,RTL_13,RTL_14,RTL_15,RTL_16,RTL_17,RTL_18,RTL_19,RTL_20,RTL_21,RTL_22,RTL_23,RTL_24,RTL_25,RTL_26,RTL_27,RTL_28,RTL_29,RTL_30,RTL_31" newline bitfld.long 0x00 8.--10. "MAJOR,ajor revision" "MAJOR_0,MAJOR_1,MAJOR_2,MAJOR_3,MAJOR_4,MAJOR_5,MAJOR_6,MAJOR_7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,CUSTOM_1,CUSTOM_2,CUSTOM_3" bitfld.long 0x00 0.--5. "MINOR,inor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x07 line.long 0x00 "PMI_SYS_CONFIG,PM profiling system configuartion register" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local tartget state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 0. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" line.long 0x04 "PMI_STATUS,PM profiling status register" bitfld.long 0x04 8. "FIFOEMPTY,PM Profiling buffer empty" "FIFOEMPTY_0,FIFOEMPTY_1" group.long 0x24++0x0F line.long 0x00 "PMI_CONFIGURATION,PM profiling configuration register" bitfld.long 0x00 30.--31. "CLAIM_3,Ownership" "CLAIM_3_0,CLAIM_3_1,CLAIM_3_2,CLAIM_3_3" bitfld.long 0x00 29. "CLAIM_2,Debugger override qualifier" "CLAIM_2_0,CLAIM_2_1" rbitfld.long 0x00 28. "CLAIM_1,Current owner" "CLAIM_1_0,CLAIM_1_1" newline bitfld.long 0x00 7. "EVT_CAPT_EN,When HIGH the PM events capture is enabled" "EVT_CAPT_EN_0,EVT_CAPT_EN_1" line.long 0x04 "PMI_CLASS_FILTERING,PM profiling class filtering register" bitfld.long 0x04 3. "SNAP_CAPT_EN_03,Snapshot capture enable - Class-ID = 0x03" "SNAP_CAPT_EN_03_0,SNAP_CAPT_EN_03_1" bitfld.long 0x04 2. "SNAP_CAPT_EN_02,Snapshot capture enable - Class-ID = 0x02" "SNAP_CAPT_EN_02_0,SNAP_CAPT_EN_02_1" bitfld.long 0x04 1. "SNAP_CAPT_EN_01,Snapshot capture enable - Class-ID = 0x01" "SNAP_CAPT_EN_01_0,SNAP_CAPT_EN_01_1" newline bitfld.long 0x04 0. "SNAP_CAPT_EN_00,Snapshot capture enable - Class-ID = 0x00" "SNAP_CAPT_EN_00_0,SNAP_CAPT_EN_00_1" line.long 0x08 "PMI_TRIGGERING,PM profiling triggering control register" bitfld.long 0x08 1. "TRIG_STOP_EN,Enable stop capturing PM events from external trigger detection" "TRIG_STOP_EN_0,TRIG_STOP_EN_1" bitfld.long 0x08 0. "TRIG_START_EN,Enable start capturing PM events from external trigger detection" "TRIG_START_EN_0,TRIG_START_EN_1" line.long 0x0C "PMI_SAMPLING,PM profiling sampling window register" bitfld.long 0x0C 16.--19. "FCLK_DIV_FACOR,FunClk divide factor ranging from 1 to 16" "FCLK_DIV_FACOR_0,FCLK_DIV_FACOR_1,FCLK_DIV_FACOR_2,FCLK_DIV_FACOR_3,FCLK_DIV_FACOR_4,FCLK_DIV_FACOR_5,FCLK_DIV_FACOR_6,FCLK_DIV_FACOR_7,FCLK_DIV_FACOR_8,FCLK_DIV_FACOR_9,FCLK_DIV_FACOR_10,FCLK_DIV_FACOR_11,FCLK_DIV_FACOR_12,FCLK_DIV_FACOR_13,FCLK_DIV_FACOR_14,FCLK_DIV_FACOR_15" hexmask.long.byte 0x0C 0.--7. 1. "SAMP_WIND_SIZE,PM events sampling window size" tree.end tree "IPU_PRM" base ad:0x4AE06500 group.long 0x00++0x07 line.long 0x00 "PM_IPU_PWRSTCTRL,This register controls the IPU domain power state to reach upon a domain sleep transition" rbitfld.long 0x00 20.--21. "PERIPHMEM_ONSTATE,PERIPHMEM memory state when domain is ON" "?,?,?,PERIPHMEM_ONSTATE_3" rbitfld.long 0x00 16.--17. "AESSMEM_ONSTATE,AESSMEM memory state when domain is ON" "?,?,?,AESSMEM_ONSTATE_3" newline bitfld.long 0x00 10. "PERIPHMEM_RETSTATE,PERIPHMEM memory state when domain is RETENTION" "PERIPHMEM_RETSTATE_0,PERIPHMEM_RETSTATE_1" bitfld.long 0x00 8. "AESSMEM_RETSTATE,AESSMEM memory state when domain is RETENTION" "AESSMEM_RETSTATE_0,AESSMEM_RETSTATE_1" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_IPU_PWRSTST,This register provides a status on the IPU domain current power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 8.--9. "PERIPHMEM_STATEST,PERIPHMEM memory state status - MEM_OFF" "PERIPHMEM_STATEST_0,PERIPHMEM_STATEST_1,PERIPHMEM_STATEST_2,PERIPHMEM_STATEST_3" rbitfld.long 0x04 4.--5. "AESSMEM_STATEST,AESSMEM memory state status - MEM_OFF" "AESSMEM_STATEST_0,AESSMEM_STATEST_1,AESSMEM_STATEST_2,AESSMEM_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_IPU1_RSTCTRL,This register controls the release of the IPU1 sub-system resets" bitfld.long 0x00 2. "RST_IPU,BELLINI system reset control" "RST_IPU_0,RST_IPU_1" bitfld.long 0x00 1. "RST_CPU1,BELLINI Cortex M3 CPU1 reset control - CLEAR" "RST_CPU1_0,RST_CPU1_1" newline bitfld.long 0x00 0. "RST_CPU0,BELLINI Cortex M3 CPU0 reset control" "RST_CPU0_0,RST_CPU0_1" line.long 0x04 "RM_IPU1_RSTST,This register logs the different reset sources of the IPU1 SS" bitfld.long 0x04 6. "RST_ICECRUSHER_CPU1,Cortex M3 CPU1 has been reset due to IPU ICECRUSHER1 reset source - RESET_NO" "RST_ICECRUSHER_CPU1_0,RST_ICECRUSHER_CPU1_1" bitfld.long 0x04 5. "RST_ICECRUSHER_CPU0,Cortex M3 CPU0 has been reset due to IPU ICECRUSHER0 reset source - RESET_NO" "RST_ICECRUSHER_CPU0_0,RST_ICECRUSHER_CPU0_1" newline bitfld.long 0x04 4. "RST_EMULATION_CPU1,Cortex M3 CPU1 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU1_0,RST_EMULATION_CPU1_1" bitfld.long 0x04 3. "RST_EMULATION_CPU0,Cortex M3 CPU0 has been reset due to emulation reset source e.g" "RST_EMULATION_CPU0_0,RST_EMULATION_CPU0_1" newline bitfld.long 0x04 2. "RST_IPU,IPU system SW reset status - RESET_NO" "RST_IPU_0,RST_IPU_1" bitfld.long 0x04 1. "RST_CPU1,BELLINI Cortex-M3 CPU1 SW reset status - RESET_NO" "RST_CPU1_0,RST_CPU1_1" newline bitfld.long 0x04 0. "RST_CPU0,BELLINI Cortex-M3 CPU0 SW reset status - RESET_NO" "RST_CPU0_0,RST_CPU0_1" group.long 0x24++0x03 line.long 0x00 "RM_IPU1_IPU1_CONTEXT,This register contains dedicated IPU1 context statuses" bitfld.long 0x00 9. "LOSTMEM_IPU_L2RAM,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_L2RAM_0,LOSTMEM_IPU_L2RAM_1" bitfld.long 0x00 8. "LOSTMEM_IPU_UNICACHE,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_IPU_UNICACHE_0,LOSTMEM_IPU_UNICACHE_1" newline bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x50++0x37 line.long 0x00 "PM_IPU_MCASP1_WKDEP,This register controls wakeup dependency based on MCASP1 service requests" bitfld.long 0x00 15. "WKUPDEP_MCASP1_DMA_DSP2,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_DMA_DSP2_0,WKUPDEP_MCASP1_DMA_DSP2_1" bitfld.long 0x00 13. "WKUPDEP_MCASP1_DMA_SDMA,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_DMA_SDMA_0,WKUPDEP_MCASP1_DMA_SDMA_1" newline bitfld.long 0x00 12. "WKUPDEP_MCASP1_DMA_DSP1,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_DMA_DSP1_0,WKUPDEP_MCASP1_DMA_DSP1_1" bitfld.long 0x00 7. "WKUPDEP_MCASP1_IRQ_EVE2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_EVE2_0,WKUPDEP_MCASP1_IRQ_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_MCASP1_IRQ_EVE1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_EVE1_0,WKUPDEP_MCASP1_IRQ_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_MCASP1_IRQ_DSP2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_DSP2_0,WKUPDEP_MCASP1_IRQ_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_MCASP1_IRQ_IPU1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_IPU1_0,WKUPDEP_MCASP1_IRQ_IPU1_1" bitfld.long 0x00 2. "WKUPDEP_MCASP1_IRQ_DSP1,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_DSP1_0,WKUPDEP_MCASP1_IRQ_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_MCASP1_IRQ_IPU2,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_IPU2_0,WKUPDEP_MCASP1_IRQ_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_MCASP1_IRQ_MPU,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP1_IRQ_MPU_0,WKUPDEP_MCASP1_IRQ_MPU_1" line.long 0x04 "RM_IPU_MCASP1_CONTEXT,This register contains dedicated MCASP context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_IPU_TIMER5_WKDEP,This register controls wakeup dependency based on TIMER5 service requests" bitfld.long 0x08 7. "WKUPDEP_TIMER5_EVE2,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_EVE2_0,WKUPDEP_TIMER5_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_TIMER5_EVE1,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_EVE1_0,WKUPDEP_TIMER5_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_TIMER5_DSP2,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_DSP2_0,WKUPDEP_TIMER5_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_TIMER5_IPU1,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_IPU1_0,WKUPDEP_TIMER5_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_TIMER5_DSP1,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_DSP1_0,WKUPDEP_TIMER5_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_TIMER5_IPU2,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_IPU2_0,WKUPDEP_TIMER5_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_TIMER5_MPU,Wakeup dependency from TIMER5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER5_MPU_0,WKUPDEP_TIMER5_MPU_1" line.long 0x0C "RM_IPU_TIMER5_CONTEXT,This register contains dedicated TIMER5 context statuses" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_IPU_TIMER6_WKDEP,This register controls wakeup dependency based on TIMER6 service requests" bitfld.long 0x10 7. "WKUPDEP_TIMER6_EVE2,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_EVE2_0,WKUPDEP_TIMER6_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_TIMER6_EVE1,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_EVE1_0,WKUPDEP_TIMER6_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_TIMER6_DSP2,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_DSP2_0,WKUPDEP_TIMER6_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_TIMER6_IPU1,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_IPU1_0,WKUPDEP_TIMER6_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_TIMER6_DSP1,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_DSP1_0,WKUPDEP_TIMER6_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TIMER6_IPU2,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_IPU2_0,WKUPDEP_TIMER6_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TIMER6_MPU,Wakeup dependency from TIMER6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER6_MPU_0,WKUPDEP_TIMER6_MPU_1" line.long 0x14 "RM_IPU_TIMER6_CONTEXT,This register contains dedicated TIMER6 context statuses" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_IPU_TIMER7_WKDEP,This register controls wakeup dependency based on TIMER7 service requests" bitfld.long 0x18 7. "WKUPDEP_TIMER7_EVE2,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_EVE2_0,WKUPDEP_TIMER7_EVE2_1" bitfld.long 0x18 6. "WKUPDEP_TIMER7_EVE1,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_EVE1_0,WKUPDEP_TIMER7_EVE1_1" newline bitfld.long 0x18 5. "WKUPDEP_TIMER7_DSP2,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_DSP2_0,WKUPDEP_TIMER7_DSP2_1" bitfld.long 0x18 4. "WKUPDEP_TIMER7_IPU1,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_IPU1_0,WKUPDEP_TIMER7_IPU1_1" newline bitfld.long 0x18 2. "WKUPDEP_TIMER7_DSP1,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_DSP1_0,WKUPDEP_TIMER7_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_TIMER7_IPU2,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_IPU2_0,WKUPDEP_TIMER7_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_TIMER7_MPU,Wakeup dependency from TIMER7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER7_MPU_0,WKUPDEP_TIMER7_MPU_1" line.long 0x1C "RM_IPU_TIMER7_CONTEXT,This register contains dedicated TIMER7 context statuses" bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_IPU_TIMER8_WKDEP,This register controls wakeup dependency based on TIMER8 service requests" bitfld.long 0x20 7. "WKUPDEP_TIMER8_EVE2,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_EVE2_0,WKUPDEP_TIMER8_EVE2_1" bitfld.long 0x20 6. "WKUPDEP_TIMER8_EVE1,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_EVE1_0,WKUPDEP_TIMER8_EVE1_1" newline bitfld.long 0x20 5. "WKUPDEP_TIMER8_DSP2,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_DSP2_0,WKUPDEP_TIMER8_DSP2_1" bitfld.long 0x20 4. "WKUPDEP_TIMER8_IPU1,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_IPU1_0,WKUPDEP_TIMER8_IPU1_1" newline bitfld.long 0x20 2. "WKUPDEP_TIMER8_DSP1,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_DSP1_0,WKUPDEP_TIMER8_DSP1_1" bitfld.long 0x20 1. "WKUPDEP_TIMER8_IPU2,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_IPU2_0,WKUPDEP_TIMER8_IPU2_1" newline bitfld.long 0x20 0. "WKUPDEP_TIMER8_MPU,Wakeup dependency from TIMER8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER8_MPU_0,WKUPDEP_TIMER8_MPU_1" line.long 0x24 "RM_IPU_TIMER8_CONTEXT,This register contains dedicated TIMER8 context statuses" bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "PM_IPU_I2C5_WKDEP,This register controls wakeup dependency based on I2C5 service requests" bitfld.long 0x28 15. "WKUPDEP_I2C5_DMA_DSP2,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_DMA_DSP2_0,WKUPDEP_I2C5_DMA_DSP2_1" bitfld.long 0x28 13. "WKUPDEP_I2C5_DMA_SDMA,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_DMA_SDMA_0,WKUPDEP_I2C5_DMA_SDMA_1" newline bitfld.long 0x28 12. "WKUPDEP_I2C5_DMA_DSP1,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_DMA_DSP1_0,WKUPDEP_I2C5_DMA_DSP1_1" bitfld.long 0x28 7. "WKUPDEP_I2C5_IRQ_EVE2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_EVE2_0,WKUPDEP_I2C5_IRQ_EVE2_1" newline bitfld.long 0x28 6. "WKUPDEP_I2C5_IRQ_EVE1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_EVE1_0,WKUPDEP_I2C5_IRQ_EVE1_1" bitfld.long 0x28 5. "WKUPDEP_I2C5_IRQ_DSP2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_DSP2_0,WKUPDEP_I2C5_IRQ_DSP2_1" newline bitfld.long 0x28 4. "WKUPDEP_I2C5_IRQ_IPU1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_IPU1_0,WKUPDEP_I2C5_IRQ_IPU1_1" bitfld.long 0x28 2. "WKUPDEP_I2C5_IRQ_DSP1,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_DSP1_0,WKUPDEP_I2C5_IRQ_DSP1_1" newline bitfld.long 0x28 1. "WKUPDEP_I2C5_IRQ_IPU2,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_IPU2_0,WKUPDEP_I2C5_IRQ_IPU2_1" bitfld.long 0x28 0. "WKUPDEP_I2C5_IRQ_MPU,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C5_IRQ_MPU_0,WKUPDEP_I2C5_IRQ_MPU_1" line.long 0x2C "RM_IPU_I2C5_CONTEXT,This register contains dedicated I2C5 context statuses" bitfld.long 0x2C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x30 "PM_IPU_UART6_WKDEP,This register controls wakeup dependency based on UART6 service requests" bitfld.long 0x30 7. "WKUPDEP_UART6_EVE2,Wakeup dependency from UART6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_EVE2_0,WKUPDEP_UART6_EVE2_1" bitfld.long 0x30 6. "WKUPDEP_UART6_EVE1,Wakeup dependency from UART6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_EVE1_0,WKUPDEP_UART6_EVE1_1" newline bitfld.long 0x30 5. "WKUPDEP_UART6_DSP2,Wakeup dependency from UART6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_DSP2_0,WKUPDEP_UART6_DSP2_1" bitfld.long 0x30 4. "WKUPDEP_UART6_IPU1,Wakeup dependency from UART6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_IPU1_0,WKUPDEP_UART6_IPU1_1" newline bitfld.long 0x30 3. "WKUPDEP_UART6_SDMA,Wakeup dependency from UART6 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_SDMA_0,WKUPDEP_UART6_SDMA_1" bitfld.long 0x30 2. "WKUPDEP_UART6_DSP1,Wakeup dependency from UART6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_DSP1_0,WKUPDEP_UART6_DSP1_1" newline bitfld.long 0x30 1. "WKUPDEP_UART6_IPU2,Wakeup dependency from UART6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_IPU2_0,WKUPDEP_UART6_IPU2_1" bitfld.long 0x30 0. "WKUPDEP_UART6_MPU,Wakeup dependency from UART6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART6_MPU_0,WKUPDEP_UART6_MPU_1" line.long 0x34 "RM_IPU_UART6_CONTEXT,This register contains dedicated UART6 context statuses" bitfld.long 0x34 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x34 1. "LOSTCONTEXT_RFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" tree.end tree "IVA_PRM" base ad:0x4AE06F00 group.long 0x00++0x07 line.long 0x00 "PM_IVA_PWRSTCTRL,This register controls the IVA power state to reach upon a domain sleep transition" rbitfld.long 0x00 22.--23. "TCM2_MEM_ONSTATE,TCM_CORE memory state when domain is ON" "?,?,?,TCM2_MEM_ONSTATE_3" rbitfld.long 0x00 20.--21. "TCM1_MEM_ONSTATE,TCM1 memory state when domain is ON" "?,?,?,TCM1_MEM_ONSTATE_3" newline rbitfld.long 0x00 18.--19. "SL2_MEM_ONSTATE,SL2 memory state when domain is ON" "?,?,?,SL2_MEM_ONSTATE_3" rbitfld.long 0x00 16.--17. "HWA_MEM_ONSTATE,HWA memory state when domain is ON" "?,?,?,HWA_MEM_ONSTATE_3" newline bitfld.long 0x00 11. "TCM2_MEM_RETSTATE,TCM2 memory state when domain is RETENTION" "TCM2_MEM_RETSTATE_0,TCM2_MEM_RETSTATE_1" bitfld.long 0x00 10. "TCM1_MEM_RETSTATE,TCM1 memory state when domain is RETENTION" "TCM1_MEM_RETSTATE_0,TCM1_MEM_RETSTATE_1" newline bitfld.long 0x00 9. "SL2_MEM_RETSTATE,SL2 memory state when domain is RETENTION" "SL2_MEM_RETSTATE_0,SL2_MEM_RETSTATE_1" rbitfld.long 0x00 8. "HWA_MEM_RETSTATE,HWA memory state when domain is RETENTION" "HWA_MEM_RETSTATE_0,?" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" rbitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,?" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_IVA_PWRSTST,This register provides a status on the current IVA power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 10.--11. "TCM2_MEM_STATEST,TCM2 memory state status - MEM_OFF" "TCM2_MEM_STATEST_0,TCM2_MEM_STATEST_1,TCM2_MEM_STATEST_2,TCM2_MEM_STATEST_3" rbitfld.long 0x04 8.--9. "TCM1_MEM_STATEST,TCM1 memory state status - MEM_OFF" "TCM1_MEM_STATEST_0,TCM1_MEM_STATEST_1,TCM1_MEM_STATEST_2,TCM1_MEM_STATEST_3" newline rbitfld.long 0x04 6.--7. "SL2_MEM_STATEST,SL2 memory state status - MEM_OFF" "SL2_MEM_STATEST_0,SL2_MEM_STATEST_1,SL2_MEM_STATEST_2,SL2_MEM_STATEST_3" rbitfld.long 0x04 4.--5. "HWA_MEM_STATEST,HWA memory state status - MEM_OFF" "HWA_MEM_STATEST_0,HWA_MEM_STATEST_1,HWA_MEM_STATEST_2,HWA_MEM_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_IVA_RSTCTRL,This register controls the release of the IVA sub-system resets" bitfld.long 0x00 2. "RST_LOGIC,IVA logic and SL2 reset control - CLEAR" "RST_LOGIC_0,RST_LOGIC_1" bitfld.long 0x00 1. "RST_SEQ2,IVA Sequencer2 reset control - CLEAR" "RST_SEQ2_0,RST_SEQ2_1" newline bitfld.long 0x00 0. "RST_SEQ1,IVA sequencer1 reset control - CLEAR" "RST_SEQ1_0,RST_SEQ1_1" line.long 0x04 "RM_IVA_RSTST,This register logs the different reset sources of the IVA domain" bitfld.long 0x04 6. "RST_ICECRUSHER_SEQ2,Sequencer2 CPU has been reset due to IVA ICECRUSHER2 reset event - RESET_NO" "RST_ICECRUSHER_SEQ2_0,RST_ICECRUSHER_SEQ2_1" bitfld.long 0x04 5. "RST_ICECRUSHER_SEQ1,Sequencer1 CPU has been reset due to IVA ICECRUSHER1 reset event - RESET_NO" "RST_ICECRUSHER_SEQ1_0,RST_ICECRUSHER_SEQ1_1" newline bitfld.long 0x04 4. "RST_EMULATION_SEQ2,Sequencer2 CPU has been reset due to emulation reset source e.g" "RST_EMULATION_SEQ2_0,RST_EMULATION_SEQ2_1" bitfld.long 0x04 3. "RST_EMULATION_SEQ1,Sequencer1 CPU has been reset due to emulation reset source e.g" "RST_EMULATION_SEQ1_0,RST_EMULATION_SEQ1_1" newline bitfld.long 0x04 2. "RST_LOGIC,IVA logic and SL2 SW reset - RESET_NO" "RST_LOGIC_0,RST_LOGIC_1" bitfld.long 0x04 1. "RST_SEQ2,IVA Sequencer2 CPU SW reset - RESET_NO" "RST_SEQ2_0,RST_SEQ2_1" newline bitfld.long 0x04 0. "RST_SEQ1,IVA Sequencer1 CPU SW reset - RESET_NO" "RST_SEQ1_0,RST_SEQ1_1" group.long 0x24++0x03 line.long 0x00 "RM_IVA_IVA_CONTEXT,This register contains dedicated IVA context statuses" bitfld.long 0x00 10. "LOSTMEM_HWA_MEM,Specify if memory-based context in HWA_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_HWA_MEM_0,LOSTMEM_HWA_MEM_1" bitfld.long 0x00 9. "LOSTMEM_TCM2_MEM,Specify if memory-based context in TCM2_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_TCM2_MEM_0,LOSTMEM_TCM2_MEM_1" newline bitfld.long 0x00 8. "LOSTMEM_TCM1_MEM,Specify if memory-based context in TCM1_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_TCM1_MEM_0,LOSTMEM_TCM1_MEM_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x2C++0x03 line.long 0x00 "RM_IVA_SL2_CONTEXT,This register contains dedicated SL2 context statuses" bitfld.long 0x00 8. "LOSTMEM_SL2_MEM,Specify if memory-based context in SL2_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_SL2_MEM_0,LOSTMEM_SL2_MEM_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "L3INIT_PRM" base ad:0x4AE07300 group.long 0x00++0x07 line.long 0x00 "PM_L3INIT_PWRSTCTRL,This register controls the L3INIT power state to reach upon a domain sleep transition" rbitfld.long 0x00 18.--19. "GMAC_BANK_ONSTATE,GMAC BANK state when domain is ON" "?,?,?,GMAC_BANK_ONSTATE_3" rbitfld.long 0x00 16.--17. "L3INIT_BANK2_ONSTATE,L3INIT BANK2 state when domain is ON" "?,?,?,L3INIT_BANK2_ONSTATE_3" newline rbitfld.long 0x00 14.--15. "L3INIT_BANK1_ONSTATE,L3INIT BANK1 state when domain is ON" "?,?,?,L3INIT_BANK1_ONSTATE_3" rbitfld.long 0x00 10. "GMAC_BANK_RETSTATE,GMAC BANK state when domain is RETENTION" "?,GMAC_BANK_RETSTATE_1" newline rbitfld.long 0x00 9. "L3INIT_BANK2_RETSTATE,L3INIT BANK2 state when domain is RETENTION" "?,L3INIT_BANK2_RETSTATE_1" rbitfld.long 0x00 8. "L3INIT_BANK1_RETSTATE,L3INIT BANK1 state when domain is RETENTION" "L3INIT_BANK1_RETSTATE_0,?" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_L3INIT_PWRSTST,This register provides a status on the current L3INIT power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 8.--9. "L3INIT_GMAC_STATEST,L3INIT GMAC state status - MEM_OFF" "L3INIT_GMAC_STATEST_0,L3INIT_GMAC_STATEST_1,L3INIT_GMAC_STATEST_2,L3INIT_GMAC_STATEST_3" rbitfld.long 0x04 6.--7. "L3INIT_BANK2_STATEST,L3INIT BANK2 state status - MEM_OFF" "L3INIT_BANK2_STATEST_0,L3INIT_BANK2_STATEST_1,L3INIT_BANK2_STATEST_2,L3INIT_BANK2_STATEST_3" newline rbitfld.long 0x04 4.--5. "L3INIT_BANK1_STATEST,L3INIT BANK1 state status - MEM_OFF" "L3INIT_BANK1_STATEST_0,L3INIT_BANK1_STATEST_1,L3INIT_BANK1_STATEST_2,L3INIT_BANK1_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" newline rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x10++0x07 line.long 0x00 "RM_PCIESS_RSTCTRL,This register controls the release of the PCIESS local reset" bitfld.long 0x00 1. "RST_LOCAL_PCIE2,PCIESS2 local reset control - CLEAR" "RST_LOCAL_PCIE2_0,RST_LOCAL_PCIE2_1" bitfld.long 0x00 0. "RST_LOCAL_PCIE1,PCIESS1 local reset control - CLEAR" "RST_LOCAL_PCIE1_0,RST_LOCAL_PCIE1_1" line.long 0x04 "RM_PCIESS_RSTST,This register logs the different reset sources of the PCIESS domain" bitfld.long 0x04 1. "RST_LOCAL_PCIE2,PCIESS2 local SW reset - RESET_NO" "RST_LOCAL_PCIE2_0,RST_LOCAL_PCIE2_1" bitfld.long 0x04 0. "RST_LOCAL_PCIE1,PCIESS1 local SW reset - RESET_NO" "RST_LOCAL_PCIE1_0,RST_LOCAL_PCIE1_1" group.long 0x28++0x0F line.long 0x00 "PM_L3INIT_MMC1_WKDEP,This register controls wakeup dependency based on MMC1 service requests" bitfld.long 0x00 7. "WKUPDEP_MMC1_EVE2,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_EVE2_0,WKUPDEP_MMC1_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_MMC1_EVE1,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_EVE1_0,WKUPDEP_MMC1_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_MMC1_DSP2,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_DSP2_0,WKUPDEP_MMC1_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_MMC1_IPU1,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_IPU1_0,WKUPDEP_MMC1_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_MMC1_SDMA,Wakeup dependency from MMC1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_SDMA_0,WKUPDEP_MMC1_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_MMC1_DSP1,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_DSP1_0,WKUPDEP_MMC1_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_MMC1_IPU2,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_IPU2_0,WKUPDEP_MMC1_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_MMC1_MPU,Wakeup dependency from MMC1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC1_MPU_0,WKUPDEP_MMC1_MPU_1" line.long 0x04 "RM_L3INIT_MMC1_CONTEXT,This register contains dedicated MMC1 context statuses" bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x08 "PM_L3INIT_MMC2_WKDEP,This register controls wakeup dependency based on MMC2 service requests" bitfld.long 0x08 7. "WKUPDEP_MMC2_EVE2,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_EVE2_0,WKUPDEP_MMC2_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_MMC2_EVE1,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_EVE1_0,WKUPDEP_MMC2_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_MMC2_DSP2,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_DSP2_0,WKUPDEP_MMC2_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_MMC2_IPU1,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_IPU1_0,WKUPDEP_MMC2_IPU1_1" newline bitfld.long 0x08 3. "WKUPDEP_MMC2_SDMA,Wakeup dependency from MMC2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_SDMA_0,WKUPDEP_MMC2_SDMA_1" bitfld.long 0x08 2. "WKUPDEP_MMC2_DSP1,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_DSP1_0,WKUPDEP_MMC2_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_MMC2_IPU2,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_IPU2_0,WKUPDEP_MMC2_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_MMC2_MPU,Wakeup dependency from MMC2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC2_MPU_0,WKUPDEP_MMC2_MPU_1" line.long 0x0C "RM_L3INIT_MMC2_CONTEXT,This register contains dedicated MMC2 context statuses" bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x40++0x17 line.long 0x00 "PM_L3INIT_USB_OTG_SS2_WKDEP,This register controls wakeup dependency based on USB_OTG_SS2 service requests" bitfld.long 0x00 7. "WKUPDEP_USB_OTG_SS2_EVE2,Wakeup dependency from USB2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_EVE2_0,WKUPDEP_USB_OTG_SS2_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_USB_OTG_SS2_EVE1,Wakeup dependency from USB2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_EVE1_0,WKUPDEP_USB_OTG_SS2_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_USB_OTG_SS2_DSP2,Wakeup dependency from USB2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_DSP2_0,WKUPDEP_USB_OTG_SS2_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_USB_OTG_SS2_IPU1,Wakeup dependency from USB2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_IPU1_0,WKUPDEP_USB_OTG_SS2_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_USB_OTG_SS2_DSP1,Wakeup dependency from USB2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_DSP1_0,WKUPDEP_USB_OTG_SS2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_USB_OTG_SS2_IPU2,Wakeup dependency from USB2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_IPU2_0,WKUPDEP_USB_OTG_SS2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_USB_OTG_SS2_MPU,Wakeup dependency from USB2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS2_MPU_0,WKUPDEP_USB_OTG_SS2_MPU_1" line.long 0x04 "RM_L3INIT_USB_OTG_SS2_CONTEXT,This register contains dedicated USB_OTG_SS2 context statuses" bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x04 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x08 "PM_L3INIT_USB_OTG_SS3_WKDEP,This register controls wakeup dependency based on USB_OTG_SS3 service requests" bitfld.long 0x08 7. "WKUPDEP_USB_OTG_SS3_EVE2,Wakeup dependency from USB3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_EVE2_0,WKUPDEP_USB_OTG_SS3_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_USB_OTG_SS3_EVE1,Wakeup dependency from USB3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_EVE1_0,WKUPDEP_USB_OTG_SS3_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_USB_OTG_SS3_DSP2,Wakeup dependency from USB3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_DSP2_0,WKUPDEP_USB_OTG_SS3_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_USB_OTG_SS3_IPU1,Wakeup dependency from USB3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_IPU1_0,WKUPDEP_USB_OTG_SS3_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_USB_OTG_SS3_DSP1,Wakeup dependency from USB3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_DSP1_0,WKUPDEP_USB_OTG_SS3_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_USB_OTG_SS3_IPU2,Wakeup dependency from USB3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_IPU2_0,WKUPDEP_USB_OTG_SS3_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_USB_OTG_SS3_MPU,Wakeup dependency from USB3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS3_MPU_0,WKUPDEP_USB_OTG_SS3_MPU_1" line.long 0x0C "RM_L3INIT_USB_OTG_SS3_CONTEXT,This register contains dedicated USB_OTG_SS3 context statuses" bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x0C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x10 "PM_L3INIT_USB_OTG_SS4_WKDEP,This register controls wakeup dependency based on USB_OTG_SS4 service requests" bitfld.long 0x10 7. "WKUPDEP_USB_OTG_SS4_EVE2,Wakeup dependency from USB4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_EVE2_0,WKUPDEP_USB_OTG_SS4_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_USB_OTG_SS4_EVE1,Wakeup dependency from USB4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_EVE1_0,WKUPDEP_USB_OTG_SS4_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_USB_OTG_SS4_DSP2,Wakeup dependency from USB4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_DSP2_0,WKUPDEP_USB_OTG_SS4_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_USB_OTG_SS4_IPU1,Wakeup dependency from USB4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_IPU1_0,WKUPDEP_USB_OTG_SS4_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_USB_OTG_SS4_DSP1,Wakeup dependency from USB4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_DSP1_0,WKUPDEP_USB_OTG_SS4_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_USB_OTG_SS4_IPU2,Wakeup dependency from USB4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_IPU2_0,WKUPDEP_USB_OTG_SS4_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_USB_OTG_SS4_MPU,Wakeup dependency from USB4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS4_MPU_0,WKUPDEP_USB_OTG_SS4_MPU_1" line.long 0x14 "RM_L3INIT_USB_OTG_SS4_CONTEXT,This register contains dedicated USB_OTG_SS4 context statuses" bitfld.long 0x14 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x14 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x5C++0x03 line.long 0x00 "RM_L3INIT_MLB_SS_CONTEXT,This register contains dedicated MLBSS context statuses" bitfld.long 0x00 8. "LOSTMEM_MLB_BANK,Specify if memory-based context in MLB_MEM memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_MLB_BANK_0,LOSTMEM_MLB_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x7C++0x03 line.long 0x00 "RM_L3INIT_IEEE1500_2_OCP_CONTEXT,This register contains dedicated IEEE1500_2_OCP context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x88++0x07 line.long 0x00 "PM_L3INIT_SATA_WKDEP,This register controls wakeup dependency based on SATA service requests" bitfld.long 0x00 7. "WKUPDEP_SATA_EVE2,Wakeup dependency from SATA module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_EVE2_0,WKUPDEP_SATA_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_SATA_EVE1,Wakeup dependency from SATA module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_EVE1_0,WKUPDEP_SATA_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_SATA_DSP2,Wakeup dependency from SATA module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_DSP2_0,WKUPDEP_SATA_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_SATA_IPU1,Wakeup dependency from SATA module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_IPU1_0,WKUPDEP_SATA_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_SATA_DSP1,Wakeup dependency from SATA module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_DSP1_0,WKUPDEP_SATA_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_SATA_IPU2,Wakeup dependency from SATA module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_SATA_IPU2_0,WKUPDEP_SATA_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_SATA_MPU,Wakeup dependency from SATA module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains - DISABLED" "WKUPDEP_SATA_MPU_0,WKUPDEP_SATA_MPU_1" line.long 0x04 "RM_L3INIT_SATA_CONTEXT,This register contains dedicated SATA context statuses" bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xB0++0x0F line.long 0x00 "PM_PCIE_PCIESS1_WKDEP,This register controls wakeup dependency based on PCIESS1 service requests" bitfld.long 0x00 7. "WKUPDEP_PCIESS1_EVE2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_EVE2_0,WKUPDEP_PCIESS1_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_PCIESS1_EVE1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_EVE1_0,WKUPDEP_PCIESS1_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_PCIESS1_DSP2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_DSP2_0,WKUPDEP_PCIESS1_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_PCIESS1_IPU1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_IPU1_0,WKUPDEP_PCIESS1_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_PCIESS1_DSP1,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_DSP1_0,WKUPDEP_PCIESS1_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_PCIESS1_IPU2,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_IPU2_0,WKUPDEP_PCIESS1_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_PCIESS1_MPU,Wakeup dependency from PCIESS1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS1_MPU_0,WKUPDEP_PCIESS1_MPU_1" line.long 0x04 "RM_PCIE_PCIESS1_CONTEXT,This register contains dedicated PCIESS1 context statuses" bitfld.long 0x04 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_PCIE_PCIESS2_WKDEP,This register controls wakeup dependency based on PCIESS2 service requests" bitfld.long 0x08 7. "WKUPDEP_PCIESS2_EVE2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_EVE2_0,WKUPDEP_PCIESS2_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_PCIESS2_EVE1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_EVE1_0,WKUPDEP_PCIESS2_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_PCIESS2_DSP2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_DSP2_0,WKUPDEP_PCIESS2_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_PCIESS2_IPU1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_IPU1_0,WKUPDEP_PCIESS2_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_PCIESS2_DSP1,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_DSP1_0,WKUPDEP_PCIESS2_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_PCIESS2_IPU2,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_IPU2_0,WKUPDEP_PCIESS2_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_PCIESS2_MPU,Wakeup dependency from PCIESS2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_PCIESS2_MPU_0,WKUPDEP_PCIESS2_MPU_1" line.long 0x0C "RM_PCIE_PCIESS2_CONTEXT,This register contains dedicated PCIESS2 context statuses" bitfld.long 0x0C 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xD4++0x03 line.long 0x00 "RM_GMAC_GMAC_CONTEXT,This register contains dedicated GMAC context statuses" bitfld.long 0x00 8. "LOSTMEM_GMAC_BANK,Specify if memory-based context in GMAC_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_GMAC_BANK_0,LOSTMEM_GMAC_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xE4++0x03 line.long 0x00 "RM_L3INIT_OCP2SCP1_CONTEXT,This register contains dedicated OCP2SCP1 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xEC++0x0B line.long 0x00 "RM_L3INIT_OCP2SCP3_CONTEXT,This register contains dedicated OCP2SCP3 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L3INIT_USB_OTG_SS1_WKDEP,This register controls wakeup dependency based on USB_OTG_SS1 service requests" bitfld.long 0x04 7. "WKUPDEP_USB_OTG_SS1_EVE2,Wakeup dependency from USB1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_EVE2_0,WKUPDEP_USB_OTG_SS1_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_USB_OTG_SS1_EVE1,Wakeup dependency from USB1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_EVE1_0,WKUPDEP_USB_OTG_SS1_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_USB_OTG_SS1_DSP2,Wakeup dependency from USB1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_DSP2_0,WKUPDEP_USB_OTG_SS1_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_USB_OTG_SS1_IPU1,Wakeup dependency from USB1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_IPU1_0,WKUPDEP_USB_OTG_SS1_IPU1_1" newline bitfld.long 0x04 2. "WKUPDEP_USB_OTG_SS1_DSP1,Wakeup dependency from USB1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_DSP1_0,WKUPDEP_USB_OTG_SS1_DSP1_1" bitfld.long 0x04 1. "WKUPDEP_USB_OTG_SS1_IPU2,Wakeup dependency from USB1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_IPU2_0,WKUPDEP_USB_OTG_SS1_IPU2_1" newline bitfld.long 0x04 0. "WKUPDEP_USB_OTG_SS1_MPU,Wakeup dependency from USB1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_USB_OTG_SS1_MPU_0,WKUPDEP_USB_OTG_SS1_MPU_1" line.long 0x08 "RM_L3INIT_USB_OTG_SS1_CONTEXT,This register contains dedicated USB_OTG_SS1 context statuses" bitfld.long 0x08 8. "LOSTMEM_L3INIT_BANK1,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_L3INIT_BANK1_0,LOSTMEM_L3INIT_BANK1_1" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" tree.end tree "L4PER_PRM" base ad:0x4AE07400 group.long 0x00++0x07 line.long 0x00 "PM_L4PER_PWRSTCTRL,This register controls the L4PER power state to reach upon a domain sleep transition" rbitfld.long 0x00 18.--19. "NONRETAINED_BANK_ONSTATE,NONRETAINED_BANK state when domain is ON" "?,?,?,NONRETAINED_BANK_ONSTATE_3" rbitfld.long 0x00 16.--17. "RETAINED_BANK_ONSTATE,RETAINED_BANK state when domain is ON" "?,?,?,RETAINED_BANK_ONSTATE_3" newline rbitfld.long 0x00 9. "NONRETAINED_BANK_RETSTATE,NONRETAINED_BANK state when domain is RETENTION" "NONRETAINED_BANK_RETSTATE_0,?" rbitfld.long 0x00 8. "RETAINED_BANK_RETSTATE,RETAINED_BANK state when domain is RETENTION" "?,RETAINED_BANK_RETSTATE_1" newline bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - RESERVED" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_L4PER_PWRSTST,This register provides a status on the current L4PER power domain state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" newline rbitfld.long 0x04 6.--7. "NONRETAINED_BANK_STATEST,NONRETAINED_BANK state status - MEM_OFF" "NONRETAINED_BANK_STATEST_0,NONRETAINED_BANK_STATEST_1,NONRETAINED_BANK_STATEST_2,NONRETAINED_BANK_STATEST_3" rbitfld.long 0x04 4.--5. "RETAINED_BANK_STATEST,RETAINED_BANK state status - MEM_OFF" "RETAINED_BANK_STATEST_0,RETAINED_BANK_STATEST_1,RETAINED_BANK_STATEST_2,RETAINED_BANK_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - RESERVED" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x0C++0x03 line.long 0x00 "RM_L4PER2_L4PER2_CONTEXT,This register contains dedicated L4_PER2 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x14++0x03 line.long 0x00 "RM_L4PER3_L4PER3_CONTEXT,This register contains dedicated L4_PER3 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x28++0x2F line.long 0x00 "PM_L4PER_TIMER10_WKDEP,This register controls wakeup dependency based on TIMER10 service requests" bitfld.long 0x00 7. "WKUPDEP_TIMER10_EVE2,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_EVE2_0,WKUPDEP_TIMER10_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_TIMER10_EVE1,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_EVE1_0,WKUPDEP_TIMER10_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_TIMER10_DSP2,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_DSP2_0,WKUPDEP_TIMER10_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_TIMER10_IPU1,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_IPU1_0,WKUPDEP_TIMER10_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_TIMER10_DSP1,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_DSP1_0,WKUPDEP_TIMER10_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_TIMER10_IPU2,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_IPU2_0,WKUPDEP_TIMER10_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_TIMER10_MPU,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER10_MPU_0,WKUPDEP_TIMER10_MPU_1" line.long 0x04 "RM_L4PER_TIMER10_CONTEXT,This register contains dedicated TIMER10 context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_L4PER_TIMER11_WKDEP,This register controls wakeup dependency based on TIMER11 service requests" bitfld.long 0x08 7. "WKUPDEP_TIMER11_EVE2,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_EVE2_0,WKUPDEP_TIMER11_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_TIMER11_EVE1,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_EVE1_0,WKUPDEP_TIMER11_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_TIMER11_DSP2,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_DSP2_0,WKUPDEP_TIMER11_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_TIMER11_IPU1,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_IPU1_0,WKUPDEP_TIMER11_IPU1_1" newline bitfld.long 0x08 2. "WKUPDEP_TIMER11_DSP1,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_DSP1_0,WKUPDEP_TIMER11_DSP1_1" bitfld.long 0x08 1. "WKUPDEP_TIMER11_IPU2,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_IPU2_0,WKUPDEP_TIMER11_IPU2_1" newline bitfld.long 0x08 0. "WKUPDEP_TIMER11_MPU,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER11_MPU_0,WKUPDEP_TIMER11_MPU_1" line.long 0x0C "RM_L4PER_TIMER11_CONTEXT,This register contains dedicated TIMER11 context statuses" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_L4PER_TIMER2_WKDEP,This register controls wakeup dependency based on TIMER2 service requests" bitfld.long 0x10 7. "WKUPDEP_TIMER2_EVE2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_EVE2_0,WKUPDEP_TIMER2_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_TIMER2_EVE1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_EVE1_0,WKUPDEP_TIMER2_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_TIMER2_DSP2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_DSP2_0,WKUPDEP_TIMER2_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_TIMER2_IPU1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_IPU1_0,WKUPDEP_TIMER2_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_TIMER2_DSP1,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_DSP1_0,WKUPDEP_TIMER2_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TIMER2_IPU2,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_IPU2_0,WKUPDEP_TIMER2_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TIMER2_MPU,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER2_MPU_0,WKUPDEP_TIMER2_MPU_1" line.long 0x14 "RM_L4PER_TIMER2_CONTEXT,This register contains dedicated TIMER2 context statuses" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_L4PER_TIMER3_WKDEP,This register controls wakeup dependency based on TIMER3 service requests" bitfld.long 0x18 7. "WKUPDEP_TIMER3_EVE2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_EVE2_0,WKUPDEP_TIMER3_EVE2_1" bitfld.long 0x18 6. "WKUPDEP_TIMER3_EVE1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_EVE1_0,WKUPDEP_TIMER3_EVE1_1" newline bitfld.long 0x18 5. "WKUPDEP_TIMER3_DSP2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_DSP2_0,WKUPDEP_TIMER3_DSP2_1" bitfld.long 0x18 4. "WKUPDEP_TIMER3_IPU1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_IPU1_0,WKUPDEP_TIMER3_IPU1_1" newline bitfld.long 0x18 2. "WKUPDEP_TIMER3_DSP1,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_DSP1_0,WKUPDEP_TIMER3_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_TIMER3_IPU2,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_IPU2_0,WKUPDEP_TIMER3_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_TIMER3_MPU,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER3_MPU_0,WKUPDEP_TIMER3_MPU_1" line.long 0x1C "RM_L4PER_TIMER3_CONTEXT,This register contains dedicated TIMER3 context statuses" bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_L4PER_TIMER4_WKDEP,This register controls wakeup dependency based on TIMER4 service requests" bitfld.long 0x20 7. "WKUPDEP_TIMER4_EVE2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_EVE2_0,WKUPDEP_TIMER4_EVE2_1" bitfld.long 0x20 6. "WKUPDEP_TIMER4_EVE1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_EVE1_0,WKUPDEP_TIMER4_EVE1_1" newline bitfld.long 0x20 5. "WKUPDEP_TIMER4_DSP2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_DSP2_0,WKUPDEP_TIMER4_DSP2_1" bitfld.long 0x20 4. "WKUPDEP_TIMER4_IPU1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_IPU1_0,WKUPDEP_TIMER4_IPU1_1" newline bitfld.long 0x20 2. "WKUPDEP_TIMER4_DSP1,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_DSP1_0,WKUPDEP_TIMER4_DSP1_1" bitfld.long 0x20 1. "WKUPDEP_TIMER4_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_IPU2_0,WKUPDEP_TIMER4_IPU2_1" newline bitfld.long 0x20 0. "WKUPDEP_TIMER4_MPU,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER4_MPU_0,WKUPDEP_TIMER4_MPU_1" line.long 0x24 "RM_L4PER_TIMER4_CONTEXT,This register contains dedicated TIMER4 context statuses" bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "PM_L4PER_TIMER9_WKDEP,This register controls wakeup dependency based on TIMER9 service requests" bitfld.long 0x28 7. "WKUPDEP_TIMER9_EVE2,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_EVE2_0,WKUPDEP_TIMER9_EVE2_1" bitfld.long 0x28 6. "WKUPDEP_TIMER9_EVE1,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_EVE1_0,WKUPDEP_TIMER9_EVE1_1" newline bitfld.long 0x28 5. "WKUPDEP_TIMER9_DSP2,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_DSP2_0,WKUPDEP_TIMER9_DSP2_1" bitfld.long 0x28 4. "WKUPDEP_TIMER9_IPU1,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_IPU1_0,WKUPDEP_TIMER9_IPU1_1" newline bitfld.long 0x28 2. "WKUPDEP_TIMER9_DSP1,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_DSP1_0,WKUPDEP_TIMER9_DSP1_1" bitfld.long 0x28 1. "WKUPDEP_TIMER9_IPU2,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_IPU2_0,WKUPDEP_TIMER9_IPU2_1" newline bitfld.long 0x28 0. "WKUPDEP_TIMER9_MPU,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER9_MPU_0,WKUPDEP_TIMER9_MPU_1" line.long 0x2C "RM_L4PER_TIMER9_CONTEXT,This register contains dedicated TIMER9 context statuses" bitfld.long 0x2C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x5C++0x2B line.long 0x00 "RM_L4PER_ELM_CONTEXT,This register contains dedicated ELM context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_GPIO2_WKDEP,This register controls wakeup dependency based on GPIO2 service requests" bitfld.long 0x04 17. "WKUPDEP_GPIO2_IRQ2_EVE2,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_EVE2_0,WKUPDEP_GPIO2_IRQ2_EVE2_1" bitfld.long 0x04 16. "WKUPDEP_GPIO2_IRQ2_EVE1,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_EVE1_0,WKUPDEP_GPIO2_IRQ2_EVE1_1" newline bitfld.long 0x04 15. "WKUPDEP_GPIO2_IRQ2_DSP2,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_DSP2_0,WKUPDEP_GPIO2_IRQ2_DSP2_1" bitfld.long 0x04 14. "WKUPDEP_GPIO2_IRQ2_IPU1,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_IPU1_0,WKUPDEP_GPIO2_IRQ2_IPU1_1" newline bitfld.long 0x04 12. "WKUPDEP_GPIO2_IRQ2_DSP1,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_DSP1_0,WKUPDEP_GPIO2_IRQ2_DSP1_1" bitfld.long 0x04 11. "WKUPDEP_GPIO2_IRQ2_IPU2,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_IPU2_0,WKUPDEP_GPIO2_IRQ2_IPU2_1" newline bitfld.long 0x04 10. "WKUPDEP_GPIO2_IRQ2_MPU,Wakeup dependency from GPIO2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ2_MPU_0,WKUPDEP_GPIO2_IRQ2_MPU_1" bitfld.long 0x04 7. "WKUPDEP_GPIO2_IRQ1_EVE2,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_EVE2_0,WKUPDEP_GPIO2_IRQ1_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_GPIO2_IRQ1_EVE1,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_EVE1_0,WKUPDEP_GPIO2_IRQ1_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_GPIO2_IRQ1_DSP2,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_DSP2_0,WKUPDEP_GPIO2_IRQ1_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_GPIO2_IRQ1_IPU1,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_IPU1_0,WKUPDEP_GPIO2_IRQ1_IPU1_1" bitfld.long 0x04 2. "WKUPDEP_GPIO2_IRQ1_DSP1,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_DSP1_0,WKUPDEP_GPIO2_IRQ1_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_GPIO2_IRQ1_IPU2,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_IPU2_0,WKUPDEP_GPIO2_IRQ1_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_GPIO2_IRQ1_MPU,Wakeup dependency from GPIO2 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO2_IRQ1_MPU_0,WKUPDEP_GPIO2_IRQ1_MPU_1" line.long 0x08 "RM_L4PER_GPIO2_CONTEXT,This register contains dedicated GPIO2 context statuses" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x0C "PM_L4PER_GPIO3_WKDEP,This register controls wakeup dependency based on GPIO3 service requests" bitfld.long 0x0C 17. "WKUPDEP_GPIO3_IRQ2_EVE2,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_EVE2_0,WKUPDEP_GPIO3_IRQ2_EVE2_1" bitfld.long 0x0C 16. "WKUPDEP_GPIO3_IRQ2_EVE1,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_EVE1_0,WKUPDEP_GPIO3_IRQ2_EVE1_1" newline bitfld.long 0x0C 15. "WKUPDEP_GPIO3_IRQ2_DSP2,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_DSP2_0,WKUPDEP_GPIO3_IRQ2_DSP2_1" bitfld.long 0x0C 14. "WKUPDEP_GPIO3_IRQ2_IPU1,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_IPU1_0,WKUPDEP_GPIO3_IRQ2_IPU1_1" newline bitfld.long 0x0C 12. "WKUPDEP_GPIO3_IRQ2_DSP1,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_DSP1_0,WKUPDEP_GPIO3_IRQ2_DSP1_1" bitfld.long 0x0C 11. "WKUPDEP_GPIO3_IRQ2_IPU2,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_IPU2_0,WKUPDEP_GPIO3_IRQ2_IPU2_1" newline bitfld.long 0x0C 10. "WKUPDEP_GPIO3_IRQ2_MPU,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ2_MPU_0,WKUPDEP_GPIO3_IRQ2_MPU_1" bitfld.long 0x0C 7. "WKUPDEP_GPIO3_IRQ1_EVE2,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_EVE2_0,WKUPDEP_GPIO3_IRQ1_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_GPIO3_IRQ1_EVE1,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_EVE1_0,WKUPDEP_GPIO3_IRQ1_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_GPIO3_IRQ1_DSP2,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_DSP2_0,WKUPDEP_GPIO3_IRQ1_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_GPIO3_IRQ1_IPU1,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_IPU1_0,WKUPDEP_GPIO3_IRQ1_IPU1_1" bitfld.long 0x0C 2. "WKUPDEP_GPIO3_IRQ1_DSP1,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_DSP1_0,WKUPDEP_GPIO3_IRQ1_DSP1_1" newline bitfld.long 0x0C 1. "WKUPDEP_GPIO3_IRQ1_IPU2,3Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_IPU2_0,WKUPDEP_GPIO3_IRQ1_IPU2_1" bitfld.long 0x0C 0. "WKUPDEP_GPIO3_IRQ1_MPU,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO3_IRQ1_MPU_0,WKUPDEP_GPIO3_IRQ1_MPU_1" line.long 0x10 "RM_L4PER_GPIO3_CONTEXT,This register contains dedicated GPIO3 context statuses" bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x14 "PM_L4PER_GPIO4_WKDEP,This register controls wakeup dependency based on GPIO4 service requests" bitfld.long 0x14 17. "WKUPDEP_GPIO4_IRQ2_EVE2,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_EVE2_0,WKUPDEP_GPIO4_IRQ2_EVE2_1" bitfld.long 0x14 16. "WKUPDEP_GPIO4_IRQ2_EVE1,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_EVE1_0,WKUPDEP_GPIO4_IRQ2_EVE1_1" newline bitfld.long 0x14 15. "WKUPDEP_GPIO4_IRQ2_DSP2,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_DSP2_0,WKUPDEP_GPIO4_IRQ2_DSP2_1" bitfld.long 0x14 14. "WKUPDEP_GPIO4_IRQ2_IPU1,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_IPU1_0,WKUPDEP_GPIO4_IRQ2_IPU1_1" newline bitfld.long 0x14 12. "WKUPDEP_GPIO4_IRQ2_DSP1,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_DSP1_0,WKUPDEP_GPIO4_IRQ2_DSP1_1" bitfld.long 0x14 11. "WKUPDEP_GPIO4_IRQ2_IPU2,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_IPU2_0,WKUPDEP_GPIO4_IRQ2_IPU2_1" newline bitfld.long 0x14 10. "WKUPDEP_GPIO4_IRQ2_MPU,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ2_MPU_0,WKUPDEP_GPIO4_IRQ2_MPU_1" bitfld.long 0x14 7. "WKUPDEP_GPIO4_IRQ1_EVE2,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_EVE2_0,WKUPDEP_GPIO4_IRQ1_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_GPIO4_IRQ1_EVE1,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_EVE1_0,WKUPDEP_GPIO4_IRQ1_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_GPIO4_IRQ1_DSP2,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_DSP2_0,WKUPDEP_GPIO4_IRQ1_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_GPIO4_IRQ1_IPU1,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_IPU1_0,WKUPDEP_GPIO4_IRQ1_IPU1_1" bitfld.long 0x14 2. "WKUPDEP_GPIO4_IRQ1_DSP1,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_DSP1_0,WKUPDEP_GPIO4_IRQ1_DSP1_1" newline bitfld.long 0x14 1. "WKUPDEP_GPIO4_IRQ1_IPU2,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_IPU2_0,WKUPDEP_GPIO4_IRQ1_IPU2_1" bitfld.long 0x14 0. "WKUPDEP_GPIO4_IRQ1_MPU,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO4_IRQ1_MPU_0,WKUPDEP_GPIO4_IRQ1_MPU_1" line.long 0x18 "RM_L4PER_GPIO4_CONTEXT,This register contains dedicated GPIO4 context statuses" bitfld.long 0x18 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x1C "PM_L4PER_GPIO5_WKDEP,This register controls wakeup dependency based on GPIO5 service requests" bitfld.long 0x1C 17. "WKUPDEP_GPIO5_IRQ2_EVE2,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_EVE2_0,WKUPDEP_GPIO5_IRQ2_EVE2_1" bitfld.long 0x1C 16. "WKUPDEP_GPIO5_IRQ2_EVE1,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_EVE1_0,WKUPDEP_GPIO5_IRQ2_EVE1_1" newline bitfld.long 0x1C 15. "WKUPDEP_GPIO5_IRQ2_DSP2,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_DSP2_0,WKUPDEP_GPIO5_IRQ2_DSP2_1" bitfld.long 0x1C 14. "WKUPDEP_GPIO5_IRQ2_IPU1,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_IPU1_0,WKUPDEP_GPIO5_IRQ2_IPU1_1" newline bitfld.long 0x1C 12. "WKUPDEP_GPIO5_IRQ2_DSP1,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_DSP1_0,WKUPDEP_GPIO5_IRQ2_DSP1_1" bitfld.long 0x1C 11. "WKUPDEP_GPIO5_IRQ2_IPU2,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_IPU2_0,WKUPDEP_GPIO5_IRQ2_IPU2_1" newline bitfld.long 0x1C 10. "WKUPDEP_GPIO5_IRQ2_MPU,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ2_MPU_0,WKUPDEP_GPIO5_IRQ2_MPU_1" bitfld.long 0x1C 7. "WKUPDEP_GPIO5_IRQ1_EVE2,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_EVE2_0,WKUPDEP_GPIO5_IRQ1_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_GPIO5_IRQ1_EVE1,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_EVE1_0,WKUPDEP_GPIO5_IRQ1_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_GPIO5_IRQ1_DSP2,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_DSP2_0,WKUPDEP_GPIO5_IRQ1_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_GPIO5_IRQ1_IPU1,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_IPU1_0,WKUPDEP_GPIO5_IRQ1_IPU1_1" bitfld.long 0x1C 2. "WKUPDEP_GPIO5_IRQ1_DSP1,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_DSP1_0,WKUPDEP_GPIO5_IRQ1_DSP1_1" newline bitfld.long 0x1C 1. "WKUPDEP_GPIO5_IRQ1_IPU2,5Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_IPU2_0,WKUPDEP_GPIO5_IRQ1_IPU2_1" bitfld.long 0x1C 0. "WKUPDEP_GPIO5_IRQ1_MPU,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO5_IRQ1_MPU_0,WKUPDEP_GPIO5_IRQ1_MPU_1" line.long 0x20 "RM_L4PER_GPIO5_CONTEXT,This register contains dedicated GPIO5 context statuses" bitfld.long 0x20 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x24 "PM_L4PER_GPIO6_WKDEP,This register controls wakeup dependency based on GPIO6 service requests" bitfld.long 0x24 17. "WKUPDEP_GPIO6_IRQ2_EVE2,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_EVE2_0,WKUPDEP_GPIO6_IRQ2_EVE2_1" bitfld.long 0x24 16. "WKUPDEP_GPIO6_IRQ2_EVE1,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_EVE1_0,WKUPDEP_GPIO6_IRQ2_EVE1_1" newline bitfld.long 0x24 15. "WKUPDEP_GPIO6_IRQ2_DSP2,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_DSP2_0,WKUPDEP_GPIO6_IRQ2_DSP2_1" bitfld.long 0x24 14. "WKUPDEP_GPIO6_IRQ2_IPU1,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_IPU1_0,WKUPDEP_GPIO6_IRQ2_IPU1_1" newline bitfld.long 0x24 12. "WKUPDEP_GPIO6_IRQ2_DSP1,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_DSP1_0,WKUPDEP_GPIO6_IRQ2_DSP1_1" bitfld.long 0x24 11. "WKUPDEP_GPIO6_IRQ2_IPU2,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_IPU2_0,WKUPDEP_GPIO6_IRQ2_IPU2_1" newline bitfld.long 0x24 10. "WKUPDEP_GPIO6_IRQ2_MPU,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ2_MPU_0,WKUPDEP_GPIO6_IRQ2_MPU_1" bitfld.long 0x24 7. "WKUPDEP_GPIO6_IRQ1_EVE2,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_EVE2_0,WKUPDEP_GPIO6_IRQ1_EVE2_1" newline bitfld.long 0x24 6. "WKUPDEP_GPIO6_IRQ1_EVE1,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_EVE1_0,WKUPDEP_GPIO6_IRQ1_EVE1_1" bitfld.long 0x24 5. "WKUPDEP_GPIO6_IRQ1_DSP2,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_DSP2_0,WKUPDEP_GPIO6_IRQ1_DSP2_1" newline bitfld.long 0x24 4. "WKUPDEP_GPIO6_IRQ1_IPU1,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_IPU1_0,WKUPDEP_GPIO6_IRQ1_IPU1_1" bitfld.long 0x24 2. "WKUPDEP_GPIO6_IRQ1_DSP1,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_DSP1_0,WKUPDEP_GPIO6_IRQ1_DSP1_1" newline bitfld.long 0x24 1. "WKUPDEP_GPIO6_IRQ1_IPU2,5Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_IPU2_0,WKUPDEP_GPIO6_IRQ1_IPU2_1" bitfld.long 0x24 0. "WKUPDEP_GPIO6_IRQ1_MPU,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO6_IRQ1_MPU_0,WKUPDEP_GPIO6_IRQ1_MPU_1" line.long 0x28 "RM_L4PER_GPIO6_CONTEXT,This register contains dedicated GPIO6 context statuses" bitfld.long 0x28 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x8C++0x03 line.long 0x00 "RM_L4PER_HDQ1W_CONTEXT,This register contains dedicated HDQ1W context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x94++0x03 line.long 0x00 "RM_L4PER2_PWMSS2_CONTEXT,This register contains dedicated PWMSS2 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x9C++0x43 line.long 0x00 "RM_L4PER2_PWMSS3_CONTEXT,This register contains dedicated PWMSS3 context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x04 "PM_L4PER_I2C1_WKDEP,This register controls wakeup dependency based on I2C1 service requests" bitfld.long 0x04 15. "WKUPDEP_I2C1_DMA_DSP2,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_DMA_DSP2_0,WKUPDEP_I2C1_DMA_DSP2_1" bitfld.long 0x04 13. "WKUPDEP_I2C1_DMA_SDMA,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_DMA_SDMA_0,WKUPDEP_I2C1_DMA_SDMA_1" newline bitfld.long 0x04 12. "WKUPDEP_I2C1_DMA_DSP1,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_DMA_DSP1_0,WKUPDEP_I2C1_DMA_DSP1_1" bitfld.long 0x04 7. "WKUPDEP_I2C1_IRQ_EVE2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_EVE2_0,WKUPDEP_I2C1_IRQ_EVE2_1" newline bitfld.long 0x04 6. "WKUPDEP_I2C1_IRQ_EVE1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_EVE1_0,WKUPDEP_I2C1_IRQ_EVE1_1" bitfld.long 0x04 5. "WKUPDEP_I2C1_IRQ_DSP2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_DSP2_0,WKUPDEP_I2C1_IRQ_DSP2_1" newline bitfld.long 0x04 4. "WKUPDEP_I2C1_IRQ_IPU1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_IPU1_0,WKUPDEP_I2C1_IRQ_IPU1_1" bitfld.long 0x04 2. "WKUPDEP_I2C1_IRQ_DSP1,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_DSP1_0,WKUPDEP_I2C1_IRQ_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_I2C1_IRQ_IPU2,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_IPU2_0,WKUPDEP_I2C1_IRQ_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_I2C1_IRQ_MPU,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C1_IRQ_MPU_0,WKUPDEP_I2C1_IRQ_MPU_1" line.long 0x08 "RM_L4PER_I2C1_CONTEXT,This register contains dedicated I2C1 context statuses" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x0C "PM_L4PER_I2C2_WKDEP,This register controls wakeup dependency based on I2C2 service requests" bitfld.long 0x0C 15. "WKUPDEP_I2C2_DMA_DSP2,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_DMA_DSP2_0,WKUPDEP_I2C2_DMA_DSP2_1" bitfld.long 0x0C 13. "WKUPDEP_I2C2_DMA_SDMA,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_DMA_SDMA_0,WKUPDEP_I2C2_DMA_SDMA_1" newline bitfld.long 0x0C 12. "WKUPDEP_I2C2_DMA_DSP1,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_DMA_DSP1_0,WKUPDEP_I2C2_DMA_DSP1_1" bitfld.long 0x0C 7. "WKUPDEP_I2C2_IRQ_EVE2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_EVE2_0,WKUPDEP_I2C2_IRQ_EVE2_1" newline bitfld.long 0x0C 6. "WKUPDEP_I2C2_IRQ_EVE1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_EVE1_0,WKUPDEP_I2C2_IRQ_EVE1_1" bitfld.long 0x0C 5. "WKUPDEP_I2C2_IRQ_DSP2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_DSP2_0,WKUPDEP_I2C2_IRQ_DSP2_1" newline bitfld.long 0x0C 4. "WKUPDEP_I2C2_IRQ_IPU1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_IPU1_0,WKUPDEP_I2C2_IRQ_IPU1_1" bitfld.long 0x0C 2. "WKUPDEP_I2C2_IRQ_DSP1,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_DSP1_0,WKUPDEP_I2C2_IRQ_DSP1_1" newline bitfld.long 0x0C 1. "WKUPDEP_I2C2_IRQ_IPU2,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_IPU2_0,WKUPDEP_I2C2_IRQ_IPU2_1" bitfld.long 0x0C 0. "WKUPDEP_I2C2_IRQ_MPU,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C2_IRQ_MPU_0,WKUPDEP_I2C2_IRQ_MPU_1" line.long 0x10 "RM_L4PER_I2C2_CONTEXT,This register contains dedicated I2C2 context statuses" bitfld.long 0x10 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x14 "PM_L4PER_I2C3_WKDEP,This register controls wakeup dependency based on I2C3 service requests" bitfld.long 0x14 15. "WKUPDEP_I2C3_DMA_DSP2,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_DMA_DSP2_0,WKUPDEP_I2C3_DMA_DSP2_1" bitfld.long 0x14 13. "WKUPDEP_I2C3_DMA_SDMA,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_DMA_SDMA_0,WKUPDEP_I2C3_DMA_SDMA_1" newline bitfld.long 0x14 12. "WKUPDEP_I2C3_DMA_DSP1,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_DMA_DSP1_0,WKUPDEP_I2C3_DMA_DSP1_1" bitfld.long 0x14 7. "WKUPDEP_I2C3_IRQ_EVE2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_EVE2_0,WKUPDEP_I2C3_IRQ_EVE2_1" newline bitfld.long 0x14 6. "WKUPDEP_I2C3_IRQ_EVE1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_EVE1_0,WKUPDEP_I2C3_IRQ_EVE1_1" bitfld.long 0x14 5. "WKUPDEP_I2C3_IRQ_DSP2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_DSP2_0,WKUPDEP_I2C3_IRQ_DSP2_1" newline bitfld.long 0x14 4. "WKUPDEP_I2C3_IRQ_IPU1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_IPU1_0,WKUPDEP_I2C3_IRQ_IPU1_1" bitfld.long 0x14 2. "WKUPDEP_I2C3_IRQ_DSP1,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_DSP1_0,WKUPDEP_I2C3_IRQ_DSP1_1" newline bitfld.long 0x14 1. "WKUPDEP_I2C3_IRQ_IPU2,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_IPU2_0,WKUPDEP_I2C3_IRQ_IPU2_1" bitfld.long 0x14 0. "WKUPDEP_I2C3_IRQ_MPU,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C3_IRQ_MPU_0,WKUPDEP_I2C3_IRQ_MPU_1" line.long 0x18 "RM_L4PER_I2C3_CONTEXT,This register contains dedicated I2C3 context statuses" bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x1C "PM_L4PER_I2C4_WKDEP,This register controls wakeup dependency based on I2C4 service requests" bitfld.long 0x1C 15. "WKUPDEP_I2C4_DMA_DSP2,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_DMA_DSP2_0,WKUPDEP_I2C4_DMA_DSP2_1" bitfld.long 0x1C 13. "WKUPDEP_I2C4_DMA_SDMA,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_DMA_SDMA_0,WKUPDEP_I2C4_DMA_SDMA_1" newline bitfld.long 0x1C 12. "WKUPDEP_I2C4_DMA_DSP1,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_DMA_DSP1_0,WKUPDEP_I2C4_DMA_DSP1_1" bitfld.long 0x1C 7. "WKUPDEP_I2C4_IRQ_EVE2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_EVE2_0,WKUPDEP_I2C4_IRQ_EVE2_1" newline bitfld.long 0x1C 6. "WKUPDEP_I2C4_IRQ_EVE1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_EVE1_0,WKUPDEP_I2C4_IRQ_EVE1_1" bitfld.long 0x1C 5. "WKUPDEP_I2C4_IRQ_DSP2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_DSP2_0,WKUPDEP_I2C4_IRQ_DSP2_1" newline bitfld.long 0x1C 4. "WKUPDEP_I2C4_IRQ_IPU1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_IPU1_0,WKUPDEP_I2C4_IRQ_IPU1_1" bitfld.long 0x1C 2. "WKUPDEP_I2C4_IRQ_DSP1,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_DSP1_0,WKUPDEP_I2C4_IRQ_DSP1_1" newline bitfld.long 0x1C 1. "WKUPDEP_I2C4_IRQ_IPU2,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_IPU2_0,WKUPDEP_I2C4_IRQ_IPU2_1" bitfld.long 0x1C 0. "WKUPDEP_I2C4_IRQ_MPU,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_I2C4_IRQ_MPU_0,WKUPDEP_I2C4_IRQ_MPU_1" line.long 0x20 "RM_L4PER_I2C4_CONTEXT,This register contains dedicated I2C4 context statuses" bitfld.long 0x20 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x24 "RM_L4PER_L4PER1_CONTEXT,This register contains dedicated L4_PER1 context statuses" bitfld.long 0x24 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" bitfld.long 0x24 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x28 "RM_L4PER2_PWMSS1_CONTEXT,This register contains dedicated PWMSS1 context statuses" bitfld.long 0x28 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x2C "PM_L4PER_TIMER13_WKDEP,This register controls wakeup dependency based on TIMER13 service requests" bitfld.long 0x2C 7. "WKUPDEP_TIMER13_EVE2,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_EVE2_0,WKUPDEP_TIMER13_EVE2_1" bitfld.long 0x2C 6. "WKUPDEP_TIMER13_EVE1,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_EVE1_0,WKUPDEP_TIMER13_EVE1_1" newline bitfld.long 0x2C 5. "WKUPDEP_TIMER13_DSP2,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_DSP2_0,WKUPDEP_TIMER13_DSP2_1" bitfld.long 0x2C 4. "WKUPDEP_TIMER13_IPU1,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_IPU1_0,WKUPDEP_TIMER13_IPU1_1" newline bitfld.long 0x2C 2. "WKUPDEP_TIMER13_DSP1,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_DSP1_0,WKUPDEP_TIMER13_DSP1_1" bitfld.long 0x2C 1. "WKUPDEP_TIMER13_IPU2,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_IPU2_0,WKUPDEP_TIMER13_IPU2_1" newline bitfld.long 0x2C 0. "WKUPDEP_TIMER13_MPU,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER13_MPU_0,WKUPDEP_TIMER13_MPU_1" line.long 0x30 "RM_L4PER3_TIMER13_CONTEXT,This register contains dedicated TIMER13 context statuses" bitfld.long 0x30 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x34 "PM_L4PER_TIMER14_WKDEP,This register controls wakeup dependency based on TIMER14 service requests" bitfld.long 0x34 7. "WKUPDEP_TIMER14_EVE2,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_EVE2_0,WKUPDEP_TIMER14_EVE2_1" bitfld.long 0x34 6. "WKUPDEP_TIMER14_EVE1,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_EVE1_0,WKUPDEP_TIMER14_EVE1_1" newline bitfld.long 0x34 5. "WKUPDEP_TIMER14_DSP2,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_DSP2_0,WKUPDEP_TIMER14_DSP2_1" bitfld.long 0x34 4. "WKUPDEP_TIMER14_IPU1,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_IPU1_0,WKUPDEP_TIMER14_IPU1_1" newline bitfld.long 0x34 2. "WKUPDEP_TIMER14_DSP1,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_DSP1_0,WKUPDEP_TIMER14_DSP1_1" bitfld.long 0x34 1. "WKUPDEP_TIMER14_IPU2,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_IPU2_0,WKUPDEP_TIMER14_IPU2_1" newline bitfld.long 0x34 0. "WKUPDEP_TIMER14_MPU,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER14_MPU_0,WKUPDEP_TIMER14_MPU_1" line.long 0x38 "RM_L4PER3_TIMER14_CONTEXT,This register contains dedicated TIMER14 context statuses" bitfld.long 0x38 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x3C "PM_L4PER_TIMER15_WKDEP,This register controls wakeup dependency based on TIMER15 service requests" bitfld.long 0x3C 7. "WKUPDEP_TIMER15_EVE2,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_EVE2_0,WKUPDEP_TIMER15_EVE2_1" bitfld.long 0x3C 6. "WKUPDEP_TIMER15_EVE1,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_EVE1_0,WKUPDEP_TIMER15_EVE1_1" newline bitfld.long 0x3C 5. "WKUPDEP_TIMER15_DSP2,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_DSP2_0,WKUPDEP_TIMER15_DSP2_1" bitfld.long 0x3C 4. "WKUPDEP_TIMER15_IPU1,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_IPU1_0,WKUPDEP_TIMER15_IPU1_1" newline bitfld.long 0x3C 2. "WKUPDEP_TIMER15_DSP1,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_DSP1_0,WKUPDEP_TIMER15_DSP1_1" bitfld.long 0x3C 1. "WKUPDEP_TIMER15_IPU2,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_IPU2_0,WKUPDEP_TIMER15_IPU2_1" newline bitfld.long 0x3C 0. "WKUPDEP_TIMER15_MPU,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER15_MPU_0,WKUPDEP_TIMER15_MPU_1" line.long 0x40 "RM_L4PER3_TIMER15_CONTEXT,This register contains dedicated TIMER15 context statuses" bitfld.long 0x40 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0xF0++0xAF line.long 0x00 "PM_L4PER_MCSPI1_WKDEP,This register controls wakeup dependency based on MCSPI1 service requests" bitfld.long 0x00 7. "WKUPDEP_MCSPI1_EVE2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_EVE2_0,WKUPDEP_MCSPI1_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_MCSPI1_EVE1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_EVE1_0,WKUPDEP_MCSPI1_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_MCSPI1_DSP2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_DSP2_0,WKUPDEP_MCSPI1_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_MCSPI1_IPU1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_IPU1_0,WKUPDEP_MCSPI1_IPU1_1" newline bitfld.long 0x00 3. "WKUPDEP_MCSPI1_SDMA,Wakeup dependency from MCSPI1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_SDMA_0,WKUPDEP_MCSPI1_SDMA_1" bitfld.long 0x00 2. "WKUPDEP_MCSPI1_DSP1,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_DSP1_0,WKUPDEP_MCSPI1_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_MCSPI1_IPU2,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_IPU2_0,WKUPDEP_MCSPI1_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_MCSPI1_MPU,Wakeup dependency from MCSPI1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI1_MPU_0,WKUPDEP_MCSPI1_MPU_1" line.long 0x04 "RM_L4PER_MCSPI1_CONTEXT,This register contains dedicated MCSPI1 context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_L4PER_MCSPI2_WKDEP,This register controls wakeup dependency based on MCSPI2 service requests" bitfld.long 0x08 7. "WKUPDEP_MCSPI2_EVE2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_EVE2_0,WKUPDEP_MCSPI2_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_MCSPI2_EVE1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_EVE1_0,WKUPDEP_MCSPI2_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_MCSPI2_DSP2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_DSP2_0,WKUPDEP_MCSPI2_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_MCSPI2_IPU1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_IPU1_0,WKUPDEP_MCSPI2_IPU1_1" newline bitfld.long 0x08 3. "WKUPDEP_MCSPI2_SDMA,Wakeup dependency from MCSPI2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_SDMA_0,WKUPDEP_MCSPI2_SDMA_1" bitfld.long 0x08 2. "WKUPDEP_MCSPI2_DSP1,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_DSP1_0,WKUPDEP_MCSPI2_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_MCSPI2_IPU2,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_IPU2_0,WKUPDEP_MCSPI2_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_MCSPI2_MPU,Wakeup dependency from MCSPI2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI2_MPU_0,WKUPDEP_MCSPI2_MPU_1" line.long 0x0C "RM_L4PER_MCSPI2_CONTEXT,This register contains dedicated MCSPI2 context statuses" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_L4PER_MCSPI3_WKDEP,This register controls wakeup dependency based on MCSPI3 service requests" bitfld.long 0x10 7. "WKUPDEP_MCSPI3_EVE2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_EVE2_0,WKUPDEP_MCSPI3_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_MCSPI3_EVE1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_EVE1_0,WKUPDEP_MCSPI3_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_MCSPI3_DSP2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_DSP2_0,WKUPDEP_MCSPI3_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_MCSPI3_IPU1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_IPU1_0,WKUPDEP_MCSPI3_IPU1_1" newline bitfld.long 0x10 3. "WKUPDEP_MCSPI3_SDMA,Wakeup dependency from MCSPI3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_SDMA_0,WKUPDEP_MCSPI3_SDMA_1" bitfld.long 0x10 2. "WKUPDEP_MCSPI3_DSP1,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_DSP1_0,WKUPDEP_MCSPI3_DSP1_1" newline bitfld.long 0x10 1. "WKUPDEP_MCSPI3_IPU2,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_IPU2_0,WKUPDEP_MCSPI3_IPU2_1" bitfld.long 0x10 0. "WKUPDEP_MCSPI3_MPU,Wakeup dependency from MCSPI3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI3_MPU_0,WKUPDEP_MCSPI3_MPU_1" line.long 0x14 "RM_L4PER_MCSPI3_CONTEXT,This register contains dedicated MCSPI3 context statuses" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_L4PER_MCSPI4_WKDEP,This register controls wakeup dependency based on MCSPI4 service requests" bitfld.long 0x18 7. "WKUPDEP_MCSPI4_EVE2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_EVE2_0,WKUPDEP_MCSPI4_EVE2_1" bitfld.long 0x18 6. "WKUPDEP_MCSPI4_EVE1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_EVE1_0,WKUPDEP_MCSPI4_EVE1_1" newline bitfld.long 0x18 5. "WKUPDEP_MCSPI4_DSP2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_DSP2_0,WKUPDEP_MCSPI4_DSP2_1" bitfld.long 0x18 4. "WKUPDEP_MCSPI4_IPU1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_IPU1_0,WKUPDEP_MCSPI4_IPU1_1" newline bitfld.long 0x18 3. "WKUPDEP_MCSPI4_SDMA,Wakeup dependency from MCSPI4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_SDMA_0,WKUPDEP_MCSPI4_SDMA_1" bitfld.long 0x18 2. "WKUPDEP_MCSPI4_DSP1,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_DSP1_0,WKUPDEP_MCSPI4_DSP1_1" newline bitfld.long 0x18 1. "WKUPDEP_MCSPI4_IPU2,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_IPU2_0,WKUPDEP_MCSPI4_IPU2_1" bitfld.long 0x18 0. "WKUPDEP_MCSPI4_MPU,Wakeup dependency from MCSPI4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCSPI4_MPU_0,WKUPDEP_MCSPI4_MPU_1" line.long 0x1C "RM_L4PER_MCSPI4_CONTEXT,This register contains dedicated MCSPI4 context statuses" bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x20 "PM_L4PER_GPIO7_WKDEP,This register controls wakeup dependency based on GPIO7 service requests" bitfld.long 0x20 17. "WKUPDEP_GPIO7_IRQ2_EVE2,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_EVE2_0,WKUPDEP_GPIO7_IRQ2_EVE2_1" bitfld.long 0x20 16. "WKUPDEP_GPIO7_IRQ2_EVE1,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_EVE1_0,WKUPDEP_GPIO7_IRQ2_EVE1_1" newline bitfld.long 0x20 15. "WKUPDEP_GPIO7_IRQ2_DSP2,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_DSP2_0,WKUPDEP_GPIO7_IRQ2_DSP2_1" bitfld.long 0x20 14. "WKUPDEP_GPIO7_IRQ2_IPU1,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_IPU1_0,WKUPDEP_GPIO7_IRQ2_IPU1_1" newline bitfld.long 0x20 12. "WKUPDEP_GPIO7_IRQ2_DSP1,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_DSP1_0,WKUPDEP_GPIO7_IRQ2_DSP1_1" bitfld.long 0x20 11. "WKUPDEP_GPIO7_IRQ2_IPU2,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_IPU2_0,WKUPDEP_GPIO7_IRQ2_IPU2_1" newline bitfld.long 0x20 10. "WKUPDEP_GPIO7_IRQ2_MPU,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ2_MPU_0,WKUPDEP_GPIO7_IRQ2_MPU_1" bitfld.long 0x20 7. "WKUPDEP_GPIO7_IRQ1_EVE2,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_EVE2_0,WKUPDEP_GPIO7_IRQ1_EVE2_1" newline bitfld.long 0x20 6. "WKUPDEP_GPIO7_IRQ1_EVE1,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_EVE1_0,WKUPDEP_GPIO7_IRQ1_EVE1_1" bitfld.long 0x20 5. "WKUPDEP_GPIO7_IRQ1_DSP2,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_DSP2_0,WKUPDEP_GPIO7_IRQ1_DSP2_1" newline bitfld.long 0x20 4. "WKUPDEP_GPIO7_IRQ1_IPU1,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_IPU1_0,WKUPDEP_GPIO7_IRQ1_IPU1_1" bitfld.long 0x20 2. "WKUPDEP_GPIO7_IRQ1_DSP1,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_DSP1_0,WKUPDEP_GPIO7_IRQ1_DSP1_1" newline bitfld.long 0x20 1. "WKUPDEP_GPIO7_IRQ1_IPU2,5Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_IPU2_0,WKUPDEP_GPIO7_IRQ1_IPU2_1" bitfld.long 0x20 0. "WKUPDEP_GPIO7_IRQ1_MPU,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO7_IRQ1_MPU_0,WKUPDEP_GPIO7_IRQ1_MPU_1" line.long 0x24 "RM_L4PER_GPIO7_CONTEXT,This register contains dedicated GPIO7 context statuses" bitfld.long 0x24 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x28 "PM_L4PER_GPIO8_WKDEP,This register controls wakeup dependency based on GPIO8 service requests" bitfld.long 0x28 17. "WKUPDEP_GPIO8_IRQ2_EVE2,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_EVE2_0,WKUPDEP_GPIO8_IRQ2_EVE2_1" bitfld.long 0x28 16. "WKUPDEP_GPIO8_IRQ2_EVE1,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_EVE1_0,WKUPDEP_GPIO8_IRQ2_EVE1_1" newline bitfld.long 0x28 15. "WKUPDEP_GPIO8_IRQ2_DSP2,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_DSP2_0,WKUPDEP_GPIO8_IRQ2_DSP2_1" bitfld.long 0x28 14. "WKUPDEP_GPIO8_IRQ2_IPU1,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_IPU1_0,WKUPDEP_GPIO8_IRQ2_IPU1_1" newline bitfld.long 0x28 12. "WKUPDEP_GPIO8_IRQ2_DSP1,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_DSP1_0,WKUPDEP_GPIO8_IRQ2_DSP1_1" bitfld.long 0x28 11. "WKUPDEP_GPIO8_IRQ2_IPU2,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_IPU2_0,WKUPDEP_GPIO8_IRQ2_IPU2_1" newline bitfld.long 0x28 10. "WKUPDEP_GPIO8_IRQ2_MPU,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ2_MPU_0,WKUPDEP_GPIO8_IRQ2_MPU_1" bitfld.long 0x28 7. "WKUPDEP_GPIO8_IRQ1_EVE2,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_EVE2_0,WKUPDEP_GPIO8_IRQ1_EVE2_1" newline bitfld.long 0x28 6. "WKUPDEP_GPIO8_IRQ1_EVE1,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_EVE1_0,WKUPDEP_GPIO8_IRQ1_EVE1_1" bitfld.long 0x28 5. "WKUPDEP_GPIO8_IRQ1_DSP2,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_DSP2_0,WKUPDEP_GPIO8_IRQ1_DSP2_1" newline bitfld.long 0x28 4. "WKUPDEP_GPIO8_IRQ1_IPU1,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_IPU1_0,WKUPDEP_GPIO8_IRQ1_IPU1_1" bitfld.long 0x28 2. "WKUPDEP_GPIO8_IRQ1_DSP1,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_DSP1_0,WKUPDEP_GPIO8_IRQ1_DSP1_1" newline bitfld.long 0x28 1. "WKUPDEP_GPIO8_IRQ1_IPU2,5Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_IPU2_0,WKUPDEP_GPIO8_IRQ1_IPU2_1" bitfld.long 0x28 0. "WKUPDEP_GPIO8_IRQ1_MPU,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO8_IRQ1_MPU_0,WKUPDEP_GPIO8_IRQ1_MPU_1" line.long 0x2C "RM_L4PER_GPIO8_CONTEXT,This register contains dedicated GPIO8 context statuses" bitfld.long 0x2C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x30 "PM_L4PER_MMC3_WKDEP,This register controls wakeup dependency based on MMC3 service requests" bitfld.long 0x30 7. "WKUPDEP_MMC3_EVE2,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_EVE2_0,WKUPDEP_MMC3_EVE2_1" bitfld.long 0x30 6. "WKUPDEP_MMC3_EVE1,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_EVE1_0,WKUPDEP_MMC3_EVE1_1" newline bitfld.long 0x30 5. "WKUPDEP_MMC3_DSP2,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_DSP2_0,WKUPDEP_MMC3_DSP2_1" bitfld.long 0x30 4. "WKUPDEP_MMC3_IPU1,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_IPU1_0,WKUPDEP_MMC3_IPU1_1" newline bitfld.long 0x30 3. "WKUPDEP_MMC3_SDMA,Wakeup dependency from MMC3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_SDMA_0,WKUPDEP_MMC3_SDMA_1" bitfld.long 0x30 2. "WKUPDEP_MMC3_DSP1,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_DSP1_0,WKUPDEP_MMC3_DSP1_1" newline bitfld.long 0x30 1. "WKUPDEP_MMC3_IPU2,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_IPU2_0,WKUPDEP_MMC3_IPU2_1" bitfld.long 0x30 0. "WKUPDEP_MMC3_MPU,Wakeup dependency from MMC3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC3_MPU_0,WKUPDEP_MMC3_MPU_1" line.long 0x34 "RM_L4PER_MMC3_CONTEXT,This register contains dedicated MMC3 context statuses" bitfld.long 0x34 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" bitfld.long 0x34 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x38 "PM_L4PER_MMC4_WKDEP,This register controls wakeup dependency based on MMC4 service requests" bitfld.long 0x38 7. "WKUPDEP_MMC4_EVE2,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_EVE2_0,WKUPDEP_MMC4_EVE2_1" bitfld.long 0x38 6. "WKUPDEP_MMC4_EVE1,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_EVE1_0,WKUPDEP_MMC4_EVE1_1" newline bitfld.long 0x38 5. "WKUPDEP_MMC4_DSP2,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_DSP2_0,WKUPDEP_MMC4_DSP2_1" bitfld.long 0x38 4. "WKUPDEP_MMC4_IPU1,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_IPU1_0,WKUPDEP_MMC4_IPU1_1" newline bitfld.long 0x38 3. "WKUPDEP_MMC4_SDMA,Wakeup dependency from MMC4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_SDMA_0,WKUPDEP_MMC4_SDMA_1" bitfld.long 0x38 2. "WKUPDEP_MMC4_DSP1,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_DSP1_0,WKUPDEP_MMC4_DSP1_1" newline bitfld.long 0x38 1. "WKUPDEP_MMC4_IPU2,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_IPU2_0,WKUPDEP_MMC4_IPU2_1" bitfld.long 0x38 0. "WKUPDEP_MMC4_MPU,Wakeup dependency from MMC4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MMC4_MPU_0,WKUPDEP_MMC4_MPU_1" line.long 0x3C "RM_L4PER_MMC4_CONTEXT,This register contains dedicated MMC4 context statuses" bitfld.long 0x3C 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" bitfld.long 0x3C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x40 "PM_L4PER_TIMER16_WKDEP,This register controls wakeup dependency based on TIMER16 service requests" bitfld.long 0x40 7. "WKUPDEP_TIMER16_EVE2,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_EVE2_0,WKUPDEP_TIMER16_EVE2_1" bitfld.long 0x40 6. "WKUPDEP_TIMER16_EVE1,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_EVE1_0,WKUPDEP_TIMER16_EVE1_1" newline bitfld.long 0x40 5. "WKUPDEP_TIMER16_DSP2,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_DSP2_0,WKUPDEP_TIMER16_DSP2_1" bitfld.long 0x40 4. "WKUPDEP_TIMER16_IPU1,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_IPU1_0,WKUPDEP_TIMER16_IPU1_1" newline bitfld.long 0x40 2. "WKUPDEP_TIMER16_DSP1,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_DSP1_0,WKUPDEP_TIMER16_DSP1_1" bitfld.long 0x40 1. "WKUPDEP_TIMER16_IPU2,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_IPU2_0,WKUPDEP_TIMER16_IPU2_1" newline bitfld.long 0x40 0. "WKUPDEP_TIMER16_MPU,6Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER16_MPU_0,WKUPDEP_TIMER16_MPU_1" line.long 0x44 "RM_L4PER3_TIMER16_CONTEXT,This register contains dedicated TIMER16 context statuses" bitfld.long 0x44 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x48 "PM_L4PER2_QSPI_WKDEP,This register controls wakeup dependency based on QSPI service requests" bitfld.long 0x48 7. "WKUPDEP_QSPI_EVE2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_EVE2_0,WKUPDEP_QSPI_EVE2_1" bitfld.long 0x48 6. "WKUPDEP_QSPI_EVE1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_EVE1_0,WKUPDEP_QSPI_EVE1_1" newline bitfld.long 0x48 5. "WKUPDEP_QSPI_DSP2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_DSP2_0,WKUPDEP_QSPI_DSP2_1" bitfld.long 0x48 4. "WKUPDEP_QSPI_IPU1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_IPU1_0,WKUPDEP_QSPI_IPU1_1" newline bitfld.long 0x48 2. "WKUPDEP_QSPI_DSP1,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_DSP1_0,WKUPDEP_QSPI_DSP1_1" bitfld.long 0x48 1. "WKUPDEP_QSPI_IPU2,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_IPU2_0,WKUPDEP_QSPI_IPU2_1" newline bitfld.long 0x48 0. "WKUPDEP_QSPI_MPU,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_QSPI_MPU_0,WKUPDEP_QSPI_MPU_1" line.long 0x4C "RM_L4PER2_QSPI_CONTEXT,This register contains dedicated QSPI context statuses" bitfld.long 0x4C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x50 "PM_L4PER_UART1_WKDEP,This register controls wakeup dependency based on UART1 service requests" bitfld.long 0x50 7. "WKUPDEP_UART1_EVE2,Wakeup dependency from UART1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_EVE2_0,WKUPDEP_UART1_EVE2_1" bitfld.long 0x50 6. "WKUPDEP_UART1_EVE1,Wakeup dependency from UART1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_EVE1_0,WKUPDEP_UART1_EVE1_1" newline bitfld.long 0x50 5. "WKUPDEP_UART1_DSP2,Wakeup dependency from UART1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_DSP2_0,WKUPDEP_UART1_DSP2_1" bitfld.long 0x50 4. "WKUPDEP_UART1_IPU1,Wakeup dependency from UART1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_IPU1_0,WKUPDEP_UART1_IPU1_1" newline bitfld.long 0x50 3. "WKUPDEP_UART1_SDMA,Wakeup dependency from UART1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_SDMA_0,WKUPDEP_UART1_SDMA_1" bitfld.long 0x50 2. "WKUPDEP_UART1_DSP1,Wakeup dependency from UART1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_DSP1_0,WKUPDEP_UART1_DSP1_1" newline bitfld.long 0x50 1. "WKUPDEP_UART1_IPU2,Wakeup dependency from UART1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_IPU2_0,WKUPDEP_UART1_IPU2_1" bitfld.long 0x50 0. "WKUPDEP_UART1_MPU,Wakeup dependency from UART1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART1_MPU_0,WKUPDEP_UART1_MPU_1" line.long 0x54 "RM_L4PER_UART1_CONTEXT,This register contains dedicated UART1 context statuses" bitfld.long 0x54 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x54 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x58 "PM_L4PER_UART2_WKDEP,This register controls wakeup dependency based on UART2 service requests" bitfld.long 0x58 7. "WKUPDEP_UART2_EVE2,Wakeup dependency from UART2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_EVE2_0,WKUPDEP_UART2_EVE2_1" bitfld.long 0x58 6. "WKUPDEP_UART2_EVE1,Wakeup dependency from UART2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_EVE1_0,WKUPDEP_UART2_EVE1_1" newline bitfld.long 0x58 5. "WKUPDEP_UART2_DSP2,Wakeup dependency from UART2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_DSP2_0,WKUPDEP_UART2_DSP2_1" bitfld.long 0x58 4. "WKUPDEP_UART2_IPU1,Wakeup dependency from UART2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_IPU1_0,WKUPDEP_UART2_IPU1_1" newline bitfld.long 0x58 3. "WKUPDEP_UART2_SDMA,2Wakeup dependency from UART2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_SDMA_0,WKUPDEP_UART2_SDMA_1" bitfld.long 0x58 2. "WKUPDEP_UART2_DSP1,Wakeup dependency from UART2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_DSP1_0,WKUPDEP_UART2_DSP1_1" newline bitfld.long 0x58 1. "WKUPDEP_UART2_IPU2,Wakeup dependency from UART2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_IPU2_0,WKUPDEP_UART2_IPU2_1" bitfld.long 0x58 0. "WKUPDEP_UART2_MPU,Wakeup dependency from UART2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART2_MPU_0,WKUPDEP_UART2_MPU_1" line.long 0x5C "RM_L4PER_UART2_CONTEXT,This register contains dedicated UART2 context statuses" bitfld.long 0x5C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x5C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x60 "PM_L4PER_UART3_WKDEP,This register controls wakeup dependency based on UART3 service requests" bitfld.long 0x60 7. "WKUPDEP_UART3_EVE2,Wakeup dependency from UART3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_EVE2_0,WKUPDEP_UART3_EVE2_1" bitfld.long 0x60 6. "WKUPDEP_UART3_EVE1,Wakeup dependency from UART3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_EVE1_0,WKUPDEP_UART3_EVE1_1" newline bitfld.long 0x60 5. "WKUPDEP_UART3_DSP2,Wakeup dependency from UART3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_DSP2_0,WKUPDEP_UART3_DSP2_1" bitfld.long 0x60 4. "WKUPDEP_UART3_IPU1,Wakeup dependency from UART3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_IPU1_0,WKUPDEP_UART3_IPU1_1" newline bitfld.long 0x60 3. "WKUPDEP_UART3_SDMA,Wakeup dependency from UART3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_SDMA_0,WKUPDEP_UART3_SDMA_1" bitfld.long 0x60 2. "WKUPDEP_UART3_DSP1,Wakeup dependency from UART3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_DSP1_0,WKUPDEP_UART3_DSP1_1" newline bitfld.long 0x60 1. "WKUPDEP_UART3_IPU2,Wakeup dependency from UART3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_IPU2_0,WKUPDEP_UART3_IPU2_1" bitfld.long 0x60 0. "WKUPDEP_UART3_MPU,Wakeup dependency from UART3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART3_MPU_0,WKUPDEP_UART3_MPU_1" line.long 0x64 "RM_L4PER_UART3_CONTEXT,This register contains dedicated UART3 context statuses" bitfld.long 0x64 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x64 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x68 "PM_L4PER_UART4_WKDEP,This register controls wakeup dependency based on UART4 service requests" bitfld.long 0x68 7. "WKUPDEP_UART4_EVE2,Wakeup dependency from UART4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_EVE2_0,WKUPDEP_UART4_EVE2_1" bitfld.long 0x68 6. "WKUPDEP_UART4_EVE1,Wakeup dependency from UART4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_EVE1_0,WKUPDEP_UART4_EVE1_1" newline bitfld.long 0x68 5. "WKUPDEP_UART4_DSP2,Wakeup dependency from UART4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_DSP2_0,WKUPDEP_UART4_DSP2_1" bitfld.long 0x68 4. "WKUPDEP_UART4_IPU1,Wakeup dependency from UART4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_IPU1_0,WKUPDEP_UART4_IPU1_1" newline bitfld.long 0x68 3. "WKUPDEP_UART4_SDMA,Wakeup dependency from UART4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_SDMA_0,WKUPDEP_UART4_SDMA_1" bitfld.long 0x68 2. "WKUPDEP_UART4_DSP1,Wakeup dependency from UART4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_DSP1_0,WKUPDEP_UART4_DSP1_1" newline bitfld.long 0x68 1. "WKUPDEP_UART4_IPU2,Wakeup dependency from UART4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_IPU2_0,WKUPDEP_UART4_IPU2_1" bitfld.long 0x68 0. "WKUPDEP_UART4_MPU,Wakeup dependency from UART4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART4_MPU_0,WKUPDEP_UART4_MPU_1" line.long 0x6C "RM_L4PER_UART4_CONTEXT,This register contains dedicated UART4 context statuses" bitfld.long 0x6C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x6C 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x70 "PM_L4PER2_MCASP2_WKDEP,This register controls wakeup dependency based on MCASP2 service requests" bitfld.long 0x70 15. "WKUPDEP_MCASP2_DMA_DSP2,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_DMA_DSP2_0,WKUPDEP_MCASP2_DMA_DSP2_1" bitfld.long 0x70 13. "WKUPDEP_MCASP2_DMA_SDMA,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_DMA_SDMA_0,WKUPDEP_MCASP2_DMA_SDMA_1" newline bitfld.long 0x70 12. "WKUPDEP_MCASP2_DMA_DSP1,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_DMA_DSP1_0,WKUPDEP_MCASP2_DMA_DSP1_1" bitfld.long 0x70 7. "WKUPDEP_MCASP2_IRQ_EVE2,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_EVE2_0,WKUPDEP_MCASP2_IRQ_EVE2_1" newline bitfld.long 0x70 6. "WKUPDEP_MCASP2_IRQ_EVE1,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_EVE1_0,WKUPDEP_MCASP2_IRQ_EVE1_1" bitfld.long 0x70 5. "WKUPDEP_MCASP2_IRQ_DSP2,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_DSP2_0,WKUPDEP_MCASP2_IRQ_DSP2_1" newline bitfld.long 0x70 4. "WKUPDEP_MCASP2_IRQ_IPU1,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_IPU1_0,WKUPDEP_MCASP2_IRQ_IPU1_1" bitfld.long 0x70 2. "WKUPDEP_MCASP2_IRQ_DSP1,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_DSP1_0,WKUPDEP_MCASP2_IRQ_DSP1_1" newline bitfld.long 0x70 1. "WKUPDEP_MCASP2_IRQ_IPU2,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_IPU2_0,WKUPDEP_MCASP2_IRQ_IPU2_1" bitfld.long 0x70 0. "WKUPDEP_MCASP2_IRQ_MPU,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP2_IRQ_MPU_0,WKUPDEP_MCASP2_IRQ_MPU_1" line.long 0x74 "RM_L4PER2_MCASP2_CONTEXT,This register contains dedicated MCASP2 context statuses" bitfld.long 0x74 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x78 "PM_L4PER2_MCASP3_WKDEP,This register controls wakeup dependency based on MCASP3 service requests" bitfld.long 0x78 15. "WKUPDEP_MCASP3_DMA_DSP2,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_DMA_DSP2_0,WKUPDEP_MCASP3_DMA_DSP2_1" bitfld.long 0x78 13. "WKUPDEP_MCASP3_DMA_SDMA,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_DMA_SDMA_0,WKUPDEP_MCASP3_DMA_SDMA_1" newline bitfld.long 0x78 12. "WKUPDEP_MCASP3_DMA_DSP1,3Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_DMA_DSP1_0,WKUPDEP_MCASP3_DMA_DSP1_1" bitfld.long 0x78 7. "WKUPDEP_MCASP3_IRQ_EVE2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_EVE2_0,WKUPDEP_MCASP3_IRQ_EVE2_1" newline bitfld.long 0x78 6. "WKUPDEP_MCASP3_IRQ_EVE1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_EVE1_0,WKUPDEP_MCASP3_IRQ_EVE1_1" bitfld.long 0x78 5. "WKUPDEP_MCASP3_IRQ_DSP2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_DSP2_0,WKUPDEP_MCASP3_IRQ_DSP2_1" newline bitfld.long 0x78 4. "WKUPDEP_MCASP3_IRQ_IPU1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_IPU1_0,WKUPDEP_MCASP3_IRQ_IPU1_1" bitfld.long 0x78 2. "WKUPDEP_MCASP3_IRQ_DSP1,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_DSP1_0,WKUPDEP_MCASP3_IRQ_DSP1_1" newline bitfld.long 0x78 1. "WKUPDEP_MCASP3_IRQ_IPU2,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_IPU2_0,WKUPDEP_MCASP3_IRQ_IPU2_1" bitfld.long 0x78 0. "WKUPDEP_MCASP3_IRQ_MPU,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP3_IRQ_MPU_0,WKUPDEP_MCASP3_IRQ_MPU_1" line.long 0x7C "RM_L4PER2_MCASP3_CONTEXT,This register contains dedicated MCASP3 context statuses" bitfld.long 0x7C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x80 "PM_L4PER_UART5_WKDEP,This register controls wakeup dependency based on UART5 service requests" bitfld.long 0x80 7. "WKUPDEP_UART5_EVE2,Wakeup dependency from UART5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_EVE2_0,WKUPDEP_UART5_EVE2_1" bitfld.long 0x80 6. "WKUPDEP_UART5_EVE1,Wakeup dependency from UART5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_EVE1_0,WKUPDEP_UART5_EVE1_1" newline bitfld.long 0x80 5. "WKUPDEP_UART5_DSP2,Wakeup dependency from UART5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_DSP2_0,WKUPDEP_UART5_DSP2_1" bitfld.long 0x80 4. "WKUPDEP_UART5_IPU1,Wakeup dependency from UART5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_IPU1_0,WKUPDEP_UART5_IPU1_1" newline bitfld.long 0x80 3. "WKUPDEP_UART5_SDMA,Wakeup dependency from UART5 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_SDMA_0,WKUPDEP_UART5_SDMA_1" bitfld.long 0x80 2. "WKUPDEP_UART5_DSP1,Wakeup dependency from UART5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_DSP1_0,WKUPDEP_UART5_DSP1_1" newline bitfld.long 0x80 1. "WKUPDEP_UART5_IPU2,Wakeup dependency from UART5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_IPU2_0,WKUPDEP_UART5_IPU2_1" bitfld.long 0x80 0. "WKUPDEP_UART5_MPU,Wakeup dependency from UART5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART5_MPU_0,WKUPDEP_UART5_MPU_1" line.long 0x84 "RM_L4PER_UART5_CONTEXT,This register contains dedicated UART5 context statuses" bitfld.long 0x84 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x84 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x88 "PM_L4PER2_MCASP5_WKDEP,This register controls wakeup dependency based on MCASP5 service requests" bitfld.long 0x88 15. "WKUPDEP_MCASP5_DMA_DSP2,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_DMA_DSP2_0,WKUPDEP_MCASP5_DMA_DSP2_1" bitfld.long 0x88 13. "WKUPDEP_MCASP5_DMA_SDMA,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_DMA_SDMA_0,WKUPDEP_MCASP5_DMA_SDMA_1" newline bitfld.long 0x88 12. "WKUPDEP_MCASP5_DMA_DSP1,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_DMA_DSP1_0,WKUPDEP_MCASP5_DMA_DSP1_1" bitfld.long 0x88 7. "WKUPDEP_MCASP5_IRQ_EVE2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_EVE2_0,WKUPDEP_MCASP5_IRQ_EVE2_1" newline bitfld.long 0x88 6. "WKUPDEP_MCASP5_IRQ_EVE1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_EVE1_0,WKUPDEP_MCASP5_IRQ_EVE1_1" bitfld.long 0x88 5. "WKUPDEP_MCASP5_IRQ_DSP2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_DSP2_0,WKUPDEP_MCASP5_IRQ_DSP2_1" newline bitfld.long 0x88 4. "WKUPDEP_MCASP5_IRQ_IPU1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_IPU1_0,WKUPDEP_MCASP5_IRQ_IPU1_1" bitfld.long 0x88 2. "WKUPDEP_MCASP5_IRQ_DSP1,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_DSP1_0,WKUPDEP_MCASP5_IRQ_DSP1_1" newline bitfld.long 0x88 1. "WKUPDEP_MCASP5_IRQ_IPU2,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_IPU2_0,WKUPDEP_MCASP5_IRQ_IPU2_1" bitfld.long 0x88 0. "WKUPDEP_MCASP5_IRQ_MPU,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP5_IRQ_MPU_0,WKUPDEP_MCASP5_IRQ_MPU_1" line.long 0x8C "RM_L4PER2_MCASP5_CONTEXT,This register contains dedicated MCASP5 context statuses" bitfld.long 0x8C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x90 "PM_L4PER2_MCASP6_WKDEP,This register controls wakeup dependency based on MCASP6 service requests" bitfld.long 0x90 15. "WKUPDEP_MCASP6_DMA_DSP2,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_DMA_DSP2_0,WKUPDEP_MCASP6_DMA_DSP2_1" bitfld.long 0x90 13. "WKUPDEP_MCASP6_DMA_SDMA,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_DMA_SDMA_0,WKUPDEP_MCASP6_DMA_SDMA_1" newline bitfld.long 0x90 12. "WKUPDEP_MCASP6_DMA_DSP1,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_DMA_DSP1_0,WKUPDEP_MCASP6_DMA_DSP1_1" bitfld.long 0x90 7. "WKUPDEP_MCASP6_IRQ_EVE2,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_EVE2_0,WKUPDEP_MCASP6_IRQ_EVE2_1" newline bitfld.long 0x90 6. "WKUPDEP_MCASP6_IRQ_EVE1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_EVE1_0,WKUPDEP_MCASP6_IRQ_EVE1_1" bitfld.long 0x90 5. "WKUPDEP_MCASP6_IRQ_DSP2,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_DSP2_0,WKUPDEP_MCASP6_IRQ_DSP2_1" newline bitfld.long 0x90 4. "WKUPDEP_MCASP6_IRQ_IPU1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_IPU1_0,WKUPDEP_MCASP6_IRQ_IPU1_1" bitfld.long 0x90 2. "WKUPDEP_MCASP6_IRQ_DSP1,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_DSP1_0,WKUPDEP_MCASP6_IRQ_DSP1_1" newline bitfld.long 0x90 1. "WKUPDEP_MCASP6_IRQ_IPU2,Wakeup dependency from MCASP6 (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_IPU2_0,WKUPDEP_MCASP6_IRQ_IPU2_1" bitfld.long 0x90 0. "WKUPDEP_MCASP6_IRQ_MPU,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP6_IRQ_MPU_0,WKUPDEP_MCASP6_IRQ_MPU_1" line.long 0x94 "RM_L4PER2_MCASP6_CONTEXT,This register contains dedicated MCASP6 context statuses" bitfld.long 0x94 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x98 "PM_L4PER2_MCASP7_WKDEP,This register controls wakeup dependency based on MCASP7 service requests" bitfld.long 0x98 15. "WKUPDEP_MCASP7_DMA_DSP2,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_DMA_DSP2_0,WKUPDEP_MCASP7_DMA_DSP2_1" bitfld.long 0x98 13. "WKUPDEP_MCASP7_DMA_SDMA,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_DMA_SDMA_0,WKUPDEP_MCASP7_DMA_SDMA_1" newline bitfld.long 0x98 12. "WKUPDEP_MCASP7_DMA_DSP1,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_DMA_DSP1_0,WKUPDEP_MCASP7_DMA_DSP1_1" bitfld.long 0x98 7. "WKUPDEP_MCASP7_IRQ_EVE2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_EVE2_0,WKUPDEP_MCASP7_IRQ_EVE2_1" newline bitfld.long 0x98 6. "WKUPDEP_MCASP7_IRQ_EVE1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_EVE1_0,WKUPDEP_MCASP7_IRQ_EVE1_1" bitfld.long 0x98 5. "WKUPDEP_MCASP7_IRQ_DSP2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_DSP2_0,WKUPDEP_MCASP7_IRQ_DSP2_1" newline bitfld.long 0x98 4. "WKUPDEP_MCASP7_IRQ_IPU1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_IPU1_0,WKUPDEP_MCASP7_IRQ_IPU1_1" bitfld.long 0x98 2. "WKUPDEP_MCASP7_IRQ_DSP1,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_DSP1_0,WKUPDEP_MCASP7_IRQ_DSP1_1" newline bitfld.long 0x98 1. "WKUPDEP_MCASP7_IRQ_IPU2,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_IPU2_0,WKUPDEP_MCASP7_IRQ_IPU2_1" bitfld.long 0x98 0. "WKUPDEP_MCASP7_IRQ_MPU,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP7_IRQ_MPU_0,WKUPDEP_MCASP7_IRQ_MPU_1" line.long 0x9C "RM_L4PER2_MCASP7_CONTEXT,This register contains dedicated MCASP7 context statuses" bitfld.long 0x9C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0xA0 "PM_L4PER2_MCASP8_WKDEP,This register controls wakeup dependency based on MCASP8 service requests" bitfld.long 0xA0 15. "WKUPDEP_MCASP8_DMA_DSP2,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_DMA_DSP2_0,WKUPDEP_MCASP8_DMA_DSP2_1" bitfld.long 0xA0 13. "WKUPDEP_MCASP8_DMA_SDMA,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_DMA_SDMA_0,WKUPDEP_MCASP8_DMA_SDMA_1" newline bitfld.long 0xA0 12. "WKUPDEP_MCASP8_DMA_DSP1,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_DMA_DSP1_0,WKUPDEP_MCASP8_DMA_DSP1_1" bitfld.long 0xA0 7. "WKUPDEP_MCASP8_IRQ_EVE2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_EVE2_0,WKUPDEP_MCASP8_IRQ_EVE2_1" newline bitfld.long 0xA0 6. "WKUPDEP_MCASP8_IRQ_EVE1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_EVE1_0,WKUPDEP_MCASP8_IRQ_EVE1_1" bitfld.long 0xA0 5. "WKUPDEP_MCASP8_IRQ_DSP2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_DSP2_0,WKUPDEP_MCASP8_IRQ_DSP2_1" newline bitfld.long 0xA0 4. "WKUPDEP_MCASP8_IRQ_IPU1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_IPU1_0,WKUPDEP_MCASP8_IRQ_IPU1_1" bitfld.long 0xA0 2. "WKUPDEP_MCASP8_IRQ_DSP1,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_DSP1_0,WKUPDEP_MCASP8_IRQ_DSP1_1" newline bitfld.long 0xA0 1. "WKUPDEP_MCASP8_IRQ_IPU2,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_IPU2_0,WKUPDEP_MCASP8_IRQ_IPU2_1" bitfld.long 0xA0 0. "WKUPDEP_MCASP8_IRQ_MPU,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP8_IRQ_MPU_0,WKUPDEP_MCASP8_IRQ_MPU_1" line.long 0xA4 "RM_L4PER2_MCASP8_CONTEXT,This register contains dedicated MCASP8 context statuses" bitfld.long 0xA4 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0xA8 "PM_L4PER2_MCASP4_WKDEP,This register controls wakeup dependency based on MCASP4 service requests" bitfld.long 0xA8 15. "WKUPDEP_MCASP4_DMA_DSP2,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_DMA_DSP2_0,WKUPDEP_MCASP4_DMA_DSP2_1" bitfld.long 0xA8 13. "WKUPDEP_MCASP4_DMA_SDMA,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_DMA_SDMA_0,WKUPDEP_MCASP4_DMA_SDMA_1" newline bitfld.long 0xA8 12. "WKUPDEP_MCASP4_DMA_DSP1,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_DMA_DSP1_0,WKUPDEP_MCASP4_DMA_DSP1_1" bitfld.long 0xA8 7. "WKUPDEP_MCASP4_IRQ_EVE2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_EVE2_0,WKUPDEP_MCASP4_IRQ_EVE2_1" newline bitfld.long 0xA8 6. "WKUPDEP_MCASP4_IRQ_EVE1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_EVE1_0,WKUPDEP_MCASP4_IRQ_EVE1_1" bitfld.long 0xA8 5. "WKUPDEP_MCASP4_IRQ_DSP2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_DSP2_0,WKUPDEP_MCASP4_IRQ_DSP2_1" newline bitfld.long 0xA8 4. "WKUPDEP_MCASP4_IRQ_IPU1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_IPU1_0,WKUPDEP_MCASP4_IRQ_IPU1_1" bitfld.long 0xA8 2. "WKUPDEP_MCASP4_IRQ_DSP1,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_DSP1_0,WKUPDEP_MCASP4_IRQ_DSP1_1" newline bitfld.long 0xA8 1. "WKUPDEP_MCASP4_IRQ_IPU2,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_IPU2_0,WKUPDEP_MCASP4_IRQ_IPU2_1" bitfld.long 0xA8 0. "WKUPDEP_MCASP4_IRQ_MPU,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_MCASP4_IRQ_MPU_0,WKUPDEP_MCASP4_IRQ_MPU_1" line.long 0xAC "RM_L4PER2_MCASP4_CONTEXT,This register contains dedicated MCASP4 context statuses" bitfld.long 0xAC 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1A4++0x03 line.long 0x00 "RM_L4SEC_AES1_CONTEXT,This register contains dedicated AES1 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1AC++0x03 line.long 0x00 "RM_L4SEC_AES2_CONTEXT,This register contains dedicated AES2 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1B4++0x03 line.long 0x00 "RM_L4SEC_DES3DES_CONTEXT,This register contains dedicated DES3DES context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1BC++0x03 line.long 0x00 "RM_L4SEC_FPKA_CONTEXT,This register contains dedicated FPKA context statuses" bitfld.long 0x00 8. "LOSTMEM_NONRETAINED_BANK,Specify if memory-based context in NONRETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_NONRETAINED_BANK_0,LOSTMEM_NONRETAINED_BANK_1" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1C4++0x03 line.long 0x00 "RM_L4SEC_RNG_CONTEXT,This register contains dedicated RNG context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1CC++0x0B line.long 0x00 "RM_L4SEC_SHA2MD51_CONTEXT,This register contains dedicated SHA2MD51 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x04 "PM_L4PER2_UART7_WKDEP,This register controls wakeup dependency based on UART7 service requests" bitfld.long 0x04 7. "WKUPDEP_UART7_EVE2,Wakeup dependency from UART7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_EVE2_0,WKUPDEP_UART7_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_UART7_EVE1,Wakeup dependency from UART7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_EVE1_0,WKUPDEP_UART7_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_UART7_DSP2,Wakeup dependency from UART7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_DSP2_0,WKUPDEP_UART7_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_UART7_IPU1,Wakeup dependency from UART7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_IPU1_0,WKUPDEP_UART7_IPU1_1" newline bitfld.long 0x04 3. "WKUPDEP_UART7_SDMA,Wakeup dependency from UART7 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_SDMA_0,WKUPDEP_UART7_SDMA_1" bitfld.long 0x04 2. "WKUPDEP_UART7_DSP1,Wakeup dependency from UART7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_DSP1_0,WKUPDEP_UART7_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_UART7_IPU2,Wakeup dependency from UART7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_IPU2_0,WKUPDEP_UART7_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_UART7_MPU,Wakeup dependency from UART7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART7_MPU_0,WKUPDEP_UART7_MPU_1" line.long 0x08 "RM_L4PER2_UART7_CONTEXT,This register contains dedicated UART7 context statuses" bitfld.long 0x08 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" group.long 0x1DC++0x1B line.long 0x00 "RM_L4SEC_DMA_CRYPTO_CONTEXT,This register contains dedicated DMA_CRYPTO context statuses" bitfld.long 0x00 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x04 "PM_L4PER2_UART8_WKDEP,This register controls wakeup dependency based on UART8 service requests" bitfld.long 0x04 7. "WKUPDEP_UART8_EVE2,Wakeup dependency from UART8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_EVE2_0,WKUPDEP_UART8_EVE2_1" bitfld.long 0x04 6. "WKUPDEP_UART8_EVE1,Wakeup dependency from UART8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_EVE1_0,WKUPDEP_UART8_EVE1_1" newline bitfld.long 0x04 5. "WKUPDEP_UART8_DSP2,Wakeup dependency from UART8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_DSP2_0,WKUPDEP_UART8_DSP2_1" bitfld.long 0x04 4. "WKUPDEP_UART8_IPU1,Wakeup dependency from UART8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_IPU1_0,WKUPDEP_UART8_IPU1_1" newline bitfld.long 0x04 3. "WKUPDEP_UART8_SDMA,Wakeup dependency from UART8 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_SDMA_0,WKUPDEP_UART8_SDMA_1" bitfld.long 0x04 2. "WKUPDEP_UART8_DSP1,Wakeup dependency from UART8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_DSP1_0,WKUPDEP_UART8_DSP1_1" newline bitfld.long 0x04 1. "WKUPDEP_UART8_IPU2,Wakeup dependency from UART8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_IPU2_0,WKUPDEP_UART8_IPU2_1" bitfld.long 0x04 0. "WKUPDEP_UART8_MPU,Wakeup dependency from UART8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART8_MPU_0,WKUPDEP_UART8_MPU_1" line.long 0x08 "RM_L4PER2_UART8_CONTEXT,This register contains dedicated UART8 context statuses" bitfld.long 0x08 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x08 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x0C "PM_L4PER2_UART9_WKDEP,This register controls wakeup dependency based on UART9 service requests" bitfld.long 0x0C 7. "WKUPDEP_UART9_EVE2,Wakeup dependency from UART9 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_EVE2_0,WKUPDEP_UART9_EVE2_1" bitfld.long 0x0C 6. "WKUPDEP_UART9_EVE1,Wakeup dependency from UART9 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_EVE1_0,WKUPDEP_UART9_EVE1_1" newline bitfld.long 0x0C 5. "WKUPDEP_UART9_DSP2,Wakeup dependency from UART9 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_DSP2_0,WKUPDEP_UART9_DSP2_1" bitfld.long 0x0C 4. "WKUPDEP_UART9_IPU1,Wakeup dependency from UART9 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_IPU1_0,WKUPDEP_UART9_IPU1_1" newline bitfld.long 0x0C 3. "WKUPDEP_UART9_SDMA,Wakeup dependency from UART9 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_SDMA_0,WKUPDEP_UART9_SDMA_1" bitfld.long 0x0C 2. "WKUPDEP_UART9_DSP1,Wakeup dependency from UART9 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_DSP1_0,WKUPDEP_UART9_DSP1_1" newline bitfld.long 0x0C 1. "WKUPDEP_UART9_IPU2,Wakeup dependency from UART9 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_IPU2_0,WKUPDEP_UART9_IPU2_1" bitfld.long 0x0C 0. "WKUPDEP_UART9_MPU,Wakeup dependency from UART9 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART9_MPU_0,WKUPDEP_UART9_MPU_1" line.long 0x10 "RM_L4PER2_UART9_CONTEXT,This register contains dedicated UART9 context statuses" bitfld.long 0x10 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x10 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" line.long 0x14 "PM_L4PER2_DCAN2_WKDEP,This register controls wakeup dependency based on DCAN2 service requests" bitfld.long 0x14 7. "WKUPDEP_DCAN2_EVE2,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_EVE2_0,WKUPDEP_DCAN2_EVE2_1" bitfld.long 0x14 6. "WKUPDEP_DCAN2_EVE1,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_EVE1_0,WKUPDEP_DCAN2_EVE1_1" newline bitfld.long 0x14 5. "WKUPDEP_DCAN2_DSP2,Wakeup dependency from DCAN2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_DSP2_0,WKUPDEP_DCAN2_DSP2_1" bitfld.long 0x14 4. "WKUPDEP_DCAN2_IPU1,Wakeup dependency from DCAN2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_IPU1_0,WKUPDEP_DCAN2_IPU1_1" newline bitfld.long 0x14 3. "WKUPDEP_DCAN2_SDMA,Wakeup dependency from DCAN2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_SDMA_0,WKUPDEP_DCAN2_SDMA_1" bitfld.long 0x14 2. "WKUPDEP_DCAN2_DSP1,Wakeup dependency from DCAN2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_DSP1_0,WKUPDEP_DCAN2_DSP1_1" newline bitfld.long 0x14 1. "WKUPDEP_DCAN2_IPU2,Wakeup dependency from DCAN2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_IPU2_0,WKUPDEP_DCAN2_IPU2_1" bitfld.long 0x14 0. "WKUPDEP_DCAN2_MPU,Wakeup dependency from DCAN2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN2_MPU_0,WKUPDEP_DCAN2_MPU_1" line.long 0x18 "RM_L4PER2_DCAN2_CONTEXT,This register contains dedicated DCAN2 context statuses" bitfld.long 0x18 8. "LOSTMEM_DCAN_BANK,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DCAN_BANK_0,LOSTMEM_DCAN_BANK_1" bitfld.long 0x18 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x1FC++0x03 line.long 0x00 "RM_L4SEC_SHA2MD52_CONTEXT,This register contains dedicated SHA2MD52 context statuses" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" tree.end tree "MPU_PRM" base ad:0x4AE06300 group.long 0x00++0x07 line.long 0x00 "PM_MPU_PWRSTCTRL,This register controls the MPU domain power state to reach upon a domain sleep transition" rbitfld.long 0x00 20.--21. "MPU_RAM_ONSTATE,MPU_RAM memory state when domain is ON" "?,?,?,MPU_RAM_ONSTATE_3" rbitfld.long 0x00 18.--19. "MPU_L2_ONSTATE,MPU_L2 memory state when domain is ON" "?,?,?,MPU_L2_ONSTATE_3" rbitfld.long 0x00 10. "MPU_RAM_RETSTATE,MPU_RAM memory state when domain is RETENTION" "?,MPU_RAM_RETSTATE_1" newline bitfld.long 0x00 9. "MPU_L2_RETSTATE,MPU_L2 memory state when domain is RETENTION" "MPU_L2_RETSTATE_0,MPU_L2_RETSTATE_1" rbitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,?" bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,LOGICRETSTATE_1" newline bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - RESERVED" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_MPU_PWRSTST,This register provides a status on the MPU domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 8.--9. "MPU_RAM_STATEST,MPU_RAM memory state status - MEM_OFF" "MPU_RAM_STATEST_0,MPU_RAM_STATEST_1,MPU_RAM_STATEST_2,MPU_RAM_STATEST_3" newline rbitfld.long 0x04 6.--7. "MPU_L2_STATEST,MPU_L2 memory state status - MEM_OFF" "MPU_L2_STATEST_0,MPU_L2_STATEST_1,MPU_L2_STATEST_2,MPU_L2_STATEST_3" rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x24++0x03 line.long 0x00 "RM_MPU_MPU_CONTEXT,This register contains dedicated MPU context statuses" bitfld.long 0x00 10. "LOSTMEM_MPU_RAM,Specify if memory-based context in MPU_RAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)" "LOSTMEM_MPU_RAM_0,LOSTMEM_MPU_RAM_1" bitfld.long 0x00 9. "LOSTMEM_MPU_L2,Specify if memory-based context in MPU_L2 memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_MPU_L2_0,LOSTMEM_MPU_L2_1" bitfld.long 0x00 1. "LOSTCONTEXT_RFF,Specify if RFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_RFF_0,LOSTCONTEXT_RFF_1" newline bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "OCP_SOCKET_PRM" base ad:0x4AE06000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION_PRM,This register contains the IP revision code for the PRM part of the PRCM" bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "SCHEME_0,SCHEME_1,?,?" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. "R_RTL,RTL Version (R) maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision (X) maintained by IP specification owner" "X_MAJOR_0,X_MAJOR_1,X_MAJOR_2,X_MAJOR_3,X_MAJOR_4,?,?,?" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "CUSTOM_0,?,?,?" bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision (Y) maintained by IP specification owner" "Y_MINOR_0,Y_MINOR_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0x10++0x13 line.long 0x00 "PRM_IRQSTATUS_MPU,This register provides status on MPU interrupt events" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" newline bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x00 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" newline bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" line.long 0x04 "PRM_IRQSTATUS_MPU_2,This register provides status on MPU interrupt events" bitfld.long 0x04 7. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" line.long 0x08 "PRM_IRQENABLE_MPU,This register is used to enable or disable MPU interrupt activation upon presence of corresponding bit" bitfld.long 0x08 31. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x08 30. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" bitfld.long 0x08 29. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" newline bitfld.long 0x08 11. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x08 10. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x08 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" newline bitfld.long 0x08 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain) - IRQ_MSK" "TRANSITION_EN_0,TRANSITION_EN_1" bitfld.long 0x08 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x08 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" newline bitfld.long 0x08 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x08 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x08 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" newline bitfld.long 0x08 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x08 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x08 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x0C "PRM_IRQENABLE_MPU_2,This register is used to enable or disable MPU interrupt activation upon presence of corresponding bit" bitfld.long 0x0C 7. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" line.long 0x10 "PRM_IRQSTATUS_IPU2,This register provides status on IPU2 interrupt events" bitfld.long 0x10 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x10 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x10 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x10 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x10 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x10 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x10 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x10 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x10 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" newline bitfld.long 0x10 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x10 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x10 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" newline bitfld.long 0x10 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x10 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x10 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" newline bitfld.long 0x10 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x10 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x28++0x03 line.long 0x00 "PRM_IRQENABLE_IPU2,This register is used to enable or disable IPU2 interrupt activation upon presence of corresponding bit" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x00 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain) - IRQ_MSK" "TRANSITION_EN_0,TRANSITION_EN_1" newline bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" newline bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" newline bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x30++0x03 line.long 0x00 "PRM_IRQSTATUS_DSP1,This register provides status on DSP1 interrupt events" bitfld.long 0x00 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x00 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" newline bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" newline bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x38++0x03 line.long 0x00 "PRM_IRQENABLE_DSP1,This register is used to enable or disable DSP1 interrupt activation upon presence of corresponding bit" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x00 13. "DPLL_USB_RECAL_EN,USB DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_USB_RECAL_EN_0,DPLL_USB_RECAL_EN_1" bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" newline bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" newline bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" newline bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" newline bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x40++0x0F line.long 0x00 "CM_PRM_PROFILING_CLKCTRL,This register manages the PRM_PROFILING clock" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status - FUNC" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" line.long 0x04 "PRM_IRQENABLE_DSP2,This register is used to enable or disable DSP2 interrupt activation upon presence of corresponding bit" bitfld.long 0x04 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x04 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x04 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x04 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x04 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x04 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x04 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x04 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x04 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x04 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x04 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x04 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x04 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x04 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x04 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x04 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x08 "PRM_IRQENABLE_EVE1,This register is used to enable or disable EVE1 interrupt activation upon presence of corresponding bit" bitfld.long 0x08 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x08 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x08 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x08 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x08 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x08 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x08 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x08 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x08 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x08 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x08 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x08 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x08 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x08 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x08 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x08 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x0C "PRM_IRQENABLE_EVE2,This register is used to enable or disable EVE2 interrupt activation upon presence of corresponding bit" bitfld.long 0x0C 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x0C 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x0C 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x0C 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x0C 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x0C 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x0C 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x0C 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x0C 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" newline bitfld.long 0x0C 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x0C 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" bitfld.long 0x0C 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" newline bitfld.long 0x0C 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x0C 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" bitfld.long 0x0C 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" newline bitfld.long 0x0C 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" group.long 0x58++0x07 line.long 0x00 "PRM_IRQENABLE_IPU1,This register is used to enable or disable IPU1 interrupt activation upon presence of corresponding bit" bitfld.long 0x00 31. "ABB_MPU_DONE_EN,MPU ABB mode change done enable - IRQ_FAL" "ABB_MPU_DONE_EN_0,ABB_MPU_DONE_EN_1" bitfld.long 0x00 30. "ABB_IVA_DONE_EN,IVA ABB mode change done enable - IRQ_FAL" "ABB_IVA_DONE_EN_0,ABB_IVA_DONE_EN_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_EN,DSPEVE ABB mode change done enable - IRQ_FAL" "ABB_DSPEVE_DONE_EN_0,ABB_DSPEVE_DONE_EN_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_EN,GPU ABB mode change done enable - IRQ_FAL" "ABB_GPU_DONE_EN_0,ABB_GPU_DONE_EN_1" bitfld.long 0x00 12. "DPLL_EVE_RECAL_EN,EVE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_EVE_RECAL_EN_0,DPLL_EVE_RECAL_EN_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_EN,DSP DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DSP_RECAL_EN_0,DPLL_DSP_RECAL_EN_1" newline bitfld.long 0x00 10. "FORCEWKUP_EN,IPU domain software supervised wakeup transition completed event interrupt enable" "FORCEWKUP_EN_0,FORCEWKUP_EN_1" bitfld.long 0x00 9. "IO_EN,IO pad event interrupt enable - IRQ_MSK" "IO_EN_0,IO_EN_1" bitfld.long 0x00 8. "TRANSITION_EN,Software supervised transition completed event interrupt enable (any domain) - IRQ_MSK" "TRANSITION_EN_0,TRANSITION_EN_1" newline bitfld.long 0x00 7. "DPLL_DDR_RECAL_EN,DDR DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_DDR_RECAL_EN_0,DPLL_DDR_RECAL_EN_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_EN,GPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GPU_RECAL_EN_0,DPLL_GPU_RECAL_EN_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_EN,GMAC DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_GMAC_RECAL_EN_0,DPLL_GMAC_RECAL_EN_1" newline bitfld.long 0x00 4. "DPLL_ABE_RECAL_EN,ABEDPLL recalibration interrupt enable - IRQ_MSK" "DPLL_ABE_RECAL_EN_0,DPLL_ABE_RECAL_EN_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_EN,PER DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_PER_RECAL_EN_0,DPLL_PER_RECAL_EN_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_EN,IVA DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_IVA_RECAL_EN_0,DPLL_IVA_RECAL_EN_1" newline bitfld.long 0x00 1. "DPLL_MPU_RECAL_EN,MPU DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_MPU_RECAL_EN_0,DPLL_MPU_RECAL_EN_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_EN,CORE DPLL recalibration interrupt enable - IRQ_MSK" "DPLL_CORE_RECAL_EN_0,DPLL_CORE_RECAL_EN_1" line.long 0x04 "PRM_IRQSTATUS_DSP2,This register provides status on DSP interrupt events" bitfld.long 0x04 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x04 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x04 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x04 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x04 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x04 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x04 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x04 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x04 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" newline bitfld.long 0x04 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x04 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x04 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x04 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x04 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" bitfld.long 0x04 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" newline bitfld.long 0x04 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" group.long 0x70++0x03 line.long 0x00 "PRM_IRQSTATUS_IPU1,This register provides status on IPU1 interrupt events" bitfld.long 0x00 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" newline bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x00 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" bitfld.long 0x00 8. "TRANSITION_ST,Software supervised transition completed event interrupt status (any domain)" "TRANSITION_ST_0,TRANSITION_ST_1" newline bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" newline bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" newline bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" rgroup.long 0xF4++0x03 line.long 0x00 "PRM_DEBUG_OUT,This register is used to monitor the PRM's 32 bit HEDEBUG BUS [warm reset insensitive]" repeat 4. (list 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0xE4)++0x03 line.long 0x00 "PRM_DEBUG_CFG$1,This register is used to configure the PRM's 32-bit debug output" hexmask.long.word 0x00 0.--8. 1. "SEL1,Internal signal block select for debug word byte-1" repeat.end repeat 2. (list 1. 2. )(list 0x00 0x04 ) group.long ($2+0x60)++0x03 line.long 0x00 "PRM_IRQSTATUS_EVE$1,This register provides status on EVE interrupt events" bitfld.long 0x00 31. "ABB_MPU_DONE_ST,MPU ABB mode change completion status" "ABB_MPU_DONE_ST_0,ABB_MPU_DONE_ST_1" bitfld.long 0x00 30. "ABB_IVA_DONE_ST,IVA ABB mode change completion status" "ABB_IVA_DONE_ST_0,ABB_IVA_DONE_ST_1" newline bitfld.long 0x00 29. "ABB_DSPEVE_DONE_ST,DSPEVE ABB mode change completion status" "ABB_DSPEVE_DONE_ST_0,ABB_DSPEVE_DONE_ST_1" bitfld.long 0x00 28. "ABB_GPU_DONE_ST,GPU ABB mode change completion status" "ABB_GPU_DONE_ST_0,ABB_GPU_DONE_ST_1" newline bitfld.long 0x00 12. "DPLL_EVE_RECAL_ST,EVE DPLL recalibration interrupt status" "DPLL_EVE_RECAL_ST_0,DPLL_EVE_RECAL_ST_1" bitfld.long 0x00 11. "DPLL_DSP_RECAL_ST,DSP DPLL recalibration interrupt status" "DPLL_DSP_RECAL_ST_0,DPLL_DSP_RECAL_ST_1" newline bitfld.long 0x00 10. "FORCEWKUP_ST,IPU domain software supervised wakeup transition completed event interrupt status" "FORCEWKUP_ST_0,FORCEWKUP_ST_1" bitfld.long 0x00 9. "IO_ST,IO pad event interrupt status" "IO_ST_0,IO_ST_1" newline bitfld.long 0x00 7. "DPLL_DDR_RECAL_ST,DDR DPLL recalibration interrupt status" "DPLL_DDR_RECAL_ST_0,DPLL_DDR_RECAL_ST_1" bitfld.long 0x00 6. "DPLL_GPU_RECAL_ST,GPU DPLL recalibration interrupt status" "DPLL_GPU_RECAL_ST_0,DPLL_GPU_RECAL_ST_1" newline bitfld.long 0x00 5. "DPLL_GMAC_RECAL_ST,GMAC DPLL recalibration interrupt status" "DPLL_GMAC_RECAL_ST_0,DPLL_GMAC_RECAL_ST_1" bitfld.long 0x00 4. "DPLL_ABE_RECAL_ST,ABE DPLL recalibration interrupt status" "DPLL_ABE_RECAL_ST_0,DPLL_ABE_RECAL_ST_1" newline bitfld.long 0x00 3. "DPLL_PER_RECAL_ST,PER DPLL recalibration interrupt status" "DPLL_PER_RECAL_ST_0,DPLL_PER_RECAL_ST_1" bitfld.long 0x00 2. "DPLL_IVA_RECAL_ST,IVA DPLL recalibration interrupt status" "DPLL_IVA_RECAL_ST_0,DPLL_IVA_RECAL_ST_1" newline bitfld.long 0x00 1. "DPLL_MPU_RECAL_ST,MPU DPLL recalibration interrupt status" "DPLL_MPU_RECAL_ST_0,DPLL_MPU_RECAL_ST_1" bitfld.long 0x00 0. "DPLL_CORE_RECAL_ST,CORE DPLL recalibration interrupt status" "DPLL_CORE_RECAL_ST_0,DPLL_CORE_RECAL_ST_1" repeat.end tree.end tree "RTC_PRM" base ad:0x4AE07C40 group.long 0x20++0x07 line.long 0x00 "PM_RTC_RTCSS_WKDEP,This register controls wakeup dependency based on RTCSS service requests" bitfld.long 0x00 17. "WKUPDEP_RTC_IRQ2_EVE2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_EVE2_0,WKUPDEP_RTC_IRQ2_EVE2_1" bitfld.long 0x00 16. "WKUPDEP_RTC_IRQ2_EVE1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_EVE1_0,WKUPDEP_RTC_IRQ2_EVE1_1" newline bitfld.long 0x00 15. "WKUPDEP_RTC_IRQ2_DSP2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_DSP2_0,WKUPDEP_RTC_IRQ2_DSP2_1" bitfld.long 0x00 14. "WKUPDEP_RTC_IRQ2_IPU1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_IPU1_0,WKUPDEP_RTC_IRQ2_IPU1_1" newline bitfld.long 0x00 12. "WKUPDEP_RTC_IRQ2_DSP1,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_DSP1_0,WKUPDEP_RTC_IRQ2_DSP1_1" bitfld.long 0x00 11. "WKUPDEP_RTC_IRQ2_IPU2,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_IPU2_0,WKUPDEP_RTC_IRQ2_IPU2_1" newline bitfld.long 0x00 10. "WKUPDEP_RTC_IRQ2_MPU,Wakeup dependency from RTCSS module (timer_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ2_MPU_0,WKUPDEP_RTC_IRQ2_MPU_1" bitfld.long 0x00 7. "WKUPDEP_RTC_IRQ1_EVE2,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_EVE2_0,WKUPDEP_RTC_IRQ1_EVE2_1" newline bitfld.long 0x00 6. "WKUPDEP_RTC_IRQ1_EVE1,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_EVE1_0,WKUPDEP_RTC_IRQ1_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_RTC_IRQ1_DSP2,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_DSP2_0,WKUPDEP_RTC_IRQ1_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_RTC_IRQ1_IPU1,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_IPU1_0,WKUPDEP_RTC_IRQ1_IPU1_1" bitfld.long 0x00 2. "WKUPDEP_RTC_IRQ1_DSP1,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_DSP1_0,WKUPDEP_RTC_IRQ1_DSP1_1" newline bitfld.long 0x00 1. "WKUPDEP_RTC_IRQ1_IPU2,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_IPU2_0,WKUPDEP_RTC_IRQ1_IPU2_1" bitfld.long 0x00 0. "WKUPDEP_RTC_IRQ1_MPU,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_RTC_IRQ1_MPU_0,WKUPDEP_RTC_IRQ1_MPU_1" line.long 0x04 "RM_RTC_RTCSS_CONTEXT,This register contains dedicated RTCSS context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "SMARTREFLEX_CORE" base ad:0x4A0DD000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "SRENABLE_0,SRENABLE_1" bitfld.long 0x00 10. "SENENABLE," "SENENABLE_0,SENENABLE_1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "ERRORGENERATORENABLE_0,ERRORGENERATORENABLE_1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "MINMAXAVGENABLE_0,MINMAXAVGENABLE_1" newline bitfld.long 0x00 1. "SENNENABLE," "SENNENABLE_0,SENNENABLE_1" bitfld.long 0x00 0. "SENPENABLE," "SENPENABLE_0,SENPENABLE_1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" bitfld.long 0x04 3. "AVGERRVALID," "AVGERRVALID_0,AVGERRVALID_1" bitfld.long 0x04 2. "MINMAXAVGVALID," "MINMAXAVGVALID_0,MINMAXAVGVALID_1" newline bitfld.long 0x04 1. "ERRORGENERATORVALID," "ERRORGENERATORVALID_0,ERRORGENERATORVALID_1" bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "MINMAXAVGACCUMVALID_0,MINMAXAVGACCUMVALID_1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "SENPGAIN_0,SENPGAIN_1,SENPGAIN_2,SENPGAIN_3,SENPGAIN_4,SENPGAIN_5,SENPGAIN_6,SENPGAIN_7,SENPGAIN_8,SENPGAIN_9,SENPGAIN_10,SENPGAIN_11,SENPGAIN_12,SENPGAIN_13,SENPGAIN_14,SENPGAIN_15" bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "SENNGAIN_0,SENNGAIN_1,SENNGAIN_2,SENNGAIN_3,SENNGAIN_4,SENNGAIN_5,SENNGAIN_6,SENNGAIN_7,SENNGAIN_8,SENNGAIN_9,SENNGAIN_10,SENNGAIN_11,SENNGAIN_12,SENNGAIN_13,SENNGAIN_14,SENNGAIN_15" newline hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "EOI_0,EOI_1" line.long 0x24 "IRQSTATUS_RAW,CU raw interrupt raw status and set" bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "MCUACCUMINTSTATRAW_0,MCUACCUMINTSTATRAW_1" bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "0,1" newline bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "0,1" bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDISABLEACKINTSTATRAW_0,MCUDISABLEACKINTSTATRAW_1" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "0,1" bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "0,1" newline bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "0,1" bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "0,1" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "MCUACCUMINTENASET_0,MCUACCUMINTENASET_1" bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "MCUVALIDINTENASET_0,MCUVALIDINTENASET_1" newline bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "MCUBOUNDSINTENASET_0,MCUBOUNDSINTENASET_1" bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "0,1" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "MCUACCUMINTENACLR_0,MCUACCUMINTENACLR_1" bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "MCUVALIDINTENACLR_0,MCUVALIDINTENACLR_1" newline bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "MCUBOUNDSINTENACLR_0,MCUBOUNDSINTENACLR_1" bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "MCUDISABLEACKINTENACLR_0,MCUDISABLEACKINTENACLR_1" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "WAKEUPENABLE_0,WAKEUPENABLE_1" bitfld.long 0x38 24.--25. "IDLEMODE," "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "VPBOUNDSINTSTATENA_0,VPBOUNDSINTSTATENA_1" bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "VPBOUNDSINTENABLE_0,VPBOUNDSINTENABLE_1" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "ERRWEIGHT_0,ERRWEIGHT_1,ERRWEIGHT_2,ERRWEIGHT_3,ERRWEIGHT_4,ERRWEIGHT_5,ERRWEIGHT_6,ERRWEIGHT_7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" tree.end tree "SMARTREFLEX_DSPEVE" base ad:0x4A183000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "SRENABLE_0,SRENABLE_1" bitfld.long 0x00 10. "SENENABLE," "SENENABLE_0,SENENABLE_1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "ERRORGENERATORENABLE_0,ERRORGENERATORENABLE_1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "MINMAXAVGENABLE_0,MINMAXAVGENABLE_1" newline bitfld.long 0x00 1. "SENNENABLE," "SENNENABLE_0,SENNENABLE_1" bitfld.long 0x00 0. "SENPENABLE," "SENPENABLE_0,SENPENABLE_1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" bitfld.long 0x04 3. "AVGERRVALID," "AVGERRVALID_0,AVGERRVALID_1" bitfld.long 0x04 2. "MINMAXAVGVALID," "MINMAXAVGVALID_0,MINMAXAVGVALID_1" newline bitfld.long 0x04 1. "ERRORGENERATORVALID," "ERRORGENERATORVALID_0,ERRORGENERATORVALID_1" bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "MINMAXAVGACCUMVALID_0,MINMAXAVGACCUMVALID_1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "SENPGAIN_0,SENPGAIN_1,SENPGAIN_2,SENPGAIN_3,SENPGAIN_4,SENPGAIN_5,SENPGAIN_6,SENPGAIN_7,SENPGAIN_8,SENPGAIN_9,SENPGAIN_10,SENPGAIN_11,SENPGAIN_12,SENPGAIN_13,SENPGAIN_14,SENPGAIN_15" bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "SENNGAIN_0,SENNGAIN_1,SENNGAIN_2,SENNGAIN_3,SENNGAIN_4,SENNGAIN_5,SENNGAIN_6,SENNGAIN_7,SENNGAIN_8,SENNGAIN_9,SENNGAIN_10,SENNGAIN_11,SENNGAIN_12,SENNGAIN_13,SENNGAIN_14,SENNGAIN_15" newline hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "EOI_0,EOI_1" line.long 0x24 "IRQSTATUS_RAW,CU raw interrupt raw status and set" bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "MCUACCUMINTSTATRAW_0,MCUACCUMINTSTATRAW_1" bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "0,1" newline bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "0,1" bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDISABLEACKINTSTATRAW_0,MCUDISABLEACKINTSTATRAW_1" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "0,1" bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "0,1" newline bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "0,1" bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "0,1" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "MCUACCUMINTENASET_0,MCUACCUMINTENASET_1" bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "MCUVALIDINTENASET_0,MCUVALIDINTENASET_1" newline bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "MCUBOUNDSINTENASET_0,MCUBOUNDSINTENASET_1" bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "0,1" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "MCUACCUMINTENACLR_0,MCUACCUMINTENACLR_1" bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "MCUVALIDINTENACLR_0,MCUVALIDINTENACLR_1" newline bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "MCUBOUNDSINTENACLR_0,MCUBOUNDSINTENACLR_1" bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "MCUDISABLEACKINTENACLR_0,MCUDISABLEACKINTENACLR_1" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "WAKEUPENABLE_0,WAKEUPENABLE_1" bitfld.long 0x38 24.--25. "IDLEMODE," "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "VPBOUNDSINTSTATENA_0,VPBOUNDSINTSTATENA_1" bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "VPBOUNDSINTENABLE_0,VPBOUNDSINTENABLE_1" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "ERRWEIGHT_0,ERRWEIGHT_1,ERRWEIGHT_2,ERRWEIGHT_3,ERRWEIGHT_4,ERRWEIGHT_5,ERRWEIGHT_6,ERRWEIGHT_7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" tree.end tree "SMARTREFLEX_GPU" base ad:0x4A185000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "SRENABLE_0,SRENABLE_1" bitfld.long 0x00 10. "SENENABLE," "SENENABLE_0,SENENABLE_1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "ERRORGENERATORENABLE_0,ERRORGENERATORENABLE_1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "MINMAXAVGENABLE_0,MINMAXAVGENABLE_1" newline bitfld.long 0x00 1. "SENNENABLE," "SENNENABLE_0,SENNENABLE_1" bitfld.long 0x00 0. "SENPENABLE," "SENPENABLE_0,SENPENABLE_1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" bitfld.long 0x04 3. "AVGERRVALID," "AVGERRVALID_0,AVGERRVALID_1" bitfld.long 0x04 2. "MINMAXAVGVALID," "MINMAXAVGVALID_0,MINMAXAVGVALID_1" newline bitfld.long 0x04 1. "ERRORGENERATORVALID," "ERRORGENERATORVALID_0,ERRORGENERATORVALID_1" bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "MINMAXAVGACCUMVALID_0,MINMAXAVGACCUMVALID_1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "SENPGAIN_0,SENPGAIN_1,SENPGAIN_2,SENPGAIN_3,SENPGAIN_4,SENPGAIN_5,SENPGAIN_6,SENPGAIN_7,SENPGAIN_8,SENPGAIN_9,SENPGAIN_10,SENPGAIN_11,SENPGAIN_12,SENPGAIN_13,SENPGAIN_14,SENPGAIN_15" bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "SENNGAIN_0,SENNGAIN_1,SENNGAIN_2,SENNGAIN_3,SENNGAIN_4,SENNGAIN_5,SENNGAIN_6,SENNGAIN_7,SENNGAIN_8,SENNGAIN_9,SENNGAIN_10,SENNGAIN_11,SENNGAIN_12,SENNGAIN_13,SENNGAIN_14,SENNGAIN_15" newline hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "EOI_0,EOI_1" line.long 0x24 "IRQSTATUS_RAW,CU raw interrupt raw status and set" bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "MCUACCUMINTSTATRAW_0,MCUACCUMINTSTATRAW_1" bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "0,1" newline bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "0,1" bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDISABLEACKINTSTATRAW_0,MCUDISABLEACKINTSTATRAW_1" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "0,1" bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "0,1" newline bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "0,1" bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "0,1" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "MCUACCUMINTENASET_0,MCUACCUMINTENASET_1" bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "MCUVALIDINTENASET_0,MCUVALIDINTENASET_1" newline bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "MCUBOUNDSINTENASET_0,MCUBOUNDSINTENASET_1" bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "0,1" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "MCUACCUMINTENACLR_0,MCUACCUMINTENACLR_1" bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "MCUVALIDINTENACLR_0,MCUVALIDINTENACLR_1" newline bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "MCUBOUNDSINTENACLR_0,MCUBOUNDSINTENACLR_1" bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "MCUDISABLEACKINTENACLR_0,MCUDISABLEACKINTENACLR_1" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "WAKEUPENABLE_0,WAKEUPENABLE_1" bitfld.long 0x38 24.--25. "IDLEMODE," "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "VPBOUNDSINTSTATENA_0,VPBOUNDSINTSTATENA_1" bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "VPBOUNDSINTENABLE_0,VPBOUNDSINTENABLE_1" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "ERRWEIGHT_0,ERRWEIGHT_1,ERRWEIGHT_2,ERRWEIGHT_3,ERRWEIGHT_4,ERRWEIGHT_5,ERRWEIGHT_6,ERRWEIGHT_7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" tree.end tree "SMARTREFLEX_IVA" base ad:0x4A187000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "SRENABLE_0,SRENABLE_1" bitfld.long 0x00 10. "SENENABLE," "SENENABLE_0,SENENABLE_1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "ERRORGENERATORENABLE_0,ERRORGENERATORENABLE_1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "MINMAXAVGENABLE_0,MINMAXAVGENABLE_1" newline bitfld.long 0x00 1. "SENNENABLE," "SENNENABLE_0,SENNENABLE_1" bitfld.long 0x00 0. "SENPENABLE," "SENPENABLE_0,SENPENABLE_1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" bitfld.long 0x04 3. "AVGERRVALID," "AVGERRVALID_0,AVGERRVALID_1" bitfld.long 0x04 2. "MINMAXAVGVALID," "MINMAXAVGVALID_0,MINMAXAVGVALID_1" newline bitfld.long 0x04 1. "ERRORGENERATORVALID," "ERRORGENERATORVALID_0,ERRORGENERATORVALID_1" bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "MINMAXAVGACCUMVALID_0,MINMAXAVGACCUMVALID_1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "SENPGAIN_0,SENPGAIN_1,SENPGAIN_2,SENPGAIN_3,SENPGAIN_4,SENPGAIN_5,SENPGAIN_6,SENPGAIN_7,SENPGAIN_8,SENPGAIN_9,SENPGAIN_10,SENPGAIN_11,SENPGAIN_12,SENPGAIN_13,SENPGAIN_14,SENPGAIN_15" bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "SENNGAIN_0,SENNGAIN_1,SENNGAIN_2,SENNGAIN_3,SENNGAIN_4,SENNGAIN_5,SENNGAIN_6,SENNGAIN_7,SENNGAIN_8,SENNGAIN_9,SENNGAIN_10,SENNGAIN_11,SENNGAIN_12,SENNGAIN_13,SENNGAIN_14,SENNGAIN_15" newline hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "EOI_0,EOI_1" line.long 0x24 "IRQSTATUS_RAW,CU raw interrupt raw status and set" bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "MCUACCUMINTSTATRAW_0,MCUACCUMINTSTATRAW_1" bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "0,1" newline bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "0,1" bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDISABLEACKINTSTATRAW_0,MCUDISABLEACKINTSTATRAW_1" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "0,1" bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "0,1" newline bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "0,1" bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "0,1" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "MCUACCUMINTENASET_0,MCUACCUMINTENASET_1" bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "MCUVALIDINTENASET_0,MCUVALIDINTENASET_1" newline bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "MCUBOUNDSINTENASET_0,MCUBOUNDSINTENASET_1" bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "0,1" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "MCUACCUMINTENACLR_0,MCUACCUMINTENACLR_1" bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "MCUVALIDINTENACLR_0,MCUVALIDINTENACLR_1" newline bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "MCUBOUNDSINTENACLR_0,MCUBOUNDSINTENACLR_1" bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "MCUDISABLEACKINTENACLR_0,MCUDISABLEACKINTENACLR_1" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "WAKEUPENABLE_0,WAKEUPENABLE_1" bitfld.long 0x38 24.--25. "IDLEMODE," "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "VPBOUNDSINTSTATENA_0,VPBOUNDSINTSTATENA_1" bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "VPBOUNDSINTENABLE_0,VPBOUNDSINTENABLE_1" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "ERRWEIGHT_0,ERRWEIGHT_1,ERRWEIGHT_2,ERRWEIGHT_3,ERRWEIGHT_4,ERRWEIGHT_5,ERRWEIGHT_6,ERRWEIGHT_7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" tree.end tree "SMARTREFLEX_MPU" base ad:0x4A0D9000 group.long 0x00++0x3B line.long 0x00 "SRCONFIG,Configuration bits for the Sensor Core and the Digital Processing" hexmask.long.word 0x00 22.--31. 1. "ACCUMDATA,Number of values to accumulate" hexmask.long.word 0x00 12.--21. 1. "SRCLKLENGTH,Determines the frequency of SRClk" newline bitfld.long 0x00 11. "SRENABLE," "SRENABLE_0,SRENABLE_1" bitfld.long 0x00 10. "SENENABLE," "SENENABLE_0,SENENABLE_1" newline bitfld.long 0x00 9. "ERRORGENERATORENABLE," "ERRORGENERATORENABLE_0,ERRORGENERATORENABLE_1" bitfld.long 0x00 8. "MINMAXAVGENABLE," "MINMAXAVGENABLE_0,MINMAXAVGENABLE_1" newline bitfld.long 0x00 1. "SENNENABLE," "SENNENABLE_0,SENNENABLE_1" bitfld.long 0x00 0. "SENPENABLE," "SENPENABLE_0,SENPENABLE_1" line.long 0x04 "SRSTATUS,Status bits that indicate that the values in the register are valid or events have occurred" bitfld.long 0x04 3. "AVGERRVALID," "AVGERRVALID_0,AVGERRVALID_1" bitfld.long 0x04 2. "MINMAXAVGVALID," "MINMAXAVGVALID_0,MINMAXAVGVALID_1" newline bitfld.long 0x04 1. "ERRORGENERATORVALID," "ERRORGENERATORVALID_0,ERRORGENERATORVALID_1" bitfld.long 0x04 0. "MINMAXAVGACCUMVALID," "MINMAXAVGACCUMVALID_0,MINMAXAVGACCUMVALID_1" line.long 0x08 "SENVAL,The current sensor values from the Sensor Core(SVT)" hexmask.long.word 0x08 16.--31. 1. "SENPVAL,The latest value of the SenPVal from the SVT sensor core" hexmask.long.word 0x08 0.--15. 1. "SENNVAL,The latest value of the SenNVal from the SVT sensor core" line.long 0x0C "SENMIN,The minimum sensor values(SVT)" hexmask.long.word 0x0C 16.--31. 1. "SENPMIN,The minimum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x0C 0.--15. 1. "SENNMIN,The minimum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x10 "SENMAX,The maximum sensor values(SVT)" hexmask.long.word 0x10 16.--31. 1. "SENPMAX,The maximum value of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x10 0.--15. 1. "SENNMAX,The maximum value of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x14 "SENAVG,The average sensor values(SVT)" hexmask.long.word 0x14 16.--31. 1. "SENPAVG,The running average of the SenPVal from the SVT sensor core since the last restart operation" hexmask.long.word 0x14 0.--15. 1. "SENNAVG,The running average of the SenNVal from the SVT sensor core since the last restart operation" line.long 0x18 "AVGWEIGHT,The weighting factor in the average computation" hexmask.long.word 0x18 16.--31. 1. "SENPAVGWEIGHT1,The weighting factor for the SenP averager" hexmask.long.word 0x18 0.--15. 1. "SENNAVGWEIGHT,The weighting factor for the SenN averager" line.long 0x1C "NVALUERECIPROCAL,The reciprocal of the SenN and SenP values used in error generation(SVT)" bitfld.long 0x1C 20.--23. "SENPGAIN,The gain value for the SVT SenP reciprocal" "SENPGAIN_0,SENPGAIN_1,SENPGAIN_2,SENPGAIN_3,SENPGAIN_4,SENPGAIN_5,SENPGAIN_6,SENPGAIN_7,SENPGAIN_8,SENPGAIN_9,SENPGAIN_10,SENPGAIN_11,SENPGAIN_12,SENPGAIN_13,SENPGAIN_14,SENPGAIN_15" bitfld.long 0x1C 16.--19. "SENNGAIN,The gain value for the SVT SenN reciprocal" "SENNGAIN_0,SENNGAIN_1,SENNGAIN_2,SENNGAIN_3,SENNGAIN_4,SENNGAIN_5,SENNGAIN_6,SENNGAIN_7,SENNGAIN_8,SENNGAIN_9,SENNGAIN_10,SENNGAIN_11,SENNGAIN_12,SENNGAIN_13,SENNGAIN_14,SENNGAIN_15" newline hexmask.long.byte 0x1C 8.--15. 1. "SENPRN,The scale value for the SVT SenP reciprocal" hexmask.long.byte 0x1C 0.--7. 1. "SENNRN,The scale value for the SVT SenN reciprocal" line.long 0x20 "IRQ_EOI,EOI protocol re-trigger" bitfld.long 0x20 0. "EOI,The value read is always '0' Write" "EOI_0,EOI_1" line.long 0x24 "IRQSTATUS_RAW,CU raw interrupt raw status and set" bitfld.long 0x24 3. "MCUACCUMINTSTATRAW,Read:Accum interrupt status Write" "MCUACCUMINTSTATRAW_0,MCUACCUMINTSTATRAW_1" bitfld.long 0x24 2. "MCUVALIDINTSTATRAW,Read:Valid interrupt status Write" "0,1" newline bitfld.long 0x24 1. "MCUBOUNDSINTSTATRAW,Read:Bounds interrupt status Write" "0,1" bitfld.long 0x24 0. "MCUDISABLEACKINTSTATRAW,Read:MCUDisable acknowledge interrupt status Write" "MCUDISABLEACKINTSTATRAW_0,MCUDISABLEACKINTSTATRAW_1" line.long 0x28 "IRQSTATUS,MCU masked interrupt status and clear" bitfld.long 0x28 3. "MCUACCUMINTSTATENA,Read:Accum interrupt status if enabled Write" "0,1" bitfld.long 0x28 2. "MCUVALIDINTSTATENA,Read:Valid interrupt status if enabled Write" "0,1" newline bitfld.long 0x28 1. "MCUBOUNDSINTSTATENA,Read:Bounds interrupt status if enabled Write" "0,1" bitfld.long 0x28 0. "MCUDISABLEACKINTSTATENA,Read:MCUDisable acknowledge interrupt status if enabled Write" "0,1" line.long 0x2C "IRQENABLE_SET,MCU interrupt enable flag set" bitfld.long 0x2C 3. "MCUACCUMINTENASET,Read" "MCUACCUMINTENASET_0,MCUACCUMINTENASET_1" bitfld.long 0x2C 2. "MCUVALIDINTENASET,Read" "MCUVALIDINTENASET_0,MCUVALIDINTENASET_1" newline bitfld.long 0x2C 1. "MCUBOUNDSINTENASET,Read" "MCUBOUNDSINTENASET_0,MCUBOUNDSINTENASET_1" bitfld.long 0x2C 0. "MCUDISABLEACKINTENASET,Read" "0,1" line.long 0x30 "IRQENABLE_CLR,MCU interrupt enable flag clear" bitfld.long 0x30 3. "MCUACCUMINTENACLR,Read" "MCUACCUMINTENACLR_0,MCUACCUMINTENACLR_1" bitfld.long 0x30 2. "MCUVALIDINTENACLR,Read" "MCUVALIDINTENACLR_0,MCUVALIDINTENACLR_1" newline bitfld.long 0x30 1. "MCUBOUNDSINTENACLR,Read" "MCUBOUNDSINTENACLR_0,MCUBOUNDSINTENACLR_1" bitfld.long 0x30 0. "MCUDISABLEACKINTENACLR,Read" "MCUDISABLEACKINTENACLR_0,MCUDISABLEACKINTENACLR_1" line.long 0x34 "SENERROR,The sensor error from the error generator" hexmask.long.byte 0x34 8.--15. 1. "AVGERROR,The average sensor error" hexmask.long.byte 0x34 0.--7. 1. "SENERROR,The percentage of sensor error" line.long 0x38 "ERRCONFIG,The sensor error configuration" bitfld.long 0x38 26. "WAKEUPENABLE,Wakeup from MCU Interrupts enable" "WAKEUPENABLE_0,WAKEUPENABLE_1" bitfld.long 0x38 24.--25. "IDLEMODE," "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x38 23. "VPBOUNDSINTSTATENA,Read: Bounds interrupt status if enabled Write" "VPBOUNDSINTSTATENA_0,VPBOUNDSINTSTATENA_1" bitfld.long 0x38 22. "VPBOUNDSINTENABLE," "VPBOUNDSINTENABLE_0,VPBOUNDSINTENABLE_1" newline bitfld.long 0x38 16.--18. "ERRWEIGHT,The AvgSenError weight" "ERRWEIGHT_0,ERRWEIGHT_1,ERRWEIGHT_2,ERRWEIGHT_3,ERRWEIGHT_4,ERRWEIGHT_5,ERRWEIGHT_6,ERRWEIGHT_7" hexmask.long.byte 0x38 8.--15. 1. "ERRMAXLIMIT,The upper limit of SenError for interrupt generation" newline hexmask.long.byte 0x38 0.--7. 1. "ERRMINLIMIT,The lower limit of SenError for interrupt generation" tree.end tree "VPE_PRM" base ad:0x4AE07C80 group.long 0x00++0x07 line.long 0x00 "PM_VPE_PWRSTCTRL,This register controls the VPE power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. "VPE_BANK_ONSTATE,DSP_L1 state when domain is ON" "?,?,?,VPE_BANK_ONSTATE_3" bitfld.long 0x00 8. "VPE_BANK_RETSTATE,VPE_BANK state when domain is RETENTION" "VPE_BANK_RETSTATE_0,VPE_BANK_RETSTATE_1" bitfld.long 0x00 4. "LOWPOWERSTATECHANGE,Power state change request when domain has already performed a sleep transition" "LOWPOWERSTATECHANGE_0,LOWPOWERSTATECHANGE_1" newline bitfld.long 0x00 2. "LOGICRETSTATE,Logic state when power domain is RETENTION - LOGIC_OFF" "LOGICRETSTATE_0,LOGICRETSTATE_1" bitfld.long 0x00 0.--1. "POWERSTATE,Power state control - OFF" "POWERSTATE_0,POWERSTATE_1,POWERSTATE_2,POWERSTATE_3" line.long 0x04 "PM_VPE_PWRSTST,This register provides a status on the VPE domain current power state" bitfld.long 0x04 24.--25. "LASTPOWERSTATEENTERED,Last low power state entered" "LASTPOWERSTATEENTERED_0,LASTPOWERSTATEENTERED_1,LASTPOWERSTATEENTERED_2,LASTPOWERSTATEENTERED_3" rbitfld.long 0x04 20. "INTRANSITION,Domain transition status - NO" "INTRANSITION_0,INTRANSITION_1" rbitfld.long 0x04 4.--5. "VPE_BANK_STATEST,VPE_BANK memory state status - MEM_OFF" "VPE_BANK_STATEST_0,VPE_BANK_STATEST_1,VPE_BANK_STATEST_2,VPE_BANK_STATEST_3" newline rbitfld.long 0x04 2. "LOGICSTATEST,Logic state status - OFF" "LOGICSTATEST_0,LOGICSTATEST_1" rbitfld.long 0x04 0.--1. "POWERSTATEST,Current power state status - OFF" "POWERSTATEST_0,POWERSTATEST_1,POWERSTATEST_2,POWERSTATEST_3" group.long 0x20++0x07 line.long 0x00 "PM_VPE_VPE_WKDEP,This register controls wakeup dependency based on VPE service requests" bitfld.long 0x00 7. "WKUPDEP_VPE_EVE2,Wakeup dependency from VPE module (Swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_EVE2_0,WKUPDEP_VPE_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_VPE_EVE1,Wakeup dependency from VPE module ( Swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_EVE1_0,WKUPDEP_VPE_EVE1_1" bitfld.long 0x00 5. "WKUPDEP_VPE_DSP2,Wakeup dependency from VPE module (Swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_DSP2_0,WKUPDEP_VPE_DSP2_1" newline bitfld.long 0x00 4. "WKUPDEP_VPE_IPU1,Wakeup dependency from VPE module (Swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_IPU1_0,WKUPDEP_VPE_IPU1_1" bitfld.long 0x00 2. "WKUPDEP_VPE_DSP1,Wakeup dependency from VPE module (Swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_DSP1_0,WKUPDEP_VPE_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_VPE_IPU2,Wakeup dependency from VPE module ( Swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_IPU2_0,WKUPDEP_VPE_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_VPE_MPU,Wakeup dependency from VPE module (Swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_VPE_MPU_0,WKUPDEP_VPE_MPU_1" line.long 0x04 "RM_VPE_VPE_CONTEXT,This register contains dedicated VPE context statuses" bitfld.long 0x04 8. "LOSTMEM_VPE_BANK,Specify if memory-based context in VPE memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_VPE_BANK_0,LOSTMEM_VPE_BANK_1" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree "WKUPAON_CM" base ad:0x4AE07800 group.long 0x00++0x03 line.long 0x00 "CM_WKUPAON_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 18. "CLKACTIVITY_UART10_GFCLK,This field indicates the state of the UART10_GFCLK clock in the domain" "CLKACTIVITY_UART10_GFCLK_0,CLKACTIVITY_UART10_GFCLK_1" rbitfld.long 0x00 17. "CLKACTIVITY_TIMER1_GFCLK,This field indicates the state of the TIMER1_GFCLK clock in the domain" "CLKACTIVITY_TIMER1_GFCLK_0,CLKACTIVITY_TIMER1_GFCLK_1" newline rbitfld.long 0x00 16. "CLKACTIVITY_DCAN1_SYS_CLK,This field indicates the state of the DCAN1_SYS_CLK clock in the domain" "CLKACTIVITY_DCAN1_SYS_CLK_0,CLKACTIVITY_DCAN1_SYS_CLK_1" rbitfld.long 0x00 15. "CLKACTIVITY_SYS_CLK_ALL,This field indicates the state of the SYS_CLK runing at SCRM level because of any SCRM clock request" "CLKACTIVITY_SYS_CLK_ALL_0,CLKACTIVITY_SYS_CLK_ALL_1" newline rbitfld.long 0x00 14. "CLKACTIVITY_SYS_CLK_FUNC,This field indicates the state of the functional SYS_CLK clocks in the domain (this exclude activity of EMU_GCLK clock)" "CLKACTIVITY_SYS_CLK_FUNC_0,CLKACTIVITY_SYS_CLK_FUNC_1" rbitfld.long 0x00 12. "CLKACTIVITY_WKUPAON_GICLK,This field indicates the state of the WKUPAON_GICLK clock in the domain" "CLKACTIVITY_WKUPAON_GICLK_0,CLKACTIVITY_WKUPAON_GICLK_1" newline rbitfld.long 0x00 11. "CLKACTIVITY_WKUPAON_SYS_GFCLK,This field indicates the state of the WKUPAON_SYS_GFCLK clock in the domain" "CLKACTIVITY_WKUPAON_SYS_GFCLK_0,CLKACTIVITY_WKUPAON_SYS_GFCLK_1" rbitfld.long 0x00 9. "CLKACTIVITY_ABE_LP_CLK,This field indicates the state of the ABE_LP_CLK clock in the domain" "CLKACTIVITY_ABE_LP_CLK_0,CLKACTIVITY_ABE_LP_CLK_1" newline rbitfld.long 0x00 8. "CLKACTIVITY_SYS_CLK,This field indicates the state of the SYS_CLK clock in the domain(it includes profiling EMU_SYS_GCLK and all functional SYS_CLK. [warm reset insensitive] - INACT. - ACT" "CLKACTIVITY_SYS_CLK_0,CLKACTIVITY_SYS_CLK_1" bitfld.long 0x00 0.--1. "CLKTRCTRL,Controls the clock state transition of the WKUPAON clock domain" "CLKTRCTRL_0,CLKTRCTRL_1,CLKTRCTRL_2,CLKTRCTRL_3" rgroup.long 0x20++0x03 line.long 0x00 "CM_WKUPAON_L4_WKUP_CLKCTRL,This register manages the WKUPAON clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x30++0x03 line.long 0x00 "CM_WKUPAON_WD_TIMER2_CLKCTRL,This register manages the WD_TIMER2 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x38++0x03 line.long 0x00 "CM_WKUPAON_GPIO1_CLKCTRL,This register manages the GPIO1 clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 8. "OPTFCLKEN_DBCLK,Optional functional clock control" "OPTFCLKEN_DBCLK_0,OPTFCLKEN_DBCLK_1" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x40++0x03 line.long 0x00 "CM_WKUPAON_TIMER1_CLKCTRL,This register manages the TIMER1 clocks" bitfld.long 0x00 24.--27. "CLKSEL,Select the source of the functional clock - RESERVED2" "CLKSEL_0,CLKSEL_1,CLKSEL_2,CLKSEL_3,CLKSEL_4,CLKSEL_5,CLKSEL_6,CLKSEL_7,CLKSEL_8,CLKSEL_9,CLKSEL_10,CLKSEL_11,CLKSEL_12,CLKSEL_13,CLKSEL_14,CLKSEL_15" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" rgroup.long 0x48++0x03 line.long 0x00 "CM_WKUPAON_TIMER12_CLKCTRL,This register manages the TIMER12 clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" rgroup.long 0x50++0x03 line.long 0x00 "CM_WKUPAON_COUNTER_32K_CLKCTRL,This register manages the COUNTER_32K clocks" bitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "?,MODULEMODE_1,?,?" group.long 0x78++0x03 line.long 0x00 "CM_WKUPAON_KBD_CLKCTRL,This register manages the KBD clocks" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x80++0x03 line.long 0x00 "CM_WKUPAON_UART10_CLKCTRL,This register manages the UART10 clocks" bitfld.long 0x00 24. "CLKSEL,Selects functional clock for UART between FUNCTION_48M_CLK and FUNC_192M_CLK - SEL_FUNC_48M_CLK" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" group.long 0x88++0x03 line.long 0x00 "CM_WKUPAON_DCAN1_CLKCTRL,This register manages the DCAN1 clocks" bitfld.long 0x00 24. "CLKSEL,Selects SYS clock for DCAN1 between SYS_CLK1 and SYS_CLK2 - SEL_SYS_CLK1" "CLKSEL_0,CLKSEL_1" rbitfld.long 0x00 16.--17. "IDLEST,Module idle status" "IDLEST_0,IDLEST_1,IDLEST_2,IDLEST_3" newline bitfld.long 0x00 0.--1. "MODULEMODE,Control the way mandatory clocks are managed" "MODULEMODE_0,MODULEMODE_1,MODULEMODE_2,MODULEMODE_3" tree.end tree "WKUPAON_PRM" base ad:0x4AE07700 group.long 0x24++0x03 line.long 0x00 "RM_WKUPAON_L4_WKUP_CONTEXT,This register contains dedicated L4_WKUP context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x30++0x1F line.long 0x00 "PM_WKUPAON_WD_TIMER2_WKDEP,This register controls wakeup dependency based on WD_TIMER2 service requests" bitfld.long 0x00 7. "WKUPDEP_WD_TIMER2_EVE2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_EVE2_0,WKUPDEP_WD_TIMER2_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_WD_TIMER2_EVE1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_EVE1_0,WKUPDEP_WD_TIMER2_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_WD_TIMER2_DSP2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_DSP2_0,WKUPDEP_WD_TIMER2_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_WD_TIMER2_IPU1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_IPU1_0,WKUPDEP_WD_TIMER2_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_WD_TIMER2_DSP1,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_DSP1_0,WKUPDEP_WD_TIMER2_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_WD_TIMER2_IPU2,Wakeup dependency from TIMER module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_WD_TIMER2_IPU2_0,WKUPDEP_WD_TIMER2_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_WD_TIMER2_MPU,Wakeup dependency from WDT2 module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains - DISABLED" "WKUPDEP_WD_TIMER2_MPU_0,WKUPDEP_WD_TIMER2_MPU_1" line.long 0x04 "RM_WKUPAON_WD_TIMER2_CONTEXT,This register contains dedicated WD_TIMER2 context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_WKUPAON_GPIO1_WKDEP,This register controls wakeup dependency based on GPIO1 service requests" bitfld.long 0x08 17. "WKUPDEP_GPIO1_IRQ2_EVE2,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_EVE2_0,WKUPDEP_GPIO1_IRQ2_EVE2_1" bitfld.long 0x08 16. "WKUPDEP_GPIO1_IRQ2_EVE1,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_EVE1_0,WKUPDEP_GPIO1_IRQ2_EVE1_1" newline bitfld.long 0x08 15. "WKUPDEP_GPIO1_IRQ2_DSP2,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_DSP2_0,WKUPDEP_GPIO1_IRQ2_DSP2_1" bitfld.long 0x08 14. "WKUPDEP_GPIO1_IRQ2_IPU1,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_IPU1_0,WKUPDEP_GPIO1_IRQ2_IPU1_1" newline bitfld.long 0x08 12. "WKUPDEP_GPIO1_IRQ2_DSP1,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_DSP1_0,WKUPDEP_GPIO1_IRQ2_DSP1_1" bitfld.long 0x08 11. "WKUPDEP_GPIO1_IRQ2_IPU2,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_IPU2_0,WKUPDEP_GPIO1_IRQ2_IPU2_1" newline bitfld.long 0x08 10. "WKUPDEP_GPIO1_IRQ2_MPU,Wakeup dependency from GPIO1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ2_MPU_0,WKUPDEP_GPIO1_IRQ2_MPU_1" bitfld.long 0x08 7. "WKUPDEP_GPIO1_IRQ1_EVE2,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_EVE2_0,WKUPDEP_GPIO1_IRQ1_EVE2_1" newline bitfld.long 0x08 6. "WKUPDEP_GPIO1_IRQ1_EVE1,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_EVE1_0,WKUPDEP_GPIO1_IRQ1_EVE1_1" bitfld.long 0x08 5. "WKUPDEP_GPIO1_IRQ1_DSP2,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_DSP2_0,WKUPDEP_GPIO1_IRQ1_DSP2_1" newline bitfld.long 0x08 4. "WKUPDEP_GPIO1_IRQ1_IPU1,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_IPU1_0,WKUPDEP_GPIO1_IRQ1_IPU1_1" bitfld.long 0x08 2. "WKUPDEP_GPIO1_IRQ1_DSP1,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_DSP1_0,WKUPDEP_GPIO1_IRQ1_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_GPIO1_IRQ1_IPU2,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_IPU2_0,WKUPDEP_GPIO1_IRQ1_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_GPIO1_IRQ1_MPU,Wakeup dependency from GPIO1 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_GPIO1_IRQ1_MPU_0,WKUPDEP_GPIO1_IRQ1_MPU_1" line.long 0x0C "RM_WKUPAON_GPIO1_CONTEXT,This register contains dedicated GPIO1 context statuses" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_WKUPAON_TIMER1_WKDEP,This register controls wakeup dependency based on TIMER1 service requests" bitfld.long 0x10 7. "WKUPDEP_TIMER1_EVE2,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_EVE2_0,WKUPDEP_TIMER1_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_TIMER1_EVE1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_EVE1_0,WKUPDEP_TIMER1_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_TIMER1_DSP2,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_DSP2_0,WKUPDEP_TIMER1_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_TIMER1_IPU1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_IPU1_0,WKUPDEP_TIMER1_IPU1_1" newline bitfld.long 0x10 2. "WKUPDEP_TIMER1_DSP1,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_DSP1_0,WKUPDEP_TIMER1_DSP1_1" bitfld.long 0x10 1. "WKUPDEP_TIMER1_IPU2,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_IPU2_0,WKUPDEP_TIMER1_IPU2_1" newline bitfld.long 0x10 0. "WKUPDEP_TIMER1_MPU,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER1_MPU_0,WKUPDEP_TIMER1_MPU_1" line.long 0x14 "RM_WKUPAON_TIMER1_CONTEXT,This register contains dedicated TIMER1 context statuses" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x18 "PM_WKUPAON_TIMER12_WKDEP,This register controls wakeup dependency based on TIMER12 service requests" bitfld.long 0x18 7. "WKUPDEP_TIMER12_EVE2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_EVE2_0,WKUPDEP_TIMER12_EVE2_1" bitfld.long 0x18 6. "WKUPDEP_TIMER12_EVE1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_EVE1_0,WKUPDEP_TIMER12_EVE1_1" newline bitfld.long 0x18 5. "WKUPDEP_TIMER12_DSP2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_DSP2_0,WKUPDEP_TIMER12_DSP2_1" bitfld.long 0x18 4. "WKUPDEP_TIMER12_IPU1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_IPU1_0,WKUPDEP_TIMER12_IPU1_1" newline bitfld.long 0x18 2. "WKUPDEP_TIMER12_DSP1,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_DSP1_0,WKUPDEP_TIMER12_DSP1_1" bitfld.long 0x18 1. "WKUPDEP_TIMER12_IPU2,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_IPU2_0,WKUPDEP_TIMER12_IPU2_1" newline bitfld.long 0x18 0. "WKUPDEP_TIMER12_MPU,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_TIMER12_MPU_0,WKUPDEP_TIMER12_MPU_1" line.long 0x1C "RM_WKUPAON_TIMER12_CONTEXT,This register contains dedicated TIMER12 context statuses" bitfld.long 0x1C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x54++0x03 line.long 0x00 "RM_WKUPAON_COUNTER_32K_CONTEXT,This register contains dedicated COUNTER_32K context statuses" bitfld.long 0x00 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" group.long 0x78++0x17 line.long 0x00 "PM_WKUPAON_KBD_WKDEP,This register controls wakeup dependency based on KBD service requests" bitfld.long 0x00 7. "WKUPDEP_KBD_EVE2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_KBD_EVE2_0,WKUPDEP_KBD_EVE2_1" bitfld.long 0x00 6. "WKUPDEP_KBD_EVE1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_KBD_EVE1_0,WKUPDEP_KBD_EVE1_1" newline bitfld.long 0x00 5. "WKUPDEP_KBD_DSP2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_KBD_DSP2_0,WKUPDEP_KBD_DSP2_1" bitfld.long 0x00 4. "WKUPDEP_KBD_IPU1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_KBD_IPU1_0,WKUPDEP_KBD_IPU1_1" newline bitfld.long 0x00 2. "WKUPDEP_KBD_DSP1,Wakeup dependency from KBD module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_KBD_DSP1_0,WKUPDEP_KBD_DSP1_1" bitfld.long 0x00 1. "WKUPDEP_KBD_IPU2,Wakeup dependency from KBD module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_KBD_IPU2_0,WKUPDEP_KBD_IPU2_1" newline bitfld.long 0x00 0. "WKUPDEP_KBD_MPU,Wakeup dependency from KBD module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_KBD_MPU_0,WKUPDEP_KBD_MPU_1" line.long 0x04 "RM_WKUPAON_KBD_CONTEXT,This register contains dedicated KBD context statuses" bitfld.long 0x04 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x08 "PM_WKUPAON_UART10_WKDEP,This register controls wakeup dependency based on UART10 service requests" bitfld.long 0x08 7. "WKUPDEP_UART10_EVE2,Wakeup dependency from UART10 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_EVE2_0,WKUPDEP_UART10_EVE2_1" bitfld.long 0x08 6. "WKUPDEP_UART10_EVE1,Wakeup dependency from UART10 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_EVE1_0,WKUPDEP_UART10_EVE1_1" newline bitfld.long 0x08 5. "WKUPDEP_UART10_DSP2,Wakeup dependency from UART10 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_DSP2_0,WKUPDEP_UART10_DSP2_1" bitfld.long 0x08 4. "WKUPDEP_UART10_IPU1,Wakeup dependency from UART10 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_IPU1_0,WKUPDEP_UART10_IPU1_1" newline bitfld.long 0x08 3. "WKUPDEP_UART10_SDMA,Wakeup dependency from UART10 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_SDMA_0,WKUPDEP_UART10_SDMA_1" bitfld.long 0x08 2. "WKUPDEP_UART10_DSP1,Wakeup dependency from UART10 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_DSP1_0,WKUPDEP_UART10_DSP1_1" newline bitfld.long 0x08 1. "WKUPDEP_UART10_IPU2,Wakeup dependency from UART10 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_IPU2_0,WKUPDEP_UART10_IPU2_1" bitfld.long 0x08 0. "WKUPDEP_UART10_MPU,Wakeup dependency from UART10 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_UART10_MPU_0,WKUPDEP_UART10_MPU_1" line.long 0x0C "RM_WKUPAON_UART10_CONTEXT,This register contains dedicated UART10 context statuses" bitfld.long 0x0C 8. "LOSTMEM_RETAINED_BANK,Specify if memory-based context in UART memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_RETAINED_BANK_0,LOSTMEM_RETAINED_BANK_1" bitfld.long 0x0C 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" line.long 0x10 "PM_WKUPAON_DCAN1_WKDEP,This register controls wakeup dependency based on DCAN1 service requests" bitfld.long 0x10 7. "WKUPDEP_DCAN1_EVE2,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_EVE2_0,WKUPDEP_DCAN1_EVE2_1" bitfld.long 0x10 6. "WKUPDEP_DCAN1_EVE1,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_EVE1_0,WKUPDEP_DCAN1_EVE1_1" newline bitfld.long 0x10 5. "WKUPDEP_DCAN1_DSP2,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_DSP2_0,WKUPDEP_DCAN1_DSP2_1" bitfld.long 0x10 4. "WKUPDEP_DCAN1_IPU1,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_IPU1_0,WKUPDEP_DCAN1_IPU1_1" newline bitfld.long 0x10 3. "WKUPDEP_DCAN1_SDMA,Wakeup dependency from DCAN1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_SDMA_0,WKUPDEP_DCAN1_SDMA_1" bitfld.long 0x10 2. "WKUPDEP_DCAN1_DSP1,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_DSP1_0,WKUPDEP_DCAN1_DSP1_1" newline bitfld.long 0x10 1. "WKUPDEP_DCAN1_IPU2,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_IPU2_0,WKUPDEP_DCAN1_IPU2_1" bitfld.long 0x10 0. "WKUPDEP_DCAN1_MPU,Wakeup dependency from DCAN1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains - DISABLED" "WKUPDEP_DCAN1_MPU_0,WKUPDEP_DCAN1_MPU_1" line.long 0x14 "RM_WKUPAON_DCAN1_CONTEXT,This register contains dedicated DCAN1 context statuses" bitfld.long 0x14 8. "LOSTMEM_DCAN_MEM,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source" "LOSTMEM_DCAN_MEM_0,LOSTMEM_DCAN_MEM_1" bitfld.long 0x14 0. "LOSTCONTEXT_DFF,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "LOSTCONTEXT_DFF_0,LOSTCONTEXT_DFF_1" tree.end tree.end tree.open "PWM_Subsystem_Resources" tree "PWMSS1_CFG" base ad:0x4843E000 rgroup.long 0x00++0x0F line.long 0x00 "PWMSS_IDVER,IP Revision Register" line.long 0x04 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x04 0. "SOFTRESET,Software reset" "0,1" line.long 0x08 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM . eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x08 9. "EPWM_CLKSTOP_REQ,This bit controls the clock stop input to the ePWM / eHRPWM module" "0,1" bitfld.long 0x08 8. "EPWM_CLK_EN,This bit controls the interface clock enable (clk_en) input to the ePWM / eHRPWM module" "0,1" bitfld.long 0x08 5. "EQEP_CLKSTOP_REQ,This bit controls the clock stop input to the eQEP module" "0,1" bitfld.long 0x08 4. "EQEP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eQEP module" "0,1" bitfld.long 0x08 1. "ECAP_CLKSTOP_REQ,This bit controls the clock stop input to the eCAP module" "0,1" bitfld.long 0x08 0. "ECAP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eCAP module" "0,1" line.long 0x0C "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM . eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x0C 9. "EPWM_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the ePWM / eHRPWM module" "0,1" bitfld.long 0x0C 8. "EPWM_CLK_EN_ACK,This bit is the clk_en status output of the ePWM / eHRPWM module" "0,1" bitfld.long 0x0C 5. "EQEP_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" bitfld.long 0x0C 4. "EQEP_CLK_EN_ACK,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x0C 1. "ECAP_CLKSTOP_ACK,TThis bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x0C 0. "ECAP_CLK_EN_ACK,TThis bit is the clk_en status output of the eCAP module" "0,1" tree.end tree "PWMSS2_CFG" base ad:0x48440000 rgroup.long 0x00++0x0F line.long 0x00 "PWMSS_IDVER,IP Revision Register" line.long 0x04 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x04 0. "SOFTRESET,Software reset" "0,1" line.long 0x08 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM . eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x08 9. "EPWM_CLKSTOP_REQ,This bit controls the clock stop input to the ePWM / eHRPWM module" "0,1" bitfld.long 0x08 8. "EPWM_CLK_EN,This bit controls the interface clock enable (clk_en) input to the ePWM / eHRPWM module" "0,1" bitfld.long 0x08 5. "EQEP_CLKSTOP_REQ,This bit controls the clock stop input to the eQEP module" "0,1" bitfld.long 0x08 4. "EQEP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eQEP module" "0,1" bitfld.long 0x08 1. "ECAP_CLKSTOP_REQ,This bit controls the clock stop input to the eCAP module" "0,1" bitfld.long 0x08 0. "ECAP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eCAP module" "0,1" line.long 0x0C "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM . eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x0C 9. "EPWM_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the ePWM / eHRPWM module" "0,1" bitfld.long 0x0C 8. "EPWM_CLK_EN_ACK,This bit is the clk_en status output of the ePWM / eHRPWM module" "0,1" bitfld.long 0x0C 5. "EQEP_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" bitfld.long 0x0C 4. "EQEP_CLK_EN_ACK,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x0C 1. "ECAP_CLKSTOP_ACK,TThis bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x0C 0. "ECAP_CLK_EN_ACK,TThis bit is the clk_en status output of the eCAP module" "0,1" tree.end tree "PWMSS3_CFG" base ad:0x48442000 rgroup.long 0x00++0x0F line.long 0x00 "PWMSS_IDVER,IP Revision Register" line.long 0x04 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x04 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x04 0. "SOFTRESET,Software reset" "0,1" line.long 0x08 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM . eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x08 9. "EPWM_CLKSTOP_REQ,This bit controls the clock stop input to the ePWM / eHRPWM module" "0,1" bitfld.long 0x08 8. "EPWM_CLK_EN,This bit controls the interface clock enable (clk_en) input to the ePWM / eHRPWM module" "0,1" bitfld.long 0x08 5. "EQEP_CLKSTOP_REQ,This bit controls the clock stop input to the eQEP module" "0,1" bitfld.long 0x08 4. "EQEP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eQEP module" "0,1" bitfld.long 0x08 1. "ECAP_CLKSTOP_REQ,This bit controls the clock stop input to the eCAP module" "0,1" bitfld.long 0x08 0. "ECAP_CLK_EN,This bit controls the interface clock enable (clk_en) input to the eCAP module" "0,1" line.long 0x0C "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM . eCAP and eQEP submodules within the PWMSSn subsystem" bitfld.long 0x0C 9. "EPWM_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the ePWM / eHRPWM module" "0,1" bitfld.long 0x0C 8. "EPWM_CLK_EN_ACK,This bit is the clk_en status output of the ePWM / eHRPWM module" "0,1" bitfld.long 0x0C 5. "EQEP_CLKSTOP_ACK,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" bitfld.long 0x0C 4. "EQEP_CLK_EN_ACK,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x0C 1. "ECAP_CLKSTOP_ACK,TThis bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x0C 0. "ECAP_CLK_EN_ACK,TThis bit is the clk_en status output of the eCAP module" "0,1" tree.end tree "PWMSS1_ECAP" base ad:0x4843E100 group.long 0x00++0x17 line.long 0x00 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" line.long 0x04 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" line.long 0x08 "PWMSS_ECAP_CAP1,Capture-1 Register" line.long 0x0C "PWMSS_ECAP_CAP2,Capture-2 Register" line.long 0x10 "PWMSS_ECAP_CAP3,Capture-3 Register" line.long 0x14 "PWMSS_ECAP_CAP4,Capture-4 Register" group.word 0x28++0x0B line.word 0x00 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3" bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. "CAPLDEN,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event" "0,1" bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1" bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1" bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1" bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1" bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1" bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1" newline bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1" bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1" line.word 0x02 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "0,1" bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select" "0,1" bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "0,1" bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "0,1,2,3" bitfld.word 0x02 5. "SYNCI_EN,Counter (TSCNT) Sync-In select mode" "0,1" bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "0,1" bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "0,1" bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "0,1,2,3" bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "0,1" line.word 0x04 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x04 7. "CMPEQ,Counter Equal" "0,1" bitfld.word 0x04 6. "PRDEQ,Counter Equal" "0,1" bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "0,1" bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1" bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1" bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1" bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1" line.word 0x06 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "0,1" bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "0,1" bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "0,1" bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "0,1" bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "0,1" bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "0,1" bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "0,1" bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "0,1" line.word 0x08 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "0,1" bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "0,1" bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "0,1" bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "0,1" bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "0,1" bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "0,1" bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "0,1" bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x0A "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "0,1" bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "0,1" bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "0,1" bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "0,1" bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "0,1" bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "0,1" bitfld.word 0x0A 1. "CEVT1,Always reads back a 0" "0,1" rgroup.long 0x5C++0x03 line.long 0x00 "PWMSS_ECAP_PID,ECAP Revision ID" tree.end tree "PWMSS2_ECAP" base ad:0x48440100 group.long 0x00++0x17 line.long 0x00 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" line.long 0x04 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" line.long 0x08 "PWMSS_ECAP_CAP1,Capture-1 Register" line.long 0x0C "PWMSS_ECAP_CAP2,Capture-2 Register" line.long 0x10 "PWMSS_ECAP_CAP3,Capture-3 Register" line.long 0x14 "PWMSS_ECAP_CAP4,Capture-4 Register" group.word 0x28++0x0B line.word 0x00 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3" bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. "CAPLDEN,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event" "0,1" bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1" bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1" bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1" bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1" bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1" bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1" newline bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1" bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1" line.word 0x02 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "0,1" bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select" "0,1" bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "0,1" bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "0,1,2,3" bitfld.word 0x02 5. "SYNCI_EN,Counter (TSCNT) Sync-In select mode" "0,1" bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "0,1" bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "0,1" bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "0,1,2,3" bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "0,1" line.word 0x04 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x04 7. "CMPEQ,Counter Equal" "0,1" bitfld.word 0x04 6. "PRDEQ,Counter Equal" "0,1" bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "0,1" bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1" bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1" bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1" bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1" line.word 0x06 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "0,1" bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "0,1" bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "0,1" bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "0,1" bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "0,1" bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "0,1" bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "0,1" bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "0,1" line.word 0x08 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "0,1" bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "0,1" bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "0,1" bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "0,1" bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "0,1" bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "0,1" bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "0,1" bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x0A "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "0,1" bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "0,1" bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "0,1" bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "0,1" bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "0,1" bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "0,1" bitfld.word 0x0A 1. "CEVT1,Always reads back a 0" "0,1" rgroup.long 0x5C++0x03 line.long 0x00 "PWMSS_ECAP_PID,ECAP Revision ID" tree.end tree "PWMSS3_ECAP" base ad:0x48442100 group.long 0x00++0x17 line.long 0x00 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" line.long 0x04 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" line.long 0x08 "PWMSS_ECAP_CAP1,Capture-1 Register" line.long 0x0C "PWMSS_ECAP_CAP2,Capture-2 Register" line.long 0x10 "PWMSS_ECAP_CAP3,Capture-3 Register" line.long 0x14 "PWMSS_ECAP_CAP4,Capture-4 Register" group.word 0x28++0x0B line.word 0x00 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Control" "0,1,2,3" bitfld.word 0x00 9.--13. "EVTFLTPS,Event Filter prescale select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x00 8. "CAPLDEN,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event" "0,1" bitfld.word 0x00 7. "CTRRST4,Counter Reset on Capture Event 4" "0,1" bitfld.word 0x00 6. "CAP4POL,Capture Event 4 Polarity select" "0,1" bitfld.word 0x00 5. "CTRRST3,Counter Reset on Capture Event 3" "0,1" bitfld.word 0x00 4. "CAP3POL,Capture Event 3 Polarity select" "0,1" bitfld.word 0x00 3. "CTRRST2,Counter Reset on Capture Event 2" "0,1" bitfld.word 0x00 2. "CAP2POL,Capture Event 2 Polarity select" "0,1" newline bitfld.word 0x00 1. "CTRRST1,Counter Reset on Capture Event 1" "0,1" bitfld.word 0x00 0. "CAP1POL,Capture Event 1 Polarity select" "0,1" line.word 0x02 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x02 10. "APWMPOL,APWM output polarity select" "0,1" bitfld.word 0x02 9. "CAPAPWM,CAP/APWM operating mode select" "0,1" bitfld.word 0x02 8. "SWSYNC,Software-forced Counter (TSCNT) Synchronizing" "0,1" bitfld.word 0x02 6.--7. "SYNCO_SEL,Sync-Out Select" "0,1,2,3" bitfld.word 0x02 5. "SYNCI_EN,Counter (TSCNT) Sync-In select mode" "0,1" bitfld.word 0x02 4. "TSCNTSTP,Time Stamp (TSCNT) Counter Stop (freeze) Control" "0,1" bitfld.word 0x02 3. "REARMRESET,One-Shot Re-Arming Control that is wait for stop trigger" "0,1" bitfld.word 0x02 1.--2. "STOPVALUE,Stop value for one-shot mode" "0,1,2,3" bitfld.word 0x02 0. "CONTONESHT,Continuous or one-shot mode control (applicable only in capture mode)" "0,1" line.word 0x04 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x04 7. "CMPEQ,Counter Equal" "0,1" bitfld.word 0x04 6. "PRDEQ,Counter Equal" "0,1" bitfld.word 0x04 5. "CNTOVF,Counter Overflow Interrupt Enable" "0,1" bitfld.word 0x04 4. "CEVT4,Capture Event 4 Interrupt Enable" "0,1" bitfld.word 0x04 3. "CEVT3,Capture Event 3 Interrupt Enable" "0,1" bitfld.word 0x04 2. "CEVT2,Capture Event 2 Interrupt Enable" "0,1" bitfld.word 0x04 1. "CEVT1,Capture Event 1 Interrupt Enable" "0,1" line.word 0x06 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x06 7. "CMPEQ,Compare Equal Compare Status Flag" "0,1" bitfld.word 0x06 6. "PRDEQ,Counter Equal Period Status Flag" "0,1" bitfld.word 0x06 5. "CNTOVF,Counter Overflow Status Flag" "0,1" bitfld.word 0x06 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode" "0,1" bitfld.word 0x06 3. "CEVT3,Capture Event 3 Status Flag" "0,1" bitfld.word 0x06 2. "CEVT2,Capture Event 2 Status Flag" "0,1" bitfld.word 0x06 1. "CEVT1,Capture Event 1 Status Flag" "0,1" bitfld.word 0x06 0. "INT,Global Interrupt Status Flag" "0,1" line.word 0x08 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x08 7. "CMPEQ,Counter Equal Compare Status Flag" "0,1" bitfld.word 0x08 6. "PRDEQ,Counter Equal Period Status Flag" "0,1" bitfld.word 0x08 5. "CNTOVF,Counter Overflow Status Flag" "0,1" bitfld.word 0x08 4. "CEVT4,Capture Event 4 Status Flag" "0,1" bitfld.word 0x08 3. "CEVT3,Capture Event 3 Status Flag" "0,1" bitfld.word 0x08 2. "CEVT2,Capture Event 2 Status Flag" "0,1" bitfld.word 0x08 1. "CEVT1,Capture Event 1 Status Flag" "0,1" bitfld.word 0x08 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x0A "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0A 7. "CMPEQ,Force Counter Equal Compare Interrupt" "0,1" bitfld.word 0x0A 6. "PRDEQ,Force Counter Equal Period Interrupt" "0,1" bitfld.word 0x0A 5. "CNTOVF,Force Counter Overflow" "0,1" bitfld.word 0x0A 4. "CEVT4,Force Capture Event 4" "0,1" bitfld.word 0x0A 3. "CEVT3,Force Capture Event 3" "0,1" bitfld.word 0x0A 2. "CEVT2,Force Capture Event 2" "0,1" bitfld.word 0x0A 1. "CEVT1,Always reads back a 0" "0,1" rgroup.long 0x5C++0x03 line.long 0x00 "PWMSS_ECAP_PID,ECAP Revision ID" tree.end tree "PWMSS1_EPWM" base ad:0x4843E200 group.word 0x00++0x0B line.word 0x00 "EPWM_TBCTL," bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3" bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit" "0,1" bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7" bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select" "0,1,2,3" bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode" "0,1,2,3" line.word 0x02 "EPWM_TBSTS," bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit" "0,1" line.word 0x04 "HRPWM_TBPHSHR," hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x06 "EPWM_TBPHS," line.word 0x08 "EPWM_TBCNT," line.word 0x0A "EPWM_TBPRD," group.word 0x0E++0x17 line.word 0x00 "EPWM_CMPCTL," rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value" "0,1" rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register.." "0,1" bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "0,1,2,3" bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A ( 0x0 = Load on 0x1 = Load on 0x2 = Load on either 0x3 = Freeze (no loads possible)" "0,1,2,3" line.word 0x02 "HRPWM_CMPAHR," hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control" line.word 0x04 "EPWM_CMPA," line.word 0x06 "EPWM_CMPB," line.word 0x08 "EPWM_AQCTLA," bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active" "0,1,2,3" bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period" "0,1,2,3" bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero" "0,1,2,3" line.word 0x0A "EPWM_AQCTLB," bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period" "0,1,2,3" bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero" "0,1,2,3" line.word 0x0C "EPWM_AQSFRC," bitfld.word 0x0C 6.--7. "RLDCSF," "0,1,2,3" bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0x0E "EPWM_AQCSFRC," bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B" "0,1,2,3" bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3" line.word 0x10 "EPWM_DBCTL," bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control" "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control" "0,1,2,3" line.word 0x12 "EPWM_DBRED," hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count" line.word 0x14 "EPWM_DBFED," hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count" line.word 0x16 "EPWM_TZSEL," hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n (TZn) select" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select" "0,1" group.word 0x28++0x15 line.word 0x00 "EPWM_TZCTL," bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3" bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3" line.word 0x02 "EPWM_TZEINT," bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" line.word 0x04 "EPWM_TZFLG," bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1" line.word 0x06 "EPWM_TZCLR," bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip (OST) Latch" "0,1" bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "0,1" bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x08 "EPWM_TZFRC," bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x0A "EPWM_ETSEL," bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation" "0,1" bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options" "0,1,2,3,4,5,6,7" line.word 0x0C "EPWM_ETPS," rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt (EPWMx_INT) Period Select" "0,1,2,3" line.word 0x0E "EPWM_ETFLG," bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "0,1" line.word 0x10 "EPWM_ETCLR," bitfld.word 0x10 0. "INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "0,1" line.word 0x12 "EPWM_ETFRC," bitfld.word 0x12 0. "INT,INT Force Bit" "0,1" line.word 0x14 "EPWM_PCCTL," bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1" group.word 0x40++0x01 line.word 0x00 "HRPWM_HRCTL," bitfld.word 0x00 3. "PULSESEL,Pulse select bits" "0,1" bitfld.word 0x00 2. "DELBUSSEL,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse" "0,1" bitfld.word 0x00 0.--1. "DELMODE,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted" "0,1,2,3" tree.end tree "PWMSS2_EPWM" base ad:0x48440200 group.word 0x00++0x0B line.word 0x00 "EPWM_TBCTL," bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3" bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit" "0,1" bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7" bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select" "0,1,2,3" bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode" "0,1,2,3" line.word 0x02 "EPWM_TBSTS," bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit" "0,1" line.word 0x04 "HRPWM_TBPHSHR," hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x06 "EPWM_TBPHS," line.word 0x08 "EPWM_TBCNT," line.word 0x0A "EPWM_TBPRD," group.word 0x0E++0x17 line.word 0x00 "EPWM_CMPCTL," rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value" "0,1" rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register.." "0,1" bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "0,1,2,3" bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A ( 0x0 = Load on 0x1 = Load on 0x2 = Load on either 0x3 = Freeze (no loads possible)" "0,1,2,3" line.word 0x02 "HRPWM_CMPAHR," hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control" line.word 0x04 "EPWM_CMPA," line.word 0x06 "EPWM_CMPB," line.word 0x08 "EPWM_AQCTLA," bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active" "0,1,2,3" bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period" "0,1,2,3" bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero" "0,1,2,3" line.word 0x0A "EPWM_AQCTLB," bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period" "0,1,2,3" bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero" "0,1,2,3" line.word 0x0C "EPWM_AQSFRC," bitfld.word 0x0C 6.--7. "RLDCSF," "0,1,2,3" bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0x0E "EPWM_AQCSFRC," bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B" "0,1,2,3" bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3" line.word 0x10 "EPWM_DBCTL," bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control" "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control" "0,1,2,3" line.word 0x12 "EPWM_DBRED," hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count" line.word 0x14 "EPWM_DBFED," hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count" line.word 0x16 "EPWM_TZSEL," hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n (TZn) select" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select" "0,1" group.word 0x28++0x15 line.word 0x00 "EPWM_TZCTL," bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3" bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3" line.word 0x02 "EPWM_TZEINT," bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" line.word 0x04 "EPWM_TZFLG," bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1" line.word 0x06 "EPWM_TZCLR," bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip (OST) Latch" "0,1" bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "0,1" bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x08 "EPWM_TZFRC," bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x0A "EPWM_ETSEL," bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation" "0,1" bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options" "0,1,2,3,4,5,6,7" line.word 0x0C "EPWM_ETPS," rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt (EPWMx_INT) Period Select" "0,1,2,3" line.word 0x0E "EPWM_ETFLG," bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "0,1" line.word 0x10 "EPWM_ETCLR," bitfld.word 0x10 0. "INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "0,1" line.word 0x12 "EPWM_ETFRC," bitfld.word 0x12 0. "INT,INT Force Bit" "0,1" line.word 0x14 "EPWM_PCCTL," bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1" group.word 0x40++0x01 line.word 0x00 "HRPWM_HRCTL," bitfld.word 0x00 3. "PULSESEL,Pulse select bits" "0,1" bitfld.word 0x00 2. "DELBUSSEL,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse" "0,1" bitfld.word 0x00 0.--1. "DELMODE,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted" "0,1,2,3" tree.end tree "PWMSS3_EPWM" base ad:0x48442200 group.word 0x00++0x0B line.word 0x00 "EPWM_TBCTL," bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits" "0,1,2,3" bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit" "0,1" bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7" bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7" bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1" bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select" "0,1,2,3" bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1" bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1" bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode" "0,1,2,3" line.word 0x02 "EPWM_TBSTS," bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1" bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1" rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit" "0,1" line.word 0x04 "HRPWM_TBPHSHR," hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits" line.word 0x06 "EPWM_TBPHS," line.word 0x08 "EPWM_TBCNT," line.word 0x0A "EPWM_TBPRD," group.word 0x0E++0x17 line.word 0x00 "EPWM_CMPCTL," rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value" "0,1" rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value" "0,1" bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register.." "0,1" bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for.." "0,1" bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "0,1,2,3" bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A ( 0x0 = Load on 0x1 = Load on 0x2 = Load on either 0x3 = Freeze (no loads possible)" "0,1,2,3" line.word 0x02 "HRPWM_CMPAHR," hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control" line.word 0x04 "EPWM_CMPA," line.word 0x06 "EPWM_CMPB," line.word 0x08 "EPWM_AQCTLA," bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active" "0,1,2,3" bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period" "0,1,2,3" bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero" "0,1,2,3" line.word 0x0A "EPWM_AQCTLB," bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active" "0,1,2,3" bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period" "0,1,2,3" bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero" "0,1,2,3" line.word 0x0C "EPWM_AQSFRC," bitfld.word 0x0C 6.--7. "RLDCSF," "0,1,2,3" bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1" bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3" bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1" bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3" line.word 0x0E "EPWM_AQCSFRC," bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B" "0,1,2,3" bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3" line.word 0x10 "EPWM_DBCTL," bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control" "0,1,2,3" bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control" "0,1,2,3" bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control" "0,1,2,3" line.word 0x12 "EPWM_DBRED," hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count" line.word 0x14 "EPWM_DBFED," hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count" line.word 0x16 "EPWM_TZSEL," hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n (TZn) select" bitfld.word 0x16 0. "CBC0,Trip-zone 0 (TZ0) select" "0,1" group.word 0x28++0x15 line.word 0x00 "EPWM_TZCTL," bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3" bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3" line.word 0x02 "EPWM_TZEINT," bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1" bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1" line.word 0x04 "EPWM_TZFLG," bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1" bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1" bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1" line.word 0x06 "EPWM_TZCLR," bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip (OST) Latch" "0,1" bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "0,1" bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1" line.word 0x08 "EPWM_TZFRC," bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1" bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1" line.word 0x0A "EPWM_ETSEL," bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation" "0,1" bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options" "0,1,2,3,4,5,6,7" line.word 0x0C "EPWM_ETPS," rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt (EPWMx_INT) Period Select" "0,1,2,3" line.word 0x0E "EPWM_ETFLG," bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "0,1" line.word 0x10 "EPWM_ETCLR," bitfld.word 0x10 0. "INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "0,1" line.word 0x12 "EPWM_ETFRC," bitfld.word 0x12 0. "INT,INT Force Bit" "0,1" line.word 0x14 "EPWM_PCCTL," bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7" bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7" bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1" group.word 0x40++0x01 line.word 0x00 "HRPWM_HRCTL," bitfld.word 0x00 3. "PULSESEL,Pulse select bits" "0,1" bitfld.word 0x00 2. "DELBUSSEL,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse" "0,1" bitfld.word 0x00 0.--1. "DELMODE,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted" "0,1,2,3" tree.end tree "PWMSS1_EQEP" base ad:0x4843E180 group.long 0x00++0x23 line.long 0x00 "EQEP_QPOSCNT," line.long 0x04 "EQEP_QPOSINIT," line.long 0x08 "EQEP_QPOSMAX," line.long 0x0C "EQEP_QPOSCMP," line.long 0x10 "EQEP_QPOSILAT," line.long 0x14 "EQEP_QPOSSLAT," line.long 0x18 "EQEP_QPOSLAT," line.long 0x1C "EQEP_QUTMR," line.long 0x20 "EQEP_QUPRD," group.word 0x24++0x1D line.word 0x00 "EQEP_QWDTMR," line.word 0x02 "EQEP_QWDPRD," line.word 0x04 "EQEP_QDECCTL," bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1" bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1" bitfld.word 0x04 11. "XCR,External clock rate" "0,1" bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "0,1" bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1" bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1" bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1" bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1" newline bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1" line.word 0x06 "EQEP_QEPCTL," bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "0,1,2,3" bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "0,1,2,3" bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3" bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "0,1,2,3" bitfld.word 0x06 7. "SWI,Software initialization of position counter" "0,1" bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1" bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "0,1,2,3" bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "0,1" bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "0,1" newline bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "0,1" bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "0,1" line.word 0x08 "EQEP_QCAPCTL," bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1" bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7" bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0A "EQEP_QPOSCTL," bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "0,1" bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "0,1" bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1" bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "0,1" hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width" line.word 0x0C "EQEP_QEINT," bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1" bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1" bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1" bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1" bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1" bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1" bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1" bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1" bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1" newline bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "0,1" bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1" line.word 0x0E "EQEP_QFLG," bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1" bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1" bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1" bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1" bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1" bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1" bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1" bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1" bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1" bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1" bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1" line.word 0x10 "EQEP_QCLR," bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1" bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1" bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1" bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1" bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1" bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1" bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1" bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1" bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1" bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1" bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1" line.word 0x12 "EQEP_QFRC," bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1" bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1" bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1" bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1" bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1" bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1" bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1" bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1" bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1" newline bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1" bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1" line.word 0x14 "EQEP_QEPSTS," rbitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1" rbitfld.word 0x14 6. "FDF,Direction on the first index marker" "0,1" rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1" rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1" bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1" bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1" bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1" rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1" line.word 0x16 "EQEP_QCTMR," line.word 0x18 "EQEP_QCPRD," line.word 0x1A "EQEP_QCTMRLAT," line.word 0x1C "EQEP_QCPRDLAT," rgroup.long 0x5C++0x03 line.long 0x00 "EQEP_REVID," tree.end tree "PWMSS2_EQEP" base ad:0x48440180 group.long 0x00++0x23 line.long 0x00 "EQEP_QPOSCNT," line.long 0x04 "EQEP_QPOSINIT," line.long 0x08 "EQEP_QPOSMAX," line.long 0x0C "EQEP_QPOSCMP," line.long 0x10 "EQEP_QPOSILAT," line.long 0x14 "EQEP_QPOSSLAT," line.long 0x18 "EQEP_QPOSLAT," line.long 0x1C "EQEP_QUTMR," line.long 0x20 "EQEP_QUPRD," group.word 0x24++0x1D line.word 0x00 "EQEP_QWDTMR," line.word 0x02 "EQEP_QWDPRD," line.word 0x04 "EQEP_QDECCTL," bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1" bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1" bitfld.word 0x04 11. "XCR,External clock rate" "0,1" bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "0,1" bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1" bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1" bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1" bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1" newline bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1" line.word 0x06 "EQEP_QEPCTL," bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "0,1,2,3" bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "0,1,2,3" bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3" bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "0,1,2,3" bitfld.word 0x06 7. "SWI,Software initialization of position counter" "0,1" bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1" bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "0,1,2,3" bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "0,1" bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "0,1" newline bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "0,1" bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "0,1" line.word 0x08 "EQEP_QCAPCTL," bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1" bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7" bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0A "EQEP_QPOSCTL," bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "0,1" bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "0,1" bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1" bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "0,1" hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width" line.word 0x0C "EQEP_QEINT," bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1" bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1" bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1" bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1" bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1" bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1" bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1" bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1" bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1" newline bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "0,1" bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1" line.word 0x0E "EQEP_QFLG," bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1" bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1" bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1" bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1" bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1" bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1" bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1" bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1" bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1" bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1" bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1" line.word 0x10 "EQEP_QCLR," bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1" bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1" bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1" bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1" bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1" bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1" bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1" bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1" bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1" bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1" bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1" line.word 0x12 "EQEP_QFRC," bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1" bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1" bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1" bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1" bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1" bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1" bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1" bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1" bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1" newline bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1" bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1" line.word 0x14 "EQEP_QEPSTS," rbitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1" rbitfld.word 0x14 6. "FDF,Direction on the first index marker" "0,1" rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1" rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1" bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1" bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1" bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1" rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1" line.word 0x16 "EQEP_QCTMR," line.word 0x18 "EQEP_QCPRD," line.word 0x1A "EQEP_QCTMRLAT," line.word 0x1C "EQEP_QCPRDLAT," rgroup.long 0x5C++0x03 line.long 0x00 "EQEP_REVID," tree.end tree "PWMSS3_EQEP" base ad:0x48442180 group.long 0x00++0x23 line.long 0x00 "EQEP_QPOSCNT," line.long 0x04 "EQEP_QPOSINIT," line.long 0x08 "EQEP_QPOSMAX," line.long 0x0C "EQEP_QPOSCMP," line.long 0x10 "EQEP_QPOSILAT," line.long 0x14 "EQEP_QPOSSLAT," line.long 0x18 "EQEP_QPOSLAT," line.long 0x1C "EQEP_QUTMR," line.long 0x20 "EQEP_QUPRD," group.word 0x24++0x1D line.word 0x00 "EQEP_QWDTMR," line.word 0x02 "EQEP_QWDPRD," line.word 0x04 "EQEP_QDECCTL," bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1" bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1" bitfld.word 0x04 11. "XCR,External clock rate" "0,1" bitfld.word 0x04 10. "SWAP,Swap quadrature clock inputs" "0,1" bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1" bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1" bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1" bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1" newline bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1" line.word 0x06 "EQEP_QEPCTL," bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation Control Bits" "0,1,2,3" bitfld.word 0x06 12.--13. "PCRM,Position counter reset mode" "0,1,2,3" bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3" bitfld.word 0x06 8.--9. "IEI,Index event initialization of position counter" "0,1,2,3" bitfld.word 0x06 7. "SWI,Software initialization of position counter" "0,1" bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1" bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter (software index marker)" "0,1,2,3" bitfld.word 0x06 3. "PHEN,Quadrature position counter enable/software reset" "0,1" bitfld.word 0x06 2. "QCLM,eQEP capture latch mode" "0,1" newline bitfld.word 0x06 1. "UTE,eQEP unit timer enable" "0,1" bitfld.word 0x06 0. "WDE,eQEP watchdog enable" "0,1" line.word 0x08 "EQEP_QCAPCTL," bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1" bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7" bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.word 0x0A "EQEP_QPOSCTL," bitfld.word 0x0A 15. "PCSHDW,Position-compare shadow enable" "0,1" bitfld.word 0x0A 14. "PCLOAD,Position-compare shadow load mode" "0,1" bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1" bitfld.word 0x0A 12. "PCE,Position-compare enable/disable" "0,1" hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width" line.word 0x0C "EQEP_QEINT," bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1" bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1" bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1" bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1" bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1" bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1" bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1" bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1" bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1" newline bitfld.word 0x0C 2. "PHE,Quadrature phase error interrupt enable" "0,1" bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1" line.word 0x0E "EQEP_QFLG," bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1" bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1" bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1" bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1" bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1" bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1" bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1" bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1" bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1" bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1" bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1" line.word 0x10 "EQEP_QCLR," bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1" bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1" bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1" bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1" bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1" bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1" bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1" bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1" bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1" newline bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1" bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1" bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1" line.word 0x12 "EQEP_QFRC," bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1" bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1" bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1" bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1" bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1" bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1" bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1" bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1" bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1" newline bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1" bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1" line.word 0x14 "EQEP_QEPSTS," rbitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1" rbitfld.word 0x14 6. "FDF,Direction on the first index marker" "0,1" rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1" rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1" bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1" bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1" bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1" rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1" line.word 0x16 "EQEP_QCTMR," line.word 0x18 "EQEP_QCPRD," line.word 0x1A "EQEP_QCTMRLAT," line.word 0x1C "EQEP_QCPRDLAT," rgroup.long 0x5C++0x03 line.long 0x00 "EQEP_REVID," tree.end tree.end tree.open "Quad_Serial_Peripheral_Interface" tree "QSPI" base ad:0x4B300000 rgroup.long 0x00++0x03 line.long 0x00 "QSPI_PID,Revision register" group.long 0x10++0x03 line.long 0x00 "QSPI_SYSCONFIG," bitfld.long 0x00 2.--3. "IDLE_MODE,Configuration of the local target state management mode" "0,1,2,3" group.long 0x20++0x13 line.long 0x00 "QSPI_INTR_STATUS_RAW_SET,This register contains raw interrupt status flags" bitfld.long 0x00 1. "WIRQ_RAW,Word Interrupt Status" "WIRQ_RAW_0,WIRQ_RAW_1" bitfld.long 0x00 0. "FIRQ_RAW,Frame Interrupt Status" "FIRQ_RAW_0,FIRQ_RAW_1" line.long 0x04 "QSPI_INTR_STATUS_ENABLED_CLEAR,This register contains status flags of the enabled interrupts" bitfld.long 0x04 1. "WIRQ_ENA,Word Interrupt Enabled Status" "WIRQ_ENA_0,WIRQ_ENA_1" bitfld.long 0x04 0. "FIRQ_ENA,Frame Interrupt Enabled Status" "FIRQ_ENA_0,FIRQ_ENA_1" line.long 0x08 "QSPI_INTR_ENABLE_SET_REG,This register enables the interrupts" bitfld.long 0x08 1. "WIRQ_ENA_SET,Word interrupt enable.Read" "WIRQ_ENA_SET_0,WIRQ_ENA_SET_1" bitfld.long 0x08 0. "FIRQ_ENA_SET,Frame interrupt enable.Read" "FIRQ_ENA_SET_0,FIRQ_ENA_SET_1" line.long 0x0C "QSPI_INTR_ENABLE_CLEAR_REG,This register disables the interrupts" bitfld.long 0x0C 1. "WIRQ_ENA_CLR,Word interrupt disable.Read" "WIRQ_ENA_CLR_0,WIRQ_ENA_CLR_1" bitfld.long 0x0C 0. "FIRQ_ENA_CLR,Frame interrupt disable.Read" "FIRQ_ENA_CLR_0,FIRQ_ENA_CLR_1" line.long 0x10 "QSPI_INTC_EOI_REG,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" group.long 0x40++0x33 line.long 0x00 "QSPI_SPI_CLOCK_CNTRL_REG,This register controls the external SPI clock generation" bitfld.long 0x00 31. "CLKEN,External SPI clock (qspi1_sclk) enable" "CLKEN_0,CLKEN_1" hexmask.long.word 0x00 0.--15. 1. "DCLK_DIV,Divide ratio for the external SPI clock (qspi1_sclk)" line.long 0x04 "QSPI_SPI_DC_REG,This register controls the different modes for each output chip select" bitfld.long 0x04 27.--28. "DD3,Data delay for chip select 3" "0,1,2,3" bitfld.long 0x04 26. "CKPH3,Clock phase for chip select 3" "0,1" bitfld.long 0x04 25. "CSP3,Chip select polarity for chip select 3" "CSP3_0,CSP3_1" bitfld.long 0x04 24. "CKP3,Clock polarity for chip select 3" "CKP3_0,CKP3_1" bitfld.long 0x04 19.--20. "DD2,Data delay for chip select 2" "0,1,2,3" newline bitfld.long 0x04 18. "CKPH2,Clock phase for chip select 2" "0,1" bitfld.long 0x04 17. "CSP2,Chip select polarity for chip select 2" "CSP2_0,CSP2_1" bitfld.long 0x04 16. "CKP2,Clock polarity for chip select 2" "CKP2_0,CKP2_1" bitfld.long 0x04 11.--12. "DD1,Data delay for chip select 1" "0,1,2,3" bitfld.long 0x04 10. "CKPH1,Clock phase for chip select 1" "0,1" newline bitfld.long 0x04 9. "CSP1,Chip select polarity for chip select 1" "CSP1_0,CSP1_1" bitfld.long 0x04 8. "CKP1,Clock polarity for chip select 1" "CKP1_0,CKP1_1" bitfld.long 0x04 3.--4. "DD0,Data delay for chip select 0" "0,1,2,3" bitfld.long 0x04 2. "CKPH0,Clock phase for chip select 0" "0,1" bitfld.long 0x04 1. "CSP0,Chip select polarity for chip select 0" "CSP0_0,CSP0_1" newline bitfld.long 0x04 0. "CKP0,Clock polarity for chip select 0" "CKP0_0,CKP0_1" line.long 0x08 "QSPI_SPI_CMD_REG,This register sets up the SPI command" bitfld.long 0x08 28.--29. "CSNUM,Device select" "0,1,2,3" hexmask.long.byte 0x08 19.--25. 1. "WLEN,Word length" bitfld.long 0x08 16.--18. "CMD,Transfer command" "0,1,2,3,4,5,6,7" bitfld.long 0x08 15. "FIRQ,Frame complete interrupt enable" "FIRQ_0,FIRQ_1" bitfld.long 0x08 14. "WIRQ,Word complete interrupt enable - WORD_COUNT_IRQ_DISABLE" "WIRQ_0,WIRQ_1" newline hexmask.long.word 0x08 0.--11. 1. "FLEN,Frame Length" line.long 0x0C "QSPI_SPI_STATUS_REG,This register contains indicators to allow the user to monitor the progression of a frame transfer" hexmask.long.word 0x0C 16.--27. 1. "WDCNT,Word count" bitfld.long 0x0C 2. "FC,Frame complete" "FC_0,FC_1" bitfld.long 0x0C 1. "WC,Word complete" "WC_0,WC_1" bitfld.long 0x0C 0. "BUSY,Busy bit" "BUSY_0,BUSY_1" line.long 0x10 "QSPI_SPI_DATA_REG,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x14 "QSPI_SPI_SETUP0_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 0 output)" bitfld.long 0x14 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x14 16.--23. 1. "WCMD,Write command" bitfld.long 0x14 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "0,1,2,3" bitfld.long 0x14 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "0,1,2,3" bitfld.long 0x14 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "0,1,2,3" newline hexmask.long.byte 0x14 0.--7. 1. "RCMD,Read Command" line.long 0x18 "QSPI_SPI_SETUP1_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 1 output)" bitfld.long 0x18 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x18 16.--23. 1. "WCMD,Write command" bitfld.long 0x18 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "0,1,2,3" bitfld.long 0x18 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "0,1,2,3" bitfld.long 0x18 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "0,1,2,3" newline hexmask.long.byte 0x18 0.--7. 1. "RCMD,Read Command" line.long 0x1C "QSPI_SPI_SETUP2_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 2 output)" bitfld.long 0x1C 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x1C 16.--23. 1. "WCMD,Write command" bitfld.long 0x1C 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "0,1,2,3" bitfld.long 0x1C 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "0,1,2,3" bitfld.long 0x1C 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "0,1,2,3" newline hexmask.long.byte 0x1C 0.--7. 1. "RCMD,Read Command" line.long 0x20 "QSPI_SPI_SETUP3_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 3 output)" bitfld.long 0x20 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x20 16.--23. 1. "WCMD,Write command" bitfld.long 0x20 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command" "0,1,2,3" bitfld.long 0x20 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "0,1,2,3" bitfld.long 0x20 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "0,1,2,3" newline hexmask.long.byte 0x20 0.--7. 1. "RCMD,Read Command" line.long 0x24 "QSPI_SPI_SWITCH_REG,This register allows initiators to switch control of the SPI core port between the configuration port and the SFI translator" bitfld.long 0x24 1. "MM_INT_EN,Memory mapped mode interrupt enable" "MM_INT_EN_0,MM_INT_EN_1" bitfld.long 0x24 0. "MMPT_S,MPT select" "MMPT_S_0,MMPT_S_1" line.long 0x28 "QSPI_SPI_DATA_REG_1,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x2C "QSPI_SPI_DATA_REG_2,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" line.long 0x30 "QSPI_SPI_DATA_REG_3,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left" tree.end tree.end tree.open "RTC" tree "RTC_SS" base ad:0x48838000 group.long 0x00++0x1B line.long 0x00 "RTC_SECONDS_REG,Used to program the required seconds value of the current time" bitfld.long 0x00 4.--6. "SEC1,2nd digit of seconds Range is 0 to 5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. "SEC0,1st digit of seconds Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RTC_MINUTES_REG,Used to program the required minutes value of the current time" bitfld.long 0x04 4.--6. "MIN1,2nd digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--3. "MIN0,1st digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RTC_HOURS_REG,Used to program the hours value of the current time" bitfld.long 0x08 7. "PM_NAM,Only used in PM_AM mode (otherwise 0)" "0,1" bitfld.long 0x08 4.--5. "HOUR1,2nd digit of hours Range is 0 to 2" "0,1,2,3" bitfld.long 0x08 0.--3. "HOUR0,1st digit of hours Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "RTC_DAYS_REG,Used to program the day of the month value of the current date" bitfld.long 0x0C 4.--5. "DAY1,2nd digit of days Range from 0 to 3" "0,1,2,3" bitfld.long 0x0C 0.--3. "DAY0,1st digit of days Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "RTC_MONTHS_REG,The MONTHS_REG is used to set the month in the year value of the current date" bitfld.long 0x10 4. "MONTH1,2nd digit of months Range from 0 to 1" "0,1" bitfld.long 0x10 0.--3. "MONTH0,1st digit of months Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "RTC_YEARS_REG,The YEARS_REG is used to program the year value of the current date" bitfld.long 0x14 4.--7. "YEAR1,2nd digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--3. "YEAR0,1st digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "RTC_WEEKS_REG,The WEEKS_REG is used to program the day of the week value of the current date" bitfld.long 0x18 0.--2. "WEEK,1st digit of Days in a week Range from 0 (Sunday) to 6 (Saturday)" "0,1,2,3,4,5,6,7" group.long 0x20++0x17 line.long 0x00 "RTC_ALARM_SECONDS_REG,The ALARM_SECONDS_REG is used to program the seconds value for the alarm interrupt" bitfld.long 0x00 4.--6. "ALARM_SEC1,2nd digit of seconds Range is 0 to 5" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. "ALARM_SEC0,1st digit of seconds Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "RTC_ALARM_MINUTES_REG,The ALARM_MINUTES_REG is used to program the minute value for the alarm interrupt" bitfld.long 0x04 4.--6. "ALARM_MIN1,2nd digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--3. "ALARM_MIN0,1st digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "RTC_ALARM_HOURS_REG,The ALARM_HOURS_REG is used to program the hour value for the alarm interrupt" bitfld.long 0x08 7. "ALARM_PM_NAM,Only used in PM_AM mode (otherwise 0)" "0,1" bitfld.long 0x08 4.--5. "ALARM_HOUR1,2nd digit of hours Range is 0 to 2" "0,1,2,3" bitfld.long 0x08 0.--3. "ALARM_HOUR0,1st digit of hours Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "RTC_ALARM_DAYS_REG,The ALARM_DAYS_REG is used to program the day of the month value for the alarm interrupt" bitfld.long 0x0C 4.--5. "ALARM_DAY1,2nd digit for days Range from 0 to 3" "0,1,2,3" bitfld.long 0x0C 0.--3. "ALARM_DAY0,1st digit for days Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "RTC_ALARM_MONTHS_REG,The ALARM_MONTHS_REG is used to program the month in the year value for the alarm interrupt" bitfld.long 0x10 4. "ALARM_MONTH1,2nd digit of months Range from 0 to 1" "0,1" bitfld.long 0x10 0.--3. "ALARM_MONTH0,1st digit of months Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "RTC_ALARM_YEARS_REG,The ALARM_YEARS_REG is used to program the year for the alarm interrupt" bitfld.long 0x14 4.--7. "ALARM_YEAR1,2nd digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--3. "ALARM_YEAR0,1st digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x17 line.long 0x00 "RTC_CTRL_REG,The CTRL_REG contains the controls to enable/disable RTC" bitfld.long 0x00 6. "RTC_DISABLE," "0,1" bitfld.long 0x00 5. "SET_32_COUNTER," "0,1" bitfld.long 0x00 4. "TEST_MODE," "0,1" bitfld.long 0x00 3. "MODE_12_24," "0,1" bitfld.long 0x00 2. "AUTO_COMP," "0,1" newline bitfld.long 0x00 1. "ROUND_30S," "0,1" bitfld.long 0x00 0. "STOP_RTC," "0,1" line.long 0x04 "RTC_STATUS_REG,The RTC STATUS_REG contains bits that signal the status of interrupts. events to the processor" bitfld.long 0x04 7. "ALARM2,Indicates that an alarm2 interrupt has been generated" "0,1" bitfld.long 0x04 6. "ALARM,Indicates that an alarm interrupt has been generated" "0,1" rbitfld.long 0x04 5. "EVENT_1D,One day has occurred" "0,1" rbitfld.long 0x04 4. "EVENT_1H,One hour has occurred" "0,1" rbitfld.long 0x04 3. "EVENT_1M,One minute has occurred" "0,1" newline rbitfld.long 0x04 2. "EVENT_1S,One second has occurred" "0,1" rbitfld.long 0x04 1. "RUN," "0,1" rbitfld.long 0x04 0. "BUSY," "0,1" line.long 0x08 "RTC_INTERRUPTS_REG,The INTERRUPTS_REG is used to enable or disable RTC from generating interrupts" bitfld.long 0x08 4. "IT_ALARM2,Enable one interrupt when the alarm value is reached (TC ALARM2 registers) by the TC registers" "0,1" bitfld.long 0x08 3. "IT_ALARM,Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers" "0,1" bitfld.long 0x08 2. "IT_TIMER,Enable periodic interrupt" "0,1" bitfld.long 0x08 0.--1. "EVERY,Interrupt period" "0,1,2,3" line.long 0x0C "RTC_COMP_LSB_REG,COMP_LSB_REG is used to program the LSB value of the 32 kHz periods to be added to the 32 kHz counter every hour" hexmask.long.byte 0x0C 0.--7. 1. "RTC_COMP_LSB,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour" line.long 0x10 "RTC_COMP_MSB_REG,The COMP_MSB_REG is used to program the MSB value of the 32 kHz periods to be added to the 32 kHz counter every hour" hexmask.long.byte 0x10 0.--7. 1. "RTC_COMP_MSB,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour" line.long 0x14 "RTC_OSC_REG,The OSC_REG is used to program the oscillator resistance value. and to select and enable the clock source" bitfld.long 0x14 6. "K32CLK_EN,32khz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk and rtc_32k_clk_rtc_32k_clk" "0,1" bitfld.long 0x14 4. "OSC32K_GZ,Disable the oscillator and applies high impedance to the output" "0,1" bitfld.long 0x14 3. "K32CLK_SEL,32khz clock source select" "0,1" bitfld.long 0x14 2. "RES_SELECT,External feedback resistor selection" "0,1" bitfld.long 0x14 1. "SW2,inverter size adjustment" "0,1" newline bitfld.long 0x14 0. "SW1,inverter size adjustment" "0,1" group.long 0x60++0x3F line.long 0x00 "RTC_SCRATCH0_REG,Used to hold some required values for the RTC register" line.long 0x04 "RTC_SCRATCH1_REG,Used to hold some required values for the RTC register" line.long 0x08 "RTC_SCRATCH2_REG,Used to hold some required values for the RTC register" line.long 0x0C "RTC_KICK0_REG,The Kick0 register allows writing to unlock the kick0 data" line.long 0x10 "RTC_KICK1_REG,Kick1 data" line.long 0x14 "RTC_REVISION_REG," line.long 0x18 "RTC_SYSCONFIG_REG," bitfld.long 0x18 0.--1. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x1C "RTC_IRQWAKEEN," bitfld.long 0x1C 1. "ALARM_WAKEEN,Wakeup generation for event Alarm" "0,1" bitfld.long 0x1C 0. "TIMMER_WAKEEN,Wakeup generation for event Timer" "0,1" line.long 0x20 "RTC_ALARM2_SECONDS_REG,The ALARM2_SECONDS_REG is used to program the seconds value of the ALARM2 time" bitfld.long 0x20 4.--6. "ALARM2_SEC1,2nd digit of seconds Range is 0 to 5" "0,1,2,3,4,5,6,7" bitfld.long 0x20 0.--3. "ALARM2_SEC0,1st digit of seconds Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x24 "RTC_ALARM2_MINUTES_REG," bitfld.long 0x24 4.--6. "ALARM2_MIN1,2nd digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" bitfld.long 0x24 0.--3. "ALARM2_MIN0,1st digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "RTC_ALARM2_HOURS_REG," bitfld.long 0x28 7. "ALARM2_PM_NAM,Only used in PM_AM mode (otherwise 0)" "0,1" bitfld.long 0x28 4.--5. "ALARM2_HOUR1,2nd digit of hours Range is 0 to 2" "0,1,2,3" bitfld.long 0x28 0.--3. "ALARM2_HOUR0,1st digit of hours Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2C "RTC_ALARM2_DAYS_REG," bitfld.long 0x2C 4.--5. "ALARM_DAY1,2nd digit for days Range from 0 to 3" "0,1,2,3" bitfld.long 0x2C 0.--3. "ALARM_DAY0,1st digit for days Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x30 "RTC_ALARM2_MONTHS_REG," bitfld.long 0x30 4. "ALARM2_MONTH1,2nd digit of months Range from 0 to 1" "0,1" bitfld.long 0x30 0.--3. "ALARM2_MONTH0,1st digit of months Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x34 "RTC_ALARM2_YEARS_REG," bitfld.long 0x34 4.--7. "ALARM2_YEAR1,2nd digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x34 0.--3. "ALARM2_YEAR0,1st digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x38 "RTC_PMIC_REG," bitfld.long 0x38 19.--22. "EXT_WAKEUP_POL_HL,External wakeup inputs polarity enable for Active High and Active Low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 17.--18. "PWR_ENABLE_SM,Power State Machine state" "0,1,2,3" bitfld.long 0x38 16. "PWR_ENABLE_EN,pwr_enable enable" "0,1" bitfld.long 0x38 12.--15. "EXT_WAKEUP_STATUS,External wakeup status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 8.--11. "EXT_WAKEUP_DB_EN,External wakeup debounce enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x38 4.--7. "EXT_WAKEUP_POL,External wakeup inputs polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 0.--3. "EXT_WAKEUP_EN,Enable External wakeup inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x3C "RTC_RTL_DEBOUNCE_REG," hexmask.long.byte 0x3C 0.--7. 1. "DEBOUNCE_REG,Debounce time see for details" tree.end tree.end tree.open "SATA_Controller" tree "DWC_ahsata" base ad:0x4A140000 group.long 0x00++0x1B line.long 0x00 "SATA_CAP,Capabilities register: Basic capabilities of the SATA AHCI core" rbitfld.long 0x00 31. "S64A,Supports 64-bit addressing - 64bit" "S64A_0_r,S64A_1_r" rbitfld.long 0x00 30. "SNCQ,Supports NCQ (Native Command Queuing) Controller supports SATA NCQ by handling DMA setup FIS natively" "SNCQ_0_r,SNCQ_1_r" rbitfld.long 0x00 29. "SSNTF,Supports SNotification register Controller supports SATA_PxSNTF (SNotification) register and its associated functionality" "SSNTF_0_r,SSNTF_1_r" bitfld.long 0x00 28. "SMPS,Supports mechanical presence switch Support of a mechanical presence switch for hot plug operation depending on integration Writable once after power up read-only afterward - NO" "SMPS_0,SMPS_1" newline bitfld.long 0x00 27. "SSS,Supports staggered spin-up Controller can support this feature through SATA_PxCMD.SUD Writable once after power up read-only afterward - NO" "SSS_0,SSS_1" rbitfld.long 0x00 26. "SALP,Supports aggressive link power management - YES" "SALP_0_r,SALP_1_r" rbitfld.long 0x00 25. "SAL,Supports Activity LED - YES" "SAL_0_r,SAL_1_r" rbitfld.long 0x00 24. "SCLO,Supports command list override Supports the SATA_PxCMD.CLO bit functionality for enumeration of PM devices - YES" "SCLO_0_r,SCLO_1_r" newline rbitfld.long 0x00 20.--23. "ISS,Interface speed support Maximum speed the HBA can support - 6G" "?,ISS_1_r,ISS_2_r,ISS_3_r,?,?,?,?,?,?,?,?,?,?,?,?" rbitfld.long 0x00 19. "SNZO,Supports Non-zero DMA offsets - YES" "SNZO_0_r,SNZO_1_r" rbitfld.long 0x00 18. "SAM,Supports AHCI mode only SATA controller supports AHCI mode only and does not support legacy task file-based register interface" "SAM_0_r,SAM_1_r" rbitfld.long 0x00 17. "SPM,Supports PM (Port Multiplier) SATA controller supports command-based switching PM on any port" "SPM_0_r,SPM_1_r" newline rbitfld.long 0x00 16. "FBSS,FIS-based switching supported Support of PM FIS-based switching" "FBSS_0_r,FBSS_1_r" rbitfld.long 0x00 15. "PMD,PIO Multiple DRQ Support of multiple DRQ block data transfers for the PIO command protocol - YES" "PMD_0_r,PMD_1_r" rbitfld.long 0x00 14. "SSC,SLUMBER state capable Support of transitions to the interface SLUMBER power management state - YES" "SSC_0_r,SSC_1_r" rbitfld.long 0x00 13. "PSC,PARTIAL state capable Support of transitions to the interface PARTIAL power management state - YES" "PSC_0_r,PSC_1_r" newline rbitfld.long 0x00 8.--12. "NCS,Number of command slots: slots supported by the SATA controller minus" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,NCS_31_r" rbitfld.long 0x00 7. "CCCS,Command completion coalescing supported - YES" "CCCS_0_r,CCCS_1_r" rbitfld.long 0x00 6. "EMS,Enclosure management supported - YES" "EMS_0_r,EMS_1_r" rbitfld.long 0x00 5. "SXS,Supports external SATA - YES" "SXS_0_r,SXS_1_r" newline rbitfld.long 0x00 0.--4. "NP,Number of ports: ports supported by the SATA controller minus" "NP_0_r,NP_1_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "SATA_GHC,Global HBA control" rbitfld.long 0x04 31. "AE,AHCI enable Always set because SATA controller supports AHCI mode only as indicated by the SATA_CAP.SAM = 1" "0,1" bitfld.long 0x04 1. "IE,Interrupt enable Global enable of SATA controller interrupts" "IE_0,IE_1" bitfld.long 0x04 0. "HR,HBA reset Global reset control - noaction" "HR_0_r,HR_1_r" line.long 0x08 "SATA_IS,Interrupt status Indicates which port has a pending interrupt" bitfld.long 0x08 0. "IPS,Interrupt pending status" "0,1" line.long 0x0C "SATA_PI,Ports implemented Indicates which ports are exposed by the SATA controller and available for use" bitfld.long 0x0C 0. "PI,Ports implemented" "0,1" line.long 0x10 "SATA_VS,AHCI version supported: 1.3 WARNING: Controller complies fully with AHCI version 1.10 and also complies with AHCI version 1.3 except for FIS-based switching. which is not currently supported" hexmask.long.word 0x10 16.--31. 1. "MJR,Major Version Number: 1" hexmask.long.word 0x10 0.--15. 1. "MNR,Minor Version Number: 3.00" line.long 0x14 "SATA_CCC_CTL,CCC (Command Completion Coalescing) control Used to configure the CCC feature for the SATA controller Reset on global reset" hexmask.long.word 0x14 16.--31. 1. "TV,Time-out value" hexmask.long.byte 0x14 8.--15. 1. "CC,Command completions Number of command completions necessary to cause a CCC interrupt Loaded prior to enabling CCC becomes read-only when SATA_CCC_CTL.EN =" rbitfld.long 0x14 3.--7. "INT,Interrupt Number of the interrupt used by the CCC feature using the number of ports configured for the core When a CCC interrupt occurs the SATA_IS.IPS[INT] bit is set to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0. "EN,Enable CCC enable - dis" "EN_0,EN_1" line.long 0x18 "SATA_CCC_PORTS,CCC ports Specifies the ports that are coalesced as part of the CCC feature when .EN = 1 Reset on global reset" bitfld.long 0x18 0. "PRT,Ports Bit-significant field Set a bit to 1 to make the corresponding port part of the CCC feature" "0,1" rgroup.long 0x24++0x03 line.long 0x00 "SATA_CAP2,Extended capabilities" bitfld.long 0x00 2. "APST,Automatic PARTIAL to SLUMBER transitions - YES" "APST_0_r,APST_1_r" bitfld.long 0x00 1. "NVMP,NVMHCI present - YES" "NVMP_0_r,NVMP_1_r" bitfld.long 0x00 0. "BOH,BIOS/OS Handoff - YES" "BOH_0_r,BOH_1_r" rgroup.long 0xA0++0x13 line.long 0x00 "SATA_BISTAFR,Built-In. Self-Test (BIST) Activate FIS Register Reset on global reset or port reset" hexmask.long.byte 0x00 8.--15. 1. "NCP,Noncompliant pattern Least significant byte of the received BIST Activate FIS second DWORD (bits [7:0])" hexmask.long.byte 0x00 0.--7. 1. "PD,Pattern definition Pattern definition field of the received BIST Activate FIS - bits [23:16] of the first DWORD" line.long 0x04 "SATA_BISTCR,BIST control register Reset on global reset or port reset" bitfld.long 0x04 20. "FERLB,Far-end retimed loopback - noaction" "FERLB_0_r,FERLB_1_w" bitfld.long 0x04 18. "TXO,Transmit only - noaction" "TXO_0,TXO_1" bitfld.long 0x04 17. "CNTCLR,Counter clear Clears BIST error count registers - noaction" "CNTCLR_0_r,CNTCLR_1_w" bitfld.long 0x04 16. "NEALB,Near-end analog loopback This mode should be initiated in the PARTIAL or SLUMBER power state or with the device disconnected from the port PHY (link NOCOMM state)" "NEALB_0_w,NEALB_1_w" newline bitfld.long 0x04 15. "LLB,Lab Loopback Mode Masks out phy_sig_det from the OOB detector in BIST Loopback Mode" "0,1" bitfld.long 0x04 13. "ERRLOSSEN,Always keep this bit at default value" "0,1" bitfld.long 0x04 12. "SDFE,Signal detect feature enable Not affected by global reset or port reset - dis" "SDFE_0,SDFE_1" bitfld.long 0x04 10. "LLC_RPD,Link layer control repeat primitive drop In normal mode the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1)" "LLC_RPD_0,LLC_RPD_1" newline bitfld.long 0x04 9. "LLC_DESCRAM,Link layer control descrambler In normal mode the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1)" "LLC_DESCRAM_0,LLC_DESCRAM_1" bitfld.long 0x04 8. "LLC_SCRAM,Link layer control scrambler In normal mode the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1)" "LLC_SCRAM_0,LLC_SCRAM_1" bitfld.long 0x04 6. "ERREN,Error enable Allow or filter (disable) PHY internal errors outside the FIS boundary to set corresponding SATA_PxSERR bits - filter" "ERREN_0,ERREN_1" bitfld.long 0x04 5. "FLIP,Flip disparity Change disparity of the current test pattern to the opposite each time its state is changed by software" "0,1" newline bitfld.long 0x04 4. "PV,Pattern version Selects either short or long version of the SSOP HTDP LTDP LFSCP COMP pattern - short" "PV_0,PV_1" bitfld.long 0x04 0.--3. "PATTERN,Pattern Defines one of the listed SATA-compliant patterns for far-end retimed/ far-end analog/ near-end analog initiator modes or noncompliant patterns for transmit-only responder mode when initiated by software writing to the SATA_BISTCR.TXO.." "PATTERN_0,PATTERN_1,PATTERN_2,PATTERN_3,PATTERN_4,PATTERN_5,PATTERN_6,PATTERN_7,PATTERN_8,?,?,?,?,?,?,?" line.long 0x08 "SATA_BISTFCTR,BIST frame-information-structure CounT register Received BIST FIS count in the loopback initiator far-end retimed. far-end analog. and near-end analog modes" line.long 0x0C "SATA_BISTSR,BIST status register Errors detected in the received BIST FIS in the loopback initiator far-end retimed. far-end analog. and near-end analog modes Updated each time a new BIST FIS is received Reset on global reset. port reset (COMRESET). or.." hexmask.long.byte 0x0C 16.--23. 1. "BRSTERR,Burst error count" hexmask.long.word 0x0C 0.--15. 1. "FRAMERR,Frame error count" line.long 0x10 "SATA_BISTDECR,BIST double-word error count register Number of DWORD errors detected in the received BIST frame in the loopback initiator far-end retimed. far-end analog. and near-end analog modes Updated each time a new BIST frame is received. when the.." group.long 0xBC++0x03 line.long 0x00 "SATA_OOBR,OOB (Out Of Band Register) register Controls the link layer OOB detection counters" bitfld.long 0x00 31. "WE,WRITE_ENABLE - no" "WE_0,WE_1" hexmask.long.byte 0x00 24.--30. 1. "CWMIN,COMWAKE_MIN in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" hexmask.long.byte 0x00 16.--23. 1. "CWMAX,COMWAKE_MAX in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" hexmask.long.byte 0x00 8.--15. 1. "CIMIN,COMINIT_MIN in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" newline hexmask.long.byte 0x00 0.--7. 1. "CIMAX,COMINIT_MAX in OOB rx clock cycles Read-only when SATA_OOBR.WE=0" group.long 0xE0++0x03 line.long 0x00 "SATA_TIMER1MS,Timer 1 ms Configuration to generate the 1-ms tick for the CCC logic Must be initialized before using the CCC feature Reset on power up. not affected by global reset" hexmask.long.tbyte 0x00 0.--19. 1. "TIMV,OCP bus clock frequency in kHz (for example reset value is 100 000 = 100 MHz)" rgroup.long 0xE8++0x33 line.long 0x00 "SATA_GPARAM1R,Global parameters register 1 Hardware configuration of the DWC AHCI SATA core" bitfld.long 0x00 31. "ALIGN_M,RX data alignment - yes" "ALIGN_M_0_r,ALIGN_M_1_r" bitfld.long 0x00 30. "RX_BUFFER,RX data buffer implemented - yes" "RX_BUFFER_0_r,RX_BUFFER_1_r" bitfld.long 0x00 28.--29. "PHY_DATA,PHY data width (in 8- or 10-bit" "PHY_DATA_0_r,PHY_DATA_1_r,PHY_DATA_2_r,?" bitfld.long 0x00 27. "PHY_RST,PHY reset mode - hi" "PHY_RST_0_r,PHY_RST_1_r" newline bitfld.long 0x00 21.--26. "PHY_CTRL,PHY control width (in bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15.--20. "PHY_STAT,PHY status width (in bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14. "LATCH_M,Test mode lock-up latches - yes" "LATCH_M_0_r,LATCH_M_1_r" bitfld.long 0x00 13. "BIST_M,BIST loopback checking" "BIST_M_0_r,BIST_M_1_r" newline bitfld.long 0x00 11.--12. "PHY_TYPE,PHY interface type - snps" "PHY_TYPE_0_r,PHY_TYPE_1_r,?,?" bitfld.long 0x00 10. "RETURN_ERR,Error response on illegal access - yes" "RETURN_ERR_0_r,RETURN_ERR_1_r" bitfld.long 0x00 8.--9. "AHB_ENDIAN,Endianness of master and slave - conf" "AHB_ENDIAN_0_r,AHB_ENDIAN_1_r,AHB_ENDIAN_2_r,?" bitfld.long 0x00 7. "S_HADDR,Slave address bus width - 64bit" "S_HADDR_0_r,S_HADDR_1_r" newline bitfld.long 0x00 6. "M_HADDR,Master address bus width - 64bit" "M_HADDR_0_r,M_HADDR_1_r" bitfld.long 0x00 3.--5. "S_HDATA,Slave Data Bus Width" "S_HDATA_0_r,S_HDATA_1_r,S_HDATA_2_r,S_HDATA_3_r,?,?,?,?" bitfld.long 0x00 0.--2. "M_HDATA,Master Data Bus Width" "M_HDATA_0_r,M_HDATA_1_r,M_HDATA_2_r,M_HDATA_3_r,?,?,?,?" line.long 0x04 "SATA_GPARAM2R,Global parameters register 2 Hardware configuration of the DWC AHCI SATA core. continued" bitfld.long 0x04 14. "DEV_CP,Cold presence detection implemented in core - yes" "DEV_CP_0_r,DEV_CP_1_r" bitfld.long 0x04 13. "DEV_MP,Mechanical presence switch implemented in core - yes" "DEV_MP_0_r,DEV_MP_1_r" bitfld.long 0x04 12. "ENCODE_M,8b/10b Encoding/decoding implemented in core - yes" "ENCODE_M_0_r,ENCODE_M_1_r" bitfld.long 0x04 11. "RXOOB_CLK_M,RX OOB clocking mode: - sep" "RXOOB_CLK_M_0_r,RXOOB_CLK_M_1_r" newline bitfld.long 0x04 10. "RX_OOB_M,RX OOB mode: sequence generation implemented - yes" "RX_OOB_M_0_r,RX_OOB_M_1_r" bitfld.long 0x04 9. "TX_OOB_M,TX OOB mode: sequence generation implemented - yes" "TX_OOB_M_0_r,TX_OOB_M_1_r" hexmask.long.word 0x04 0.--8. 1. "RXOOB_CLK,RX OOB clock frequency in MHz" line.long 0x08 "SATA_PPARAMR,Port parameter register Hardware configuration of the DWC AHCI SATA core port selected by .PSEL" bitfld.long 0x08 11. "TX_MEM_M,TX FIFO memory mode: - sync" "TX_MEM_M_0_r,TX_MEM_M_1_r" bitfld.long 0x08 10. "TX_MEM_S,TX FIFO memory selection: - int" "TX_MEM_S_0_r,TX_MEM_S_1_r" bitfld.long 0x08 9. "RX_MEM_M,RX FIFO memory mode: - sync" "RX_MEM_M_0_r,RX_MEM_M_1_r" bitfld.long 0x08 8. "RX_MEM_S,RX FIFO memory selection: - int" "RX_MEM_S_0_r,RX_MEM_S_1_r" newline bitfld.long 0x08 4.--7. "TXFIFO_DEPTH,Tx FIFO Depth in dwords (log2) - 3" "?,?,?,TXFIFO_DEPTH_3_r,TXFIFO_DEPTH_4_r,TXFIFO_DEPTH_5_r,TXFIFO_DEPTH_6_r,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 0.--3. "RXFIFO_DEPTH,Rx FIFO Depth in dwords (log2) - 3" "?,?,?,?,RXFIFO_DEPTH_4_r,RXFIFO_DEPTH_5_r,RXFIFO_DEPTH_6_r,RXFIFO_DEPTH_7_r,?,?,?,?,?,?,?,?" line.long 0x0C "SATA_TESTR,Test register Puts the SATA controller slave interface in a test mode and selects a port for BIST operation" bitfld.long 0x0C 16.--18. "PSEL,Port select: Selects the port for BIST operation - 0" "PSEL_0,?,?,?,?,?,?,?" bitfld.long 0x0C 0. "TEST_IF,Test interface - default" "TEST_IF_0,TEST_IF_1" line.long 0x10 "SATA_VERSIONR,Version register" line.long 0x14 "SATA_IDR,ID register. containing the 32-bit Highlander (HL) revision" line.long 0x18 "SATA_PxCLB,Port command List base address 32-bit base physical address for the command list for this port" hexmask.long.tbyte 0x18 10.--31. 1. "CLB,Command list base address (bits 31:10)" hexmask.long.word 0x18 0.--9. 1. "ZERO,Always 0 as address is 1 KiB-aligned" line.long 0x1C "SATA_PxCLBU,Port Command List Base Upper address Upper half of the 64-bit base physical address for the command list for this Port" line.long 0x20 "SATA_PxFB,Port Frame-information-structure Base address 32-bit base physical address for received FISes for this port" hexmask.long.tbyte 0x20 8.--31. 1. "FB,FIS base address (bits 31:8)" hexmask.long.byte 0x20 0.--7. 1. "ZERO,Always 0 as address is 256-bytes aligned" line.long 0x24 "SATA_PxFBU,FIS Base Upper Address Upper half of the 64-bit base physical address for received FISes for this port" line.long 0x28 "SATA_PxIS,Port interrupt status Bits are set by internal conditions and cleared (when possible) by writing 1 to them" bitfld.long 0x28 31. "CPDS,Cold port detect status Set when the pX_cp_det input changes its state due to the insertion or removal of a device Valid only if the port supports cold presence detection as indicated by the SATA_PxCMD.CPD bit set to 1" "CPDS_0_r,CPDS_1_r" bitfld.long 0x28 30. "TFES,Task file error status Set whenever the SATA_PxTFD.STS register is updated by the device and the error bit (bit 0) is set" "TFES_0_r,TFES_1_r" bitfld.long 0x28 29. "HBFS,Host bus fatal error status Set when master (DMA) detects an ERROR response from the slave - noaction" "HBFS_0_r,HBFS_1_r" bitfld.long 0x28 28. "HBDS,Host bus data error status This bit is always cleared to 0" "HBDS_0_r,HBDS_1_r" newline bitfld.long 0x28 27. "IFS,Interface fatal error status This bit is set when any of the following conditions is detected: 1) SYNC escape is received from the device during H2D register or data FIS transmission. 2) One or more of the following errors are detected during data.." "IFS_0_r,IFS_1_r" bitfld.long 0x28 26. "INFS,Interface nonfatal error status Set when any of the following conditions is detected: 1) One or more of the following errors are detected during nondata FIS transfer: - 10b to 8b decode error (SATA_PxSERR.DIAG_B) - Protocol (SATA_PxSERR.ERR_P) -.." "INFS_0_r,INFS_1_r" bitfld.long 0x28 24. "OFS,Overflow status Set when command list overflow is detected during read or write operation when the software builds command table that has fever total bytes than the transaction given to the device" "OFS_0_r,OFS_1_r" bitfld.long 0x28 23. "IPMS,Incorrect PM status FIS received from a device in which the PM field did not match what was expected May be set during enumeration of devices on a PM due to the normal PM enumeration process Must be used only after enumeration is complete on the PM.." "IPMS_0_r,IPMS_1_r" newline rbitfld.long 0x28 22. "PRCS,PhyRdy change status Reflects the state of SATA_PxSERR.DIAG_N To clear this bit clear the SATA_PxSERR.DIAG_N bit to 0" "PRCS_0_r,PRCS_1_r" bitfld.long 0x28 7. "DMPS,Device mechanical presence status Set when the pX_mp_switch input changes its state as a result of a mechanical switch attached to this port opening or closing Valid only when SATA_CAP.SMPS and SATA_PxCMD.MPSP are set - noaction" "DMPS_0_r,DMPS_1_r" rbitfld.long 0x28 6. "PCS,Port connect change status This bit reflects the state of the SATA_PxSERR.DIAG_X bit" "PCS_0_r,PCS_1_r" bitfld.long 0x28 5. "DPS,Descriptor processed A PRD with the I bit set has transferred all of its data" "DPS_0_r,DPS_1_r" newline rbitfld.long 0x28 4. "UFS,Unknown FIS interrupt An unknown FIS was received and has been copied into system memory" "UFS_0_r,UFS_1_r" bitfld.long 0x28 3. "SDBS,Set device bits interrupt A Set Device Bits FIS is received with the I bit set and copied into system memory" "SDBS_0_r,SDBS_1_r" bitfld.long 0x28 2. "DSS,DMA setup FIS interrupt A DMA Setup FIS is received with the I bit set and copied into system memory" "DSS_0_r,DSS_1_r" bitfld.long 0x28 1. "PSS,PIO setup FIS interrupt A PIO Setup FIS is received with the I bit set copied into system memory and the data related to the FIS is transferred" "PSS_0_r,PSS_1_r" newline bitfld.long 0x28 0. "DHRS,Device to host register FIS interrupt A D2H register FIS is received with the I bit set and copied into system memory" "DHRS_0_r,DHRS_1_r" line.long 0x2C "SATA_PxIE,Port interrupt enable Enables and disables the reporting of the corresponding interrupt to system software When a bit is set (1). .IE = 1. and the corresponding interrupt condition in is active. then the SATA controller interrupt output is.." bitfld.long 0x2C 31. "CPDE,Cold port detect enable - dis" "CPDE_0,CPDE_1" bitfld.long 0x2C 30. "TFEE,Task file error enable - dis" "TFEE_0,TFEE_1" bitfld.long 0x2C 29. "HBFE,Host bus fatal error enable - dis" "HBFE_0,HBFE_1" bitfld.long 0x2C 28. "HBDE,Host bus data error enable - dis" "HBDE_0,HBDE_1" newline bitfld.long 0x2C 27. "IFE,Interface fatal error enable - dis" "IFE_0,IFE_1" bitfld.long 0x2C 26. "INFE,Interface non fatal error enable - dis" "INFE_0,INFE_1" bitfld.long 0x2C 24. "OFE,Overflow enable - dis" "OFE_0,OFE_1" bitfld.long 0x2C 23. "IPME,Incorrect PM enable - dis" "IPME_0,IPME_1" newline bitfld.long 0x2C 22. "PRCE,PhyRdy change enable - dis" "PRCE_0,PRCE_1" bitfld.long 0x2C 7. "DMPE,Device mechanical presence enable - dis" "DMPE_0,DMPE_1" bitfld.long 0x2C 6. "PCE,Port connect change enable - dis" "PCE_0,PCE_1" bitfld.long 0x2C 5. "DPE,Descriptor processed interrupt enable - dis" "DPE_0,DPE_1" newline bitfld.long 0x2C 4. "UFE,Unknown FIS interrupt enable - dis" "UFE_0,UFE_1" bitfld.long 0x2C 3. "SDBE,Set device bits interrupt enable - dis" "SDBE_0,SDBE_1" bitfld.long 0x2C 2. "DSE,DMA setup FIS interrupt enable - dis" "DSE_0,DSE_1" bitfld.long 0x2C 1. "PSE,PIO setup FIS interrupt enable - dis" "PSE_0,PSE_1" newline bitfld.long 0x2C 0. "DHRE,Device to host register FIS interrupt enable - dis" "DHRE_0,DHRE_1" line.long 0x30 "SATA_PxCMD,Port command" bitfld.long 0x30 28.--31. "ICC,Interface communication control Control of power management states of the interface If the link layer is in the L_IDLE state writes cause the port to request a transition to a given interface state" "ICC_0_r,ICC_1,ICC_2,?,?,?,ICC_6,?,?,?,?,?,?,?,?,?" bitfld.long 0x30 27. "ASP,Aggressive SLUMBER/PARTIAL - PARTIAL" "ASP_0,ASP_1" bitfld.long 0x30 26. "ALPE,Aggressive link power management enable - dis" "ALPE_0,ALPE_1" bitfld.long 0x30 25. "DLAE,Drive LED on ATAPI enable - dis" "DLAE_0,DLAE_1" newline bitfld.long 0x30 24. "ATAPI,Device is ATAPI Used by the port to determine whether or not to assert pX_act_led output when commands are active" "ATAPI_0,ATAPI_1" bitfld.long 0x30 23. "APSTE,Auto PARTIAL to SLUMBER transition enable - dis" "APSTE_0,APSTE_1" bitfld.long 0x30 22. "FBSCP,FIS-based Switching Capable Port May only be set to ?1? if CAP.SPM = CAP.FBSS = 1 (not the case)" "FBSCP_0,FBSCP_1" bitfld.long 0x30 21. "ESP,External SATA port Writable once after power up read-only afterward - int" "ESP_0,ESP_1" newline bitfld.long 0x30 20. "CPD,Cold presence detect Writable once after power up read-only afterward - no" "CPD_0,CPD_1" bitfld.long 0x30 19. "MPSP,Mechanical presence switch attached to port Writable once after power up read-only afterward - no" "MPSP_0,MPSP_1" bitfld.long 0x30 18. "HPCP,Hot plug capable port Writable once after power up read-only afterward - no" "HPCP_0,HPCP_1" bitfld.long 0x30 17. "PMA,PM attached Software is responsible for detecting the presence of a PM" "PMA_0,PMA_1" newline rbitfld.long 0x30 16. "CPS,Cold presence state Reports whether a device is currently detected on this port as indicated by the pX_cp_det input state (assuming SATA_PxCMD.CPD = 1)" "CPS_0_r,CPS_1_r" rbitfld.long 0x30 15. "CR,Command list running For details see the AHCI state-machine in Section 5.3.2 of the AHCI specification" "CR_0_r,CR_1_r" rbitfld.long 0x30 14. "FR,FIS receive running For details see Section 10.3.2 of the AHCI specification" "FR_0_r,FR_1_r" rbitfld.long 0x30 13. "MPSS,Mechanical presence switch state Reports the state of a mechanical presence switch attached to this port as indicated by the pX_mp_switch input state (assuming SATA_CAP.SMPS = 1 and SATA_PxCMD.MPSP = 1) Cleared to 0 when SATA_CAP.SMPS =" "MPSS_0_r,MPSS_1_r" newline rbitfld.long 0x30 8.--12. "CCS,Current command slot This field is valid when SATA_PxCMD.ST is set to 1 and is set to the command slot value of the command currently issued by the port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x30 4. "FRE,FIS receive enable Must not be set until SATA_PxFB / SATA_PxFBU is programmed with a valid pointer to the FIS receive area Base can be moved after clearing FRE and waiting for FR to clear to 0" "FRE_0,FRE_1" bitfld.long 0x30 3. "CLO,Command list override - noaction" "CLO_0_r,CLO_1_r" bitfld.long 0x30 2. "POD,Power-on device Writable if SATA_PxCMD.CPD = 1 (cold presence detection enabled) otherwise read-only -1" "POD_0,POD_1" newline bitfld.long 0x30 1. "SUD,Spin-up device Writable if SATA_CAP.SSS = 1 (staggered spin-up supported) else read-only 1" "SUD_0,SUD_1" bitfld.long 0x30 0. "ST,Start - newEnum1" "ST_0,ST_1" rgroup.long 0x120++0x1F line.long 0x00 "SATA_PxTFD,Port Task File Data: copies specific fields of the task file when FISes are received" hexmask.long.byte 0x00 8.--15. 1. "ERR,Err: Latest copy of the task file error register" bitfld.long 0x00 7. "STS_BSY,Status busy Latest copy of the 8-bit task file status register bit 7 STS_BSY = Interface is busy" "0,1" bitfld.long 0x00 4.--6. "STS_CS2,Status command-specific Latest copy of the 8-bit task file status register bits 6:4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "STS_DRQ,Status data request Latest copy of the 8-bit task file status register bit 3 STS_DRQ = Data transfer is requested" "0,1" newline bitfld.long 0x00 1.--2. "STS_CS,Status command-specific Latest copy of the 8-bit task file status register bits 2:1" "0,1,2,3" bitfld.long 0x00 0. "STS_ERR,Status error Latest copy of the 8-bit task file status register bit 0 STS_ERR = Error during the transfer" "0,1" line.long 0x04 "SATA_PxSIG,Port signature: Signature received from a device on the first D2H register FIS" hexmask.long.byte 0x04 24.--31. 1. "SIG_LBAH,Signature LBA high (cylinder high) register" hexmask.long.byte 0x04 16.--23. 1. "SIG_LBAM,Signature LBA mid (cylinder low) register" hexmask.long.byte 0x04 8.--15. 1. "SIG_LBAL,Signature LBA low (sector number) register" hexmask.long.byte 0x04 0.--7. 1. "SIG_SCR,Signature sector count register" line.long 0x08 "SATA_PxSSTS,Port SATA status Current state of the interface and host. updated continuously and asynchronously" bitfld.long 0x08 8.--11. "IPM,Interface power management: Current interface state - 2" "IPM_0_r,IPM_1_r,IPM_2_r,?,?,?,IPM_6_r,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 4.--7. "SPD,Current interface speed: Negotiated interface communication speed - 3" "SPD_0_r,SPD_1_r,SPD_2_r,SPD_3_r,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x08 0.--3. "DET,Device detection: Interface device detection and PHY state - 3" "DET_0_r,DET_1_r,?,DET_3_r,DET_4_r,?,?,?,?,?,?,?,?,?,?,?" line.long 0x0C "SATA_PxSCTL,Port SATA control Control of SATA interface capabilities" rbitfld.long 0x0C 16.--19. "PMP,PM port: This field is not used by the AHCI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x0C 12.--15. "SPM,Select power management: This field is not used by the AHCI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 8.--11. "IPM,Interface power management transitions allowed: Indicates which power states the HBA is allowed to transition to" "IPM_0,IPM_1,IPM_2,IPM_3,?,?,?,?,?,?,?,?,?,?,?,?" bitfld.long 0x0C 4.--7. "SPD,Speed allowed: Highest allowable speed of the interface The two MSBs are always 2'b00 (not writable) as for all unreserved field values" "SPD_0,SPD_1,SPD_2,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x0C 0.--3. "DET,Device detection initialization: Controls the HBA device detection and interface initialization" "DET_0,DET_1,?,?,DET_4,?,?,?,?,?,?,?,?,?,?,?" line.long 0x10 "SATA_PxSERR,Port SATA error Detected interface errors accumulated since the last time it cleared" bitfld.long 0x10 26. "DIAG_X," "0,1" bitfld.long 0x10 25. "DIAG_F,Unknown FIS type: One or more FISes were received by the transport layer with good CRC but had a type field that was not recognized/known and the length was = 64 bytes" "0,1" bitfld.long 0x10 24. "DIAG_T,Transport state transition error: Transport Layer protocol violation detected" "0,1" bitfld.long 0x10 23. "DIAG_S,Link sequence error: One or more Link state machine error conditions encountered including device doing SYNC escape during FIS transmission" "0,1" newline bitfld.long 0x10 22. "DIAG_H,Handshake error: One or more R-ERRp received in response to frame transmission" "0,1" bitfld.long 0x10 21. "DIAG_C,CRC error: One ore more CRC errors detected by the link layer during FIS reception" "0,1" rbitfld.long 0x10 20. "DIAG_D,Disparity error: Not used by AHCI always 0" "0,1" bitfld.long 0x10 19. "DIAG_B,10bit-to-8bit decode error: Errors detected by the 10b8b decoder" "0,1" newline bitfld.long 0x10 18. "DIAG_W,Comm wake: Comm wake signal detected by the PHY" "0,1" bitfld.long 0x10 17. "DIAG_I,PHY internal error: Internal error detected by the PHY" "0,1" bitfld.long 0x10 16. "DIAG_N,PhyRdy" "0,1" bitfld.long 0x10 11. "ERR_E,Internal error: One or more errors detected on the master (DMA) or the slave (MMR access) interfaces" "0,1" newline bitfld.long 0x10 10. "ERR_P,Protocol error: Any of the following conditions: - Transport state transition error (DIAG_T) - Link sequence error (DIAG_S) - RxFIFO overflow - Link bad end error (WTRM instead of EOF received)" "0,1" bitfld.long 0x10 9. "ERR_C,Nonrecovered persistent communication error: PHY Ready signal is negated due to loss of communication with the device or problems with the interface but not after transition from ACTIVE to PARTIAL or SLUMBER power management state" "0,1" bitfld.long 0x10 8. "ERR_T,Nonrecovered transient data integrity error: Any of the following conditions are set during data FIS transfer: - ERR_P (Protocol) - DIAG_C (CRC) - DIAG_H (Handshake) - ERR_C (PHY Ready negation)" "0,1" bitfld.long 0x10 1. "ERR_M,Recovered communication error: PHY Ready condition is detected after interface initialization but not after transition from PARTIAL or SLUMBER power management state to ACTIVE state" "0,1" newline bitfld.long 0x10 0. "ERR_I,Recovered data integrity error: Any of the following conditions are set during non-data FIS transfer: - ERR_P (Protocol) - DIAG_C (CRC) - DIAG_H (Handshake) - ERR_C (PHY Ready negation)" "0,1" line.long 0x14 "SATA_PxSACT,Port SATA active (SActive): Indicates which command slots contain commands" line.long 0x18 "SATA_PxCI,Port command issue: Indicates that a command is constructed and may be carried out" line.long 0x1C "SATA_PxSNTF,Port SATA notification: Used to determine if asynchronous notification events have occurred for directly connected devices and devices connected to a PM" hexmask.long.word 0x1C 0.--15. 1. "PMN,PM notify: Indicates whether a particular device with the corresponding PM port number issued a set device bits FIS to the SATA controller Port with the notification bit set: - PM Port 0h sets bit 0" group.long 0x170++0x03 line.long 0x00 "SATA_PxDMACR,Port DMA control register" bitfld.long 0x00 4.--7. "RXTS,Receive transaction size: DMA transaction size for receive operations (system bus write device read)" "RXTS_0,RXTS_1,RXTS_2,RXTS_3,RXTS_4,RXTS_5,RXTS_6,?,?,?,?,?,?,?,?,?" bitfld.long 0x00 0.--3. "TXTS,Transmit transaction size: DMA transaction size for transmit operations (system bus read device write)" "TXTS_0,TXTS_1,TXTS_2,TXTS_3,TXTS_4,TXTS_5,?,?,?,?,?,?,?,?,?,?" tree.end tree "SATAMAC_wrapper" base ad:0x4A141100 group.long 0x00++0x07 line.long 0x00 "SATA_SYSCONFIG,This register controls the idle and standby modes of Highlander 08 modules" bitfld.long 0x00 16. "OVERRIDE0,Override for clock stopping" "OVERRIDE0_0,OVERRIDE0_1" bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator-state management mode" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" line.long 0x04 "SATA_CDRLOCK,Programmable delay for CDR lock indication" hexmask.long.word 0x04 0.--11. 1. "CDR_LOCK_DELAY,CDR lock delay in parallel (10-bit) serdes interface clock cycles" tree.end tree.end tree.open "SATA_PHY_Subsystem" tree "DPLLCTRL_SATA" base ad:0x4A096800 rgroup.long 0x04++0x1F line.long 0x00 "PLL_STATUS,This register contains the status information" bitfld.long 0x00 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x00 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" bitfld.long 0x00 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" newline bitfld.long 0x00 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" bitfld.long 0x00 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x00 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" newline bitfld.long 0x00 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" bitfld.long 0x00 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x04 "PLL_GO,This register contains the GO bit" bitfld.long 0x04 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x08 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" hexmask.long.word 0x08 9.--20. 1. "PLL_REGM,M Divider for PLL" hexmask.long.byte 0x08 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x0C "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0C 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,?,?" bitfld.long 0x0C 1.--3. "PLL_SELFREQDCO,DCO frequency range selector for DPLL_SATA 0x2 Set if DCO frequency is between 500MHz and 1000MHz 0x4 Set if DCO frequency is between 1000MHz and 2000MHz Other values: Reserved" "PLL_SELFREQDCO_0,PLL_SELFREQDCO_1,PLL_SELFREQDCO_2,PLL_SELFREQDCO_3,PLL_SELFREQDCO_4,PLL_SELFREQDCO_5,PLL_SELFREQDCO_6,PLL_SELFREQDCO_7" bitfld.long 0x0C 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x10 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.byte 0x10 10.--17. 1. "PLL_SD,Sigma delta divider setting for DPLL_USB_OTG_SS based on the PLL lock configuration" line.long 0x14 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x14 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x14 0. "EN_SSC,Spread Spectrum Clocking enable - SSC_Off" "EN_SSC_0,EN_SSC_1" line.long 0x18 "PLL_SSC_CONFIGURATION2," bitfld.long 0x18 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x18 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider control for SSC" hexmask.long.tbyte 0x18 0.--19. 1. "DELTAM,DeltaM control for SSC" line.long 0x1C "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.tbyte 0x1C 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" tree.end tree "OCP2SCP3" base ad:0x4A090000 rgroup.long 0x00++0x03 line.long 0x00 "OCP2SCP_REVISION,IP Revision Identifier (X.Y.R)" bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,Function: Indicates a software compatible module family" bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. "MAJOR,ajor Revision This field changes when there is a major feature change" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. "MINOR,inor Revision This field changes when features are scaled up or down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x0B line.long 0x00 "OCP2SCP_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 3.--4. "IDLEMODE,- ForceIdle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software Reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,OCP interface clock gating control" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "OCP2SCP_SYSSTATUS,System Status register" bitfld.long 0x04 0. "RESETDONE,- Complete" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "OCP2SCP_TIMING,Interrupt Status Register (legacy) for first line of interrupt" bitfld.long 0x08 7.--9. "DIVISIONRATIO,Division Ration of the SCP clock in relation to OCP input clock" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "SYNC1,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--3. "SYNC2,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "SATA_PHY_RX" base ad:0x4A096000 group.long 0x0C++0x03 line.long 0x00 "SATAPHYRX_ANA_PROGRAMMABILITY_REG1,Some programmability for different analog circuits in the IP" hexmask.long.tbyte 0x00 8.--31. 1. "MEM_ANATESTMODE,Programmability for Analog circuits in the IP" bitfld.long 0x00 5.--6. "MEM_PLLDIV,This is a test mode" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "SATAPHYRX_TRIM_REG4,The IP requires some values to be remembered in EFUSE" bitfld.long 0x00 30.--31. "MEM_DLL_TRIM_SEL,Determines which of the 4 EFUSE registers EFUSE_dll_rateN_coarsetrim should be used as the trim code by the DLL" "0,1,2,3" group.long 0x24++0x07 line.long 0x00 "SATAPHYRX_DLL_REG1,This register is used to program DLL settings" bitfld.long 0x00 30.--31. "MEM_DLL_PHINT_RATE,Programs the DLL and the Phase Interpolator analog circuits to work with different clock frequencies" "0,1,2,3" line.long 0x04 "SATAPHYRX_DIGITAL_MODES_REG1,This register contains control bits which affect different circuits in digital section of the IP" bitfld.long 0x04 31. "MEM_INV_RXPN_PAIR,If '1' interchanges RXP and RXN effectively by inverting the received data samples" "0,1" bitfld.long 0x04 30. "MEM_OVRD_INV_RXPN_PAIR,Pin override control" "0,1" bitfld.long 0x04 27.--28. "MEM_HS_RATE,Determines the ratio of pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) frequency and the output data rate" "0,1,2,3" bitfld.long 0x04 26. "MEM_OVRD_HS_RATE,Pin override control" "0,1" newline bitfld.long 0x04 23. "MEM_CDR_FASTLOCK,'1' to reduce lock time of CDR (clock-data-recovery circuit)" "0,1" bitfld.long 0x04 21.--22. "MEM_CDR_LBW,CDR band-width control" "0,1,2,3" bitfld.long 0x04 19.--20. "MEM_CDR_STEPCNT,CDR 2nd order setting" "0,1,2,3" bitfld.long 0x04 16.--18. "MEM_CDR_STL,CDR settling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 13.--15. "MEM_CDR_THR,CDR 1st order threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12. "MEM_CDR_THR_MODE,CDR 1st order threshold" "0,1" bitfld.long 0x04 11. "MEM_CDR_2NDO_SDM_MODE,If '1' the 2nd Order CDR block uses a 1st order Sigma Delta Modulator to accomplish frequency offset If '0' a simple rate transformer is used for the same purpose" "0,1" group.long 0x38++0x03 line.long 0x00 "SATAPHYRX_EQUALIZER_REG1,The IP has an Equalizer (with analog and digital parts) which addresses Inter Symbol Interference (ISI)" hexmask.long.word 0x00 16.--31. 1. "MEM_EQLEV,Equalizer level control" bitfld.long 0x00 11.--15. "MEM_EQFTC,Equalizer zero freq control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7.--10. "MEM_EQCTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. "MEM_OVRD_EQLEV,Continuosly forces the Equalizer output with the eqlev[15:0]" "0,1" newline bitfld.long 0x00 1. "MEM_OVRD_EQFTC,Continuosly forces the Equalizer output with the eqftc[4:0]" "0,1" group.long 0x44++0x03 line.long 0x00 "SATAPHYRX_IO_AND_A2D_OVERRIDES_REG1,This register has controls for SATA PHY RX tunning" bitfld.long 0x00 9.--10. "MEM_CDR_LOS_SOURCE," "0,1,2,3" tree.end tree "SATA_PHY_TX" base ad:0x4A096400 group.long 0x0C++0x03 line.long 0x00 "SATAPHYTX_FUNC_CONFIG_REG,Functional Configuration registers" bitfld.long 0x00 31. "MEM_INVPAIR,Invert polarity of TXP/TXN" "0,1" group.long 0x2C++0x07 line.long 0x00 "SATAPHYTX_TEST_CONFIG_REG,Test related configuration registers" bitfld.long 0x00 30. "MEM_EN_LPBK,Loopback enable for test" "0,1" bitfld.long 0x00 29. "MEM_ENTXPATT,Enable Test pattern to input of the serializer instead of TD" "0,1" bitfld.long 0x00 26.--28. "MEM_TESTPATT,Select the LFSR mode to generate the required pattern" "0,1,2,3,4,5,6,7" line.long 0x04 "SATAPHYTX_PATTGEN_PRELOAD,Pattern generator (31 bit) LFSR Seed or preload value" hexmask.long 0x04 1.--31. 1. "MEM_PATTGEN_PRELOAD_VAL,Preload value to the LFSR pattern generator" tree.end tree.end tree.open "Spinlock" tree "Spinlock" base ad:0x4A0F6000 tree "REG_Bundle_0" repeat 16. (list 240. 241. 242. 243. 244. 245. 246. 247. 248. 249. 250. 251. 252. 253. 254. 255. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xBC0)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 224. 225. 226. 227. 228. 229. 230. 231. 232. 233. 234. 235. 236. 237. 238. 239. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xB80)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 208. 209. 210. 211. 212. 213. 214. 215. 216. 217. 218. 219. 220. 221. 222. 223. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xB40)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 192. 193. 194. 195. 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. 207. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xB00)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 176. 177. 178. 179. 180. 181. 182. 183. 184. 185. 186. 187. 188. 189. 190. 191. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xAC0)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA80)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 144. 145. 146. 147. 148. 149. 150. 151. 152. 153. 154. 155. 156. 157. 158. 159. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA40)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xA00)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x9C0)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x980)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x940)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x900)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x8C0)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x880)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x840)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x03 line.long 0x00 "SPINLOCK_LOCK_REG_i_$1,This register contains the state of one lock" bitfld.long 0x00 0. "TAKEN,Lock State - FREE" "TAKEN_0_w,TAKEN_1_w" repeat.end tree.end rgroup.long 0x00++0x03 line.long 0x00 "SPINLOCK_REVISION,This register contains the IP revision code" group.long 0x10++0x07 line.long 0x00 "SPINLOCK_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management (IDLE request/acknowledgement control)" "SIDLEMODE_0_r,SIDLEMODE_1_r,SIDLEMODE_2_r,SIDLEMODE_3_r" rbitfld.long 0x00 2. "ENWAKEUP,Asynchronous wakeup gereration" "ENWAKEUP_0_r,ENWAKEUP_1_r" bitfld.long 0x00 1. "SOFTRESET,Module software reset" "SOFTRESET_0_w,SOFTRESET_1_w" rbitfld.long 0x00 0. "AUTOGATING,Internal interface clock gating strategy" "AUTOGATING_0_r,AUTOGATING_1_r" line.long 0x04 "SPINLOCK_SYSTATUS,This register provides status information about this instance of the Spinlock module" hexmask.long.byte 0x04 24.--31. 1. "NUMLOCKS,Number of lock registers implemeted" bitfld.long 0x04 15. "IU7,In-Use flag 0 covering lock registers" "IU7_0_r,IU7_1_r" bitfld.long 0x04 14. "IU6,In-Use flag 0 covering lock registers" "IU6_0_r,IU6_1_r" bitfld.long 0x04 13. "IU5,In-Use flag 0 covering lock registers" "IU5_0_r,IU5_1_r" bitfld.long 0x04 12. "IU4,In-Use flag 0 covering lock registers" "IU4_0_r,IU4_1_r" newline bitfld.long 0x04 11. "IU3,In-Use flag 0 covering lock registers" "IU3_0_r,IU3_1_r" bitfld.long 0x04 10. "IU2,In-Use flag 0 covering lock registers" "IU2_0_r,IU2_1_r" bitfld.long 0x04 9. "IU1,In-Use flag 0 covering lock registers" "IU1_0_r,IU1_1_r" bitfld.long 0x04 8. "IU0,In-Use flag 0 covering lock registers" "IU0_0_r,IU0_1_r" bitfld.long 0x04 0. "RESETDONE,Reset done status" "RESETDONE_0_r,RESETDONE_1_r" tree.end tree.end tree.open "SuperSpeed_USB_DRD" repeat 2. (list 1. 2. )(list ad:0x4A084000 ad:0x4A085000 ) tree "USB2PHY$1" base $2 group.long 0x00++0x03 line.long 0x00 "USB2PHY_TERMINATION_CONTROL,Contains bits related to control of terminations in USB2PHY" bitfld.long 0x00 21. "MEM_USE_RTERM_RMX_REG,Override termination resistor trim code with MEM_RTERM_RMX bitfield value" "0,1" bitfld.long 0x00 15.--20. "MEM_RTERM_RMX,The value written to this field is used as termination resistor trim code if bit [21] MEM_USE_RTERM_RMX_REG is set to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 0.--5. "RTERM_RMX,Returns the current value of RTERM_RMX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x14++0x03 line.long 0x00 "USB2PHY_CHRG_DET,This is the charger detect register" bitfld.long 0x00 29. "MEM_USE_CHG_DET_REG,Use bits 28:24 and 18:17 from this register" "0,1" bitfld.long 0x00 28. "MEM_DIS_CHG_DET,When read returns current value of charger detect input" "0,1" bitfld.long 0x00 27. "MEM_SRC_ON_DM,When read returns current value of charger detect input" "0,1" bitfld.long 0x00 26. "MEM_SINK_ON_DP,When read returns current value of charger detect input" "0,1" newline bitfld.long 0x00 25. "MEM_CHG_DET_EXT_CTL,When read returns current value of charger detect input" "0,1" bitfld.long 0x00 24. "MEM_RESTART_CHG_DET,Restart the charger detection protocol when this bit is set from 0 to 1" "0,1" rbitfld.long 0x00 23. "CHG_DET_DONE,Charger detect protocol has completed" "0,1" rbitfld.long 0x00 22. "CHG_DETECTED,Reflects charger-enable (CE) output pin" "0,1" newline rbitfld.long 0x00 21. "DATA_DET,Output of the data detect comparator" "0,1" bitfld.long 0x00 18. "MEM_CHG_ISINK_EN,When read returns current value of charger detect input" "0,1" bitfld.long 0x00 17. "MEM_CHG_VSRC_EN,When read returns current value of charger detect input" "0,1" rbitfld.long 0x00 16. "COMP_DP,Comparator on the DP line value" "0,1" newline rbitfld.long 0x00 15. "COMP_DM,Comparator on the DM line value" "0,1" bitfld.long 0x00 0. "MEM_FOR_CE,Force output pin CE = 1 when this bit is set to 1" "0,1" group.long 0x30++0x03 line.long 0x00 "USB2PHY_GPIO,GPIO mode configurations and read-only info fields" bitfld.long 0x00 31. "MEM_USEGPIOMODEREG,When set to 1 use bits 30:24 from this register instead of primary inputs" "0,1" bitfld.long 0x00 30. "MEM_GPIOMODE,Overrides the GPIO MODE primary input" "0,1" bitfld.long 0x00 29. "MEM_DPGPIOGZ,Overrides the DP GPIO GZ primary input" "0,1" bitfld.long 0x00 28. "MEM_DMGPIOGZ,Overrides the DM GPIO GZ primary input" "0,1" newline bitfld.long 0x00 27. "MEM_DPGPIOA,Overrides the DP GPIO A primary input" "0,1" bitfld.long 0x00 26. "MEM_DMGPIOA,Overrides the DM GPIO A primary input" "0,1" rbitfld.long 0x00 25. "DPGPIOY,DP GPIO Y output value status" "0,1" rbitfld.long 0x00 24. "DMGPIOY,DM GPIO Y output value status" "0,1" newline bitfld.long 0x00 19. "MEM_DMGPIOPIPD,GPIO mode DM pulldown enabled" "0,1" bitfld.long 0x00 18. "MEM_DPGPIOPIPD,GPIO mode DP pulldown enabled" "0,1" group.long 0x48++0x03 line.long 0x00 "USB2PHY_AD_INTERFACE_REG3,AD interface register 3" hexmask.long.byte 0x00 10.--17. 1. "MEM_SPARE_IN_LDO,This bit field can be used to compensate for external Common Mode Filter (CMF) or series switch resistance" group.long 0x50++0x03 line.long 0x00 "USB2PHY_ANA_CONFIG2,Used to configure and debug the analog blocks" bitfld.long 0x00 15.--19. "MEM_FSRX_TEST,Following are the bit setting to improve HS eye diagram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x78++0x03 line.long 0x00 "USB2PHY_CEGPIO_REG,This register contains bits for configuring functionality for CE pad" bitfld.long 0x00 0.--5. "MEM_CE_SELECT,CE pin output mode: CE IS NOT PINNED OUT IN THIS DEVICE! - Charger detected" "MEM_CE_SELECT_0,MEM_CE_SELECT_1,MEM_CE_SELECT_2,MEM_CE_SELECT_3,MEM_CE_SELECT_4,MEM_CE_SELECT_5,MEM_CE_SELECT_6,MEM_CE_SELECT_7,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" tree.end repeat.end repeat 4. (list 1. 2. 3. 4. )(list ad:0x48890000 ad:0x488D0000 ad:0x48910000 ad:0x48950000 ) tree "USB_DWC$1" base $2 repeat 15. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. ) tree "Channel_$1" group.long 0x4C0++0x03 line.long 0x00 "USB_DB_j_16,Doorbell (xHCI)" hexmask.long.word 0x00 16.--31. 1. "DB_STREAM_ID,See xHCI specification" hexmask.long.byte 0x00 0.--7. 1. "DB_TARGET,See xHCI specification" group.long 0xC908++0x03 line.long 0x00 "USB_DEPCMDPAR0_i_16,Device physical endpoint-n command parameter 0 Must be programmed before issuing the command" group.long 0xC904++0x03 line.long 0x00 "USB_DEPCMDPAR1_i_16,Device physical endpoint-n command parameter 1 Must be programmed before issuing the command. if required by the command" group.long 0xC900++0x03 line.long 0x00 "USB_DEPCMDPAR2_i_16,Device physical endpoint-n command parameter 2" group.long 0xC90C++0x03 line.long 0x00 "USB_DEPCMD_i_16,Device physical endpoint-n command" hexmask.long.word 0x00 16.--31. 1. "CMDPARAM_EVTPARAM,Read: Event parameters (see )" bitfld.long 0x00 12.--15. "CMDSTATUS,Command Completion Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. "HIPRI_FORCERM,HighPriority/ForceRM" "HIPRI_FORCERM_0_w,HIPRI_FORCERM_1_w" bitfld.long 0x00 10. "CMDACT,Command Active" "CMDACT_0_r,CMDACT_1_r" newline bitfld.long 0x00 8. "CMDIOC,Command Interrupt On Complete" "CMDIOC_0_w,CMDIOC_1_w" bitfld.long 0x00 0.--3. "CMDTYP,Command Type" "?,CMDTYP_1_w,CMDTYP_2_w,CMDTYP_3_w,CMDTYP_4_w,CMDTYP_5_w,CMDTYP_6_w,CMDTYP_7_w,CMDTYP_8_w,CMDTYP_9_w,?,?,?,?,?,?" tree.end repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. ) tree "Channel_$1" group.long 0x480++0x03 line.long 0x00 "USB_DB_j_0,Doorbell (xHCI)" hexmask.long.word 0x00 16.--31. 1. "DB_STREAM_ID,See xHCI specification" hexmask.long.byte 0x00 0.--7. 1. "DB_TARGET,See xHCI specification" group.long 0xC808++0x03 line.long 0x00 "USB_DEPCMDPAR0_i_0,Device physical endpoint-n command parameter 0 Must be programmed before issuing the command" group.long 0xC804++0x03 line.long 0x00 "USB_DEPCMDPAR1_i_0,Device physical endpoint-n command parameter 1 Must be programmed before issuing the command. if required by the command" group.long 0xC800++0x03 line.long 0x00 "USB_DEPCMDPAR2_i_0,Device physical endpoint-n command parameter 2" group.long 0xC80C++0x03 line.long 0x00 "USB_DEPCMD_i_0,Device physical endpoint-n command" hexmask.long.word 0x00 16.--31. 1. "CMDPARAM_EVTPARAM,Read: Event parameters (see )" bitfld.long 0x00 12.--15. "CMDSTATUS,Command Completion Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. "HIPRI_FORCERM,HighPriority/ForceRM" "HIPRI_FORCERM_0_w,HIPRI_FORCERM_1_w" bitfld.long 0x00 10. "CMDACT,Command Active" "CMDACT_0_r,CMDACT_1_r" newline bitfld.long 0x00 8. "CMDIOC,Command Interrupt On Complete" "CMDIOC_0_w,CMDIOC_1_w" bitfld.long 0x00 0.--3. "CMDTYP,Command Type" "?,CMDTYP_1_w,CMDTYP_2_w,CMDTYP_3_w,CMDTYP_4_w,CMDTYP_5_w,CMDTYP_6_w,CMDTYP_7_w,CMDTYP_8_w,CMDTYP_9_w,?,?,?,?,?,?" tree.end repeat.end tree "Channel_31" group.long 0xC9F8++0x03 line.long 0x00 "USB_DEPCMDPAR0_i_31,Device physical endpoint-n command parameter 0 Must be programmed before issuing the command" group.long 0xC9F4++0x03 line.long 0x00 "USB_DEPCMDPAR1_i_31,Device physical endpoint-n command parameter 1 Must be programmed before issuing the command. if required by the command" group.long 0xC9F0++0x03 line.long 0x00 "USB_DEPCMDPAR2_i_31,Device physical endpoint-n command parameter 2" group.long 0xC9FC++0x03 line.long 0x00 "USB_DEPCMD_i_31,Device physical endpoint-n command" hexmask.long.word 0x00 16.--31. 1. "CMDPARAM_EVTPARAM,Read: Event parameters (see )" bitfld.long 0x00 12.--15. "CMDSTATUS,Command Completion Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. "HIPRI_FORCERM,HighPriority/ForceRM" "HIPRI_FORCERM_0_w,HIPRI_FORCERM_1_w" bitfld.long 0x00 10. "CMDACT,Command Active" "CMDACT_0_r,CMDACT_1_r" newline bitfld.long 0x00 8. "CMDIOC,Command Interrupt On Complete" "CMDIOC_0_w,CMDIOC_1_w" bitfld.long 0x00 0.--3. "CMDTYP,Command Type" "?,CMDTYP_1_w,CMDTYP_2_w,CMDTYP_3_w,CMDTYP_4_w,CMDTYP_5_w,CMDTYP_6_w,CMDTYP_7_w,CMDTYP_8_w,CMDTYP_9_w,?,?,?,?,?,?" group.long 0x57C++0x03 line.long 0x00 "USB_DB_j_63,Doorbell (xHCI)" hexmask.long.word 0x00 16.--31. 1. "DB_STREAM_ID,See xHCI specification" hexmask.long.byte 0x00 0.--7. 1. "DB_TARGET,See xHCI specification" repeat 16. (list 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x53C)++0x03 line.long 0x00 "USB_DB_j_$1,Doorbell (xHCI)" hexmask.long.word 0x00 16.--31. 1. "DB_STREAM_ID,See xHCI specification" hexmask.long.byte 0x00 0.--7. 1. "DB_TARGET,See xHCI specification" repeat.end repeat 16. (list 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x4FC)++0x03 line.long 0x00 "USB_DB_j_$1,Doorbell (xHCI)" hexmask.long.word 0x00 16.--31. 1. "DB_STREAM_ID,See xHCI specification" hexmask.long.byte 0x00 0.--7. 1. "DB_TARGET,See xHCI specification" repeat.end tree.end rgroup.long 0x00++0x03 line.long 0x00 "USB_CAPLENGTH,Capability registers length + host controller interface (HCI) version number" hexmask.long.word 0x00 16.--31. 1. "HCIVERSION,Host Controller Interface Version (xHCI) in BCD" newline hexmask.long.byte 0x00 0.--7. 1. "CAPLENGTH,Capability Register Length: length of the xHCI Capabilities registers bank in bytes; also the offset of the xHCI Operational registers bank (starting withUSB_USBCMD) with respect to xHCI base (i.e. the current register)" group.long 0x58++0x03 line.long 0x00 "USB_CONFIG,Configure (xHCI)" hexmask.long.byte 0x00 0.--7. 1. "MAXSLOTSEN,See xHCI specification" group.long 0x3C++0x03 line.long 0x00 "USB_CRCR_HI,Command ring control register. upper half (xHCI)" group.long 0x38++0x03 line.long 0x00 "USB_CRCR_LO,Command ring control register. lower half (xHCI)" hexmask.long 0x00 6.--31. 1. "CMD_RING_PNTR,See xHCI specification" newline bitfld.long 0x00 3. "CRR,See xHCI specification" "0,1" newline bitfld.long 0x00 2. "CA,See xHCI specification" "0,1" newline bitfld.long 0x00 1. "CS,See xHCI specification" "0,1" newline bitfld.long 0x00 0. "RCS,See xHCI specification" "0,1" group.long 0xC720++0x03 line.long 0x00 "USB_DALEPENA,Device active USB endpoint enable" bitfld.long 0x00 31. "USBACTEP15_IN,USB Activate Endpoint 15 IN" "0,1" newline bitfld.long 0x00 30. "USBACTEP15_OUT,USB Activate Endpoint 15 OUT" "0,1" newline bitfld.long 0x00 29. "USBACTEP14_IN,USB Activate Endpoint 14 IN" "0,1" newline bitfld.long 0x00 28. "USBACTEP14_OUT,USB Activate Endpoint 14 OUT" "0,1" newline bitfld.long 0x00 27. "USBACTEP13_IN,USB Activate Endpoint 13 IN" "0,1" newline bitfld.long 0x00 26. "USBACTEP13_OUT,USB Activate Endpoint 13 OUT" "0,1" newline bitfld.long 0x00 25. "USBACTEP12_IN,USB Activate Endpoint 12 IN" "0,1" newline bitfld.long 0x00 24. "USBACTEP12_OUT,USB Activate Endpoint 12 OUT" "0,1" newline bitfld.long 0x00 23. "USBACTEP11_IN,USB Activate Endpoint 11 IN" "0,1" newline bitfld.long 0x00 22. "USBACTEP11_OUT,USB Activate Endpoint 11 OUT" "0,1" newline bitfld.long 0x00 21. "USBACTEP10_IN,USB Activate Endpoint 10 IN" "0,1" newline bitfld.long 0x00 20. "USBACTEP10_OUT,USB Activate Endpoint 10 OUT" "0,1" newline bitfld.long 0x00 19. "USBACTEP9_IN,USB Activate Endpoint 9 IN" "0,1" newline bitfld.long 0x00 18. "USBACTEP9_OUT,USB Activate Endpoint 9 OUT" "0,1" newline bitfld.long 0x00 17. "USBACTEP8_IN,USB Activate Endpoint 8 IN" "0,1" newline bitfld.long 0x00 16. "USBACTEP8_OUT,USB Activate Endpoint 8 OUT" "0,1" newline bitfld.long 0x00 15. "USBACTEP7_IN,USB Activate Endpoint 7 IN" "0,1" newline bitfld.long 0x00 14. "USBACTEP7_OUT,USB Activate Endpoint 7 OUT" "0,1" newline bitfld.long 0x00 13. "USBACTEP6_IN,USB Activate Endpoint 6 IN" "0,1" newline bitfld.long 0x00 12. "USBACTEP6_OUT,USB Activate Endpoint 6 OUT" "0,1" newline bitfld.long 0x00 11. "USBACTEP5_IN,USB Activate Endpoint 5 IN" "0,1" newline bitfld.long 0x00 10. "USBACTEP5_OUT,USB Activate Endpoint 5 OUT" "0,1" newline bitfld.long 0x00 9. "USBACTEP4_IN,USB Activate Endpoint 4 IN" "0,1" newline bitfld.long 0x00 8. "USBACTEP4_OUT,USB Activate Endpoint 4 OUT" "0,1" newline bitfld.long 0x00 7. "USBACTEP3_IN,USB Activate Endpoint 3 IN" "0,1" newline bitfld.long 0x00 6. "USBACTEP3_OUT,USB Activate Endpoint 3 OUT" "0,1" newline bitfld.long 0x00 5. "USBACTEP2_IN,USB Activate Endpoint 2 IN" "0,1" newline bitfld.long 0x00 4. "USBACTEP2_OUT,USB Activate Endpoint 2 OUT" "0,1" newline bitfld.long 0x00 3. "USBACTEP1_IN,USB Activate Endpoint 1 IN" "0,1" newline bitfld.long 0x00 2. "USBACTEP1_OUT,USB Activate Endpoint 1 OUT" "0,1" newline bitfld.long 0x00 1. "USBACTEP0_IN,USB Activate Endpoint 0 IN (control)" "0,1" newline bitfld.long 0x00 0. "USBACTEP0_OUT,USB Activate Endpoint 0 OUT (control)" "0,1" rgroup.long 0x14++0x03 line.long 0x00 "USB_DBOFF,Doorbell offset (xHCI): Byte offset of the doorbell register array (. with respect to the xHCI base (that is. register)" hexmask.long 0x00 2.--31. 1. "DOORBELL_ARRAY_OFFSET,Byte address offset MSBs" newline bitfld.long 0x00 0.--1. "ZERO,Byte address offset LSBs always 0 (offset is 32-bit = 4-byte aligned)" "0,1,2,3" group.long 0x54++0x03 line.long 0x00 "USB_DCBAAP_HI,Device context base address array pointer. upper half (xHCI)" group.long 0x50++0x03 line.long 0x00 "USB_DCBAAP_LO,Device context base address array pointer. lower half (xHCI)" hexmask.long 0x00 6.--31. 1. "DEVICE_CONTEXT_BAAP,See xHCI specification" group.long 0xC700++0x0B line.long 0x00 "USB_DCFG,Device configuration: Configures the core in device mode after power-on or after certain control commands or enumeration" bitfld.long 0x00 23. "IGNORESTREAMPP,Ignore Packet-Pending for Stream management" "IGNORESTREAMPP_0,IGNORESTREAMPP_1" newline bitfld.long 0x00 22. "LPMCAP,Link Power Management (LPM) Capability" "LPMCAP_0,LPMCAP_1" newline bitfld.long 0x00 17.--21. "NUMP,Number of Receive Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 12.--16. "INTRNUM,Interrupt Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--11. "PERFRINT,Periodic Frame Interrupt" "PERFRINT_0,PERFRINT_1,PERFRINT_2,PERFRINT_3" newline hexmask.long.byte 0x00 3.--9. 1. "DEVADDR,Device Address" newline bitfld.long 0x00 0.--2. "DEVSPD,Device Speed: USB speed at which the core should connect" "DEVSPD_0,DEVSPD_1,DEVSPD_2,DEVSPD_3,DEVSPD_4,?,?,?" line.long 0x04 "USB_DCTL,Device control" bitfld.long 0x04 31. "RUNSTOP,Run/Stop - stop" "RUNSTOP_0,RUNSTOP_1" newline bitfld.long 0x04 30. "CSFTRST,Core Soft Reset" "CSFTRST_0_r,CSFTRST_1_r" newline bitfld.long 0x04 28. "HIRDTHRES_4,Host Initiated Resume Duration (HIRD) Threshold MSbit: See HIRDTHRES_TIME" "0,1" newline bitfld.long 0x04 24.--27. "HIRDTHRES_TIME,Host Initiated Resume Duration (HIRD) Threshold LSBits = timeout value" "HIRDTHRES_TIME_0,HIRDTHRES_TIME_1,HIRDTHRES_TIME_2,HIRDTHRES_TIME_3,HIRDTHRES_TIME_4,HIRDTHRES_TIME_5,HIRDTHRES_TIME_6,HIRDTHRES_TIME_7,HIRDTHRES_TIME_8,HIRDTHRES_TIME_9,HIRDTHRES_TIME_10,HIRDTHRES_TIME_11,HIRDTHRES_TIME_12,?,?,?" newline bitfld.long 0x04 23. "APPL1RES,LPM Response Programmed by Application: Handshake response made to LPM token" "APPL1RES_0,APPL1RES_1" newline bitfld.long 0x04 19. "KEEPCONNECT,Used for Save-and-Restore operation" "KEEPCONNECT_0,KEEPCONNECT_1" newline bitfld.long 0x04 18. "L1HIBERNATIONEN,DO NOT USE SAR NOT IMPLEMENTED" "0,1" newline bitfld.long 0x04 17. "CRS,Controller Restore State" "CRS_0_w,CRS_1_w" newline bitfld.long 0x04 16. "CSS,Controller Save State" "CSS_0_w,CSS_1_w" newline bitfld.long 0x04 12. "INITU2ENA,Initiate U2 Enable" "INITU2ENA_0,INITU2ENA_1" newline bitfld.long 0x04 11. "ACCEPTU2ENA,Accept U2 Enable" "ACCEPTU2ENA_0,ACCEPTU2ENA_1" newline bitfld.long 0x04 10. "INITU1ENA,Initiate U1 Enable" "INITU1ENA_0,INITU1ENA_1" newline bitfld.long 0x04 9. "ACCEPTU1ENA,Accept U1 Enable" "ACCEPTU1ENA_0,ACCEPTU1ENA_1" newline bitfld.long 0x04 5.--8. "ULSTCHNGREQ,USB/Link State Change Request" "ULSTCHNGREQ_0,?,?,?,ULSTCHNGREQ_4,ULSTCHNGREQ_5,ULSTCHNGREQ_6,?,ULSTCHNGREQ_8,?,ULSTCHNGREQ_10,ULSTCHNGREQ_11,?,?,?,?" newline bitfld.long 0x04 1.--4. "TSTCTL,Test Control - 1" "TSTCTL_0,TSTCTL_1,TSTCTL_2,TSTCTL_3,TSTCTL_4,TSTCTL_5,?,?,?,?,?,?,?,?,?,?" line.long 0x08 "USB_DEVTEN,Device event enable: Enables the generation of device-specific events (see USB_DEVT)" bitfld.long 0x08 13. "INACTTIMEOUTRCVEDEN,U2 Inactive Timeout Received Event Enable" "0,1" newline bitfld.long 0x08 12. "VNDRDEVTSTRCVEDEN,Vendor Device Test Received event Enable" "0,1" newline bitfld.long 0x08 11. "EVNTOVERFLOWEN,Event Overflow event Enable" "0,1" newline bitfld.long 0x08 10. "CMDCMPLTEN,Command Complete event Enable" "0,1" newline bitfld.long 0x08 9. "ERRTICERREN,Erratic Error event Enable" "0,1" newline bitfld.long 0x08 7. "SOFEN,Start of (micro)Frame event Enable" "0,1" newline bitfld.long 0x08 6. "EOPFEN,End of Periodic Frame event Enable" "0,1" newline bitfld.long 0x08 5. "HIBERNATIONREQEVTEN,Hibernation Request Event Enable" "0,1" newline bitfld.long 0x08 4. "WKUPEVTEN,Resume/Remote Wakeup Detected Event Enable" "0,1" newline bitfld.long 0x08 3. "ULSTCNGEN,USB/Link State Change event Enable" "0,1" newline bitfld.long 0x08 2. "CONNECTDONEEN,Connection Done event Enable" "0,1" newline bitfld.long 0x08 1. "USBRSTEN,USB Reset Enable" "0,1" newline bitfld.long 0x08 0. "DISCONNEVTEN,Disconnct Event Enable" "0,1" group.long 0xC714++0x03 line.long 0x00 "USB_DGCMD,Device generic command: Generic command interface to send link management packets and notifications" rbitfld.long 0x00 15. "CMDSTATUS,Command Status" "CMDSTATUS_0_r,CMDSTATUS_1_r" newline bitfld.long 0x00 10. "CMDACT,Command active" "CMDACT_0_r,CMDACT_1_r" newline bitfld.long 0x00 8. "CMDIOC,Command Interrupt On Complete" "?,CMDIOC_1_w" newline hexmask.long.byte 0x00 0.--7. 1. "CMDTYP,Command Type" group.long 0xC710++0x03 line.long 0x00 "USB_DGCMDPAR,Device generic command parameter: To be programmed before or along with the device command itself" group.long 0x34++0x03 line.long 0x00 "USB_DNCTRL,Device notification control register (xHCI)" bitfld.long 0x00 15. "N15,See xHCI specification" "0,1" newline bitfld.long 0x00 14. "N14,See xHCI specification" "0,1" newline bitfld.long 0x00 13. "N13,See xHCI specification" "0,1" newline bitfld.long 0x00 12. "N12,See xHCI specification" "0,1" newline bitfld.long 0x00 11. "N11,See xHCI specification" "0,1" newline bitfld.long 0x00 10. "N10,See xHCI specification" "0,1" newline bitfld.long 0x00 9. "N9,See xHCI specification" "0,1" newline bitfld.long 0x00 8. "N8,See xHCI specification" "0,1" newline bitfld.long 0x00 7. "N7,See xHCI specification" "0,1" newline bitfld.long 0x00 6. "N6,See xHCI specification" "0,1" newline bitfld.long 0x00 5. "N5,See xHCI specification" "0,1" newline bitfld.long 0x00 4. "N4,See xHCI specification" "0,1" newline bitfld.long 0x00 3. "N3,See xHCI specification" "0,1" newline bitfld.long 0x00 2. "N2,See xHCI specification" "0,1" newline bitfld.long 0x00 1. "N1,See xHCI specification" "0,1" newline bitfld.long 0x00 0. "N0,See xHCI specification" "0,1" rgroup.long 0xC70C++0x03 line.long 0x00 "USB_DSTS,Device status" bitfld.long 0x00 29. "DCNRD,Device Controller Not Ready - wait" "DCNRD_0_r,DCNRD_1_r" newline bitfld.long 0x00 28. "SRE,Save/Restore Error" "0,1" newline bitfld.long 0x00 25. "RSS,Restore State Status triggered by writing 1 to RSS - restoring" "RSS_0_r,RSS_1_r" newline bitfld.long 0x00 24. "SSS,Save State Status triggered by writing 1 to SSS - saving" "SSS_0_r,SSS_1_r" newline bitfld.long 0x00 23. "COREIDLE,Core Idle status" "COREIDLE_0_r,COREIDLE_1_r" newline bitfld.long 0x00 22. "DEVCTRLHLT,Device Controller Halted" "0,1" newline bitfld.long 0x00 18.--21. "USBLNKST,USB/Link State" "USBLNKST_0_r,USBLNKST_1_r,USBLNKST_2_r,USBLNKST_3_r,USBLNKST_4_r,USBLNKST_5_r,USBLNKST_6_r,USBLNKST_7_r,USBLNKST_8_r,USBLNKST_9_r,USBLNKST_10_r,USBLNKST_11_r,?,?,USBLNKST_14_r,USBLNKST_15_r" newline bitfld.long 0x00 17. "RXFIFOEMPTY,Rx FIFO Empty - empty" "RXFIFOEMPTY_0_r,RXFIFOEMPTY_1_r" newline hexmask.long.word 0x00 3.--16. 1. "SOFFN,received Start Of Frame's Frame Number" newline bitfld.long 0x00 0.--2. "CONNECTSPD,Connection Speed" "CONNECTSPD_0_r,CONNECTSPD_1_r,CONNECTSPD_2_r,CONNECTSPD_3_r,CONNECTSPD_4_r,?,?,?" group.long 0x47C++0x03 line.long 0x00 "USB_ERDP_HI,Event ring dequeue pointer. upper half (xHCI)" group.long 0x478++0x03 line.long 0x00 "USB_ERDP_LO,Event ring dequeue pointer. lower half (xHCI)" hexmask.long 0x00 4.--31. 1. "ERD_PNTR,See xHCI specification" newline bitfld.long 0x00 3. "EHB,See xHCI specification" "0,1" newline bitfld.long 0x00 0.--2. "DESI,See xHCI specification" "0,1,2,3,4,5,6,7" group.long 0x474++0x03 line.long 0x00 "USB_ERSTBA_HI,Event ring segment table base address. upper half (xHCI)" group.long 0x470++0x03 line.long 0x00 "USB_ERSTBA_LO,Event ring segment table base address. lower half (xHCI)" hexmask.long 0x00 6.--31. 1. "ERS_TABLE_BAR,See xHCI specification" group.long 0x468++0x03 line.long 0x00 "USB_ERSTSZ,Event ring segment table size (xHCI)" hexmask.long.word 0x00 0.--15. 1. "ERS_TABLE_SIZE,See xHCI specification" rgroup.long 0xC134++0x03 line.long 0x00 "USB_GBUSERRADDRHI,Global Bus Error (non-precise) Address. MSbits: Base address of the first system bus DMA transfer that got a bus error" rgroup.long 0xC130++0x03 line.long 0x00 "USB_GBUSERRADDRLO,Global Bus Error (non-precise) Address. LSbits: Base address of the first system bus DMA transfer that got a bus error" group.long 0xC110++0x03 line.long 0x00 "USB_GCTL,Global control register" hexmask.long.word 0x00 19.--31. 1. "PWRDNSCALE,Power Down Scale: In P3 state PIPE clock stops and is replaced internally by the suspend clock to create a 16kHz reference" newline bitfld.long 0x00 18. "MASTERFILTBYPASS,Master Filter Bypass" "0,1" newline bitfld.long 0x00 17. "BYPSSETADDR,Override of the device address bypassing the SET ADDRESS control transfer" "BYPSSETADDR_0,BYPSSETADDR_1" newline bitfld.long 0x00 16. "U2RSTECN,If the super speed connection fails during POLL or LMP exchange the device connects at non-SS mode" "0,1" newline bitfld.long 0x00 14.--15. "FRMSCLDWN,Frame scale-down This field scales down device view of a SOF (FS/LS) / uSOF (HS) / ITP (SS) duration" "FRMSCLDWN_0,FRMSCLDWN_1,FRMSCLDWN_2,FRMSCLDWN_3" newline bitfld.long 0x00 12.--13. "PRTCAPDIR,Port Capability Direction - hst" "?,PRTCAPDIR_1,PRTCAPDIR_2,PRTCAPDIR_3" newline bitfld.long 0x00 11. "CORESOFTRESET,Core Soft Reset" "CORESOFTRESET_0,CORESOFTRESET_1" newline bitfld.long 0x00 8. "DEBUGATTACH,Debug Attach" "0,1" newline bitfld.long 0x00 6.--7. "RAMCLKSEL,RAM Clock Select" "RAMCLKSEL_0,RAMCLKSEL_1,RAMCLKSEL_2,RAMCLKSEL_3" newline bitfld.long 0x00 4.--5. "SCALEDOWN,Scale-Down Mode Enable Switches to shorter non-standard protocol time intervals to speed up simulation" "SCALEDOWN_0,SCALEDOWN_1,SCALEDOWN_2,SCALEDOWN_3" newline bitfld.long 0x00 3. "DISSCRAMBLE,Disable Scrambling" "0,1" newline bitfld.long 0x00 0. "DSBLCLKGTNG,Disable Clock Gating" "0,1" repeat 2. (list 0. 1. )(list 0x00 0x04 ) rgroup.long ($2+0xC178)++0x03 line.long 0x00 "USB_GDBGEPINFO$1,Global debug endpoint information register 0" repeat.end group.long 0xC160++0x03 line.long 0x00 "USB_GDBGFIFOSPACE,Global debug FIFO/queue space available" hexmask.long.word 0x00 16.--31. 1. "SPACE_AVAILABLE,Space available (in the selected FIFO/queue) 64-bit words" newline hexmask.long.byte 0x00 0.--7. 1. "FIFOQUEUESELECT_PORTSELECT,FIFO/queue select or port select" rgroup.long 0xC174++0x03 line.long 0x00 "USB_GDBGLSP,Global debug LSP. for internal use only" group.long 0xC170++0x03 line.long 0x00 "USB_GDBGLSPMUX,Global debug LSP MUX. for internal use only" bitfld.long 0x00 16.--21. "TRACEPORTMUXSEL,Select the 64-bit analyzer trace vector" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,TRACEPORTMUXSEL_63" newline bitfld.long 0x00 8.--13. "HOSTSELECT,Host LSP Select[13:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 4.--7. "DEVSELECT,Host LSP Select[7:4] in Host mode Device LSP Select in Device mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "EPSELECT,Host LSP Select[3:0] in Host mode Device LSP Select in Device mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xC164++0x03 line.long 0x00 "USB_GDBGLTSSM,Global debug LTSSM Port number is defined by [3:0] PORTSELECT" bitfld.long 0x00 29. "PORTSHUTDOWN," "0,1" newline bitfld.long 0x00 28. "PORTSWAPPING," "0,1" newline bitfld.long 0x00 27. "PORTDIRECTION,Current direction of the port" "PORTDIRECTION_0_r,PORTDIRECTION_1_r" newline bitfld.long 0x00 26. "LTDBTIMEOUT,LTSSM Debug Timeout" "0,1" newline bitfld.long 0x00 22.--25. "LTDBLINKSTATE,LTSSM Debug: Link State - U3" "LTDBLINKSTATE_0_r,LTDBLINKSTATE_1_r,LTDBLINKSTATE_2_r,LTDBLINKSTATE_3_r,LTDBLINKSTATE_4_r,LTDBLINKSTATE_5_r,LTDBLINKSTATE_6_r,LTDBLINKSTATE_7_r,LTDBLINKSTATE_8_r,LTDBLINKSTATE_9_r,LTDBLINKSTATE_10_r,LTDBLINKSTATE_11_r,?,?,?,?" newline bitfld.long 0x00 18.--21. "LTDBSUBSTATE,LTSSM Debug: Link Sub-State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17. "ELASTICBUFFERMODE,Debug PIPE Status: ElasticBufferMode" "0,1" newline bitfld.long 0x00 16. "TXELECIDLE,Debug PIPE Status: TxElecIdle" "0,1" newline bitfld.long 0x00 15. "RXPOLARITY,Debug PIPE Status: RxPolarity" "0,1" newline bitfld.long 0x00 14. "TXDETRXLOOPBACK,Debug PIPE Status: TxDetRxLoopback" "0,1" newline bitfld.long 0x00 11.--13. "LTDBPHYCMDSTATE,LTSSM Debug Phy Command State" "LTDBPHYCMDSTATE_0_r,LTDBPHYCMDSTATE_1_r,LTDBPHYCMDSTATE_2_r,LTDBPHYCMDSTATE_3_r,LTDBPHYCMDSTATE_4_r,LTDBPHYCMDSTATE_5_r,?,?" newline bitfld.long 0x00 9.--10. "POWERDOWN,Debug PIPE Status: PowerDown" "0,1,2,3" newline bitfld.long 0x00 8. "RXEQTRAIN,Debug PIPE Status: RxEqTrain" "0,1" newline bitfld.long 0x00 6.--7. "TXDEEMPHASIS,Debug PIPE Status: TxDeemphasis" "0,1,2,3" newline bitfld.long 0x00 3.--5. "LTDBCLKSTATE,LTSSM Debug Clock State - CLK_P3" "LTDBCLKSTATE_0_r,LTDBCLKSTATE_1_r,LTDBCLKSTATE_2_r,LTDBCLKSTATE_3_r,LTDBCLKSTATE_4_r,LTDBCLKSTATE_5_r,?,?" newline bitfld.long 0x00 2. "TXSWING,Debug PIPE Status: TxSwing" "0,1" newline bitfld.long 0x00 1. "RXTERMINATION,Debug PIPE Status: RxTermination" "0,1" newline bitfld.long 0x00 0. "TXONESZEROS,Debug PIPE Status: TxOnesZeros" "0,1" group.long 0xC404++0x03 line.long 0x00 "USB_GEVNTADRHI,Global event address: Upper 32 bits of start address of the external memory for the event buffer" group.long 0xC400++0x03 line.long 0x00 "USB_GEVNTADRLO,Global event address: Lower 32 bits of start address of the external memory for the event buffer" group.long 0xC40C++0x03 line.long 0x00 "USB_GEVNTCOUNT,Global event buffer count" hexmask.long.word 0x00 0.--15. 1. "EVNTCOUNT,Event count When read returns the number of valid events in the event buffer in bytes When written hardware decrements the count by the value written" group.long 0xC408++0x03 line.long 0x00 "USB_GEVNTSIZ,Global event buffer size" bitfld.long 0x00 31. "EVNTINTRPTMASK,Event interrupt mask Prevents the interrupt from being generated when set to 1 The events are queued wven when the mask is set" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "EVENTSIZ,Event buffer size Size of the event buffer in bytes; must be a multiple of 4" group.long 0xC124++0x03 line.long 0x00 "USB_GGPIO,Global general-purpose input/output register" hexmask.long.word 0x00 16.--31. 1. "GPO,General-purpose output" newline hexmask.long.word 0x00 0.--15. 1. "GPI,General-purpose inputs" rgroup.long 0xC140++0x1F line.long 0x00 "USB_GHWPARAMS0,Global hardware parameters 0" hexmask.long.byte 0x00 24.--31. 1. "DWC_USB3_AWIDTH,Global hardware configuration parameter DWC_USB3_AWIDTH: (Master) Address Width (in bits)" newline hexmask.long.byte 0x00 16.--23. 1. "DWC_USB3_SDWIDTH,Global hardware configuration parameter DWC_USB3_SDWIDTH: Slave Data Width (in bits)" newline hexmask.long.byte 0x00 8.--15. 1. "DWC_USB3_MDWIDTH,Global hardware configuration parameter DWC_USB3_MDWIDTH: Master Data Width (in bits)" newline bitfld.long 0x00 6.--7. "DWC_USB3_SBUS_TYPE,Global hardware configuration parameter DWC_USB3_SBUS_TYPE: (System bus) Slave type - native" "DWC_USB3_SBUS_TYPE_0_r,?,?,?" newline bitfld.long 0x00 3.--5. "DWC_USB3_MBUS_TYPE,Global hardware configuration parameter DWC_USB3_MBUS_TYPE: (System bus) Master type - axi" "?,DWC_USB3_MBUS_TYPE_1_r,?,?,?,?,?,?" newline bitfld.long 0x00 0.--2. "DWC_USB3_MODE,Global hardware configuration parameter DWC_USB3_MODE - drd" "DWC_USB3_MODE_0_r,DWC_USB3_MODE_1_r,DWC_USB3_MODE_2_r,?,?,?,?,?" line.long 0x04 "USB_GHWPARAMS1,Global hardware parameters 1" bitfld.long 0x04 30. "DWC_USB3_RM_OPT_FEATURES,Global hardware configuration parameter DWC_USB3_RM_OPT_FEATURES: Remove Optional Features - yes" "DWC_USB3_RM_OPT_FEATURES_0_r,DWC_USB3_RM_OPT_FEATURES_1_r" newline bitfld.long 0x04 28. "DWC_USB3_RAM_BUS_CLKS_SYNC,Global hardware configuration parameter DWC_USB3_RAM_BUS_CLKS_SYNC: RAM vs" "DWC_USB3_RAM_BUS_CLKS_SYNC_0_r,DWC_USB3_RAM_BUS_CLKS_SYNC_1_r" newline bitfld.long 0x04 27. "DWC_USB3_MAC_RAM_CLKS_SYNC,Global hardware configuration parameter DWC_USB3_MAC_RAM_CLKS_SYNC: MAC vs" "DWC_USB3_MAC_RAM_CLKS_SYNC_0_r,DWC_USB3_MAC_RAM_CLKS_SYNC_1_r" newline bitfld.long 0x04 26. "DWC_USB3_MAC_PHY_CLKS_SYNC,Global hardware configuration parameter DWC_USB3_MAC_PHY_CLKS_SYNC: MAC vs" "DWC_USB3_MAC_PHY_CLKS_SYNC_0_r,DWC_USB3_MAC_PHY_CLKS_SYNC_1_r" newline bitfld.long 0x04 24.--25. "DWC_USB3_EN_PWROPT,Global hardware configuration parameter DWC_USB3_EN_PWROPT: Power optimization - clock_hibernation" "DWC_USB3_EN_PWROPT_0_r,DWC_USB3_EN_PWROPT_1_r,DWC_USB3_EN_PWROPT_2_r,?" newline bitfld.long 0x04 23. "DWC_USB3_SPRAM_TYP,Global hardware configuration parameter DWC_USB3_SPRAM_TYP - SP" "?,DWC_USB3_SPRAM_TYP_1_r" newline bitfld.long 0x04 21.--22. "DWC_USB3_NUM_RAMS,Global hardware configuration parameter DWC_USB3_NUM_RAMS: Number of internal RAMs - 3" "?,DWC_USB3_NUM_RAMS_1_r,DWC_USB3_NUM_RAMS_2_r,DWC_USB3_NUM_RAMS_3_r" newline bitfld.long 0x04 15.--20. "DWC_USB3_DEVICE_NUM_INT,Global hardware configuration parameter DWC_USB3_DEVICE_NUM_INT: Number of interrupts (and event buffers) in device mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 12.--14. "DWC_USB3_ASPACEWIDTH,Global hardware configuration parameter DWC_USB3_ASPACEWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 9.--11. "DWC_USB3_REQINFOWIDTH,Global hardware configuration parameter DWC_USB3_REQINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 6.--8. "DWC_USB3_DATAINFOWIDTH,Global hardware configuration parameter DWC_USB3_DATAINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 3.--5. "DWC_USB3_BURSTWIDTH,Global hardware configuration parameter DWC_USB3_BURSTWIDTH minus one fixed to" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 0.--2. "DWC_USB3_IDWIDTH,Global hardware configuration parameter DWC_USB3_IDWIDTH minus 1 Note: Sets only the master port's ID width" "0,1,2,3,4,5,6,7" line.long 0x08 "USB_GHWPARAMS2,Global hardware parameters 2" line.long 0x0C "USB_GHWPARAMS3,Global hardware parameters 3" hexmask.long.byte 0x0C 23.--30. 1. "DWC_USB3_CACHE_TOTAL_XFER_RESOURCES,Global hardware configuration parameter DWC_USB3_NUM_CACHE_TOTAL_XFER_RESOURCES: Cache total transfer resources" newline bitfld.long 0x0C 18.--22. "DWC_USB3_NUM_IN_EPS,Global hardware configuration parameter DWC_USB3_NUM_IN_EPS: Number of IN endpoints with EP0 counting as one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x0C 12.--17. "DWC_USB3_NUM_EPS,Global hardware configuration parameter DWC_USB3_NUM_EPS: Total number of endpoints (IN+OUT with EP0 counting as 2 separate ones)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 11. "DWC_USB3_ULPI_CARKIT,Global hardware configuration parameter DWC_USB3_ULPI_CARKIT: ULPI (optional) car-kit mode implementation - vc" "DWC_USB3_ULPI_CARKIT_0_r,DWC_USB3_ULPI_CARKIT_1_r" newline bitfld.long 0x0C 10. "DWC_USB3_VENDOR_CTL_INTERFACE,Global hardware configuration parameter DWC_USB3_VENDOR_CTL_INTERFACE: (UTMI) Vendor Control i/f implementation - vc" "DWC_USB3_VENDOR_CTL_INTERFACE_0_r,DWC_USB3_VENDOR_CTL_INTERFACE_1_r" newline bitfld.long 0x0C 6.--7. "DWC_USB3_HSPHY_DWIDTH,Global hardware configuration parameter DWC_USB3_HSPHY_DWIDTH: HS PHY data width - 8_16" "DWC_USB3_HSPHY_DWIDTH_0_r,DWC_USB3_HSPHY_DWIDTH_1_r,DWC_USB3_HSPHY_DWIDTH_2_r,?" newline bitfld.long 0x0C 4.--5. "DWC_USB3_FSPHY_INTERFACE,Global hardware configuration parameter DWC_USB3_FSPHY_INTERFACE: Full (/Low)-Speed (serial) PHY interface - none" "DWC_USB3_FSPHY_INTERFACE_0_r,?,?,?" newline bitfld.long 0x0C 2.--3. "DWC_USB3_HSPHY_INTERFACE,Global hardware configuration parameter DWC_USB3_HSPHY_INTERFACE: High-speed PHY interface - both" "DWC_USB3_HSPHY_INTERFACE_0_r,DWC_USB3_HSPHY_INTERFACE_1_r,DWC_USB3_HSPHY_INTERFACE_2_r,DWC_USB3_HSPHY_INTERFACE_3_r" newline bitfld.long 0x0C 0.--1. "DWC_USB3_SSPHY_INTERFACE,Global hardware configuration parameter DWC_USB3_SSPHY_INTERFACE: Super Speed PHY interface" "DWC_USB3_SSPHY_INTERFACE_0_r,DWC_USB3_SSPHY_INTERFACE_1_r,?,?" line.long 0x10 "USB_GHWPARAMS4,Global hardware parameters 4" bitfld.long 0x10 28.--31. "DWC_USB3_BMU_LSP_DEPTH,Global hardware configuration parameter DWC_USB3_BMU_LSP_DEPTH: Bus Management Unit / List Processor buffer depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 24.--27. "DWC_USB3_BMU_PTL_DEPTH,Global hardware configuration parameter DWC_USB3_BMU_PTL_DEPTH: Bus Management Unit / Protocol Transaction Layer buffer depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 23. "DWC_USB3_EN_ISOC_SUPT,Global hardware configuration parameter DWC_USB3_EN_ISOC_SUPT: Enable Isochronous Support - iso" "DWC_USB3_EN_ISOC_SUPT_0_r,DWC_USB3_EN_ISOC_SUPT_1_r" newline bitfld.long 0x10 17.--20. "DWC_USB3_NUM_SS_USB_INSTANCES,Global hardware configuration parameter DWC_USB3_NUM_SS_USB_INSTANCES: Number of (independent) SS USB schedulers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 13.--16. "DWC_USB3_HIBER_SCRATCHBUFS,Global hardware configuration parameter DWC_USB3_HIBER_SCRATCHBUFS: Number of 4-kbyte buffers required in system memory to store context during hibernation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x10 0.--5. "DWC_USB3_CACHE_TRBS_PER_TRANSFER,Global hardware configuration parameter DWC_USB3_CACHE_TRBS_PER_TRANSFER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "USB_GHWPARAMS5,Global hardware parameters 5" bitfld.long 0x14 22.--27. "DWC_USB3_DFQ_FIFO_DEPTH,Global hardware configuration parameter DWC_USB3_DFQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 16.--21. "DWC_USB3_DWQ_FIFO_DEPTH,Global hardware configuration parameter DWC_USB3_DWQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 10.--15. "DWC_USB3_TXQ_FIFO_DEPTH,Global hardware configuration parameter DWC_USB3_TXQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 4.--9. "DWC_USB3_RXQ_FIFO_DEPTH,Global hardware configuration parameter DWC_USB3_RXQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x14 0.--3. "DWC_USB3_BMU_BUSGM_DEPTH,Global hardware configuration parameter DWC_USB3_BMU_BUSGM_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "USB_GHWPARAMS6,Global hardware parameters 6" hexmask.long.word 0x18 16.--31. 1. "DWC_USB3_RAM0_DEPTH,Depth of RAM 0 in 64-bit words" newline bitfld.long 0x18 15. "BUSFLTRSSUPPORT,Filtering (debounce) on OTG UTMI+ inputs (iddig vbusvalid avalid bvalid sessend)" "BUSFLTRSSUPPORT_0_r,BUSFLTRSSUPPORT_1_r" newline bitfld.long 0x18 14. "BCSUPPORT,Battery Charger detection (ACA = Accessory Charger Adapter) support implemented internally" "BCSUPPORT_0_r,BCSUPPORT_1_r" newline bitfld.long 0x18 13. "OTGSSSUPPORT,OTG SuperSpeed support (aka OTG3.0) - yes" "OTGSSSUPPORT_0_r,OTGSSSUPPORT_1_r" newline bitfld.long 0x18 12. "ADPSUPPORT,OTG2.0 ADP (Attach Detection Protocol) support implemented internally" "ADPSUPPORT_0_r,ADPSUPPORT_1_r" newline bitfld.long 0x18 11. "HNPSUPPORT,OTG2.0 HNP (Host Negotiation Protocol) support" "HNPSUPPORT_0_r,HNPSUPPORT_1_r" newline bitfld.long 0x18 10. "SRPSUPPORT,OTG2.0 SRP (Session Request Protocol) support" "SRPSUPPORT_0_r,SRPSUPPORT_1_r" newline bitfld.long 0x18 7. "DWC_USB3_EN_FPGA,Global hardware configuration parameter DWC_USB3_EN_FPGA" "0,1" newline bitfld.long 0x18 0.--5. "DWC_USB3_PSQ_FIFO_DEPTH,Global hardware configuration parameter DWC_USB3_PSQ_FIFO_DEPTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "USB_GHWPARAMS7,Global hardware parameters 7" hexmask.long.word 0x1C 16.--31. 1. "DWC_USB3_RAM2_DEPTH,Depth of RAM 2 in 64-bit words" newline hexmask.long.word 0x1C 0.--15. 1. "DWC_USB3_RAM1_DEPTH,Depth of RAM 1 in 64-bit words" rgroup.long 0xC600++0x07 line.long 0x00 "USB_GHWPARAMS8,Global hardware parameters 8" line.long 0x04 "USB_GHWPARAMS9,Global hardware parameters 9" hgroup.long 0xC18C++0x03 hide.long 0x00 "USB_GPRTBIMAP_FSHI,Global port to USB instance mapping register. full/low-speed. high bits [63:32]" group.long 0xC188++0x03 line.long 0x00 "USB_GPRTBIMAP_FSLO,Global port to USB instance mapping register. full/low-speed. low bits [31:0]" bitfld.long 0x00 0.--3. "BINUM1,FS USB instance number for port number 1 Application-programmable ID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xC184++0x03 hide.long 0x00 "USB_GPRTBIMAP_HSHI,Global port to USB instance mapping register. high-speed. high bits [63:32]" group.long 0xC180++0x03 line.long 0x00 "USB_GPRTBIMAP_HSLO,Global port to USB instance mapping register. high-speed. low bits [31:0]" bitfld.long 0x00 0.--3. "BINUM1,HS USB instance number for port number 1 Application-programmable ID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xC13C++0x03 hide.long 0x00 "USB_GPRTBIMAPHI,Global Port-to-SS USB Instance Mapping. high bits [63:32]" group.long 0xC138++0x03 line.long 0x00 "USB_GPRTBIMAPLO,Global port-to-SS USB instance mapping. low bits [31:0]" bitfld.long 0x00 0.--3. "BINUM1,SS USB instance number for port number 1 Application-programmable ID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC380++0x0B line.long 0x00 "USB_GRXFIFOSIZ0,Global Receive FIFO Size" hexmask.long.word 0x00 16.--31. 1. "RXFSTADDR,Receive FIFO RAM Start Address in 64-bit RAM words" newline hexmask.long.word 0x00 0.--15. 1. "RXFDEP,Receive FIFO Depth in 64-bit RAM words - min" line.long 0x04 "USB_GRXFIFOSIZ1,Global receive FIFO size" hexmask.long.word 0x04 16.--31. 1. "RXFSTADDR,Receive FIFO RAM Start Address in 64-bit RAM words" newline hexmask.long.word 0x04 0.--15. 1. "RXFDEP,Receive FIFO Depth in 64-bit RAM words - min" line.long 0x08 "USB_GRXFIFOSIZ2,Global receive FIFO size" hexmask.long.word 0x08 16.--31. 1. "RXFSTADDR,Receive FIFO RAM Start Address in 64-bit RAM words" newline hexmask.long.word 0x08 0.--15. 1. "RXFDEP,Receive FIFO Depth in 64-bit RAM words - min" group.long 0xC10C++0x03 line.long 0x00 "USB_GRXTHRCFG,Global RX Threshold Control Register" bitfld.long 0x00 29. "USBRXPKTCNTSEL,USB ReceivePacket Count Enable Enables/disables USB reception multi-packet thresholding - dis" "USBRXPKTCNTSEL_0,USBRXPKTCNTSEL_1" newline bitfld.long 0x00 24.--27. "USBRXPKTCNT,USB Receive Packet Count: Number of packets that must be available in the RX FIFO before the core can start the corresponding USB RX transaction (burst)" "USBRXPKTCNT_0,USBRXPKTCNT_1,?,?,?,?,?,?,?,?,?,?,?,?,?,USBRXPKTCNT_15" newline bitfld.long 0x00 19.--23. "USBMAXRXBURSTSIZE,USB Maximum Receive Burst Size" "USBMAXRXBURSTSIZE_0,USBMAXRXBURSTSIZE_1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,USBMAXRXBURSTSIZE_16,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" group.long 0xC100++0x07 line.long 0x00 "USB_GSBUSCFG0,Global device Bus Configuration Register 0" bitfld.long 0x00 12. "DESCBIGEND,Endian mode for descriptor accesses" "DESCBIGEND_0,DESCBIGEND_1" newline bitfld.long 0x00 11. "DATBIGEND,Endian mode for data accesses" "DATBIGEND_0,DATBIGEND_1" newline bitfld.long 0x00 7. "INCR256BRSTENA,INCR256 Burst Type Enable" "0,1" newline bitfld.long 0x00 6. "INCR128BRSTENA,INCR128 Burst Type Enable" "0,1" newline bitfld.long 0x00 5. "INCR64BRSTENA,INCR64 Burst Type Enable" "0,1" newline bitfld.long 0x00 4. "INCR32BRSTENA,INCR32 Burst Type Enable" "0,1" newline bitfld.long 0x00 3. "INCR16BRSTENA,INCR16 Burst Type Enable" "0,1" newline bitfld.long 0x00 2. "INCR8BRSTENA,INCR8 Burst Type Enable" "0,1" newline bitfld.long 0x00 1. "INCR4BRSTENA,INCR4 Burst Type Enable" "0,1" newline bitfld.long 0x00 0. "INCRBRSTENA,Undefined Length INCR Burst Type Enable: DO NOT ENABLE When enabled this has higher priority than other burst types" "0,1" line.long 0x04 "USB_GSBUSCFG1,Global device bus configuration register 1" bitfld.long 0x04 12. "EN1KPAGE,1k-page boundary enable - DIS" "EN1KPAGE_0,EN1KPAGE_1" newline bitfld.long 0x04 8.--11. "PIPETRANSLIMIT,Maximum number of outstanding (read or write) pipelined sequential (i.e. in-order) transaction requests on the master interface (field value+1)" "PIPETRANSLIMIT_0,PIPETRANSLIMIT_1,?,?,?,?,?,?,?,?,?,?,?,?,?,PIPETRANSLIMIT_15" rgroup.long 0xC120++0x03 line.long 0x00 "USB_GSNPSID,Synopsys ID: Core identification and release number" hexmask.long.word 0x00 16.--31. 1. "SYNOPSYSID_CORE,SYNOPSYSID MSBytes: core identifier - id" newline hexmask.long.word 0x00 0.--15. 1. "SYNOPSYSID_REL,SYNOPSYSID LSBytes: version number For instance version" group.long 0xC118++0x03 line.long 0x00 "USB_GSTS,Global status register" hexmask.long.word 0x00 20.--31. 1. "CBELT,Current BELT Value In Host mode this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command" newline rbitfld.long 0x00 10. "OTG_IP,OTG interrupt status - pend" "OTG_IP_0_r,OTG_IP_1_r" newline rbitfld.long 0x00 9. "BC_IP,Battery Charger interrupt status: NOT IMPLEMENTED" "0,1" newline rbitfld.long 0x00 8. "ADP_IP,ADP interrupt status: NOT IMPLEMENTED" "0,1" newline rbitfld.long 0x00 7. "HOST_IP,Host interrupt status - pend" "HOST_IP_0_r,HOST_IP_1_r" newline rbitfld.long 0x00 6. "DEVICE_IP,Device interrupt status - pend" "DEVICE_IP_0_r,DEVICE_IP_1_r" newline bitfld.long 0x00 5. "CSRTIMEOUT,Control/Status Register access Timeout status flag" "CSRTIMEOUT_0_r,CSRTIMEOUT_1_r" newline bitfld.long 0x00 4. "BUSERRADDRVLD,Bus Error Address Valid status flag" "BUSERRADDRVLD_0_r,BUSERRADDRVLD_1_r" newline rbitfld.long 0x00 0.--1. "CURMOD,Current Mode of Operation" "CURMOD_0_r,CURMOD_1_r,CURMOD_2_r,?" group.long 0xC300++0x07 line.long 0x00 "USB_GTXFIFOSIZ0,Global Transmit FIFO Size" hexmask.long.word 0x00 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x00 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x04 "USB_GTXFIFOSIZ1,Global Transmit FIFO Size" hexmask.long.word 0x04 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x04 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" group.long 0xC328++0x17 line.long 0x00 "USB_GTXFIFOSIZ10,Global Transmit FIFO Size" hexmask.long.word 0x00 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x00 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x04 "USB_GTXFIFOSIZ11,Global Transmit FIFO Size" hexmask.long.word 0x04 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x04 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x08 "USB_GTXFIFOSIZ12,Global Transmit FIFO Size" hexmask.long.word 0x08 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x08 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x0C "USB_GTXFIFOSIZ13,Global Transmit FIFO Size" hexmask.long.word 0x0C 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x0C 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x10 "USB_GTXFIFOSIZ14,Global Transmit FIFO Size" hexmask.long.word 0x10 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x10 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x14 "USB_GTXFIFOSIZ15,Global Transmit FIFO Size" hexmask.long.word 0x14 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x14 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" group.long 0xC308++0x1F line.long 0x00 "USB_GTXFIFOSIZ2,Global Transmit FIFO Size" hexmask.long.word 0x00 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x00 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x04 "USB_GTXFIFOSIZ3,Global Transmit FIFO Size" hexmask.long.word 0x04 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x04 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x08 "USB_GTXFIFOSIZ4,Global Transmit FIFO Size" hexmask.long.word 0x08 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x08 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x0C "USB_GTXFIFOSIZ5,Global Transmit FIFO Size" hexmask.long.word 0x0C 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x0C 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x10 "USB_GTXFIFOSIZ6,Global Transmit FIFO Size" hexmask.long.word 0x10 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x10 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x14 "USB_GTXFIFOSIZ7,Global Transmit FIFO Size" hexmask.long.word 0x14 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x14 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x18 "USB_GTXFIFOSIZ8,Global Transmit FIFO Size" hexmask.long.word 0x18 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x18 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" line.long 0x1C "USB_GTXFIFOSIZ9,Global Transmit FIFO Size" hexmask.long.word 0x1C 16.--31. 1. "TXFSTADDR,Transmit FIFO RAM start address in 64-bit RAM words" newline hexmask.long.word 0x1C 0.--15. 1. "TXFDEP,Transmit FIFO depth in 64-bit RAM words" group.long 0xC108++0x03 line.long 0x00 "USB_GTXTHRCFG,Global TX threshold control register" bitfld.long 0x00 29. "USBTXPKTCNTSEL,USB Transmit Packet Count Enable: Enables/disables USB trasnmission multi-packet thresholding - dis" "USBTXPKTCNTSEL_0,USBTXPKTCNTSEL_1" newline bitfld.long 0x00 24.--27. "USBTXPKTCNT,USB Transmit Packet Count : Number of packets that must be in the TXFIFO before transmission for the corresponding USB transaction (burst) can start" "USBTXPKTCNT_0,USBTXPKTCNT_1,?,?,?,?,?,?,?,?,?,?,?,?,?,USBTXPKTCNT_15" newline hexmask.long.byte 0x00 16.--23. 1. "USBMAXTXBURSTSIZE,USB Maximum Transmit Burst Size" group.long 0xC12C++0x03 line.long 0x00 "USB_GUCTL,Global user control register" bitfld.long 0x00 21. "NOEXTRDL,No Extra Delay between SOF and the 1st packet (when host) - dis" "NOEXTRDL_0,NOEXTRDL_1" newline bitfld.long 0x00 18.--20. "PSQEXTRRESSP,Protocol Status Queue Extra Reserved Space (Debug only)" "PSQEXTRRESSP_0,PSQEXTRRESSP_1,?,?,?,?,?,?" newline bitfld.long 0x00 17. "SPRSCTRLTRANSEN,Sparse Control Transaction Enable" "SPRSCTRLTRANSEN_0,SPRSCTRLTRANSEN_1" newline bitfld.long 0x00 16. "RESBWHSEPS,Reserving (more) Bandwidth for HS Periodic EPs" "RESBWHSEPS_0,RESBWHSEPS_1" newline bitfld.long 0x00 15. "CMDEVADDR,Compliance Mode for Device Address" "CMDEVADDR_0,CMDEVADDR_1" newline bitfld.long 0x00 14. "USBHSTINAUTORETRYEN,Host IN Auto Retry Enable: host core behaviour upon data packet CRC errors or internal overrun scenarios in non-isochronous IN transfers" "USBHSTINAUTORETRYEN_0,USBHSTINAUTORETRYEN_1" newline bitfld.long 0x00 9.--10. "DTCT,Device Timeout Coarse Tuning: time the host waits for a response from device before timeout" "DTCT_0,DTCT_1,DTCT_2,DTCT_3" newline hexmask.long.word 0x00 0.--8. 1. "DTFT,Device Timeout Fine Tuning: time the host waits for a response from device before timeout" group.long 0xC128++0x03 line.long 0x00 "USB_GUID,Global user ID register" group.long 0xC280++0x03 line.long 0x00 "USB_GUSB2PHYACC,Global USB2.0 PHY access" rbitfld.long 0x00 26. "DISULPIDRVR,Disable ULPI drivers for carkit mode" "0,1" newline bitfld.long 0x00 25. "NEWREGREQ,New register request" "NEWREGREQ_0_r,NEWREGREQ_1_r" newline rbitfld.long 0x00 24. "VSTSDONE,VStatus Done" "VSTSDONE_0_r,VSTSDONE_1_r" newline rbitfld.long 0x00 23. "VSTSBSY,VStatus busy" "VSTSBSY_0_r,VSTSBSY_1_r" newline bitfld.long 0x00 22. "REGWR,Register write" "REGWR_0,REGWR_1" newline bitfld.long 0x00 16.--21. "REGADDR,Register address ULPI PHY register address for immediate PHY register set access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. "EXTREGADDR,ULPI: PHY extended register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.byte 0x00 0.--7. 1. "REGDATA,Register data (read and write data)" group.long 0xC200++0x03 line.long 0x00 "USB_GUSB2PHYCFG,Global USB2.0 (UTMI/ULPI) PHY configuration" bitfld.long 0x00 31. "PHYSOFTRST,PHY Soft Reset" "PHYSOFTRST_0,PHYSOFTRST_1" newline bitfld.long 0x00 18. "ULPIEXTVBUSINDICATOR,ULPI External VBUS Indicator Indicates the ULPI PHY VBUS over-current indicator" "ULPIEXTVBUSINDICATOR_0,ULPIEXTVBUSINDICATOR_1" newline bitfld.long 0x00 17. "ULPIEXTVBUSDRV,ULPI External VBUS Drive Selects supply source to drive 5V on VBUS in the ULPI PHY" "ULPIEXTVBUSDRV_0,ULPIEXTVBUSDRV_1" newline bitfld.long 0x00 16. "ULPICLKSUSM,Sets the ClockSuspendM bit in the Interface Control register on the ULPI PHY" "0,1" newline bitfld.long 0x00 15. "ULPIAUTORES,ULPI Auto Resume" "ULPIAUTORES_0,ULPIAUTORES_1" newline bitfld.long 0x00 10.--13. "USBTRDTIM,USB 2.0 Turnaround Time in PHY clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8. "ENBLSLPM,Enable UTMI Sleep" "ENBLSLPM_0,ENBLSLPM_1" newline rbitfld.long 0x00 7. "PHYSEL,PHY Select" "0,1" newline bitfld.long 0x00 6. "SUSPHY,Suspend enable for USB2.0 HS/FS/LS PHY (ULPI or UTMI)" "SUSPHY_0,SUSPHY_1" newline rbitfld.long 0x00 5. "FSINTF,Full-Speed Serial Interface Select" "0,1" newline bitfld.long 0x00 4. "ULPI_UTMI_SEL,ULPI or UTMI+ Select - utmi" "ULPI_UTMI_SEL_0,ULPI_UTMI_SEL_1" newline bitfld.long 0x00 3. "PHYIF,PHY Interface" "PHYIF_0,PHYIF_1" newline bitfld.long 0x00 0.--2. "TOUTCAL,HS/FS Timeout Calibration" "0,1,2,3,4,5,6,7" group.long 0xC2C0++0x03 line.long 0x00 "USB_GUSB3PIPECTL,Global USB3.0 PIPE control" bitfld.long 0x00 31. "PHYSOFTRST,PHY Soft Reset" "PHYSOFTRST_0,PHYSOFTRST_1" newline bitfld.long 0x00 27. "UX_EXIT_IN_PX,Workaround for SS PHY injecting a glitch on RxElecIdle while receiving Ux exit LFPS and PowerDown change is in progress" "UX_EXIT_IN_PX_0,UX_EXIT_IN_PX_1" newline bitfld.long 0x00 26. "PING_ENHANCEMENT_EN,Ping Enhancement Enable: Extended downstream port U1 ping receive timeout" "PING_ENHANCEMENT_EN_0,PING_ENHANCEMENT_EN_1" newline bitfld.long 0x00 25. "U1U2EXITFAIL_TO_RECOV,Enhancement to prevent interoperability issue in case of incorrect LFPS handshake by the remote link" "U1U2EXITFAIL_TO_RECOV_0,U1U2EXITFAIL_TO_RECOV_1" newline bitfld.long 0x00 24. "REQUEST_P1P2P3,Control the systematic request of P1/P2/P3 for U1/U2/U3 - none" "REQUEST_P1P2P3_0,REQUEST_P1P2P3_1" newline bitfld.long 0x00 23. "STARTRXDETU3RXDET,Manual control for periodic Rx detection required in U3 and Rx.Detect host mode" "STARTRXDETU3RXDET_0_w,STARTRXDETU3RXDET_1_w" newline bitfld.long 0x00 22. "DISRXDETU3RXDET,Disable the HW-scheduled periodic Rx detection required in U3 and SS.Disabled for host mode" "DISRXDETU3RXDET_0,DISRXDETU3RXDET_1" newline bitfld.long 0x00 19.--21. "P1P2P3DELAY,If DelayP0toP1P2P3=1 delays the transition to P1/P2/P3 when entering U1/U2/U3 until P1P2P3Delay*8b10b errors occur or RxValid=0 on PIPE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18. "DELAYP0TOP1P2P3,Delay PHY change from P0 to P1/P2/P3 when link state changes from U0 to U1/U2/U3 respectively" "DELAYP0TOP1P2P3_0,DELAYP0TOP1P2P3_1" newline bitfld.long 0x00 17. "SUSPENDENABLE,Suspend Enable for USB3.0 SS PHY" "SUSPENDENABLE_0,SUSPENDENABLE_1" newline rbitfld.long 0x00 15.--16. "DATWIDTH,PIPE Data Width (input from phy: refer to PIPE standard) Field updated to the input's value immediately after reset" "DATWIDTH_0_r,DATWIDTH_1_r,DATWIDTH_2_r,?" newline bitfld.long 0x00 14. "ABORTRXDETINU2,Abort Rx Detect in U2" "ABORTRXDETINU2_0,ABORTRXDETINU2_1" newline bitfld.long 0x00 13. "SKIPRXDET,Skip Rx Detect" "0,1" newline bitfld.long 0x00 12. "LFPSP0ALGN,LFPS P0 Align" "LFPSP0ALGN_0,LFPSP0ALGN_1" newline bitfld.long 0x00 11. "P3P2TRANOK,P3-to-P2 Transitions OK - notset" "P3P2TRANOK_0,P3P2TRANOK_1" newline bitfld.long 0x00 10. "P3EXSIGP2,PHY power state behaviour upon U3 exit handshake" "P3EXSIGP2_0,P3EXSIGP2_1" newline bitfld.long 0x00 9. "LFPSFILT,LFPS Filter" "0,1" newline bitfld.long 0x00 6. "TXSWING,Tx Swing (output to PHY: refer to PIPE standard)" "0,1" newline bitfld.long 0x00 3.--5. "TXMARGIN,Tx Margin[2:0] (output to PHY: refer to PIPE standard)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--2. "TXDEEMPHASIS,Tx Deemphasis (output to PHY: refer to PIPE standard) The value driven to the PHY is controlled by the LTSSM during USB3.0 Compliance mode" "0,1,2,3" newline bitfld.long 0x00 0. "ELASTICBUFFERMODE,Elastic Buffer Mode (output to PHY: refer to PIPE standard)" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "USB_HCCPARAMS,Host controller capability parameters (xHCI)" hexmask.long.word 0x00 16.--31. 1. "XECP,xHCI Extended Capabilties Pointer" newline bitfld.long 0x00 12.--15. "MAXPSASIZE,Maximum Primary Stream Array Size: See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8. "PAE,Parse All Event data: see xHCI 1.0 standard w errata" "0,1" newline bitfld.long 0x00 7. "NSS,No Secondary SID Support See xHCI specification" "0,1" newline bitfld.long 0x00 6. "LTC,Latency Tolerance messaging Capability See xHCI specification" "0,1" newline bitfld.long 0x00 5. "LHRC,Light HC Reset Capability: See xHCI specification" "0,1" newline bitfld.long 0x00 4. "PIND,Port Indicators: See xHCI specification" "0,1" newline bitfld.long 0x00 3. "PPC,Port Power Control: See xHCI specification" "0,1" newline bitfld.long 0x00 2. "CSZ,Context Size: See xHCI specification" "0,1" newline bitfld.long 0x00 1. "BNC,Bandwidth Negotiation Capability: See xHCI specification" "0,1" newline bitfld.long 0x00 0. "AC64,64-bit Address Capability: See xHCI specification" "0,1" rgroup.long 0x04++0x0B line.long 0x00 "USB_HCSPARAMS1,Host controller structural parameters 1 (xHCI)" hexmask.long.byte 0x00 24.--31. 1. "MAXPORTS,See xHCI specification" newline hexmask.long.word 0x00 8.--18. 1. "MAXINTRS,See xHCI specification" newline hexmask.long.byte 0x00 0.--7. 1. "MAXSLOTS,See xHCI specification" line.long 0x04 "USB_HCSPARAMS2,Host controller structural parameters 2 (xHCI)" bitfld.long 0x04 27.--31. "MAXSCRATCHPADBUFS_LO,Max Scratchpad Buffers lower bits: See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 26. "SPR,Scratchpad Restore: See xHCI specification - yes" "SPR_0_r,SPR_1_r" newline bitfld.long 0x04 21.--25. "MAXSCRATCHPADBUFS_HI,Max Scratchpad Buffers higher bits: see xHCI 1.0 standard" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x04 4.--7. "ERSTMAX,Event Ring Segment Table Max: See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 0.--3. "IST,Isochronous Scheduling Threshold: See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "USB_HCSPARAMS3,Host controller structural parameters 3 (xHCI)" hexmask.long.word 0x08 16.--31. 1. "U2_DEVICE_EXIT_LAT,U2 device exit latency: Worst-case latency to transition from U2 to U0 in micros" newline hexmask.long.byte 0x08 0.--7. 1. "U1_DEVICE_EXIT_LAT,U1 device exit latency: Worst-case latency to transition a root hub port link state (PLS) from U1 to U0 in micros" group.long 0x460++0x07 line.long 0x00 "USB_IMAN,Interrupter Management (xHCI)" bitfld.long 0x00 1. "IE,Interrupt enable - DIS" "IE_0,IE_1" newline bitfld.long 0x00 0. "IP,Interrupt pending" "IP_0,IP_1" line.long 0x04 "USB_IMOD,Interrupter moderation (xHCI)" hexmask.long.word 0x04 16.--31. 1. "IMODC,Interrupt moderation counter: Loaded to IMODI whenever IP is cleared to 0 counts down to 0 and stops" newline hexmask.long.word 0x04 0.--15. 1. "IMODI,Interrupt moderation interval: Minimum inter-IRQ interval in 250-ns increments" rgroup.long 0x440++0x03 line.long 0x00 "USB_MFINDEX,Microframe index (xHCI)" hexmask.long.word 0x00 0.--13. 1. "MICROFRAME_INDEX,See xHCI specification" group.long 0xCC00++0x13 line.long 0x00 "USB_OCFG,OTG configuration" bitfld.long 0x00 3. "OTGSFTRSTMSK,Protects OTG PHY and VBUS filters from the following software resets: xHCIUSB_USBCMD[1] HCRST (host) USB_DCTL[30] CSFTRST (device)" "OTGSFTRSTMSK_0,OTGSFTRSTMSK_1" newline bitfld.long 0x00 2. "OTGVERSION,Debug always write 0" "0,1" newline bitfld.long 0x00 1. "HNPCAP,HNP Capabilty Enable" "HNPCAP_0,HNPCAP_1" newline bitfld.long 0x00 0. "SRPCAP,SRP Capability enable" "SRPCAP_0,SRPCAP_1" line.long 0x04 "USB_OCTL,OTG control IMPORTANT NOTE: Register is reinitialized on ID change. but is not affected by a software reset" bitfld.long 0x04 7. "OTG3_GOERR,To be set upon TRSP_ACK_ERR TRSP_CNF_ERR or TRSP_WRST_ERR timeout" "OTG3_GOERR_0,OTG3_GOERR_1_w" newline bitfld.long 0x04 6. "PERIMODE,Peripheral Mode" "PERIMODE_0_r,PERIMODE_1_r" newline bitfld.long 0x04 5. "PRTPWRCTL,Port Power Control" "PRTPWRCTL_0_r,PRTPWRCTL_1_r" newline bitfld.long 0x04 4. "HNPREQ,HNP Request" "HNPREQ_0,HNPREQ_1" newline bitfld.long 0x04 3. "SESREQ,Session Request" "SESREQ_0_r,SESREQ_1_w" newline bitfld.long 0x04 2. "TERMSELDLPULSE,TermSelect Data Line Pulse" "TERMSELDLPULSE_0,TERMSELDLPULSE_1" newline bitfld.long 0x04 1. "DEVSETHNPEN,Device Set HNP Enable" "DEVSETHNPEN_0,DEVSETHNPEN_1" newline bitfld.long 0x04 0. "HSTSETHNPEN,Host Set HNP Enable" "HSTSETHNPEN_0,HSTSETHNPEN_1" line.long 0x08 "USB_OEVT,OTG event: OTG interrupt status" rbitfld.long 0x08 31. "DEVICEMODE,Dual-role device's mode based on iddig input" "DEVICEMODE_0_r,DEVICEMODE_1_r" newline bitfld.long 0x08 24. "OTGCONIDSTSCHNGEVNT,Connector ID status change event" "OTGCONIDSTSCHNGEVNT_0_r,OTGCONIDSTSCHNGEVNT_1_r" newline bitfld.long 0x08 23. "HRRCONFNOTIFEVNT,Host Role Request Confirm Notifier Event" "HRRCONFNOTIFEVNT_0_r,HRRCONFNOTIFEVNT_1_r" newline bitfld.long 0x08 22. "HRRINITNOTIFEVNT,Host Role Request Initiate Notifier Event" "HRRINITNOTIFEVNT_0_r,HRRINITNOTIFEVNT_1_r" newline bitfld.long 0x08 21. "OTGADEVIDLEEVNT,A-device A-IDLE Event" "OTGADEVIDLEEVNT_0_r,OTGADEVIDLEEVNT_1_r" newline bitfld.long 0x08 20. "OTGADEVBHOSTENDEVNT,A-device B-host End Event" "OTGADEVBHOSTENDEVNT_0_r,OTGADEVBHOSTENDEVNT_1_r" newline bitfld.long 0x08 19. "OTGADEVHOSTEVNT,A-device Host Event" "OTGADEVHOSTEVNT_0_r,OTGADEVHOSTEVNT_1_r" newline bitfld.long 0x08 18. "OTGADEVHNPCHNGDETEVNT,A-device HNP change Detected Event" "OTGADEVHNPCHNGDETEVNT_0_r,OTGADEVHNPCHNGDETEVNT_1_r" newline bitfld.long 0x08 17. "OTGADEVSRPDETEVNT,A-device SRP Detected Event" "OTGADEVSRPDETEVNT_0_r,OTGADEVSRPDETEVNT_1_r" newline bitfld.long 0x08 16. "OTGADEVSESSENDDETEVNT,A-device Session End Detected Event" "OTGADEVSESSENDDETEVNT_0_r,OTGADEVSESSENDDETEVNT_1_r" newline bitfld.long 0x08 11. "OTGBDEVHOSTENDEVNT,B-device Host End Event" "OTGBDEVHOSTENDEVNT_0_r,OTGBDEVHOSTENDEVNT_1_r" newline bitfld.long 0x08 10. "OTGBDEVHNPCHNGEVNT,B-device HNP Change Event" "OTGBDEVHNPCHNGEVNT_0_r,OTGBDEVHNPCHNGEVNT_1_r" newline bitfld.long 0x08 9. "OTGBDEVSESSVLDDETEVNT,B-device Session Valid Detected Event" "OTGBDEVSESSVLDDETEVNT_0_r,OTGBDEVSESSVLDDETEVNT_1_r" newline bitfld.long 0x08 8. "OTGBDEVVBUSCHNGEVNT,B-device VBUS Change Event" "OTGBDEVVBUSCHNGEVNT_0_r,OTGBDEVVBUSCHNGEVNT_1_r" newline rbitfld.long 0x08 3. "BSESVLD,B-Session Valid" "BSESVLD_0_r,BSESVLD_1_r" newline rbitfld.long 0x08 2. "HSTNEGSTS,Host Negotiation Status" "HSTNEGSTS_0_r,HSTNEGSTS_1_r" newline rbitfld.long 0x08 1. "SESREQSTS,Session Request Status" "SESREQSTS_0_r,SESREQSTS_1_r" newline bitfld.long 0x08 0. "OEVTERROR,No errors currently defined" "OEVTERROR_0_r,OEVTERROR_1_r" line.long 0x0C "USB_OEVTEN,OTG event enable: OTG interrupt event enable" bitfld.long 0x0C 24. "OTGCONIDSTSCHNGEVNTEN,Connector ID Status Change Event Enable" "OTGCONIDSTSCHNGEVNTEN_0,OTGCONIDSTSCHNGEVNTEN_1" newline bitfld.long 0x0C 23. "HRRCONFNOTIFEVNTEN,Host Role Request Confirm Notifier Event Enable" "HRRCONFNOTIFEVNTEN_0,HRRCONFNOTIFEVNTEN_1" newline bitfld.long 0x0C 22. "HRRINITNOTIFEVNTEN,Host Role Request Initiate Notifier Event Enable" "HRRINITNOTIFEVNTEN_0,HRRINITNOTIFEVNTEN_1" newline bitfld.long 0x0C 21. "OTGADEVIDLEEVNTEN,A-device A-IDLE Event Enable" "OTGADEVIDLEEVNTEN_0,OTGADEVIDLEEVNTEN_1" newline bitfld.long 0x0C 20. "OTGADEVBHOSTENDEVNTEN,A-device B-host End Event Enable" "OTGADEVBHOSTENDEVNTEN_0,OTGADEVBHOSTENDEVNTEN_1" newline bitfld.long 0x0C 19. "OTGADEVHOSTEVNTEN,A-device Host Event Enable" "OTGADEVHOSTEVNTEN_0,OTGADEVHOSTEVNTEN_1" newline bitfld.long 0x0C 18. "OTGADEVHNPCHNGDETEVNTEN,A-device HNP change Detected Event Enable" "OTGADEVHNPCHNGDETEVNTEN_0,OTGADEVHNPCHNGDETEVNTEN_1" newline bitfld.long 0x0C 17. "OTGADEVSRPDETEVNTEN,A-device SRP Detected Event Enable" "OTGADEVSRPDETEVNTEN_0,OTGADEVSRPDETEVNTEN_1" newline bitfld.long 0x0C 16. "OTGADEVSESSENDDETEVNTEN,A-device Session End Detected Event Enable" "OTGADEVSESSENDDETEVNTEN_0,OTGADEVSESSENDDETEVNTEN_1" newline bitfld.long 0x0C 11. "OTGBDEVHOSTENDEVNTEN,B-device Host End Event Enable" "OTGBDEVHOSTENDEVNTEN_0,OTGBDEVHOSTENDEVNTEN_1" newline bitfld.long 0x0C 10. "OTGBDEVHNPCHNGEVNTEN,B-device HNP Change Event Enable" "OTGBDEVHNPCHNGEVNTEN_0,OTGBDEVHNPCHNGEVNTEN_1" newline bitfld.long 0x0C 9. "OTGBDEVSESSVLDDETEVNTEN,B-device Session Valid Detected Event Enable" "OTGBDEVSESSVLDDETEVNTEN_0,OTGBDEVSESSVLDDETEVNTEN_1" newline bitfld.long 0x0C 8. "OTGBDEVVBUSCHNGEVNTEN,B-device VBUS Change Event Enable" "OTGBDEVVBUSCHNGEVNTEN_0,OTGBDEVVBUSCHNGEVNTEN_1" line.long 0x10 "USB_OSTS,OTG status" bitfld.long 0x10 8.--11. "OTGSTATE,[A-device and B-device] OTG state machine state for debug" "OTGSTATE_0_r,OTGSTATE_1_r,OTGSTATE_2_r,OTGSTATE_3_r,OTGSTATE_4_r,OTGSTATE_5_r,OTGSTATE_6_r,OTGSTATE_7_r,OTGSTATE_8_r,OTGSTATE_9_r,OTGSTATE_10_r,OTGSTATE_11_r,OTGSTATE_12_r,OTGSTATE_13_r,OTGSTATE_14_r,OTGSTATE_15_r" newline bitfld.long 0x10 4. "PERIPHERALSTATE,[A-device and B-device] Current role of the controller" "PERIPHERALSTATE_0_r,PERIPHERALSTATE_1_r" newline bitfld.long 0x10 3. "XHCIPRTPOWER,[A-device] xHCI host port power" "0,1" newline bitfld.long 0x10 2. "BSESVLD,[B-device] VBUS B-session valid status" "BSESVLD_0_r,BSESVLD_1_r" newline bitfld.long 0x10 1. "VBUSVLD,[A-device] VBUS valid status" "VBUSVLD_0_r,VBUSVLD_1_r" newline bitfld.long 0x10 0. "CONIDSTS,[A-device and B-device] Connector ID status" "CONIDSTS_0_r,CONIDSTS_1_r" rgroup.long 0x28++0x03 line.long 0x00 "USB_PAGESIZE,Page size register (xHCI)" hexmask.long.word 0x00 0.--15. 1. "PAGE_SIZE,Supported system memory page size" group.long 0x42C++0x03 line.long 0x00 "USB_PORTHLPMC1,Port 1 (USB2.0) Hardware LPM Control (xHCI) Field structure is protocol-dependent (here: USB2.0)" bitfld.long 0x00 10.--13. "BESLD,See xHCI 1.0 standard w errata" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 2.--9. 1. "L1_TIMEOUT,See xHCI 1.0 standard w errata" newline bitfld.long 0x00 0.--1. "HIRDM,See xHCI 1.0 standard w errata" "0,1,2,3" hgroup.long 0x43C++0x03 hide.long 0x00 "USB_PORTHLPMC2,Port 2 (USB3.0) Hardware LPM Control (xHCI) Field structure is protocol-dependent (here: USB3.0)" rgroup.long 0x428++0x03 line.long 0x00 "USB_PORTLI1,Port 1 (USB2.0) link info (xHCI)" hexmask.long.word 0x00 0.--15. 1. "LINK_ERROR_COUNT,See xHCI specification" rgroup.long 0x438++0x03 line.long 0x00 "USB_PORTLI2,Port 2 (USB3.0) link info (xHCI)" hexmask.long.word 0x00 0.--15. 1. "LINK_ERROR_COUNT,See xHCI specification" group.long 0x424++0x03 line.long 0x00 "USB_PORTPMSC1,Port 1 (USB2.0) Power mManagement status and control (xHCI) Note that the PMSC register makeup is protocol-dependent (here: USB2.0)" bitfld.long 0x00 28.--31. "PORT_TEST_CONTROL,See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16. "HLE,See xHCI specification" "0,1" newline hexmask.long.byte 0x00 8.--15. 1. "L1_DEVICE_SLOT,See xHCI specification" newline bitfld.long 0x00 4.--7. "BESL,See xHCI 1.0 standard w" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 3. "RWE,See xHCI specification" "0,1" newline rbitfld.long 0x00 0.--2. "L1S,See xHCI specification" "0,1,2,3,4,5,6,7" group.long 0x434++0x03 line.long 0x00 "USB_PORTPMSC2,Port 2 (USB3.0) power management (LPM) status and control (xHCI) Note that the PMSC register makeup is protocol-dependent (here: USB3.0)" bitfld.long 0x00 16. "FLA,See xHCI specification" "0,1" newline hexmask.long.byte 0x00 8.--15. 1. "U2_TIMEOUT,See xHCI specification" newline hexmask.long.byte 0x00 0.--7. 1. "U1_TIMEOUT,See xHCI specification" group.long 0x420++0x03 line.long 0x00 "USB_PORTSC1,Port 1 (USB2.0) status and control (xHCI)" bitfld.long 0x00 31. "WPR,See xHCI specification" "0,1" newline rbitfld.long 0x00 30. "DR,See xHCI specification" "0,1" newline bitfld.long 0x00 27. "WOE,See xHCI specification" "0,1" newline bitfld.long 0x00 26. "WDE,See xHCI specification" "0,1" newline bitfld.long 0x00 25. "WCE,See xHCI specification" "0,1" newline rbitfld.long 0x00 24. "CAS,See xHCI specification" "0,1" newline bitfld.long 0x00 23. "CEC,See xHCI specification" "0,1" newline bitfld.long 0x00 22. "PLC,See xHCI specification" "0,1" newline bitfld.long 0x00 21. "PRC,See xHCI specification" "0,1" newline bitfld.long 0x00 20. "OCC,See xHCI specification" "0,1" newline bitfld.long 0x00 19. "WRC,See xHCI specification" "0,1" newline bitfld.long 0x00 18. "PEC,See xHCI specification" "0,1" newline bitfld.long 0x00 17. "CSC,See xHCI specification" "0,1" newline bitfld.long 0x00 16. "LWS,See xHCI specification" "0,1" newline bitfld.long 0x00 14.--15. "PIC,See xHCI specification" "0,1,2,3" newline rbitfld.long 0x00 10.--13. "PORTSPEED,See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9. "PP,See xHCI specification" "0,1" newline bitfld.long 0x00 5.--8. "PLS,See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "PR,See xHCI specification" "0,1" newline rbitfld.long 0x00 3. "OCA,See xHCI specification" "0,1" newline bitfld.long 0x00 1. "PED,See xHCI specification" "0,1" newline rbitfld.long 0x00 0. "CCS,See xHCI specification" "0,1" group.long 0x430++0x03 line.long 0x00 "USB_PORTSC2,Port 2 (USB3.0) status and control (xHCI)" bitfld.long 0x00 31. "WPR,See xHCI specification" "0,1" newline rbitfld.long 0x00 30. "DR,See xHCI specification" "0,1" newline bitfld.long 0x00 27. "WOE,See xHCI specification" "0,1" newline bitfld.long 0x00 26. "WDE,See xHCI specification" "0,1" newline bitfld.long 0x00 25. "WCE,See xHCI specification" "0,1" newline rbitfld.long 0x00 24. "CAS,See xHCI specification" "0,1" newline bitfld.long 0x00 23. "CEC,See xHCI specification" "0,1" newline bitfld.long 0x00 22. "PLC,See xHCI specification" "0,1" newline bitfld.long 0x00 21. "PRC,See xHCI specification" "0,1" newline bitfld.long 0x00 20. "OCC,See xHCI specification" "0,1" newline bitfld.long 0x00 19. "WRC,See xHCI specification" "0,1" newline bitfld.long 0x00 18. "PEC,See xHCI specification" "0,1" newline bitfld.long 0x00 17. "CSC,See xHCI specification" "0,1" newline bitfld.long 0x00 16. "LWS,See xHCI specification" "0,1" newline bitfld.long 0x00 14.--15. "PIC,See xHCI specification" "0,1,2,3" newline rbitfld.long 0x00 10.--13. "PORTSPEED,See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9. "PP,See xHCI specification" "0,1" newline bitfld.long 0x00 5.--8. "PLS,See xHCI specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "PR,See xHCI specification" "0,1" newline rbitfld.long 0x00 3. "OCA,See xHCI specification" "0,1" newline bitfld.long 0x00 1. "PED,See xHCI specification" "0,1" newline rbitfld.long 0x00 0. "CCS,See xHCI specification" "0,1" rgroup.long 0x18++0x03 line.long 0x00 "USB_RTSOFF,RunTime space offset (xHCI): Byte offset of the runtime register bank (starting with). with respect to the xHCI base (that is. register)" hexmask.long 0x00 5.--31. 1. "RUNTIME_REG_SPACE_OFFSET,Byte address offset MSBs" newline bitfld.long 0x00 0.--4. "ZERO,Byte address offset LSBs always 0 (offset is 32-byte aligned)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x890++0x1F line.long 0x00 "USB_SUPTPRT2_DW0,Supported protocol capability USB2.0. 32-bit dword 0" hexmask.long.byte 0x00 24.--31. 1. "MAJREV,Major Revision BCD-encoded" newline hexmask.long.byte 0x00 16.--23. 1. "MINREV,Minor Revision BCD-encoded" newline hexmask.long.byte 0x00 8.--15. 1. "NCP,Next Capability Pointer: 32-bit dword offset of the next capability" newline hexmask.long.byte 0x00 0.--7. 1. "ECID,Extended Capability ID code (descriptor size in bytes) - prot" line.long 0x04 "USB_SUPTPRT2_DW1,Supported protocol capability USB2.0. 32-bit dword" hexmask.long.byte 0x04 24.--31. 1. "CHAR3,ASCII ' ' (space)" newline hexmask.long.byte 0x04 16.--23. 1. "CHAR2,ASCII 'B'" newline hexmask.long.byte 0x04 8.--15. 1. "CHAR1,ASCII 'S'" newline hexmask.long.byte 0x04 0.--7. 1. "CHAR0,ASCII 'U'" line.long 0x08 "USB_SUPTPRT2_DW2,Supported protocol capability USB2.0. 32-bit dword 2" bitfld.long 0x08 28.--31. "PSIC,Port Speed ID Count" "PSIC_0_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x08 19. "HLC,Hardware LPM Capability" "0,1" newline bitfld.long 0x08 18. "IHI,Integrated Hub Implemented" "0,1" newline bitfld.long 0x08 17. "HSO,High-Speed Only" "0,1" newline hexmask.long.byte 0x08 8.--15. 1. "CPC,Compatible Port Count: Number of consecutive ports of the root hub that support this protocol from CPO to CPO+CPC-1" newline hexmask.long.byte 0x08 0.--7. 1. "CPO,Compatible Port Offset: Starting port number of root hub port(s) that support this protocol" line.long 0x0C "USB_SUPTPRT2_DW3,Supported protocol capability USB2.0. 32-bit dword 3" bitfld.long 0x0C 0.--4. "PST,Protocol Slot Type see xHCI 1.0 standard w errata" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "USB_SUPTPRT3_DW0,Supported protocol capability USB3.0. 32-bit dword 0" hexmask.long.byte 0x10 24.--31. 1. "MAJREV,Major Revision BCD-encoded" newline hexmask.long.byte 0x10 16.--23. 1. "MINREV,Minor Revision BCD-encoded" newline hexmask.long.byte 0x10 8.--15. 1. "NCP,Next Capability Pointer: 32-bit dword offset of the next capability" newline hexmask.long.byte 0x10 0.--7. 1. "ECID,Extended Capability ID code (descriptor size in bytes) - prot" line.long 0x14 "USB_SUPTPRT3_DW1,Supported protocol capability USB3.0. 32-bit dword" hexmask.long.byte 0x14 24.--31. 1. "CHAR3,ASCII ' ' (space)" newline hexmask.long.byte 0x14 16.--23. 1. "CHAR2,ASCII 'B'" newline hexmask.long.byte 0x14 8.--15. 1. "CHAR1,ASCII 'S'" newline hexmask.long.byte 0x14 0.--7. 1. "CHAR0,ASCII 'U'" line.long 0x18 "USB_SUPTPRT3_DW2,Supported protocol capability USB3.0. 32-bit dword 2" bitfld.long 0x18 28.--31. "PSIC,Port Speed ID Count" "PSIC_0_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline hexmask.long.byte 0x18 8.--15. 1. "CPC,Compatible Port Count: Number of consecutive ports of the root hub that support this protocol from CPO to CPO+CPC-1" newline hexmask.long.byte 0x18 0.--7. 1. "CPO,Compatible Port Offset: Starting port number of root hub port(s) that support this protocol" line.long 0x1C "USB_SUPTPRT3_DW3,Supported protocol capability USB3.0. 32-bit dword 3" bitfld.long 0x1C 0.--4. "PST,Protocol Slot Type see xHCI 1.0 standard with errata" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "USB_USBCMD,USB command register (xHCI)" bitfld.long 0x00 11. "EU3S,Enable U3 MFINDEX Stop: See xHCI specification" "0,1" newline bitfld.long 0x00 10. "EWE,Enable Wrap Event: See xHCI specification" "0,1" newline bitfld.long 0x00 9. "CRS,Controller Restore State: See xHCI specification" "0,1" newline bitfld.long 0x00 8. "CSS,Controller Save State: See xHCI specification" "0,1" newline bitfld.long 0x00 7. "LHCRST,Light Host Controller Reset: See xHCI specification" "0,1" newline bitfld.long 0x00 3. "HSEE,Host System Error Enable: See xHCI specification" "0,1" newline bitfld.long 0x00 2. "INTE,Interrupter Enable: See xHCI specification" "0,1" newline bitfld.long 0x00 1. "HCRST,Host Controller Reset: See xHCI specification" "0,1" newline bitfld.long 0x00 0. "R_S,Run/Stop: See xHCI specification" "0,1" group.long 0x884++0x03 line.long 0x00 "USB_USBLEGCTLSTS,USB legacy control/status" bitfld.long 0x00 31. "SB,See xHCI specification" "0,1" newline bitfld.long 0x00 30. "SPC,See xHCI specification" "0,1" newline bitfld.long 0x00 29. "SOOC,See xHCI specification" "0,1" newline rbitfld.long 0x00 20. "SHSE,See xHCI specification" "0,1" newline rbitfld.long 0x00 16. "SEI,See xHCI specification" "0,1" newline bitfld.long 0x00 15. "SBE,See xHCI specification" "0,1" newline bitfld.long 0x00 14. "SPCE,See xHCI specification" "0,1" newline bitfld.long 0x00 13. "SOOE,See xHCI specification" "0,1" newline bitfld.long 0x00 4. "SHSEE,See xHCI specification" "0,1" newline bitfld.long 0x00 0. "USE,See xHCI specification" "0,1" group.long 0x880++0x03 line.long 0x00 "USB_USBLEGSUP,USB legacy support capability" bitfld.long 0x00 24. "HCOOS,HC OS Owned Semaphore: See xHCI specification" "0,1" newline bitfld.long 0x00 16. "HCBOS,HC BIOS Owned Semaphore: See xHCI specification" "0,1" newline hexmask.long.byte 0x00 8.--15. 1. "NCP,Next Capability Pointer: 32-bit dword offset of the next capability" newline hexmask.long.byte 0x00 0.--7. 1. "ECID,Extended Capability ID code (descriptor size in bytes) - prot" group.long 0x24++0x03 line.long 0x00 "USB_USBSTS,USB status register (xHCI)" rbitfld.long 0x00 12. "HCE,Host Controller Error: See xHCI specification" "0,1" newline rbitfld.long 0x00 11. "CNR,Controller not ready (see xHCI specification)" "CNR_0_r,CNR_1_r" newline bitfld.long 0x00 10. "SRE,Save/Restore Error: See xHCI specification" "0,1" newline rbitfld.long 0x00 9. "RSS,Restore State Status: See xHCI specification" "0,1" newline rbitfld.long 0x00 8. "SSS,Save State Status: See xHCI specification" "0,1" newline bitfld.long 0x00 4. "PCD,Port Change Detect: See xHCI specification" "0,1" newline bitfld.long 0x00 3. "EINT,Event Interrupt: See xHCI specification" "0,1" newline bitfld.long 0x00 2. "HSE,Host System Error: See xHCI specification" "0,1" newline rbitfld.long 0x00 0. "HCH,Host Controller Halted: See xHCI specification" "0,1" tree.end repeat.end repeat 4. (list 1. 2. 3. 4. )(list ad:0x48880000 ad:0x488C0000 ad:0x48900000 ad:0x48940000 ) tree "USB_WRAPPER$1" base $2 rgroup.long 0x00++0x03 line.long 0x00 "USB_REVISION,USB_WRAPPER Revision Identifier" group.long 0x10++0x03 line.long 0x00 "USB_SYSCONFIG,Controls various parameters of the master and slave interfaces" bitfld.long 0x00 17. "WRAPRESET,Software reset for the USB_WRAPPER register set" "WRAPRESET_0_r,WRAPRESET_1_r" bitfld.long 0x00 16. "DMADISABLE,Disable/Enable control of the DMA master (initiator) to block read/write accesses" "DMADISABLE_0_r,DMADISABLE_1_r" newline bitfld.long 0x00 4.--5. "STANDBYMODE,PM mode of local initiator (master)" "STANDBYMODE_0,STANDBYMODE_1,STANDBYMODE_2,STANDBYMODE_3" bitfld.long 0x00 2.--3. "IDLEMODE,PM mode of local target (slave)" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" group.long 0x20++0x23 line.long 0x00 "USB_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output" bitfld.long 0x00 0.--4. "LINE_NUMBER,Write the IRQ line number to apply SW EOI to it" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "USB_IRQSTATUS_RAW_0,Raw status of main core interrupt request" bitfld.long 0x04 0. "COREIRQ_ST,IRQ status for core: see status registerUSB_IMAN[0] IP" "COREIRQ_ST_0_r,COREIRQ_ST_1_r" line.long 0x08 "USB_IRQSTATUS_0,'regular' status of main core interrupt request" bitfld.long 0x08 0. "COREIRQ_ST,IRQ status for core: see status registerUSB_IMAN[0] IP - noaction" "COREIRQ_ST_0_r,COREIRQ_ST_1_r" line.long 0x0C "USB_IRQENABLE_SET_0,Enable of main core interrupt request" bitfld.long 0x0C 0. "COREIRQ_EN,IRQ enable for main core interrupt - noaction" "COREIRQ_EN_0_r,COREIRQ_EN_1_r" line.long 0x10 "USB_IRQENABLE_CLR_0,Enable of main core interrupt request" bitfld.long 0x10 0. "COREIRQ_EN,IRQ enable for main core interrupt - noaction" "COREIRQ_EN_0_r,COREIRQ_EN_1_r" line.long 0x14 "USB_IRQSTATUS_RAW_1,Raw status of secondary interrupt requests" bitfld.long 0x14 17. "DMADISABLECLR,DMA-disable self-clear IRQ status:USB_SYSCONFIG[17] DMADISABLE hardware-cleared (to 0) because of DMA access" "DMADISABLECLR_0_r,DMADISABLECLR_1_r" bitfld.long 0x14 16. "OEVT,OTG event in core IRQ status: see status registerUSB_OEVT - noaction" "OEVT_0_r,OEVT_1_r" newline bitfld.long 0x14 13. "DRVVBUS_RISE,Drive VBUS control rise IRQ status - noaction" "DRVVBUS_RISE_0_r,DRVVBUS_RISE_1_r" bitfld.long 0x14 12. "CHRGVBUS_RISE,Charge VBUS control rise IRQ status - noaction" "CHRGVBUS_RISE_0_r,CHRGVBUS_RISE_1_r" newline bitfld.long 0x14 11. "DISCHRGVBUS_RISE,Discharge VBUS control rise IRQ status - noaction" "DISCHRGVBUS_RISE_0_r,DISCHRGVBUS_RISE_1_r" bitfld.long 0x14 8. "IDPULLUP_RISE,ID pullup control rise IRQ status - noaction" "IDPULLUP_RISE_0_r,IDPULLUP_RISE_1_r" newline bitfld.long 0x14 5. "DRVVBUS_FALL,Drive VBUS control fall IRQ status - noaction" "DRVVBUS_FALL_0_r,DRVVBUS_FALL_1_r" bitfld.long 0x14 4. "CHRGVBUS_FALL,Charge VBUS control fall IRQ status - noaction" "CHRGVBUS_FALL_0_r,CHRGVBUS_FALL_1_r" newline bitfld.long 0x14 3. "DISCHRGVBUS_FALL,Discharge VBUS control fall IRQ status - noaction" "DISCHRGVBUS_FALL_0_r,DISCHRGVBUS_FALL_1_r" bitfld.long 0x14 0. "IDPULLUP_FALL,ID pullup control fall IRQ status - noaction" "IDPULLUP_FALL_0_r,IDPULLUP_FALL_1_r" line.long 0x18 "USB_IRQSTATUS_1,Regular status of secondary interrupt requests" bitfld.long 0x18 17. "DMADISABLECLR,DMA-disable self-clear IRQ status:USB_SYSCONFIG[17] DMADISABLE hardware-cleared (to 0) because of DMA access" "DMADISABLECLR_0_r,DMADISABLECLR_1_r" bitfld.long 0x18 16. "OEVT,OTG event in core IRQ status: see status registerUSB_OEVT" "OEVT_0_r,OEVT_1_r" newline bitfld.long 0x18 13. "DRVVBUS_RISE,Drive VBUS control rise IRQ status - noaction" "DRVVBUS_RISE_0_r,DRVVBUS_RISE_1_r" bitfld.long 0x18 12. "CHRGVBUS_RISE,Charge VBUS control rise IRQ status - noaction" "CHRGVBUS_RISE_0_r,CHRGVBUS_RISE_1_r" newline bitfld.long 0x18 11. "DISCHRGVBUS_RISE,Discharge VBUS control rise IRQ status - noaction" "DISCHRGVBUS_RISE_0_r,DISCHRGVBUS_RISE_1_r" bitfld.long 0x18 8. "IDPULLUP_RISE,ID pullup control rise IRQ status - noaction" "IDPULLUP_RISE_0_r,IDPULLUP_RISE_1_r" newline bitfld.long 0x18 5. "DRVVBUS_FALL,Drive VBUS control fall IRQ status - noaction" "DRVVBUS_FALL_0_r,DRVVBUS_FALL_1_r" bitfld.long 0x18 4. "CHRGVBUS_FALL,Charge VBUS control fall IRQ status - noaction" "CHRGVBUS_FALL_0_r,CHRGVBUS_FALL_1_r" newline bitfld.long 0x18 3. "DISCHRGVBUS_FALL,Discharge VBUS control fall IRQ status - noaction" "DISCHRGVBUS_FALL_0_r,DISCHRGVBUS_FALL_1_r" bitfld.long 0x18 0. "IDPULLUP_FALL,ID pullup control fall IRQ status - noaction" "IDPULLUP_FALL_0_r,IDPULLUP_FALL_1_r" line.long 0x1C "USB_IRQENABLE_SET_1,Enable secondary interrupt requests" bitfld.long 0x1C 17. "DMADISABLECLR_EN,DMA-disable self-clear IRQ enable - noaction" "DMADISABLECLR_EN_0_r,DMADISABLECLR_EN_1_r" bitfld.long 0x1C 16. "OEVT_EN,OTG event in core IRQ enable - noaction" "OEVT_EN_0_r,OEVT_EN_1_r" newline bitfld.long 0x1C 13. "DRVVBUS_RISE_EN,Drive VBUS control rise IRQ enable - noaction" "DRVVBUS_RISE_EN_0_r,DRVVBUS_RISE_EN_1_r" bitfld.long 0x1C 12. "CHRGVBUS_RISE_EN,Charge VBUS control rise IRQ enable - noaction" "CHRGVBUS_RISE_EN_0_r,CHRGVBUS_RISE_EN_1_r" newline bitfld.long 0x1C 11. "DISCHRGVBUS_RISE_EN,Discharge VBUS control rise IRQ enable - noaction" "DISCHRGVBUS_RISE_EN_0_r,DISCHRGVBUS_RISE_EN_1_r" bitfld.long 0x1C 8. "IDPULLUP_RISE_EN,ID pullup control rise IRQ enable - noaction" "IDPULLUP_RISE_EN_0_r,IDPULLUP_RISE_EN_1_r" newline bitfld.long 0x1C 5. "DRVVBUS_FALL_EN,Drive VBUS control fall IRQ enable - noaction" "DRVVBUS_FALL_EN_0_r,DRVVBUS_FALL_EN_1_r" bitfld.long 0x1C 4. "CHRGVBUS_FALL_EN,Charge VBUS control fall IRQ enable - noaction" "CHRGVBUS_FALL_EN_0_r,CHRGVBUS_FALL_EN_1_r" newline bitfld.long 0x1C 3. "DISCHRGVBUS_FALL_EN,Discharge VBUS control fall IRQ enable - noaction" "DISCHRGVBUS_FALL_EN_0_r,DISCHRGVBUS_FALL_EN_1_r" bitfld.long 0x1C 0. "IDPULLUP_FALL_EN,ID pullup control fall IRQ enable - noaction" "IDPULLUP_FALL_EN_0_r,IDPULLUP_FALL_EN_1_r" line.long 0x20 "USB_IRQENABLE_CLR_1,Enable secondary interrupt requests" bitfld.long 0x20 17. "DMADISABLECLR_EN,DMA-disable self-clear IRQ enable - noaction" "DMADISABLECLR_EN_0_r,DMADISABLECLR_EN_1_r" bitfld.long 0x20 16. "OEVT_EN,OTG event in core IRQ enable - noaction" "OEVT_EN_0_r,OEVT_EN_1_r" newline bitfld.long 0x20 13. "DRVVBUS_RISE_EN,Drive VBUS control rise IRQ enable - noaction" "DRVVBUS_RISE_EN_0_r,DRVVBUS_RISE_EN_1_r" bitfld.long 0x20 12. "CHRGVBUS_RISE_EN,Charge VBUS control rise IRQ enable - noaction" "CHRGVBUS_RISE_EN_0_r,CHRGVBUS_RISE_EN_1_r" newline bitfld.long 0x20 11. "DISCHRGVBUS_RISE_EN,Discharge VBUS control rise IRQ enable - noaction" "DISCHRGVBUS_RISE_EN_0_r,DISCHRGVBUS_RISE_EN_1_r" bitfld.long 0x20 8. "IDPULLUP_RISE_EN,ID pullup control rise IRQ enable - noaction" "IDPULLUP_RISE_EN_0_r,IDPULLUP_RISE_EN_1_r" newline bitfld.long 0x20 5. "DRVVBUS_FALL_EN,Drive VBUS control fall IRQ enable - noaction" "DRVVBUS_FALL_EN_0_r,DRVVBUS_FALL_EN_1_r" bitfld.long 0x20 4. "CHRGVBUS_FALL_EN,Charge VBUS control fall IRQ enable - noaction" "CHRGVBUS_FALL_EN_0_r,CHRGVBUS_FALL_EN_1_r" newline bitfld.long 0x20 3. "DISCHRGVBUS_FALL_EN,Discharge VBUS control fall IRQ enable - noaction" "DISCHRGVBUS_FALL_EN_0_r,DISCHRGVBUS_FALL_EN_1_r" bitfld.long 0x20 0. "IDPULLUP_FALL_EN,ID pullup control fall IRQ enable - noaction" "IDPULLUP_FALL_EN_0_r,IDPULLUP_FALL_EN_1_r" rgroup.long 0x80++0x07 line.long 0x00 "USB_UTMI_OTG_CTRL," bitfld.long 0x00 5. "DRVVBUS,Drive 5V on VBUS" "DRVVBUS_0_r,DRVVBUS_1_r" bitfld.long 0x00 4. "CHRGVBUS,Charge VBUS through a resistor for VBUS-pulsing SRP" "CHRGVBUS_0_r,CHRGVBUS_1_r" newline bitfld.long 0x00 3. "DISCHRGVBUS,Discharge VBUS through a resistor until the session-end VBUS state is reached" "DISCHRGVBUS_0_r,DISCHRGVBUS_1_r" bitfld.long 0x00 0. "IDPULLUP,Pull-up to the (OTG) ID line to allow its sampling - Enable" "IDPULLUP_0_r,IDPULLUP_1_r" line.long 0x04 "USB_UTMI_OTG_STATUS," bitfld.long 0x04 31. "SW_MODE,Controls the source of UTMI / PIPE status for VBUS and OTG ID (vbusvalid sessvalid sessend iddig powerpresent) - io" "SW_MODE_0,SW_MODE_1" bitfld.long 0x04 10. "PORT_OVERCURRENT,Over-current status for non-OTG host only" "PORT_OVERCURRENT_0,PORT_OVERCURRENT_1" newline bitfld.long 0x04 9. "POWERPRESENT,Software-programmed value of PIPE3.0 PowerPresent (VBUS status) seen by the core alternative to HW input" "0,1" bitfld.long 0x04 8. "TXBITSTUFFENABLE,Software-programmed UTMI output txbitstuffenable[h] Note: as per UTMI+ used only in UTMI Opmode 0b11 (i.e. SYNC and EOP generation disabled) - nobs" "TXBITSTUFFENABLE_0,TXBITSTUFFENABLE_1" newline bitfld.long 0x04 4. "IDDIG,Software-programmed value of UTMI+ IdDig (OTG ID status) seen by the core alternative to hardware input" "IDDIG_0,IDDIG_1" bitfld.long 0x04 3. "SESSEND,Software-programmed value of UTMI+ SessEnd (VBUS status) seen by the core alternative to HW input" "SESSEND_0,SESSEND_1" newline bitfld.long 0x04 2. "SESSVALID,Software-programmed value of UTMI+ SessValid (VBUS status) seen by the core alternative to hardware inputs AValid and BValid" "SESSVALID_0,SESSVALID_1" bitfld.long 0x04 1. "VBUSVALID,Software-programmed value of UTMI+ VbusValid (VBUS status) seen by the core alternative to hardware input" "VBUSVALID_0,VBUSVALID_1" group.long 0x100++0x13 line.long 0x00 "USB_MMRAM_OFFSET,Offset of Memory-mapped RAM accesses" bitfld.long 0x00 15.--19. "OFFSET_MSB,Byte offset MSBits = page offset - core_bot" "OFFSET_MSB_0,OFFSET_MSB_1,?,?,?,?,?,?,OFFSET_MSB_8,?,?,?,?,?,?,?,OFFSET_MSB_16,?,?,?,?,?,?,?,OFFSET_MSB_24,?,?,?,?,?,?,?" hexmask.long.word 0x00 0.--14. 1. "OFFSET_LSB,Byte offset LSBits always 0" line.long 0x04 "USB_FLADJ,Jitter adjustment and other pseudo-static parameters" bitfld.long 0x04 31. "CORE_SW_RESET,Active-high core software reset" "CORE_SW_RESET_0,CORE_SW_RESET_1" bitfld.long 0x04 29. "XHCI_REVISION,Switches to the legacy xHCI 0.96 host SW API mode" "XHCI_REVISION_0,XHCI_REVISION_1" newline bitfld.long 0x04 28. "HOST_U3_PORT_DISABLE,USB3.0 port disable overriding xHCI driver" "HOST_U3_PORT_DISABLE_0,HOST_U3_PORT_DISABLE_1" bitfld.long 0x04 27. "HOST_U2_PORT_DISABLE,USB2.0 port disable overriding xHCI driver" "HOST_U2_PORT_DISABLE_0,HOST_U2_PORT_DISABLE_1" newline bitfld.long 0x04 21.--26. "FLADJ_30MHZ,HS Jitter Adjustment in 30-MHz periods" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "USB_DEBUG_CFG,Configuration of debug output (observability)" bitfld.long 0x08 0.--2. "SEL,selection of observed local signals - UTMI" "SEL_0,SEL_1,SEL_2,SEL_3,SEL_4,SEL_5,?,?" line.long 0x0C "USB_DEBUG_DATA,Data currently visible on DEBUG output (observability) port See [2:0] SEL bit field" bitfld.long 0x0C 31. "DEBUG31,SEL =" "0,1" bitfld.long 0x0C 30. "DEBUG30,SEL =" "0,1" newline bitfld.long 0x0C 29. "DEBUG29,SEL =" "0,1" bitfld.long 0x0C 28. "DEBUG28,SEL =" "0,1" newline bitfld.long 0x0C 27. "DEBUG27,SEL =" "0,1" bitfld.long 0x0C 26. "DEBUG26,SEL =" "0,1" newline bitfld.long 0x0C 25. "DEBUG25,SEL =" "0,1" bitfld.long 0x0C 24. "DEBUG24,SEL =" "0,1" newline bitfld.long 0x0C 23. "DEBUG23,SEL =" "0,1" bitfld.long 0x0C 22. "DEBUG22,SEL =" "0,1" newline bitfld.long 0x0C 21. "DEBUG21,SEL =" "0,1" bitfld.long 0x0C 20. "DEBUG20,SEL =" "0,1" newline bitfld.long 0x0C 19. "DEBUG19,SEL =" "0,1" bitfld.long 0x0C 18. "DEBUG18,SEL =" "0,1" newline bitfld.long 0x0C 17. "DEBUG17,SEL =" "0,1" bitfld.long 0x0C 16. "DEBUG16,SEL =" "0,1" newline bitfld.long 0x0C 15. "DEBUG15,SEL =" "0,1" bitfld.long 0x0C 14. "DEBUG14,SEL =" "0,1" newline bitfld.long 0x0C 13. "DEBUG13,SEL =" "0,1" bitfld.long 0x0C 12. "DEBUG12,SEL =" "0,1" newline bitfld.long 0x0C 11. "DEBUG11,SEL =" "0,1" bitfld.long 0x0C 10. "DEBUG10,SEL =" "0,1" newline bitfld.long 0x0C 9. "DEBUG9,SEL =" "0,1" bitfld.long 0x0C 8. "DEBUG8,SEL =" "0,1" newline bitfld.long 0x0C 7. "DEBUG7,SEL =" "0,1" bitfld.long 0x0C 6. "DEBUG6,SEL =" "0,1" newline bitfld.long 0x0C 5. "DEBUG5,SEL =" "0,1" bitfld.long 0x0C 4. "DEBUG4,SEL =" "0,1" newline bitfld.long 0x0C 3. "DEBUG3,SEL =" "0,1" bitfld.long 0x0C 2. "DEBUG2,SEL =" "0,1" newline bitfld.long 0x0C 1. "DEBUG1,SEL =" "0,1" bitfld.long 0x0C 0. "DEBUG0,SEL =" "0,1" line.long 0x10 "USB_DEV_EBC_EN,Enable External Buffer Control (EBC) for selected endpoints" bitfld.long 0x10 31. "OUTEP15,Enable EBC HW throttling for OUT EP 15 (USB receive) - dis" "OUTEP15_0,OUTEP15_1" bitfld.long 0x10 15. "INEP15,Enable EBC HW throttling for IN EP 15 (USB transmit) - dis" "INEP15_0,INEP15_1" tree.end repeat.end tree.end tree.open "System_DMA" tree "DMA_SYSTEM" base ad:0x4A056000 rgroup.long 0x00++0x03 line.long 0x00 "DMA4_REVISION,This register contains the DMA revision code" rgroup.long 0x28++0x07 line.long 0x00 "DMA4_SYSSTATUS,The register provides status information about the module excluding the interrupt status information (see interrupt status register)" bitfld.long 0x00 0. "RESETDONE,Internal reset monitoring - OnGoing" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x04 "DMA4_OCP_SYSCONFIG,DMA system configuration register" bitfld.long 0x04 12.--13. "MIDLEMODE,Read write power management standby/wait control - Force" "MIDLEMODE_0,MIDLEMODE_1,MIDLEMODE_2,MIDLEMODE_3" newline rbitfld.long 0x04 8.--9. "CLOCKACTIVITY,Clocks activities during wake-up Bit" "0,1,2,3" newline bitfld.long 0x04 5. "EMUFREE,Enable sensitivity to MSuspend - Frozen" "EMUFREE_0,EMUFREE_1" newline bitfld.long 0x04 3.--4. "SIDLEMODE,Configuration port power management Idle req/ack control - Force" "SIDLEMODE_0,SIDLEMODE_1,SIDLEMODE_2,SIDLEMODE_3" newline bitfld.long 0x04 0. "AUTOIDLE,Internal interface clock gating strategy - FreeRunning" "AUTOIDLE_0,AUTOIDLE_1" rgroup.long 0x64++0x03 line.long 0x00 "DMA4_CAPS_0,DMA Capabilities Register 0 LSW" bitfld.long 0x00 21. "LINK_LIST_CPBLTY_TYPE4,Link List capability for type4 descriptor capability" "LINK_LIST_CPBLTY_TYPE4_0,LINK_LIST_CPBLTY_TYPE4_1" newline bitfld.long 0x00 20. "LINK_LIST_CPBLTY_TYPE123,Link List capability for type123 descriptor capability" "LINK_LIST_CPBLTY_TYPE123_0,LINK_LIST_CPBLTY_TYPE123_1" newline bitfld.long 0x00 19. "CONST_FILL_CPBLTY,Constant_Fill_Capability - NoLCH" "CONST_FILL_CPBLTY_0_r,CONST_FILL_CPBLTY_1_r" newline bitfld.long 0x00 18. "TRANSPARENT_BLT_CPBLTY,Transparent_BLT_Capability - NoLCH" "TRANSPARENT_BLT_CPBLTY_0_r,TRANSPARENT_BLT_CPBLTY_1_r" rgroup.long 0x6C++0x0F line.long 0x00 "DMA4_CAPS_2,DMA Capabilities Register 2" bitfld.long 0x00 8. "SEPARATE_SRC_AND_DST_INDEX_CPBLTY,Separate_source/destination_index_capability - NotSupported" "SEPARATE_SRC_AND_DST_INDEX_CPBLTY_0_r,SEPARATE_SRC_AND_DST_INDEX_CPBLTY_1_r" newline bitfld.long 0x00 7. "DST_DOUBLE_INDEX_ADRS_CPBLTY,Destination_double_index_address_capability - NotSupported" "DST_DOUBLE_INDEX_ADRS_CPBLTY_0_r,DST_DOUBLE_INDEX_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 6. "DST_SINGLE_INDEX_ADRS_CPBLTY,Destination_single_index_address_capability - NotSupported" "DST_SINGLE_INDEX_ADRS_CPBLTY_0_r,DST_SINGLE_INDEX_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 5. "DST_POST_INCRMNT_ADRS_CPBLTY,Destination_post_increment_address_capability - NotSupported" "DST_POST_INCRMNT_ADRS_CPBLTY_0_r,DST_POST_INCRMNT_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 4. "DST_CONST_ADRS_CPBLTY,Destination_constant_address_capability - NotSupported" "DST_CONST_ADRS_CPBLTY_0_r,DST_CONST_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 3. "SRC_DOUBLE_INDEX_ADRS_CPBLTY,Source_double_index_address_capability - NotSupported" "SRC_DOUBLE_INDEX_ADRS_CPBLTY_0_r,SRC_DOUBLE_INDEX_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 2. "SRC_SINGLE_INDEX_ADRS_CPBLTY,Source_single_index_address_capability - NotSupported" "SRC_SINGLE_INDEX_ADRS_CPBLTY_0_r,SRC_SINGLE_INDEX_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 1. "SRC_POST_INCREMENT_ADRS_CPBLTY,Source_post_increment_address_capability - NotSupported" "SRC_POST_INCREMENT_ADRS_CPBLTY_0_r,SRC_POST_INCREMENT_ADRS_CPBLTY_1_r" newline bitfld.long 0x00 0. "SRC_CONST_ADRS_CPBLTY,Source_constant_address_capability - NotSupported" "SRC_CONST_ADRS_CPBLTY_0_r,SRC_CONST_ADRS_CPBLTY_1_r" line.long 0x04 "DMA4_CAPS_3,DMA Capabilities Register 3" bitfld.long 0x04 7. "BLOCK_SYNCHR_CPBLTY," "BLOCK_SYNCHR_CPBLTY_0_r,BLOCK_SYNCHR_CPBLTY_1_r" newline bitfld.long 0x04 6. "PKT_SYNCHR_CPBLTY,Packet_synchronization_capability - NotSupported" "PKT_SYNCHR_CPBLTY_0_r,PKT_SYNCHR_CPBLTY_1_r" newline bitfld.long 0x04 5. "CHANNEL_CHANINIG_CPBLTY," "CHANNEL_CHANINIG_CPBLTY_0_r,CHANNEL_CHANINIG_CPBLTY_1_r" newline bitfld.long 0x04 4. "CHANNEL_INTERLEAVE_CPBLTY," "CHANNEL_INTERLEAVE_CPBLTY_0_r,CHANNEL_INTERLEAVE_CPBLTY_1_r" newline bitfld.long 0x04 1. "FRAME_SYNCHR_CPBLTY," "FRAME_SYNCHR_CPBLTY_0_r,FRAME_SYNCHR_CPBLTY_1_r" newline bitfld.long 0x04 0. "ELMNT_SYNCHR_CPBLTY," "ELMNT_SYNCHR_CPBLTY_0_r,ELMNT_SYNCHR_CPBLTY_1_r" line.long 0x08 "DMA4_CAPS_4,DMA Capabilities Register 4" bitfld.long 0x08 14. "EOSB_INTERRUPT_CPBLTY,End of Super Block detection capability" "EOSB_INTERRUPT_CPBLTY_0,EOSB_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 12. "DRAIN_END_INTERRUPT_CPBLTY,Drain End detection capability" "DRAIN_END_INTERRUPT_CPBLTY_0,DRAIN_END_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 11. "MISALIGNED_ADRS_ERR_INTERRUPT_CPBLTY,Misaligned error detection capability" "MISALIGNED_ADRS_ERR_INTERRUPT_CPBLTY_0,MISALIGNED_ADRS_ERR_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 10. "SUPERVISOR_ERR_INTERRUPT_CPBLTY,Supervisor error detection capability" "SUPERVISOR_ERR_INTERRUPT_CPBLTY_0,SUPERVISOR_ERR_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 8. "TRANS_ERR_INTERRUPT_CPBLTY,Transaction error detection capability" "TRANS_ERR_INTERRUPT_CPBLTY_0,TRANS_ERR_INTERRUPT_CPBLTY_1" newline bitfld.long 0x08 7. "PKT_INTERRUPT_CPBLTY,End of Packet detection capability" "PKT_INTERRUPT_CPBLTY_0_r,PKT_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 6. "SYNC_STATUS_CPBLTY,Sync_status_capability - NotSupported" "SYNC_STATUS_CPBLTY_0_r,SYNC_STATUS_CPBLTY_1_r" newline bitfld.long 0x08 5. "BLOCK_INTERRUPT_CPBLTY,End of block detection capability" "BLOCK_INTERRUPT_CPBLTY_0_r,BLOCK_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 4. "LAST_FRAME_INTERRUPT_CPBLTY,Start of last frame detection capability" "LAST_FRAME_INTERRUPT_CPBLTY_0_r,LAST_FRAME_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 3. "FRAME_INTERRUPT_CPBLTY,End of frame detection capability" "FRAME_INTERRUPT_CPBLTY_0_r,FRAME_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 2. "HALF_FRAME_INTERRUPT_CPBLTY,Detection capability of the half of frame end" "HALF_FRAME_INTERRUPT_CPBLTY_0_r,HALF_FRAME_INTERRUPT_CPBLTY_1_r" newline bitfld.long 0x08 1. "EVENT_DROP_INTERRUPT_CPBLTY,Request collision detection capability" "EVENT_DROP_INTERRUPT_CPBLTY_0_r,EVENT_DROP_INTERRUPT_CPBLTY_1_r" line.long 0x0C "DMA4_GCR,FIFO sharing between high and low priority channel" bitfld.long 0x0C 24. "CHANNEL_ID_GATE,Gates the Channel ID bus monitoring on both Read and Write ports" "0,1" newline hexmask.long.byte 0x0C 16.--23. 1. "ARBITRATION_RATE,Arbitration switching rate between prioritized and regular channel queues" newline bitfld.long 0x0C 14.--15. "HI_LO_FIFO_BUDGET,Allow to have a separate Global FIFO budget for high and low priority channels" "HI_LO_FIFO_BUDGET_0,HI_LO_FIFO_BUDGET_1,HI_LO_FIFO_BUDGET_2,HI_LO_FIFO_BUDGET_3" newline bitfld.long 0x0C 12.--13. "HI_THREAD_RESERVED,Allow thread reservation for high priority channel on both read and write ports" "HI_THREAD_RESERVED_0,HI_THREAD_RESERVED_1,HI_THREAD_RESERVED_2,HI_THREAD_RESERVED_3" newline hexmask.long.byte 0x0C 0.--7. 1. "MAX_CHANNEL_FIFO_DEPTH,Maximum FIFO depth allocated to one logical channel" repeat 12. (list 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. ) tree "DMA_Channel_$1" group.long 0x858++0x03 line.long 0x00 "DMA4_CCDNi_20," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x83C++0x07 line.long 0x00 "DMA4_CCENi_20,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_20,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x800++0x03 line.long 0x00 "DMA4_CCRi_20,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "0,1" bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x838++0x03 line.long 0x00 "DMA4_CDACi_20,Channel Destination Address Value" group.long 0x82C++0x07 line.long 0x00 "DMA4_CDEIi_20,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_20,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x850++0x03 line.long 0x00 "DMA4_CDPi_20,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x820++0x03 line.long 0x00 "DMA4_CDSAi_20,Channel Destination Start Address" group.long 0x814++0x07 line.long 0x00 "DMA4_CENi_20,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_20,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x808++0x03 line.long 0x00 "DMA4_CICRi_20,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x804++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_20,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x854++0x03 line.long 0x00 "DMA4_CNDPi_20,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x844++0x03 line.long 0x00 "DMA4_COLORi_20,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x834++0x03 line.long 0x00 "DMA4_CSACi_20,Channel Source Address Value" group.long 0x810++0x03 line.long 0x00 "DMA4_CSDPi_20,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x824++0x07 line.long 0x00 "DMA4_CSEIi_20,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_20,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x80C++0x03 line.long 0x00 "DMA4_CSRi_20,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "0,1" bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x81C++0x03 line.long 0x00 "DMA4_CSSAi_20,Channel Source Start Address" tree.end repeat.end repeat 16. (list 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. ) tree "DMA_Channel_$1" group.long 0x498++0x03 line.long 0x00 "DMA4_CCDNi_10," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0x47C++0x07 line.long 0x00 "DMA4_CCENi_10,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_10,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x440++0x03 line.long 0x00 "DMA4_CCRi_10,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "0,1" bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x478++0x03 line.long 0x00 "DMA4_CDACi_10,Channel Destination Address Value" group.long 0x46C++0x07 line.long 0x00 "DMA4_CDEIi_10,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_10,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0x490++0x03 line.long 0x00 "DMA4_CDPi_10,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0x460++0x03 line.long 0x00 "DMA4_CDSAi_10,Channel Destination Start Address" group.long 0x454++0x07 line.long 0x00 "DMA4_CENi_10,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_10,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x448++0x03 line.long 0x00 "DMA4_CICRi_10,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x444++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_10,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x494++0x03 line.long 0x00 "DMA4_CNDPi_10,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0x484++0x03 line.long 0x00 "DMA4_COLORi_10,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0x474++0x03 line.long 0x00 "DMA4_CSACi_10,Channel Source Address Value" group.long 0x450++0x03 line.long 0x00 "DMA4_CSDPi_10,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0x464++0x07 line.long 0x00 "DMA4_CSEIi_10,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_10,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x44C++0x03 line.long 0x00 "DMA4_CSRi_10,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "0,1" bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x45C++0x03 line.long 0x00 "DMA4_CSSAi_10,Channel Source Start Address" tree.end repeat.end repeat 4. (list 0. 1. 2. 3. ) tree "DMA_Channel_$1" group.long 0xD8++0x03 line.long 0x00 "DMA4_CCDNi_0," hexmask.long.word 0x00 0.--15. 1. "CURRENT_DESCRIPTOR_NBR,This register when read contains the current active descriptor number in the link list" group.long 0xBC++0x07 line.long 0x00 "DMA4_CCENi_0,Channel Current Transferred Element Number in the current frame" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT_ELMNT_NBR,Channel current transferred element number in the current frame" line.long 0x04 "DMA4_CCFNi_0,Channel Current Transferred Frame Number in the current transfer" hexmask.long.word 0x04 0.--15. 1. "CURRENT_FRAME_NBR,Channel current transferred frame number in the current transfer" group.long 0x80++0x03 line.long 0x00 "DMA4_CCRi_0,Channel Control Register" bitfld.long 0x00 26. "WRITE_PRIORITY,Channel priority on the Write side" "WRITE_PRIORITY_0,WRITE_PRIORITY_1" bitfld.long 0x00 25. "BUFFERING_DISABLE,This bit allows to disable the default buffering functionality when transfer is source synchronized" "BUFFERING_DISABLE_0,BUFFERING_DISABLE_1" newline bitfld.long 0x00 24. "SEL_SRC_DST_SYNC,Specifies that element packet frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "SEL_SRC_DST_SYNC_0,SEL_SRC_DST_SYNC_1" bitfld.long 0x00 23. "PREFETCH,Enables the prefetch mode" "PREFETCH_0,PREFETCH_1" newline bitfld.long 0x00 22. "SUPERVISOR,Enables the supervisor mode" "SUPERVISOR_0,SUPERVISOR_1" bitfld.long 0x00 19.--20. "SYNCHRO_CONTROL_UPPER,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction as 2 MSB with the 5 bits of the synchro channel bit field" "0,1,2,3" newline bitfld.long 0x00 18. "BS,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer" "0,1" bitfld.long 0x00 17. "TRANSPARENT_COPY_ENABLE,Transparent copy enable" "TRANSPARENT_COPY_ENABLE_0,TRANSPARENT_COPY_ENABLE_1" newline bitfld.long 0x00 16. "CONST_FILL_ENABLE,Constant fill enable" "CONST_FILL_ENABLE_0,CONST_FILL_ENABLE_1" bitfld.long 0x00 14.--15. "DST_AMODE,Selects the addressing mode on the Write Port of a channel" "DST_AMODE_0,DST_AMODE_1,DST_AMODE_2,DST_AMODE_3" newline bitfld.long 0x00 12.--13. "SRC_AMODE,Selects the addressing mode on the Read Port of a channel" "SRC_AMODE_0,SRC_AMODE_1,SRC_AMODE_2,SRC_AMODE_3" rbitfld.long 0x00 10. "WR_ACTIVE,Indicates if the channel write context is active or not" "WR_ACTIVE_0_r,WR_ACTIVE_1_r" newline rbitfld.long 0x00 9. "RD_ACTIVE,Indicates if the channel read context is active or not" "RD_ACTIVE_0_r,RD_ACTIVE_1_r" bitfld.long 0x00 8. "SUSPEND_SENSITIVE,Logical channel suspend enable bit" "SUSPEND_SENSITIVE_0,SUSPEND_SENSITIVE_1" newline bitfld.long 0x00 7. "ENABLE,Logical channel enable" "ENABLE_0,ENABLE_1" bitfld.long 0x00 6. "READ_PRIORITY,Channel priority on the read side" "READ_PRIORITY_0,READ_PRIORITY_1" newline bitfld.long 0x00 5. "FS,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS =" "0,1" bitfld.long 0x00 0.--4. "SYNCHRO_CONTROL,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xB8++0x03 line.long 0x00 "DMA4_CDACi_0,Channel Destination Address Value" group.long 0xAC++0x07 line.long 0x00 "DMA4_CDEIi_0,Channel Destination Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_DST_ELMNT_INDEX,Channel destination element index" line.long 0x04 "DMA4_CDFIi_0,Channel Destination Frame Index (Signed) or 16-bit Packet size" group.long 0xD0++0x03 line.long 0x00 "DMA4_CDPi_0,This register controls the various parameters of the link list mechanism" bitfld.long 0x00 10. "FAST,Sets the fast-start mode for linked list descriptor types 1 2 and" "FAST_0,FAST_1" bitfld.long 0x00 8.--9. "TRANSFER_MODE,Enable linked-list transfer mode" "TRANSFER_MODE_0,TRANSFER_MODE_1,TRANSFER_MODE_2,TRANSFER_MODE_3" newline bitfld.long 0x00 7. "PAUSE_LINK_LIST,Suspend the linked-list transfer at completion of the current block transfer" "PAUSE_LINK_LIST_0,PAUSE_LINK_LIST_1" bitfld.long 0x00 4.--6. "NEXT_DESCRIPTOR_TYPE,Next Descriptor Type" "NEXT_DESCRIPTOR_TYPE_0,NEXT_DESCRIPTOR_TYPE_1,NEXT_DESCRIPTOR_TYPE_2,NEXT_DESCRIPTOR_TYPE_3,NEXT_DESCRIPTOR_TYPE_4,NEXT_DESCRIPTOR_TYPE_5,NEXT_DESCRIPTOR_TYPE_6,NEXT_DESCRIPTOR_TYPE_7" newline bitfld.long 0x00 2.--3. "SRC_VALID,Source address valid" "SRC_VALID_0,SRC_VALID_1,SRC_VALID_2,SRC_VALID_3" bitfld.long 0x00 0.--1. "DEST_VALID,Destination address valid" "DEST_VALID_0,DEST_VALID_1,DEST_VALID_2,DEST_VALID_3" group.long 0xA0++0x03 line.long 0x00 "DMA4_CDSAi_0,Channel Destination Start Address" group.long 0x94++0x07 line.long 0x00 "DMA4_CENi_0,Channel Element Number" hexmask.long.tbyte 0x00 0.--23. 1. "CHANNEL_ELMNT_NBR,Number of elements within a frame (unsigned) to transfer" line.long 0x04 "DMA4_CFNi_0,Channel Frame Number" hexmask.long.word 0x04 0.--15. 1. "CHANNEL_FRAME_NBR,Number of frames within the block to be transferred (unsigned)" group.long 0x88++0x03 line.long 0x00 "DMA4_CICRi_0,Channel Interrupt Control Register" bitfld.long 0x00 14. "SUPER_BLOCK_IE,Enables the end of super block interrupt" "0,1" bitfld.long 0x00 12. "DRAIN_IE,Enables the end of draining interrupt" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ERR_IE,Enables the address misaligned error event interrupt" "MISALIGNED_ERR_IE_0,MISALIGNED_ERR_IE_1" bitfld.long 0x00 10. "SUPERVISOR_ERR_IE,Enables the supervisor transaction error event interrupt" "SUPERVISOR_ERR_IE_0,SUPERVISOR_ERR_IE_1" newline bitfld.long 0x00 8. "TRANS_ERR_IE,Enables the transaction error event interrupt" "TRANS_ERR_IE_0,TRANS_ERR_IE_1" bitfld.long 0x00 7. "PKT_IE,Enables the end of Packet interrupt" "PKT_IE_0,PKT_IE_1" newline bitfld.long 0x00 5. "BLOCK_IE,Enables the end of block interrupt" "BLOCK_IE_0,BLOCK_IE_1" bitfld.long 0x00 4. "LAST_IE,Last frame interrupt enable (start of last frame)" "LAST_IE_0,LAST_IE_1" newline bitfld.long 0x00 3. "FRAME_IE,Frame interrupt enable (end of frame)" "FRAME_IE_0,FRAME_IE_1" bitfld.long 0x00 2. "HALF_IE,Enables or disables the half frame interrupt" "HALF_IE_0,HALF_IE_1" newline bitfld.long 0x00 1. "DROP_IE,Synchronization event drop interrupt enable (request collision)" "DROP_IE_0,DROP_IE_1" group.long 0x84++0x03 line.long 0x00 "DMA4_CLNK_CTRLi_0,Channel Link Control Register" bitfld.long 0x00 15. "ENABLE_LNK,Enables or disable the channel linking" "ENABLE_LNK_0,ENABLE_LNK_1" bitfld.long 0x00 0.--4. "NEXTLCH_ID,Defines the NextLCh_ID which is used to build logical channel chaining queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD4++0x03 line.long 0x00 "DMA4_CNDPi_0,This register contains the Next descriptor Address Pointer for the link list Mechanism" hexmask.long 0x00 2.--31. 1. "NEXT_DESCRIPTOR_POINTER,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.long 0xC4++0x03 line.long 0x00 "DMA4_COLORi_0,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x00 0.--23. 1. "CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN,Color key or solid color pattern: The pattern is replicated according to the data type" rgroup.long 0xB4++0x03 line.long 0x00 "DMA4_CSACi_0,Channel Source Address Value" group.long 0x90++0x03 line.long 0x00 "DMA4_CSDPi_0,Channel Source Destination Parameters" bitfld.long 0x00 21. "SRC_ENDIAN,Channel source endianness control" "SRC_ENDIAN_0,SRC_ENDIAN_1" bitfld.long 0x00 20. "SRC_ENDIAN_LOCK,Endianness Lock" "SRC_ENDIAN_LOCK_0,SRC_ENDIAN_LOCK_1" newline bitfld.long 0x00 19. "DST_ENDIAN,Channel Destination endianness control" "DST_ENDIAN_0,DST_ENDIAN_1" bitfld.long 0x00 18. "DST_ENDIAN_LOCK,Endianness Lock" "DST_ENDIAN_LOCK_0,DST_ENDIAN_LOCK_1" newline bitfld.long 0x00 16.--17. "WRITE_MODE,Used to enable writing mode without posting or with posting" "WRITE_MODE_0,WRITE_MODE_1,WRITE_MODE_2,WRITE_MODE_3" bitfld.long 0x00 14.--15. "DST_BURST_EN,Used to enable bursting on the Write Port" "DST_BURST_EN_0,DST_BURST_EN_1,DST_BURST_EN_2,DST_BURST_EN_3" newline bitfld.long 0x00 13. "DST_PACKED,Destination receives packed data" "DST_PACKED_0,DST_PACKED_1" bitfld.long 0x00 7.--8. "SRC_BURST_EN,Used to enable bursting on the Read Port" "SRC_BURST_EN_0,SRC_BURST_EN_1,SRC_BURST_EN_2,SRC_BURST_EN_3" newline bitfld.long 0x00 6. "SRC_PACKED,Source provides packed data" "SRC_PACKED_0,SRC_PACKED_1" bitfld.long 0x00 0.--1. "DATA_TYPE,Defines the type of the data moved in the channel" "DATA_TYPE_0,DATA_TYPE_1,DATA_TYPE_2,DATA_TYPE_3" group.long 0xA4++0x07 line.long 0x00 "DMA4_CSEIi_0,Channel Source Element Index (Signed)" hexmask.long.word 0x00 0.--15. 1. "CHANNEL_SRC_ELMNT_INDEX,Channel source element index" line.long 0x04 "DMA4_CSFIi_0,Channel Source Frame Index (Signed) or 16-bit Packet size" group.long 0x8C++0x03 line.long 0x00 "DMA4_CSRi_0,Channel Status Register" bitfld.long 0x00 14. "SUPER_BLOCK,End of Super block event" "0,1" bitfld.long 0x00 12. "DRAIN_END,End of channel draining" "0,1" newline bitfld.long 0x00 11. "MISALIGNED_ADRS_ERR,Misaligned address error event" "MISALIGNED_ADRS_ERR_0_w,MISALIGNED_ADRS_ERR_1_r" bitfld.long 0x00 10. "SUPERVISOR_ERR,Supervisor transaction error event" "SUPERVISOR_ERR_0_w,SUPERVISOR_ERR_1_r" newline bitfld.long 0x00 8. "TRANS_ERR,Transaction error event" "TRANS_ERR_0_w,TRANS_ERR_1_r" bitfld.long 0x00 7. "PKT,End of Packet transfer" "PKT_0_w,PKT_1_r" newline bitfld.long 0x00 6. "SYNC,Synchronization status of a channel" "SYNC_0_w,SYNC_1_r" bitfld.long 0x00 5. "BLOCK,End of block event" "BLOCK_0_w,BLOCK_1_r" newline bitfld.long 0x00 4. "LAST,Last frame (start of last frame)" "LAST_0_w,LAST_1_r" bitfld.long 0x00 3. "FRAME,End of frame event" "FRAME_0_w,FRAME_1_r" newline bitfld.long 0x00 2. "HALF,Half of frame event" "HALF_0_w,HALF_1_r" bitfld.long 0x00 1. "DROP,Synchronization event drop occured during the transfer" "DROP_0_w,DROP_1_r" group.long 0x9C++0x03 line.long 0x00 "DMA4_CSSAi_0,Channel Source Start Address" group.long 0x18++0x03 line.long 0x00 "DMA4_IRQENABLE_Lj_0,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on line Lj" group.long 0x08++0x03 line.long 0x00 "DMA4_IRQSTATUS_Lj_0,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj" tree.end repeat.end tree.end tree.end tree.open "UART_IrDA_CIR" repeat 10. (list 3. 5. 6. 1. 2. 4. 7. 8. 9. 10. )(list ad:0x48020000 ad:0x48066000 ad:0x48068000 ad:0x4806A000 ad:0x4806C000 ad:0x4806E000 ad:0x48420000 ad:0x48422000 ad:0x48424000 ad:0x4AE2B000 ) tree "UART$1" base $2 group.long 0x00++0x03 line.long 0x00 "UART_DLL,This register. with. stores the 14-bit divisor for generation of the baud clock in the baud rate generator" hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Stores the 8-bit LSB divisor value" rgroup.long 0x00++0x03 line.long 0x00 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register" hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register" group.long 0x00++0x07 line.long 0x00 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register" hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit holding register" line.long 0x04 "UART_DLH,This register. with. stores the 14-bit divisor for generating the baud clock in the baud rate generator" bitfld.long 0x04 0.--5. "CLOCK_MSB,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "UART_IER,Interrupt enable register" bitfld.long 0x00 7. "CTS_IT," "CTS_IT_0,CTS_IT_1" newline bitfld.long 0x00 6. "RTS_IT," "RTS_IT_0,RTS_IT_1" newline bitfld.long 0x00 5. "XOFF_IT," "XOFF_IT_0,XOFF_IT_1" newline bitfld.long 0x00 4. "SLEEP_MODE," "SLEEP_MODE_0,SLEEP_MODE_1" newline bitfld.long 0x00 3. "MODEM_STS_IT," "MODEM_STS_IT_0,MODEM_STS_IT_1" newline bitfld.long 0x00 2. "LINE_STS_IT," "LINE_STS_IT_0,LINE_STS_IT_1" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0,THR_IT_1" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0,RHR_IT_1" group.long 0x04++0x03 line.long 0x00 "UART_IER_CIR,There are 6 types of interrupt in these modes. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually" bitfld.long 0x00 5. "TX_STATUS_IT," "TX_STATUS_IT_0,TX_STATUS_IT_1" newline bitfld.long 0x00 3. "RX_OVERRUN_IT," "RX_OVERRUN_IT_0,RX_OVERRUN_IT_1" newline bitfld.long 0x00 2. "RX_STOP_IT," "RX_STOP_IT_0,RX_STOP_IT_1" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0,THR_IT_1" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0,RHR_IT_1" group.long 0x04++0x07 line.long 0x00 "UART_IER_IRDA,There are 8 types of interrupt in these modes. received EOF. LSR interrupt. TX status. status FIFO interrupt. RX overrun. last byte in RX FIFO. THR interrupt and RHR interrupt and they can be enabled/disabled individually" bitfld.long 0x00 7. "EOF_IT," "EOF_IT_0,EOF_IT_1" newline bitfld.long 0x00 6. "LINE_STS_IT," "LINE_STS_IT_0,LINE_STS_IT_1" newline bitfld.long 0x00 5. "TX_STATUS_IT," "TX_STATUS_IT_0,TX_STATUS_IT_1" newline bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "STS_FIFO_TRIG_IT_0,STS_FIFO_TRIG_IT_1" newline bitfld.long 0x00 3. "RX_OVERRUN_IT," "RX_OVERRUN_IT_0,RX_OVERRUN_IT_1" newline bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "LAST_RX_BYTE_IT_0,LAST_RX_BYTE_IT_1" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0,THR_IT_1" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0,RHR_IT_1" line.long 0x04 "UART_EFR,Enhanced feature register" bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "AUTO_CTS_EN_0,AUTO_CTS_EN_1" newline bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "AUTO_RTS_EN_0,AUTO_RTS_EN_1" newline bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "SPECIAL_CHAR_DETECT_0,SPECIAL_CHAR_DETECT_1" newline bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "ENHANCED_EN_0,ENHANCED_EN_1" newline bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of software flow control can be selected by programming bit" "SW_FLOW_CONTROL_0,SW_FLOW_CONTROL_1,SW_FLOW_CONTROL_2,SW_FLOW_CONTROL_3,SW_FLOW_CONTROL_4,SW_FLOW_CONTROL_5,SW_FLOW_CONTROL_6,SW_FLOW_CONTROL_7,SW_FLOW_CONTROL_8,SW_FLOW_CONTROL_9,SW_FLOW_CONTROL_10,SW_FLOW_CONTROL_11,SW_FLOW_CONTROL_12,SW_FLOW_CONTROL_13,SW_FLOW_CONTROL_14,SW_FLOW_CONTROL_15" group.long 0x08++0x03 line.long 0x00 "UART_FCR,FIFO control register" bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] =" "RX_FIFO_TRIG_0,RX_FIFO_TRIG_1,RX_FIFO_TRIG_2,RX_FIFO_TRIG_3" newline bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] =" "TX_FIFO_TRIG_0,TX_FIFO_TRIG_1,TX_FIFO_TRIG_2,TX_FIFO_TRIG_3" newline bitfld.long 0x00 3. "DMA_MODE,This register is considered ifUART_SCR[0] = 0" "DMA_MODE_0_w,DMA_MODE_1_w" newline bitfld.long 0x00 2. "TX_FIFO_CLEAR," "TX_FIFO_CLEAR_0_w,TX_FIFO_CLEAR_1_w" newline bitfld.long 0x00 1. "RX_FIFO_CLEAR," "RX_FIFO_CLEAR_0_w,RX_FIFO_CLEAR_1_w" newline bitfld.long 0x00 0. "FIFO_EN," "FIFO_EN_0_w,FIFO_EN_1_w" rgroup.long 0x08++0x03 line.long 0x00 "UART_IIR,Interrupt identification register" bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents ofUART_FCR[0] on both bits" "FCR_MIRROR_0,FCR_MIRROR_1,FCR_MIRROR_2,FCR_MIRROR_3" newline bitfld.long 0x00 1.--5. "IT_TYPE," "?,IT_TYPE_1_r,IT_TYPE_2_r,IT_TYPE_3_r,?,?,IT_TYPE_6_r,?,IT_TYPE_8_r,?,?,?,?,?,?,?,IT_TYPE_16_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 0. "IT_PENDING," "?,IT_PENDING_1_r" rgroup.long 0x08++0x03 line.long 0x00 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active" bitfld.long 0x00 5. "TX_STATUS_IT," "?,TX_STATUS_IT_1_r" newline bitfld.long 0x00 3. "RX_OE_IT," "?,RX_OE_IT_1_r" newline bitfld.long 0x00 2. "RX_STOP_IT," "?,RX_STOP_IT_1_r" newline bitfld.long 0x00 1. "THR_IT," "?,THR_IT_1_r" newline bitfld.long 0x00 0. "RHR_IT," "?,RHR_IT_1_r" rgroup.long 0x08++0x0B line.long 0x00 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active" bitfld.long 0x00 7. "EOF_IT," "EOF_IT_0_r,EOF_IT_1_r" newline bitfld.long 0x00 6. "LINE_STS_IT," "LINE_STS_IT_0_r,LINE_STS_IT_1_r" newline bitfld.long 0x00 5. "TX_STATUS_IT," "TX_STATUS_IT_0_r,TX_STATUS_IT_1_r" newline bitfld.long 0x00 4. "STS_FIFO_IT," "STS_FIFO_IT_0_r,STS_FIFO_IT_1_r" newline bitfld.long 0x00 3. "RX_OE_IT," "RX_OE_IT_0_r,RX_OE_IT_1_r" newline bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "RX_FIFO_LAST_BYTE_IT_0_r,RX_FIFO_LAST_BYTE_IT_1_r" newline bitfld.long 0x00 1. "THR_IT," "THR_IT_0_r,THR_IT_1_r" newline bitfld.long 0x00 0. "RHR_IT," "RHR_IT_0_r,RHR_IT_1_r" line.long 0x04 "UART_LCR,Line control register" bitfld.long 0x04 7. "DIV_EN," "DIV_EN_0,DIV_EN_1" newline bitfld.long 0x04 6. "BREAK_EN,Break control bit" "BREAK_EN_0,BREAK_EN_1" newline bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format (ifUART_LCR[3] = 1)" "PARITY_TYPE2_0,PARITY_TYPE2_1" newline bitfld.long 0x04 4. "PARITY_TYPE1," "PARITY_TYPE1_0,PARITY_TYPE1_1" newline bitfld.long 0x04 3. "PARITY_EN," "?,PARITY_EN_1" newline bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop-bits" "NB_STOP_0,NB_STOP_1" newline bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "CHAR_LENGTH_0,CHAR_LENGTH_1,CHAR_LENGTH_2,CHAR_LENGTH_3" line.long 0x08 "UART_MCR,Modem control register" bitfld.long 0x08 6. "TCR_TLR," "?,TCR_TLR_1" newline bitfld.long 0x08 5. "XON_EN," "?,XON_EN_1" newline bitfld.long 0x08 4. "LOOPBACK_EN," "?,LOOPBACK_EN_1" newline bitfld.long 0x08 3. "CD_STS_CH," "?,CD_STS_CH_1" newline bitfld.long 0x08 2. "RI_STS_CH," "?,RI_STS_CH_1" newline bitfld.long 0x08 1. "RTS,In loopback controls theUART_MSR[4] bit" "RTS_0,RTS_1" newline bitfld.long 0x08 0. "DTR," "?,DTR_1" group.long 0x10++0x07 line.long 0x00 "UART_XON1_ADDR1,UART mode: XON1 character. IrDA mode: ADDR1 address" hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" line.long 0x04 "UART_LSR,Line status register" bitfld.long 0x04 7. "RX_FIFO_STS," "?,RX_FIFO_STS_1_r" newline bitfld.long 0x04 6. "TX_SR_E," "?,TX_SR_E_1_r" newline bitfld.long 0x04 5. "TX_FIFO_E," "?,TX_FIFO_E_1_r" newline bitfld.long 0x04 4. "RX_BI," "?,RX_BI_1_r" newline bitfld.long 0x04 3. "RX_FE," "?,RX_FE_1_r" newline bitfld.long 0x04 2. "RX_PE," "?,RX_PE_1_r" newline bitfld.long 0x04 1. "RX_OE," "?,RX_OE_1_r" newline bitfld.long 0x04 0. "RX_FIFO_E," "?,RX_FIFO_E_1_r" rgroup.long 0x14++0x03 line.long 0x00 "UART_LSR_CIR,Line status register in CIR mode" bitfld.long 0x00 7. "THR_EMPTY," "?,THR_EMPTY_1_r" newline bitfld.long 0x00 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (UART_EBLR)" "RX_STOP_0_r,RX_STOP_1_r" newline bitfld.long 0x00 0. "RX_FIFO_E," "?,RX_FIFO_E_1_r" rgroup.long 0x14++0x03 line.long 0x00 "UART_LSR_IRDA,When the LSR is read. LSR[4:2] reflect the error bits [FL. CRC. ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)" bitfld.long 0x00 7. "THR_EMPTY," "?,THR_EMPTY_1_r" newline bitfld.long 0x00 6. "STS_FIFO_FULL," "?,STS_FIFO_FULL_1_r" newline bitfld.long 0x00 5. "RX_LAST_BYTE," "?,RX_LAST_BYTE_1_r" newline bitfld.long 0x00 4. "FRAME_TOO_LONG," "?,FRAME_TOO_LONG_1_r" newline bitfld.long 0x00 3. "ABORT," "?,ABORT_1_r" newline bitfld.long 0x00 2. "CRC," "?,CRC_1_r" newline bitfld.long 0x00 1. "STS_FIFO_E," "?,STS_FIFO_E_1_r" newline bitfld.long 0x00 0. "RX_FIFO_E," "?,RX_FIFO_E_1_r" group.long 0x14++0x07 line.long 0x00 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" line.long 0x04 "UART_MSR,Modem status register" bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1" newline bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1" newline bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1" newline bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1" newline bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input (orUART_MCR[3] in loopback) changed" "0,1" newline bitfld.long 0x04 2. "RI_STS,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high" "0,1" newline bitfld.long 0x04 1. "DSR_STS," "?,DSR_STS_1_r" newline bitfld.long 0x04 0. "CTS_STS," "?,CTS_STS_1_r" group.long 0x18++0x03 line.long 0x00 "UART_TCR,Transmission control register" bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "RX_FIFO_TRIG_START_0,RX_FIFO_TRIG_START_1,RX_FIFO_TRIG_START_2,RX_FIFO_TRIG_START_3,RX_FIFO_TRIG_START_4,RX_FIFO_TRIG_START_5,RX_FIFO_TRIG_START_6,RX_FIFO_TRIG_START_7,RX_FIFO_TRIG_START_8,RX_FIFO_TRIG_START_9,RX_FIFO_TRIG_START_10,RX_FIFO_TRIG_START_11,RX_FIFO_TRIG_START_12,RX_FIFO_TRIG_START_13,RX_FIFO_TRIG_START_14,RX_FIFO_TRIG_START_15" newline bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "RX_FIFO_TRIG_HALT_0,RX_FIFO_TRIG_HALT_1,RX_FIFO_TRIG_HALT_2,RX_FIFO_TRIG_HALT_3,RX_FIFO_TRIG_HALT_4,RX_FIFO_TRIG_HALT_5,RX_FIFO_TRIG_HALT_6,RX_FIFO_TRIG_HALT_7,RX_FIFO_TRIG_HALT_8,RX_FIFO_TRIG_HALT_9,RX_FIFO_TRIG_HALT_10,RX_FIFO_TRIG_HALT_11,RX_FIFO_TRIG_HALT_12,RX_FIFO_TRIG_HALT_13,RX_FIFO_TRIG_HALT_14,RX_FIFO_TRIG_HALT_15" group.long 0x18++0x07 line.long 0x00 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Stores the 8-bit XOFF1 character used in UART modes" line.long 0x04 "UART_SPR,Scratchpad register" hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register" group.long 0x1C++0x03 line.long 0x00 "UART_TLR,Trigger level register" bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "RX_FIFO_TRIG_DMA_0,RX_FIFO_TRIG_DMA_1,RX_FIFO_TRIG_DMA_2,RX_FIFO_TRIG_DMA_3,RX_FIFO_TRIG_DMA_4,RX_FIFO_TRIG_DMA_5,RX_FIFO_TRIG_DMA_6,RX_FIFO_TRIG_DMA_7,RX_FIFO_TRIG_DMA_8,RX_FIFO_TRIG_DMA_9,RX_FIFO_TRIG_DMA_10,RX_FIFO_TRIG_DMA_11,RX_FIFO_TRIG_DMA_12,RX_FIFO_TRIG_DMA_13,RX_FIFO_TRIG_DMA_14,RX_FIFO_TRIG_DMA_15" newline bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "TX_FIFO_TRIG_DMA_0,TX_FIFO_TRIG_DMA_1,TX_FIFO_TRIG_DMA_2,TX_FIFO_TRIG_DMA_3,TX_FIFO_TRIG_DMA_4,TX_FIFO_TRIG_DMA_5,TX_FIFO_TRIG_DMA_6,TX_FIFO_TRIG_DMA_7,TX_FIFO_TRIG_DMA_8,TX_FIFO_TRIG_DMA_9,TX_FIFO_TRIG_DMA_10,TX_FIFO_TRIG_DMA_11,TX_FIFO_TRIG_DMA_12,TX_FIFO_TRIG_DMA_13,TX_FIFO_TRIG_DMA_14,TX_FIFO_TRIG_DMA_15" group.long 0x1C++0x0F line.long 0x00 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Stores the 8-bit XOFF2 character used in UART modes" line.long 0x04 "UART_MDR1,Mode definition register 1" bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "FRAME_END_MODE_0,FRAME_END_MODE_1" newline bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "SIP_MODE_0,SIP_MODE_1" newline bitfld.long 0x04 5. "SCT,Store and control the transmission" "SCT_0,SCT_1" newline bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "SET_TXIR_0,SET_TXIR_1" newline bitfld.long 0x04 3. "IR_SLEEP," "?,IR_SLEEP_1" newline bitfld.long 0x04 0.--2. "MODE_SELECT," "?,MODE_SELECT_1,MODE_SELECT_2,MODE_SELECT_3,MODE_SELECT_4,MODE_SELECT_5,MODE_SELECT_6,MODE_SELECT_7" line.long 0x08 "UART_MDR2,Mode definition register 2" rbitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate function forUART_MDR1[4] (SET_TXIR)" "SET_TXIR_ALT_0,SET_TXIR_ALT_1" newline bitfld.long 0x08 6. "IRRXINVERT,IR mode only (IrDA and CIR)" "IRRXINVERT_0,IRRXINVERT_1" newline bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR pulse modulation definition" "CIR_PULSE_MODE_0,CIR_PULSE_MODE_1,CIR_PULSE_MODE_2,CIR_PULSE_MODE_3" newline bitfld.long 0x08 3. "UART_PULSE,UART mode only" "UART_PULSE_0,UART_PULSE_1" newline bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,IR-IrDA mode only" "STS_FIFO_TRIG_0,STS_FIFO_TRIG_1,STS_FIFO_TRIG_2,STS_FIFO_TRIG_3" newline rbitfld.long 0x08 0. "IRTX_UNDERRUN,IrDA transmission status interrupt" "IRTX_UNDERRUN_0_r,IRTX_UNDERRUN_1_r" line.long 0x0C "UART_SFLSR,Status FIFO line status register" bitfld.long 0x0C 4. "OE_ERROR," "OE_ERROR_0,OE_ERROR_1" newline bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "FRAME_TOO_LONG_ERROR_0,FRAME_TOO_LONG_ERROR_1" newline bitfld.long 0x0C 2. "ABORT_DETECT," "ABORT_DETECT_0,ABORT_DETECT_1" newline bitfld.long 0x0C 1. "CRC_ERROR," "CRC_ERROR_0,CRC_ERROR_1" group.long 0x28++0x07 line.long 0x00 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length" line.long 0x04 "UART_RESUME,IR-IrDA and IR-CIR modes only" hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x2C++0x07 line.long 0x00 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "TXFLH_0,TXFLH_1,TXFLH_2,TXFLH_3,TXFLH_4,TXFLH_5,TXFLH_6,TXFLH_7,TXFLH_8,TXFLH_9,TXFLH_10,TXFLH_11,TXFLH_12,TXFLH_13,TXFLH_14,TXFLH_15,TXFLH_16,TXFLH_17,TXFLH_18,TXFLH_19,TXFLH_20,TXFLH_21,TXFLH_22,TXFLH_23,TXFLH_24,TXFLH_25,TXFLH_26,TXFLH_27,TXFLH_28,TXFLH_29,TXFLH_30,TXFLH_31" line.long 0x04 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x07 line.long 0x00 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length" line.long 0x04 "UART_RXFLH,Received frame length register high" bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "RXFLH_0,RXFLH_1,RXFLH_2,RXFLH_3,RXFLH_4,RXFLH_5,RXFLH_6,RXFLH_7,RXFLH_8,RXFLH_9,RXFLH_10,RXFLH_11,RXFLH_12,RXFLH_13,RXFLH_14,RXFLH_15" rgroup.long 0x34++0x07 line.long 0x00 "UART_SFREGH,Status FIFO register high" bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "SFREGH_0,SFREGH_1,SFREGH_2,SFREGH_3,SFREGH_4,SFREGH_5,SFREGH_6,SFREGH_7,SFREGH_8,SFREGH_9,SFREGH_10,SFREGH_11,SFREGH_12,SFREGH_13,SFREGH_14,SFREGH_15" line.long 0x04 "UART_BLR,BOF control register" bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "STS_FIFO_RESET_0,STS_FIFO_RESET_1" newline bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "XBOF_TYPE_0,XBOF_TYPE_1" rgroup.long 0x38++0x13 line.long 0x00 "UART_UASR,UART autobauding status register" bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,PARITY_TYPE_1_r,PARITY_TYPE_2_r,PARITY_TYPE_3_r" newline bitfld.long 0x00 5. "BIT_BY_CHAR," "?,BIT_BY_CHAR_1_r" newline bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "SPEED_0_r,SPEED_1_r,SPEED_2_r,SPEED_3_r,SPEED_4_r,SPEED_5_r,SPEED_6_r,SPEED_7_r,SPEED_8_r,SPEED_9_r,SPEED_10_r,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?" line.long 0x04 "UART_ACREG,Auxiliary control register" bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "PULSE_TYPE_0,PULSE_TYPE_1" newline bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "SD_MOD_0,SD_MOD_1" newline bitfld.long 0x04 5. "DIS_IR_RX," "?,DIS_IR_RX_1" newline bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "DIS_TX_UNDERRUN_0,DIS_TX_UNDERRUN_1" newline bitfld.long 0x04 3. "SEND_SIP,MIR/FIR modes only" "SEND_SIP_0,SEND_SIP_1" newline bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "SCTX_EN_0,SCTX_EN_1" newline bitfld.long 0x04 1. "ABORT_EN,Frame abort" "ABORT_EN_0,ABORT_EN_1" newline bitfld.long 0x04 0. "EOT_EN,EOT (end of transmission) bit" "EOT_EN_0,EOT_EN_1" line.long 0x08 "UART_SCR,Supplementary control register" bitfld.long 0x08 7. "RX_TRIG_GRANU1," "?,RX_TRIG_GRANU1_1" newline bitfld.long 0x08 6. "TX_TRIG_GRANU1," "?,TX_TRIG_GRANU1_1" newline bitfld.long 0x08 5. "DSR_IT," "?,DSR_IT_1" newline bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "?,RX_CTS_DSR_WAKE_UP_ENABLE_1" newline bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "?,TX_EMPTY_CTL_IT_1" newline bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if theUART_SCR[0] bit =" "DMA_MODE_2_0,DMA_MODE_2_1,DMA_MODE_2_2,DMA_MODE_2_3" newline bitfld.long 0x08 0. "DMA_MODE_CTL," "?,DMA_MODE_CTL_1" line.long 0x0C "UART_SSR,Supplementary status register" bitfld.long 0x0C 2. "DMA_COUNTER_RST," "?,DMA_COUNTER_RST_1" newline rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "?,RX_CTS_DSR_WAKE_UP_STS_1_r" newline rbitfld.long 0x0C 0. "TX_FIFO_FULL," "?,TX_FIFO_FULL_1_r" line.long 0x10 "UART_EBLR,BOF length register" hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IrDA mode: This register allows definition of up to 176 xBOFs the maximum required by IrDA specification" rgroup.long 0x50++0x27 line.long 0x00 "UART_MVR,Module version register" line.long 0x04 "UART_SYSC,System configuration register" bitfld.long 0x04 3.--4. "IDLEMODE,Power management req/ack control ref: OCP Design Guidelines Version" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" newline bitfld.long 0x04 2. "ENAWAKEUP,Wake-up feature control" "ENAWAKEUP_0,ENAWAKEUP_1" newline bitfld.long 0x04 1. "SOFTRESET,Software reset" "SOFTRESET_0,SOFTRESET_1" newline bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x08 "UART_SYSS,System status register" bitfld.long 0x08 0. "RESETDONE,Internal reset monitoring" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x0C "UART_WER,Wake-up enable register" bitfld.long 0x0C 7. "TX_WAKEUP_EN," "?,TX_WAKEUP_EN_1" newline bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "?,EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_1" newline bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "?,EVENT_5_RHR_INTERRUPT_1" newline bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "?,EVENT_4_RX_ACTIVITY_1" newline bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "?,EVENT_3_DCD_CD_ACTIVITY_1" newline bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "?,EVENT_2_RI_ACTIVITY_1" newline bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "?,EVENT_1_DSR_ACTIVITY_1" newline bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "?,EVENT_0_CTS_ACTIVITY_1" line.long 0x10 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at (12x multiple)" line.long 0x14 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,Shows the number of received bytes in the RX FIFO" line.long 0x18 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,Shows the number of written bytes in the TX FIFO" line.long 0x1C "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables TX FIFO empty corresponding interrupt" "EN_TXFIFO_EMPTY_0,EN_TXFIFO_EMPTY_1" newline bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables RX FIFO empty corresponding interrupt" "EN_RXFIFO_EMPTY_0,EN_RXFIFO_EMPTY_1" line.long 0x20 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "TXFIFO_EMPTY_STS_0,TXFIFO_EMPTY_STS_1" newline bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "RXFIFO_EMPTY_STS_0,RXFIFO_EMPTY_STS_1" line.long 0x24 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if nondefault frequency is used.UART_MDR3[1] must be set to 1 after this value is set" group.long 0x80++0x07 line.long 0x00 "UART_MDR3,Mode definition register 3" bitfld.long 0x00 2. "SET_DMA_TX_THRESHOLD,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register" "0,1" newline bitfld.long 0x00 1. "NONDEFAULT_FREQ,Used to enable the NONDEFAULT fclk frequencies" "NONDEFAULT_FREQ_0,NONDEFAULT_FREQ_1" newline bitfld.long 0x00 0. "DISABLE_CIR_RX_DEMOD,Used to enable CIR RX demodulation" "DISABLE_CIR_RX_DEMOD_0,DISABLE_CIR_RX_DEMOD_1" line.long 0x04 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" bitfld.long 0x04 0.--5. "TX_DMA_THRESHOLD,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end repeat.end tree.end tree.open "USB3_PHY_Subsystem" tree "DPLLCTRL_USB_OTG_SS" base ad:0x4A084C00 rgroup.long 0x04++0x1F line.long 0x00 "PLL_STATUS,This register contains the status information" bitfld.long 0x00 16. "PLL_TICOPWDN,PLL TICOPWDN status" "PLL_TICOPWDN_0_r,PLL_TICOPWDN_1_r" bitfld.long 0x00 15. "PLL_LDOPWDN,PLL LDOPWDN status" "PLL_LDOPWDN_0_r,PLL_LDOPWDN_1_r" bitfld.long 0x00 12. "SSC_EN_ACK,Spread Spectrum Clocking acknowledge - SSC_act" "SSC_EN_ACK_0_r,SSC_EN_ACK_1_r" newline bitfld.long 0x00 5. "PLL_HIGHJITTER,PLL High Jitter status - High_Jiitter" "PLL_HIGHJITTER_0_r,PLL_HIGHJITTER_1_r" bitfld.long 0x00 3. "PLL_LOSSREF,PLL Reference Loss status - Ref_Inp_Inact" "PLL_LOSSREF_0_r,PLL_LOSSREF_1_r" bitfld.long 0x00 2. "PLL_RECAL,PLL re-calibration status If this bit is active the PLL needs to be re-calibrated - Recal_required" "PLL_RECAL_0_r,PLL_RECAL_1_r" newline bitfld.long 0x00 1. "PLL_LOCK,PLL Lock status See the programming guide for the use of this bit - DSI_PLL_Lock" "PLL_LOCK_0_r,PLL_LOCK_1_r" bitfld.long 0x00 0. "PLLCTRL_RESET_DONE,PLLCTRL reset done status - RDone" "PLLCTRL_RESET_DONE_0_r,PLLCTRL_RESET_DONE_1_r" line.long 0x04 "PLL_GO,This register contains the GO bit" bitfld.long 0x04 0. "PLL_GO,Request (re-)locking sequence of the PLL" "PLL_GO_0,PLL_GO_1" line.long 0x08 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" hexmask.long.word 0x08 9.--20. 1. "PLL_REGM,M Divider for PLL" hexmask.long.byte 0x08 1.--8. 1. "PLL_REGN,N Divider for PLL (Reference)" line.long 0x0C "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0C 9.--10. "PLL_LOCKSEL,Selects the lock criteria for the PLL - PHASELOCK" "PLL_LOCKSEL_0,PLL_LOCKSEL_1,?,?" bitfld.long 0x0C 1.--3. "PLL_SELFREQDCO,DCO frequency range selector for DPLL_USB_OTG_SS 0x2 Set if DCO frequency is between 500MHz and 1000MHz 0x4 Set if DCO frequency is between 1000MHz and 2000MHz Other values: Reserved" "PLL_SELFREQDCO_0,PLL_SELFREQDCO_1,PLL_SELFREQDCO_2,PLL_SELFREQDCO_3,PLL_SELFREQDCO_4,PLL_SELFREQDCO_5,PLL_SELFREQDCO_6,PLL_SELFREQDCO_7" bitfld.long 0x0C 0. "PLL_IDLE,PLL IDLE: - IDLE_notsel" "PLL_IDLE_0,PLL_IDLE_1" line.long 0x10 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.byte 0x10 10.--17. 1. "PLL_SD,Sigma delta divider setting for DPLL_USB_OTG_SS based on the PLL lock configuration" line.long 0x14 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x14 2. "DOWNSPREAD,Forces the clock spreading only in the down spectrum" "DOWNSPREAD_0,DOWNSPREAD_1" bitfld.long 0x14 0. "EN_SSC,Spread Spectrum Clocking enable - SSC_Off" "EN_SSC_0,EN_SSC_1" line.long 0x18 "PLL_SSC_CONFIGURATION2," bitfld.long 0x18 30. "DELTAM2,MSB of DeltaM control bus" "0,1" hexmask.long.word 0x18 20.--29. 1. "MODFREQDIVIDER,Modulation Frequency Divider control for SSC" hexmask.long.tbyte 0x18 0.--19. 1. "DELTAM,DeltaM control for SSC" line.long 0x1C "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL" hexmask.long.tbyte 0x1C 0.--17. 1. "PLL_REGM_F,Fractional part of M divider" tree.end tree "OCP2SCP1" base ad:0x4A080000 rgroup.long 0x00++0x03 line.long 0x00 "OCP2SCP_REVISION,IP Revision Identifier (X.Y.R)" group.long 0x10++0x0B line.long 0x00 "OCP2SCP_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x00 3.--4. "IDLEMODE,- ForceIdle" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software Reset" "SOFTRESET_0,SOFTRESET_1" bitfld.long 0x00 0. "AUTOIDLE,OCP interface clock gating control" "AUTOIDLE_0,AUTOIDLE_1" line.long 0x04 "OCP2SCP_SYSSTATUS,System Status register" bitfld.long 0x04 0. "RESETDONE,- Complete" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "OCP2SCP_TIMING,Interrupt Status Register (legacy) for first line of interrupt" bitfld.long 0x08 7.--9. "DIVISIONRATIO,Division Ration of the SCP clock in relation to OCP input clock" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--6. "SYNC1,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--3. "SYNC2,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "USB3_PHY_RX" base ad:0x4A084400 group.long 0x0C++0x03 line.long 0x00 "USB3PHYRX_ANA_PROGRAMMABILITY_REG1,Some programmability for different analog circuits in the IP" hexmask.long.tbyte 0x00 8.--31. 1. "MEM_ANATESTMODE,Programmability for Analog circuits in the IP" bitfld.long 0x00 5.--6. "MEM_PLLDIV,This is a test mode" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "USB3PHYRX_TRIM_REG4,The IP requires some values to be remembered in EFUSE" bitfld.long 0x00 30.--31. "MEM_DLL_TRIM_SEL,Determines which of the 4 EFUSE registers EFUSE_dll_rateN_coarsetrim should be used as the trim code by the DLL" "0,1,2,3" group.long 0x24++0x07 line.long 0x00 "USB3PHYRX_DLL_REG1,This register is used to program DLL settings" bitfld.long 0x00 30.--31. "MEM_DLL_PHINT_RATE,Programs the DLL and the Phase Interpolator analog circuits to work with different clock frequencies" "0,1,2,3" line.long 0x04 "USB3PHYRX_DIGITAL_MODES_REG1,This register contains control bits which affect different circuits in digital section of the IP" bitfld.long 0x04 31. "MEM_INV_RXPN_PAIR,If '1' interchanges RXP and RXN effectively by inverting the received data samples" "0,1" bitfld.long 0x04 30. "MEM_OVRD_INV_RXPN_PAIR,Pin override control" "0,1" bitfld.long 0x04 27.--28. "MEM_HS_RATE,Determines the ratio of pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) frequency and the output data rate" "0,1,2,3" bitfld.long 0x04 26. "MEM_OVRD_HS_RATE,Pin override control" "0,1" newline bitfld.long 0x04 23. "MEM_CDR_FASTLOCK,'1' to reduce lock time of CDR (clock-data-recovery circuit)" "0,1" bitfld.long 0x04 21.--22. "MEM_CDR_LBW,CDR band-width control" "0,1,2,3" bitfld.long 0x04 19.--20. "MEM_CDR_STEPCNT,CDR 2nd order setting" "0,1,2,3" bitfld.long 0x04 16.--18. "MEM_CDR_STL,CDR settling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 13.--15. "MEM_CDR_THR,CDR 1st order threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12. "MEM_CDR_THR_MODE,CDR 1st order threshold" "0,1" bitfld.long 0x04 11. "MEM_CDR_2NDO_SDM_MODE,If '1' the 2nd Order CDR block uses a 1st order Sigma Delta Modulator to accomplish frequency offset If '0' a simple rate transformer is used for the same purpose" "0,1" group.long 0x38++0x03 line.long 0x00 "USB3PHYRX_EQUALIZER_REG1,The IP has an Equalizer (with analog and digital parts) which addresses Inter Symbol Interference (ISI)" hexmask.long.word 0x00 16.--31. 1. "MEM_EQLEV,Equalizer level control" bitfld.long 0x00 11.--15. "MEM_EQFTC,Equalizer zero freq control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7.--10. "MEM_EQCTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. "MEM_OVRD_EQLEV,Continuosly forces the Equalizer output with the eqlev[15:0]" "0,1" newline bitfld.long 0x00 1. "MEM_OVRD_EQFTC,Continuosly forces the Equalizer output with the eqftc[4:0]" "0,1" tree.end tree "USB3_PHY_TX" base ad:0x4A084800 group.long 0x0C++0x03 line.long 0x00 "USB3PHYTX_FUNC_CONFIG_REG,Functional Configuration registers" bitfld.long 0x00 31. "MEM_INVPAIR,Invert polarity of TXP/TXN" "0,1" group.long 0x2C++0x07 line.long 0x00 "USB3PHYTX_TEST_CONFIG_REG,Test related configuration registers" bitfld.long 0x00 30. "MEM_EN_LPBK,Loopback enable for test" "0,1" bitfld.long 0x00 29. "MEM_ENTXPATT,Enable Test pattern to input of the serializer instead of TD" "0,1" bitfld.long 0x00 26.--28. "MEM_TESTPATT,Select the LFSR mode to generate the required pattern" "0,1,2,3,4,5,6,7" line.long 0x04 "USB3PHYTX_PATTGEN_PRELOAD,Pattern generator (31 bit) LFSR Seed or preload value" hexmask.long 0x04 1.--31. 1. "MEM_PATTGEN_PRELOAD_VAL,Preload value to the LFSR pattern generator" tree.end tree.end tree.open "VCOP_CPU_and_Instruction_Set" tree "EVE1_VCOP" base ad:0x42084000 rgroup.long 0x00++0x13 line.long 0x00 "VCOP_PID," line.long 0x04 "VCOP_CTRL,VCOP Control Register" bitfld.long 0x04 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x04 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" line.long 0x08 "VCOP_STATUS,VCOP status register" bitfld.long 0x08 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x08 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x08 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" line.long 0x0C "VCOP_MAX_ITERS," hexmask.long.word 0x0C 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x0C 0.--15. 1. "MAX_ITERS,Maximum iteration count" line.long 0x10 "VCOP_ERROR,Error interrupt enalbe and status register" bitfld.long 0x10 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x10 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x10 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x10 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" bitfld.long 0x10 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" newline bitfld.long 0x10 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x10 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x10 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" bitfld.long 0x10 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x10 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" newline bitfld.long 0x10 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x10 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x10 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" bitfld.long 0x10 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x10 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" newline bitfld.long 0x10 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x20++0x07 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" line.long 0x04 "VCOP_PARAM_PTR," rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x40++0x03 line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x60++0x03 line.long 0x00 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end repeat.end tree.end tree "EVE2_VCOP" base ad:0x42184000 rgroup.long 0x00++0x13 line.long 0x00 "VCOP_PID," line.long 0x04 "VCOP_CTRL,VCOP Control Register" bitfld.long 0x04 1. "STEP_GO,Starts executing a single i4 iteration" "STEP_GO_0,STEP_GO_1" bitfld.long 0x04 0. "STEP_EN,Enable Single Step mode" "STEP_EN_0,STEP_EN_1" line.long 0x08 "VCOP_STATUS,VCOP status register" bitfld.long 0x08 2. "VEC_RDY,Vector core ready to accept next vector instruction" "0,1" bitfld.long 0x08 1. "VEC_DONE,Vector core has completed execution of submitted vector loops" "0,1" bitfld.long 0x08 0. "STEP_RDY,Ready for next step (single step)" "STEP_RDY_0,STEP_RDY_1" line.long 0x0C "VCOP_MAX_ITERS," hexmask.long.word 0x0C 16.--31. 1. "RESESERVED,Reserved" hexmask.long.word 0x0C 0.--15. 1. "MAX_ITERS,Maximum iteration count" line.long 0x10 "VCOP_ERROR,Error interrupt enalbe and status register" bitfld.long 0x10 23. "ERR_DIS7,Error Interrupt disable" "ERR_DIS7_0,ERR_DIS7_1" bitfld.long 0x10 22. "ERR_DIS6,Error Interrupt disable" "ERR_DIS6_0,ERR_DIS6_1" bitfld.long 0x10 21. "ERR_DIS5,Error Interrupt disable" "ERR_DIS5_0,ERR_DIS5_1" bitfld.long 0x10 20. "ERR_DIS4,Error Interrupt disable" "ERR_DIS4_0,ERR_DIS4_1" bitfld.long 0x10 19. "ERR_DIS3,Error Interrupt disable" "ERR_DIS3_0,ERR_DIS3_1" newline bitfld.long 0x10 18. "ERR_DIS2,Error Interrupt disable" "ERR_DIS2_0,ERR_DIS2_1" bitfld.long 0x10 17. "ERR_DIS1,Error Interrupt disable" "ERR_DIS1_0,ERR_DIS1_1" bitfld.long 0x10 16. "ERR_DIS0,Error Interrupt disable" "ERR_DIS0_0,ERR_DIS0_1" bitfld.long 0x10 7. "ERR_ST7,ST_PDDA bank conflict error status" "ERR_ST7_0,ERR_ST7_1" bitfld.long 0x10 6. "ERR_ST6,ST WBUF out-of-bound error status" "ERR_ST6_0,ERR_ST6_1" newline bitfld.long 0x10 5. "ERR_ST5,ST IBUF out-of-bound error status" "ERR_ST5_0,ERR_ST5_1" bitfld.long 0x10 4. "ERR_ST4,LD WBUF out-of-bound error status" "ERR_ST4_0,ERR_ST4_1" bitfld.long 0x10 3. "ERR_ST3,LD IBUF out-of-bound error status" "ERR_ST3_0,ERR_ST3_1" bitfld.long 0x10 2. "ERR_ST2,Illegal parameter error status" "ERR_ST2_0,ERR_ST2_1" bitfld.long 0x10 1. "ERR_ST1,Illegal instruction error status" "ERR_ST1_0,ERR_ST1_1" newline bitfld.long 0x10 0. "ERR_ST0,Illegal instruction error status" "ERR_ST0_0,ERR_ST0_1" rgroup.long 0x20++0x07 line.long 0x00 "VCOP_VLOOP_PTR,The VLOOP pointer" line.long 0x04 "VCOP_PARAM_PTR," rgroup.long 0x30++0x0B line.long 0x00 "VCOP_I0_I1,I0. I1 loop variables register provides a snapshot of i0 and i1" hexmask.long.word 0x00 16.--31. 1. "I1,Snapshot of I1 loop variable" hexmask.long.word 0x00 0.--15. 1. "I0,Snapshot of I0 loop variable" line.long 0x04 "VCOP_I2_I3,I2. I3 loop variables register provides a snapshot of i2 and i3" hexmask.long.word 0x04 16.--31. 1. "I3,Snapshot of I2 loop variable" hexmask.long.word 0x04 0.--15. 1. "I2,Snapshot of I3 loop variable" line.long 0x08 "VCOP_I4,I4 loop variables register provides a snapshot of i4" hexmask.long.word 0x08 0.--15. 1. "I4,Snapshot of I4 loop variable" repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. ) tree "Channel_$1" rgroup.long 0x40++0x03 line.long 0x00 "VCOP_LD_PTR_i_0,The LD pointer registers 0 to 7 or (VCOP_LD_PTR(0..7)) is a snapshot of the LD memory address" rgroup.long 0x60++0x03 line.long 0x00 "VCOP_ST_PTR_j_0,The ST pointer registers 0 to 7 (VCOP_VLOOP_ST_PTR(0..7)) is a snapshot of the ST memory address" tree.end repeat.end tree.end tree.end tree.open "VCP_Overview" tree "VCP1_L3_MAIN" base ad:0x46400000 group.long 0x00++0x17 line.long 0x00 "VCP_VCPIC0,The VCP version 2 Input Configuration Register 0" hexmask.long.byte 0x00 24.--31. 1. "POLY3,Polynomial generator G" hexmask.long.byte 0x00 16.--23. 1. "POLY2,Polynomial generator G" hexmask.long.byte 0x00 8.--15. 1. "POLY1,Polynomial generator G" hexmask.long.byte 0x00 0.--7. 1. "POLY0,Polynomial generator G" line.long 0x04 "VCP_VCPIC1,The VCP version 2 Input Configuration Register 1" bitfld.long 0x04 28. "YAMEN,Yamamoto algorithm enable bit" "YAMEN_0,YAMEN_1" hexmask.long.word 0x04 16.--27. 1. "YAMT,Yamamoto threshold value bits" line.long 0x08 "VCP_VCPIC2,The VCP version 2 Input Configuration Register 2" hexmask.long.word 0x08 16.--31. 1. "R,Reliability length bits" hexmask.long.word 0x08 0.--15. 1. "F,Frame length bits" line.long 0x0C "VCP_VCPIC3,The VCP version 2 Input Configuration Register 3" bitfld.long 0x0C 28. "OUT_ORDER,Defines the order of VCP output for decoded data" "OUT_ORDER_0,OUT_ORDER_1" bitfld.long 0x0C 24. "ITBEN,Traceback state index enable/disable" "ITBEN_0,ITBEN_1" hexmask.long.byte 0x0C 16.--23. 1. "ITBI,Traceback state index" hexmask.long.word 0x0C 0.--15. 1. "C,Convergence distance bits" line.long 0x10 "VCP_VCPIC4,The VCP version 2 Input Configuration Register 4" hexmask.long.word 0x10 16.--28. 1. "IMINS,Minimum initial state metric value bits" hexmask.long.word 0x10 0.--12. 1. "IMAXS,Maximum initial state metric value bits" line.long 0x14 "VCP_VCPIC5,The VCP version 2 Input Configuration Register 5" bitfld.long 0x14 31. "SDHD,Output decision type select bit" "SDHD_0,SDHD_1" bitfld.long 0x14 30. "OUTF,Output parameters read flag bit" "OUTF_0,OUTF_1" bitfld.long 0x14 28.--29. "TB,Traceback mode select bits" "TB_0,TB_1,TB_2,TB_3" bitfld.long 0x14 20.--24. "SYMR,Determines decision buffer length in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--19. "SYMX,Determines branch metrics buffer length in input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x14 0.--7. 1. "IMAXI,Maximum initial state metric value bits" group.long 0x48++0x07 line.long 0x00 "VCP_VCPOUT0,The VCP version 2 Output Register 0" hexmask.long.word 0x00 16.--28. 1. "FMINS,Minimum initial state metric value for the final trellis stage" hexmask.long.word 0x00 0.--12. 1. "FMAXS,Maximum state metric value for the final trellis stage (at trellis stage R+C)" line.long 0x04 "VCP_VCPOUT1,The VCP version 2 Output Register 1" bitfld.long 0x04 16. "YAM,Yamamoto bit result" "YAM_0,YAM_1" hexmask.long.byte 0x04 0.--7. 1. "FMAXI,State index for the state with the final maximum state metric" group.long 0x80++0x03 line.long 0x00 "VCP_VCPWBM,VCP branch metrics write FIFO register" rgroup.long 0xC0++0x03 line.long 0x00 "VCP_VCPRDECS,VCP decisions read FIFO register" tree.end tree "VCP2_L3_MAIN" base ad:0x46800000 group.long 0x00++0x17 line.long 0x00 "VCP_VCPIC0,The VCP version 2 Input Configuration Register 0" hexmask.long.byte 0x00 24.--31. 1. "POLY3,Polynomial generator G" hexmask.long.byte 0x00 16.--23. 1. "POLY2,Polynomial generator G" hexmask.long.byte 0x00 8.--15. 1. "POLY1,Polynomial generator G" hexmask.long.byte 0x00 0.--7. 1. "POLY0,Polynomial generator G" line.long 0x04 "VCP_VCPIC1,The VCP version 2 Input Configuration Register 1" bitfld.long 0x04 28. "YAMEN,Yamamoto algorithm enable bit" "YAMEN_0,YAMEN_1" hexmask.long.word 0x04 16.--27. 1. "YAMT,Yamamoto threshold value bits" line.long 0x08 "VCP_VCPIC2,The VCP version 2 Input Configuration Register 2" hexmask.long.word 0x08 16.--31. 1. "R,Reliability length bits" hexmask.long.word 0x08 0.--15. 1. "F,Frame length bits" line.long 0x0C "VCP_VCPIC3,The VCP version 2 Input Configuration Register 3" bitfld.long 0x0C 28. "OUT_ORDER,Defines the order of VCP output for decoded data" "OUT_ORDER_0,OUT_ORDER_1" bitfld.long 0x0C 24. "ITBEN,Traceback state index enable/disable" "ITBEN_0,ITBEN_1" hexmask.long.byte 0x0C 16.--23. 1. "ITBI,Traceback state index" hexmask.long.word 0x0C 0.--15. 1. "C,Convergence distance bits" line.long 0x10 "VCP_VCPIC4,The VCP version 2 Input Configuration Register 4" hexmask.long.word 0x10 16.--28. 1. "IMINS,Minimum initial state metric value bits" hexmask.long.word 0x10 0.--12. 1. "IMAXS,Maximum initial state metric value bits" line.long 0x14 "VCP_VCPIC5,The VCP version 2 Input Configuration Register 5" bitfld.long 0x14 31. "SDHD,Output decision type select bit" "SDHD_0,SDHD_1" bitfld.long 0x14 30. "OUTF,Output parameters read flag bit" "OUTF_0,OUTF_1" bitfld.long 0x14 28.--29. "TB,Traceback mode select bits" "TB_0,TB_1,TB_2,TB_3" bitfld.long 0x14 20.--24. "SYMR,Determines decision buffer length in output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--19. "SYMX,Determines branch metrics buffer length in input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x14 0.--7. 1. "IMAXI,Maximum initial state metric value bits" group.long 0x48++0x07 line.long 0x00 "VCP_VCPOUT0,The VCP version 2 Output Register 0" hexmask.long.word 0x00 16.--28. 1. "FMINS,Minimum initial state metric value for the final trellis stage" hexmask.long.word 0x00 0.--12. 1. "FMAXS,Maximum state metric value for the final trellis stage (at trellis stage R+C)" line.long 0x04 "VCP_VCPOUT1,The VCP version 2 Output Register 1" bitfld.long 0x04 16. "YAM,Yamamoto bit result" "YAM_0,YAM_1" hexmask.long.byte 0x04 0.--7. 1. "FMAXI,State index for the state with the final maximum state metric" group.long 0x80++0x03 line.long 0x00 "VCP_VCPWBM,VCP branch metrics write FIFO register" rgroup.long 0xC0++0x03 line.long 0x00 "VCP_VCPRDECS,VCP decisions read FIFO register" tree.end tree "VCP1_L4_PER2Interconnect" base ad:0x48446000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION,VCP version" hexmask.long.word 0x00 16.--31. 1. "SOURCE_IP,Source of VCP IP" hexmask.long.word 0x00 0.--15. 1. "REV_IP,VCP IP Revision number" group.long 0x10++0x03 line.long 0x00 "VCP_SYSCONFIG,System Configuration Register is used to set the idle modes for the VCP modules" bitfld.long 0x00 2.--3. "IDLEMODE,Idle mode bit" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 0. "RESET_DONE,Reset done is a read only and shows the status of the reset from the idle command" "0,1" group.long 0x20++0x03 line.long 0x00 "VCP_IRQ_EOI,End of interrupt register" bitfld.long 0x00 0. "LINE_NUMBER,Software End of Interrupt (EOI) control" "0,1" group.long 0x28++0x0B line.long 0x00 "VCP_IRQSTATUS,IRQ status register captures the current active status of the interrupts after the enabling function" bitfld.long 0x00 0. "STATUS,VCP IRQ enable status" "STATUS_0,STATUS_1" line.long 0x04 "VCP_IRQENABLE_SET,The VCP set enable interrupt register allows the user to enable the VCP error interrupt" bitfld.long 0x04 0. "ENABLE_SET,VCP IRQ enable status" "ENABLE_SET_0,ENABLE_SET_1" line.long 0x08 "VCP_IRQENABLE_CLR,The VCP clear enable interrupt register allows the user to disable the VCP error interrupt" bitfld.long 0x08 0. "ENABLE_CLR,VCP IRQ enable status" "ENABLE_CLR_0,ENABLE_CLR_1" rgroup.long 0x50++0x03 line.long 0x00 "VCP_DEBUG,Debug Configuration Register is used to view that status of various events in the VCP1 and VCP2 including emulation suspend mode request and DMA status for read and write requests" bitfld.long 0x00 3. "EMUSUSP,Status of the emulation suspend mode request" "EMUSUSP_0,EMUSUSP_1" bitfld.long 0x00 1. "DMA_X_REQ,Status of the VCP tranmit event (VCPnXEVT)" "DMA_X_REQ_0,DMA_X_REQ_1" bitfld.long 0x00 0. "DMA_R_REQ,Status of the VCP receive event (VCPnREVT)" "DMA_R_REQ_0,DMA_R_REQ_1" group.long 0x118++0x03 line.long 0x00 "VCP_VCPEXE,VCP version 2 execution register" bitfld.long 0x00 0.--3. "COMMAND,VCP command select bits" "COMMAND_0,COMMAND_1,COMMAND_2,COMMAND_3,COMMAND_4,COMMAND_5,COMMAND_6,?,?,?,?,?,?,?,?,?" group.long 0x120++0x03 line.long 0x00 "VCP_VCPEND,VCP Endian Mode Register" bitfld.long 0x00 9. "SLPZVSS_EN,Sleep mode for SLPZVSS_EN" "SLPZVSS_EN_0,?" bitfld.long 0x00 8. "SLPZVDD_EN,Sleep mode for SLPZVDD_EN" "SLPZVDD_EN_0,?" bitfld.long 0x00 1. "SD,Traceback soft-decision memory format select bit" "SD_0,SD_1" bitfld.long 0x00 0. "BM,Branch metrics memory format select bit" "BM_0,BM_1" rgroup.long 0x140++0x07 line.long 0x00 "VCP_VCPSTAT0,VCP Status Register 0" hexmask.long.tbyte 0x00 12.--28. 1. "NSYMPROC,Number of symbols processed bits" bitfld.long 0x00 6. "EMUHALT,Emulation halt status bit" "EMUHALT_0,EMUHALT_1" bitfld.long 0x00 5. "OFFUL,Output FIFO buffer full status bit" "OFFUL_0,OFFUL_1" bitfld.long 0x00 4. "IFEMP,Input FIFO buffer empty status bit" "IFEMP_0,IFEMP_1" bitfld.long 0x00 3. "WIC,Waiting for input configuration bit" "WIC_0,WIC_1" newline bitfld.long 0x00 2. "ERR,VCP error status bit" "ERR_0,ERR_1" bitfld.long 0x00 1. "RUN,VCP running status bit" "RUN_0,RUN_1" bitfld.long 0x00 0. "PAUSE,VCP pause status bit" "PAUSE_0,PAUSE_1" line.long 0x04 "VCP_VCPSTAT1,VCP Status Register 1" hexmask.long.word 0x04 16.--31. 1. "NSYMOF,Number of symbols in the output FIFO buffer" hexmask.long.word 0x04 0.--15. 1. "NSYMIF,Number of symbols in the input FIFO buffer" rgroup.long 0x150++0x03 line.long 0x00 "VCP_VCPERR,VCP Error Register" bitfld.long 0x00 6. "E_SYMR,SMAR error" "E_SYMR_0,E_SYMR_1" bitfld.long 0x00 5. "E_SYMX,SMAX Error" "E_SYMX_0,E_SYMX_1" bitfld.long 0x00 4. "MAXIMINERR,MAXIMIN ERROR" "MAXIMINERR_0,MAXIMINERR_1" bitfld.long 0x00 3. "FCTLERR,FCTL error" "FCTLERR_0,FCTLERR_1" bitfld.long 0x00 2. "FTLERR,FTL Error" "FTLERR_0,FTLERR_1" newline bitfld.long 0x00 1. "TBNAERR,TBNA Error" "TBNAERR_0,TBNAERR_1" bitfld.long 0x00 0. "ERROR,Error" "ERROR_0,ERROR_1" group.long 0x160++0x03 line.long 0x00 "VCP_VCPEMU,VCP Emulation Control Register" bitfld.long 0x00 1. "SOFT,Soft bit" "SOFT_0,SOFT_1" bitfld.long 0x00 0. "FREE,Free bit" "FREE_0,FREE_1" tree.end tree "VCP2_L4_PER2Interconnect" base ad:0x48448000 rgroup.long 0x00++0x03 line.long 0x00 "REVISION,VCP version" hexmask.long.word 0x00 16.--31. 1. "SOURCE_IP,Source of VCP IP" hexmask.long.word 0x00 0.--15. 1. "REV_IP,VCP IP Revision number" group.long 0x10++0x03 line.long 0x00 "VCP_SYSCONFIG,System Configuration Register is used to set the idle modes for the VCP modules" bitfld.long 0x00 2.--3. "IDLEMODE,Idle mode bit" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" rbitfld.long 0x00 0. "RESET_DONE,Reset done is a read only and shows the status of the reset from the idle command" "0,1" group.long 0x20++0x03 line.long 0x00 "VCP_IRQ_EOI,End of interrupt register" bitfld.long 0x00 0. "LINE_NUMBER,Software End of Interrupt (EOI) control" "0,1" group.long 0x28++0x0B line.long 0x00 "VCP_IRQSTATUS,IRQ status register captures the current active status of the interrupts after the enabling function" bitfld.long 0x00 0. "STATUS,VCP IRQ enable status" "STATUS_0,STATUS_1" line.long 0x04 "VCP_IRQENABLE_SET,The VCP set enable interrupt register allows the user to enable the VCP error interrupt" bitfld.long 0x04 0. "ENABLE_SET,VCP IRQ enable status" "ENABLE_SET_0,ENABLE_SET_1" line.long 0x08 "VCP_IRQENABLE_CLR,The VCP clear enable interrupt register allows the user to disable the VCP error interrupt" bitfld.long 0x08 0. "ENABLE_CLR,VCP IRQ enable status" "ENABLE_CLR_0,ENABLE_CLR_1" rgroup.long 0x50++0x03 line.long 0x00 "VCP_DEBUG,Debug Configuration Register is used to view that status of various events in the VCP1 and VCP2 including emulation suspend mode request and DMA status for read and write requests" bitfld.long 0x00 3. "EMUSUSP,Status of the emulation suspend mode request" "EMUSUSP_0,EMUSUSP_1" bitfld.long 0x00 1. "DMA_X_REQ,Status of the VCP tranmit event (VCPnXEVT)" "DMA_X_REQ_0,DMA_X_REQ_1" bitfld.long 0x00 0. "DMA_R_REQ,Status of the VCP receive event (VCPnREVT)" "DMA_R_REQ_0,DMA_R_REQ_1" group.long 0x118++0x03 line.long 0x00 "VCP_VCPEXE,VCP version 2 execution register" bitfld.long 0x00 0.--3. "COMMAND,VCP command select bits" "COMMAND_0,COMMAND_1,COMMAND_2,COMMAND_3,COMMAND_4,COMMAND_5,COMMAND_6,?,?,?,?,?,?,?,?,?" group.long 0x120++0x03 line.long 0x00 "VCP_VCPEND,VCP Endian Mode Register" bitfld.long 0x00 9. "SLPZVSS_EN,Sleep mode for SLPZVSS_EN" "SLPZVSS_EN_0,?" bitfld.long 0x00 8. "SLPZVDD_EN,Sleep mode for SLPZVDD_EN" "SLPZVDD_EN_0,?" bitfld.long 0x00 1. "SD,Traceback soft-decision memory format select bit" "SD_0,SD_1" bitfld.long 0x00 0. "BM,Branch metrics memory format select bit" "BM_0,BM_1" rgroup.long 0x140++0x07 line.long 0x00 "VCP_VCPSTAT0,VCP Status Register 0" hexmask.long.tbyte 0x00 12.--28. 1. "NSYMPROC,Number of symbols processed bits" bitfld.long 0x00 6. "EMUHALT,Emulation halt status bit" "EMUHALT_0,EMUHALT_1" bitfld.long 0x00 5. "OFFUL,Output FIFO buffer full status bit" "OFFUL_0,OFFUL_1" bitfld.long 0x00 4. "IFEMP,Input FIFO buffer empty status bit" "IFEMP_0,IFEMP_1" bitfld.long 0x00 3. "WIC,Waiting for input configuration bit" "WIC_0,WIC_1" newline bitfld.long 0x00 2. "ERR,VCP error status bit" "ERR_0,ERR_1" bitfld.long 0x00 1. "RUN,VCP running status bit" "RUN_0,RUN_1" bitfld.long 0x00 0. "PAUSE,VCP pause status bit" "PAUSE_0,PAUSE_1" line.long 0x04 "VCP_VCPSTAT1,VCP Status Register 1" hexmask.long.word 0x04 16.--31. 1. "NSYMOF,Number of symbols in the output FIFO buffer" hexmask.long.word 0x04 0.--15. 1. "NSYMIF,Number of symbols in the input FIFO buffer" rgroup.long 0x150++0x03 line.long 0x00 "VCP_VCPERR,VCP Error Register" bitfld.long 0x00 6. "E_SYMR,SMAR error" "E_SYMR_0,E_SYMR_1" bitfld.long 0x00 5. "E_SYMX,SMAX Error" "E_SYMX_0,E_SYMX_1" bitfld.long 0x00 4. "MAXIMINERR,MAXIMIN ERROR" "MAXIMINERR_0,MAXIMINERR_1" bitfld.long 0x00 3. "FCTLERR,FCTL error" "FCTLERR_0,FCTLERR_1" bitfld.long 0x00 2. "FTLERR,FTL Error" "FTLERR_0,FTLERR_1" newline bitfld.long 0x00 1. "TBNAERR,TBNA Error" "TBNAERR_0,TBNAERR_1" bitfld.long 0x00 0. "ERROR,Error" "ERROR_0,ERROR_1" group.long 0x160++0x03 line.long 0x00 "VCP_VCPEMU,VCP Emulation Control Register" bitfld.long 0x00 1. "SOFT,Soft bit" "SOFT_0,SOFT_1" bitfld.long 0x00 0. "FREE,Free bit" "FREE_0,FREE_1" tree.end tree.end tree.open "VIP" tree "VIP1_Slice0_csc" base ad:0x48975700 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" tree.end tree "VIP1_Slice1_csc" base ad:0x48975C00 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" tree.end tree "VIP2_Slice0_csc" base ad:0x48995700 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" tree.end tree "VIP2_Slice1_csc" base ad:0x48995C00 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" tree.end tree "VIP3_Slice0_csc" base ad:0x489B5700 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" tree.end tree "VIP3_Slice1_csc" base ad:0x489B5C00 group.long 0x00++0x17 line.long 0x00 "VIP_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Coefficients of color space converter" line.long 0x04 "VIP_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VIP_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VIP_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VIP_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VIP_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" tree.end tree "VIP1_Slice0_parser" base ad:0x48975500 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "0,1" bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "0,1" bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "0,1,2,3" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" bitfld.long 0x04 8. "ENABLE," "0,1" bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "0,1,2,3" bitfld.long 0x04 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" bitfld.long 0x0C 8. "ENABLE," "0,1" bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" bitfld.long 0x0C 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" tree.end tree "VIP1_Slice1_parser" base ad:0x48975A00 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "0,1" bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "0,1" bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "0,1,2,3" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" bitfld.long 0x04 8. "ENABLE," "0,1" bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "0,1,2,3" bitfld.long 0x04 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" bitfld.long 0x0C 8. "ENABLE," "0,1" bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" bitfld.long 0x0C 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" tree.end tree "VIP2_Slice0_parser" base ad:0x48995500 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "0,1" bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "0,1" bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "0,1,2,3" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" bitfld.long 0x04 8. "ENABLE," "0,1" bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "0,1,2,3" bitfld.long 0x04 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" bitfld.long 0x0C 8. "ENABLE," "0,1" bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" bitfld.long 0x0C 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" tree.end tree "VIP2_Slice1_parser" base ad:0x48995A00 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "0,1" bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "0,1" bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "0,1,2,3" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" bitfld.long 0x04 8. "ENABLE," "0,1" bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "0,1,2,3" bitfld.long 0x04 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" bitfld.long 0x0C 8. "ENABLE," "0,1" bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" bitfld.long 0x0C 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" tree.end tree "VIP3_Slice0_parser" base ad:0x489B5500 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "0,1" bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "0,1" bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "0,1,2,3" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" bitfld.long 0x04 8. "ENABLE," "0,1" bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "0,1,2,3" bitfld.long 0x04 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" bitfld.long 0x0C 8. "ENABLE," "0,1" bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" bitfld.long 0x0C 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" tree.end tree "VIP3_Slice1_parser" base ad:0x489B5A00 group.long 0x00++0xDF line.long 0x00 "VIP_MAIN,ain Configuration for VIP Parser" bitfld.long 0x00 5. "CLIP_ACTIVE,Discrete Sync Only" "0,1" bitfld.long 0x00 4. "CLIP_BLNK,Discrete Sync Only" "0,1" bitfld.long 0x00 0.--1. "DATA_INTERFACE_MODE," "0,1,2,3" line.long 0x04 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x04 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x04 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x04 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 23. "SW_RESET," "0,1" bitfld.long 0x04 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x04 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x04 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x04 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x04 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x04 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x04 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x04 9. "FID_POLARITY," "0,1" bitfld.long 0x04 8. "ENABLE," "0,1" bitfld.long 0x04 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x04 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x04 4.--5. "CTRL_CHAN_SEL,Embedded Sync Only In 8b mode" "0,1,2,3" bitfld.long 0x04 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" bitfld.long 0x08 28.--30. "REPACK_SEL," "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x08 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" newline hexmask.long.word 0x08 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x0C "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0C 31. "ANALYZER_FVH_ERR_CORRECTION_ENABLE,Embedded Sync Only" "0,1" bitfld.long 0x0C 30. "ANALYZER_2X4X_SRCNUM_POS,Embedded Sync Only" "0,1" bitfld.long 0x0C 24.--29. "FID_SKEW_POSTCOUNT,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 23. "SW_RESET," "0,1" bitfld.long 0x0C 22. "DISCRETE_BASIC_MODE,This register is valid for Discrete Sync mode only" "0,1" bitfld.long 0x0C 16.--21. "FID_SKEW_PRECOUNT,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x0C 15. "USE_ACTVID_HSYNC_N,Discrete Sync Only" "0,1" bitfld.long 0x0C 14. "FID_DETECT_MODE,Discrete Sync Only" "0,1" bitfld.long 0x0C 13. "ACTVID_POLARITY,Discrete Sync Only" "0,1" newline bitfld.long 0x0C 12. "VSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 11. "HSYNC_POLARITY,Discrete Sync Only" "0,1" bitfld.long 0x0C 10. "PIXCLK_EDGE_POLARITY," "0,1" newline bitfld.long 0x0C 9. "FID_POLARITY," "0,1" bitfld.long 0x0C 8. "ENABLE," "0,1" bitfld.long 0x0C 7. "CLR_ASYNC_FIFO_RD," "0,1" newline bitfld.long 0x0C 6. "CLR_ASYNC_FIFO_WR," "0,1" bitfld.long 0x0C 4.--5. "CTRL_CHAN_SEL,PORT B supports on 8b mode" "0,1,2,3" bitfld.long 0x0C 0.--3. "SYNC_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x10 16.--27. 1. "SRC0_NUMPIX,Number of expected pixels on Source Number 0" bitfld.long 0x10 13.--14. "ANC_CHAN_SEL_8B,In 8b mode Vertically Ancillary Data typically resides in the Luma sites" "0,1,2,3" hexmask.long.word 0x10 0.--11. 1. "SRC0_NUMLINES,Number of expected lines on Source Number 0" line.long 0x14 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x14 21. "PORT_B_CFG_DISABLE_COMPLETE_MASK,Port B Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 20. "PORT_A_CFG_DISABLE_COMPLETE_MASK,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x14 19. "PORT_B_ANC_PROTOCOL_VIOLATION_MASK,Port B ANC VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 18. "PORT_B_YUV_PROTOCOL_VIOLATION_MASK,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 17. "PORT_A_ANC_PROTOCOL_VIOLATION_MASK,Port A ANC VPI Protocol Violation Mask" "0,1" bitfld.long 0x14 16. "PORT_A_YUV_PROTOCOL_VIOLATION_MASK,Port A YUV VPI Protocol Violation Mask" "0,1" newline bitfld.long 0x14 15. "PORT_B_SRC0_SIZE,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" bitfld.long 0x14 14. "PORT_A_SRC0_SIZE,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x14 13. "PORT_B_DISCONN,Port B Link Disconnect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 12. "PORT_B_CONN,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x14 11. "PORT_A_DISCONN,Port A Link Disconnect Scrnum 0 Mask" "0,1" bitfld.long 0x14 10. "PORT_A_CONN,Port A Link Connect Srcnum 0 Mask" "0,1" newline bitfld.long 0x14 9. "OUTPUT_FIFO_PRTB_ANC_OF,Output FIFO Port B Ancillary Overflow Mask" "0,1" bitfld.long 0x14 7. "OUTPUT_FIFO_PRTB_YUV_OF,Output FIFO Port B Luma Overflow Mask" "0,1" bitfld.long 0x14 6. "OUTPUT_FIFO_PRTA_ANC_OF,Output FIFO Port A Ancillary Overflow Mask" "0,1" newline bitfld.long 0x14 4. "OUTPUT_FIFO_PRTA_YUV_OF,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x14 3. "ASYNC_FIFO_PRTB_OF,Port B Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x14 2. "ASYNC_FIFO_PRTA_OF,Port A Async FIFO Overflow FIQ Mask" "0,1" newline bitfld.long 0x14 1. "PRTB_VDET_MASK,Port B Video Detect FIQ Mask" "0,1" bitfld.long 0x14 0. "PRTA_VDET_MASK,Port A Video Detect FIQ Mask" "0,1" line.long 0x18 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x18 21. "PORT_A_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 20. "PORT_A_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x18 19. "PORT_B_YUV_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 18. "PORT_B_ANC_PROTOCOL_VIOLATION_CLR,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 17. "PORT_A_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x18 16. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x18 15. "PORT_B_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" bitfld.long 0x18 14. "PORT_A_SRC0_SIZE_CLR,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x18 13. "PORT_B_DISCONN_CLR,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" newline bitfld.long 0x18 12. "PORT_B_CONN_CLR,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x18 11. "PORT_A_DISCONN_CLR,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" bitfld.long 0x18 10. "PORT_A_CONN_CLR,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" newline bitfld.long 0x18 9. "OUTPUT_FIFO_PRTB_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" bitfld.long 0x18 7. "OUTPUT_FIFO_PRTB_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" bitfld.long 0x18 6. "OUTPUT_FIFO_PRTA_ANC_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" newline bitfld.long 0x18 4. "OUTPUT_FIFO_PRTA_YUV_CLR,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x18 3. "ASYNC_FIFO_PRTB_CLR,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" bitfld.long 0x18 2. "ASYNC_FIFO_PRTA_CLR,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" newline bitfld.long 0x18 1. "PRTB_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" bitfld.long 0x18 0. "PRTA_VDET_CLR,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" line.long 0x1C "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x1C 21. "PORT_B_CFG_DISABLE_COMPLETE_CLR,Port B Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 20. "PORT_A_CFG_DISABLE_COMPLETE,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x1C 19. "PORT_B_ANC_PROTOCOL_VIOLATION,Port B ANC VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 18. "PORT_B_YUV_PROTOCOL_VIOLATION,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 17. "PORT_A_ANC_PROTOCOL_VIOLATION,Port A ANC VPI Protocol Violation FIQ" "0,1" bitfld.long 0x1C 16. "PORT_A_YUV_PROTOCOL_VIOLATION,Port A YUV VPI Protocol Violation FIQ" "0,1" newline bitfld.long 0x1C 15. "PORT_B_SRC0_SIZE_STATUS,Port B Source 0 Size FIQ" "0,1" bitfld.long 0x1C 14. "PORT_A_SRC0_SIZE_STATUS,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x1C 13. "PORT_B_DISCONN_STATUS,Port B Disconnect FIQ" "0,1" newline bitfld.long 0x1C 12. "PORT_B_CONN_STATUS,Port B Connect FIQ" "0,1" bitfld.long 0x1C 11. "PORT_A_DISCONN_STATUS,Port A Disconnect FIQ" "0,1" bitfld.long 0x1C 10. "PORT_A_CONN_STATUS,Port A Connect FIQ" "0,1" newline bitfld.long 0x1C 9. "OUTPUT_FIFO_PRTB_ANC_STATUS,Output FIFO Port B Ancillary Overflow Status" "0,1" bitfld.long 0x1C 8. "OUTPUT_FIFO_PRTB_CHROMA_STATUS,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x1C 7. "OUTPUT_FIFO_PRTB_LUMA_STATUS,Output FIFO Port B Luma Overflow Status" "0,1" newline bitfld.long 0x1C 6. "OUTPUT_FIFO_PRTA_ANC_STATUS,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x1C 5. "OUTPUT_FIFO_PRTA_CHROMA_STATUS,Output FIFO Port A Chroma Overflow Status" "0,1" bitfld.long 0x1C 4. "OUTPUT_FIFO_PRTA_LUMA_STATUS,Output FIFO Port A Luma Overflow Status" "0,1" newline bitfld.long 0x1C 3. "ASYNC_FIFO_PRTB_STATUS,Async FIFO Port B Overflow Status" "0,1" bitfld.long 0x1C 2. "ASYNC_FIFO_PRTA_STATUS,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x1C 1. "PRTB_VDET_STATUS,VDET Status for Port B" "0,1" newline bitfld.long 0x1C 0. "PRTA_VDET_STATUS,VDET Status for Port A" "0,1" line.long 0x20 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x20 31. "PRTA_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 30. "PRTA_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x20 29. "PRTA_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x20 28. "PRTA_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x20 27. "PRTA_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x20 26. "PRTA_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x20 25. "PRTA_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 24. "PRTA_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x20 23. "PRTA_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x20 22. "PRTA_SRC11_PREV_SOURCE_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x20 21. "PRTA_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x20 20. "PRTA_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x20 19. "PRTA_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 18. "PRTA_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x20 17. "PRTA_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x20 16. "PRTA_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x20 15. "PRTA_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x20 14. "PRTA_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x20 13. "PRTA_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 12. "PRTA_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x20 11. "PRTA_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x20 10. "PRTA_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x20 9. "PRTA_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x20 8. "PRTA_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x20 7. "PRTA_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 6. "PRTA_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x20 5. "PRTA_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x20 4. "PRTA_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x20 3. "PRTA_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x20 2. "PRTA_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x20 1. "PRTA_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x20 0. "PRTA_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port A" "0,1" line.long 0x24 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x24 31. "PRTA_SRC15_CURR_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 30. "PRTA_SRC15_PREV_ENC_FID,For Source ID 15 from Port A" "0,1" bitfld.long 0x24 29. "PRTA_SRC14_CURR_ENC_FID,For Source ID 14 from Port A" "0,1" newline bitfld.long 0x24 28. "PRTA_SRC14_PREV_ENC_FID,For Source ID 14 from Port A" "0,1" bitfld.long 0x24 27. "PRTA_SRC13_CURR_ENC_FID,For Source ID 13 from Port A" "0,1" bitfld.long 0x24 26. "PRTA_SRC13_PREV_ENC_FID,For Source ID 13 from Port A" "0,1" newline bitfld.long 0x24 25. "PRTA_SRC12_CURR_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 24. "PRTA_SRC12_PREV_ENC_FID,For Source ID 12 from Port A" "0,1" bitfld.long 0x24 23. "PRTA_SRC11_CURR_ENC_FID,For Source ID 11 from Port A" "0,1" newline bitfld.long 0x24 22. "PRTA_SRC11_PREV_ENC_FID,For Source ID 11 from Port A" "0,1" bitfld.long 0x24 21. "PRTA_SRC10_CURR_ENC_FID,For Source ID 10 from Port A" "0,1" bitfld.long 0x24 20. "PRTA_SRC10_PREV_ENC_FID,For Source ID 10 from Port A" "0,1" newline bitfld.long 0x24 19. "PRTA_SRC9_CURR_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 18. "PRTA_SRC9_PREV_ENC_FID,For Source ID 9 from Port A" "0,1" bitfld.long 0x24 17. "PRTA_SRC8_CURR_ENC_FID,For Source ID 8 from Port A" "0,1" newline bitfld.long 0x24 16. "PRTA_SRC8_PREV_ENC_FID,For Source ID 8 from Port A" "0,1" bitfld.long 0x24 15. "PRTA_SRC7_CURR_ENC_FID,For Source ID 7 from Port A" "0,1" bitfld.long 0x24 14. "PRTA_SRC7_PREV_ENC_FID,For Source ID 7 from Port A" "0,1" newline bitfld.long 0x24 13. "PRTA_SRC6_CURR_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 12. "PRTA_SRC6_PREV_ENC_FID,For Source ID 6 from Port A" "0,1" bitfld.long 0x24 11. "PRTA_SRC5_CURR_ENC_FID,For Source ID 5 from Port A" "0,1" newline bitfld.long 0x24 10. "PRTA_SRC5_PREV_ENC_FID,For Source ID 5 from Port A" "0,1" bitfld.long 0x24 9. "PRTA_SRC4_CURR_ENC_FID,For Source ID 4 from Port A" "0,1" bitfld.long 0x24 8. "PRTA_SRC4_PREV_ENC_FID,For Source ID 4 from Port A" "0,1" newline bitfld.long 0x24 7. "PRTA_SRC3_CURR_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 6. "PRTA_SRC3_PREV_ENC_FID,For Source ID 3 from Port A" "0,1" bitfld.long 0x24 5. "PRTA_SRC2_CURR_ENC_FID,For Source ID 2 from Port A" "0,1" newline bitfld.long 0x24 4. "PRTA_SRC2_PREV_ENC_FID,For Source ID 2 from Port A" "0,1" bitfld.long 0x24 3. "PRTA_SRC1_CURR_ENC_FID,For Source ID 1 from Port A" "0,1" bitfld.long 0x24 2. "PRTA_SRC1_PREV_ENC_FID,For Source ID 1 from Port A" "0,1" newline bitfld.long 0x24 1. "PRTA_SRC0_CURR_ENC_FID,For Source ID 0 from Port A" "0,1" bitfld.long 0x24 0. "PRTA_SRC0_PREV_ENC_FID,For Source ID 0 from Port A" "0,1" line.long 0x28 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x28 31. "PRTB_SRC15_CURR_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 30. "PRTB_SRC15_PREV_SOURCE_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x28 29. "PRTB_SRC14_CURR_SOURCE_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x28 28. "PRTB_SRC14_PREV_SOURCE_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x28 27. "PRTB_SRC13_CURR_SOURCE_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x28 26. "PRTB_SRC13_PREV_SOURCE_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x28 25. "PRTB_SRC12_CURR_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 24. "PRTB_SRC12_PREV_SOURCE_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x28 23. "PRTB_SRC11_CURR_SOURCE_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x28 22. "PRTB_SRC11_PREV_SOURCE_FID,For Source ID 11" "0,1" bitfld.long 0x28 21. "PRTB_SRC10_CURR_SOURCE_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x28 20. "PRTB_SRC10_PREV_SOURCE_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x28 19. "PRTB_SRC9_CURR_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 18. "PRTB_SRC9_PREV_SOURCE_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x28 17. "PRTB_SRC8_CURR_SOURCE_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x28 16. "PRTB_SRC8_PREV_SOURCE_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x28 15. "PRTB_SRC7_CURR_SOURCE_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x28 14. "PRTB_SRC7_PREV_SOURCE_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x28 13. "PRTB_SRC6_CURR_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 12. "PRTB_SRC6_PREV_SOURCE_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x28 11. "PRTB_SRC5_CURR_SOURCE_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x28 10. "PRTB_SRC5_PREV_SOURCE_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x28 9. "PRTB_SRC4_CURR_SOURCE_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x28 8. "PRTB_SRC4_PREV_SOURCE_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x28 7. "PRTB_SRC3_CURR_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 6. "PRTB_SRC3_PREV_SOURCE_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x28 5. "PRTB_SRC2_CURR_SOURCE_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x28 4. "PRTB_SRC2_PREV_SOURCE_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x28 3. "PRTB_SRC1_CURR_SOURCE_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x28 2. "PRTB_SRC1_PREV_SOURCE_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x28 1. "PRTB_SRC0_CURR_SOURCE_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x28 0. "PRTB_SRC0_PREV_SOURCE_FID,For Source ID 0 from Port B" "0,1" line.long 0x2C "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x2C 31. "PRTB_SRC15_CURR_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 30. "PRTB_SRC15_PREV_ENC_FID,For Source ID 15 from Port B" "0,1" bitfld.long 0x2C 29. "PRTB_SRC14_CURR_ENC_FID,For Source ID 14 from Port B" "0,1" newline bitfld.long 0x2C 28. "PRTB_SRC14_PREV_ENC_FID,For Source ID 14 from Port B" "0,1" bitfld.long 0x2C 27. "PRTB_SRC13_CURR_ENC_FID,For Source ID 13 from Port B" "0,1" bitfld.long 0x2C 26. "PRTB_SRC13_PREV_ENC_FID,For Source ID 13 from Port B" "0,1" newline bitfld.long 0x2C 25. "PRTB_SRC12_CURR_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 24. "PRTB_SRC12_PREV_ENC_FID,For Source ID 12 from Port B" "0,1" bitfld.long 0x2C 23. "PRTB_SRC11_CURR_ENC_FID,For Source ID 11 from Port B" "0,1" newline bitfld.long 0x2C 22. "PRTB_SRC11_PREV_ENC_FID,For Source ID 11 from Port B" "0,1" bitfld.long 0x2C 21. "PRTB_SRC10_CURR_ENC_FID,For Source ID 10 from Port B" "0,1" bitfld.long 0x2C 20. "PRTB_SRC10_PREV_ENC_FID,For Source ID 10 from Port B" "0,1" newline bitfld.long 0x2C 19. "PRTB_SRC9_CURR_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 18. "PRTB_SRC9_PREV_ENC_FID,For Source ID 9 from Port B" "0,1" bitfld.long 0x2C 17. "PRTB_SRC8_CURR_ENC_FID,For Source ID 8 from Port B" "0,1" newline bitfld.long 0x2C 16. "PRTB_SRC8_PREV_ENC_FID,For Source ID 8 from Port B" "0,1" bitfld.long 0x2C 15. "PRTB_SRC7_CURR_ENC_FID,For Source ID 7 from Port B" "0,1" bitfld.long 0x2C 14. "PRTB_SRC7_PREV_ENC_FID,For Source ID 7 from Port B" "0,1" newline bitfld.long 0x2C 13. "PRTB_SRC6_CURR_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 12. "PRTB_SRC6_PREV_ENC_FID,For Source ID 6 from Port B" "0,1" bitfld.long 0x2C 11. "PRTB_SRC5_CURR_ENC_FID,For Source ID 5 from Port B" "0,1" newline bitfld.long 0x2C 10. "PRTB_SRC5_PREV_ENC_FID,For Source ID 5 from Port B" "0,1" bitfld.long 0x2C 9. "PRTB_SRC4_CURR_ENC_FID,For Source ID 4 from Port B" "0,1" bitfld.long 0x2C 8. "PRTB_SRC4_PREV_ENC_FID,For Source ID 4 from Port B" "0,1" newline bitfld.long 0x2C 7. "PRTB_SRC3_CURR_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 6. "PRTB_SRC3_PREV_ENC_FID,For Source ID 3 from Port B" "0,1" bitfld.long 0x2C 5. "PRTB_SRC2_CURR_ENC_FID,For Source ID 2 from Port B" "0,1" newline bitfld.long 0x2C 4. "PRTB_SRC2_PREV_ENC_FID,For Source ID 2 from Port B" "0,1" bitfld.long 0x2C 3. "PRTB_SRC1_CURR_ENC_FID,For Source ID 1 from Port B" "0,1" bitfld.long 0x2C 2. "PRTB_SRC1_PREV_ENC_FID,For Source ID 1 from Port B" "0,1" newline bitfld.long 0x2C 1. "PRTB_SRC0_CURR_ENC_FID,For Source ID 0 from Port B" "0,1" bitfld.long 0x2C 0. "PRTB_SRC0_PREV_ENC_FID,For Source ID 0 from Port B" "0,1" line.long 0x30 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x30 16.--26. 1. "PRTA_SRC0_WIDTH,On Port A" hexmask.long.word 0x30 0.--10. 1. "PRTA_SRC0_HEIGHT,On Port A" line.long 0x34 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x34 16.--26. 1. "PRTA_SRC1_WIDTH,On Port A" hexmask.long.word 0x34 0.--10. 1. "PRTA_SRC1_HEIGHT,On Port A" line.long 0x38 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x38 16.--26. 1. "PRTA_SRC2_WIDTH,On Port A" hexmask.long.word 0x38 0.--10. 1. "PRTA_SRC2_HEIGHT,On Port A" line.long 0x3C "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x3C 16.--26. 1. "PRTA_SRC3_WIDTH,On Port A" hexmask.long.word 0x3C 0.--10. 1. "PRTA_SRC3_HEIGHT,On Port A" line.long 0x40 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x40 16.--26. 1. "PRTA_SRC4_WIDTH,On Port A" hexmask.long.word 0x40 0.--10. 1. "PRTA_SRC4_HEIGHT,On Port A" line.long 0x44 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x44 16.--26. 1. "PRTA_SRC5_WIDTH,On Port A" hexmask.long.word 0x44 0.--10. 1. "PRTA_SRC5_HEIGHT,On Port A" line.long 0x48 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x48 16.--26. 1. "PRTA_SRC6_WIDTH,On Port A" hexmask.long.word 0x48 0.--10. 1. "PRTA_SRC6_HEIGHT,On Port A" line.long 0x4C "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x4C 16.--26. 1. "PRTA_SRC7_WIDTH,On Port A" hexmask.long.word 0x4C 0.--10. 1. "PRTA_SRC7_HEIGHT,On Port A" line.long 0x50 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x50 16.--26. 1. "PRTA_SRC8_WIDTH,On Port A" hexmask.long.word 0x50 0.--10. 1. "PRTA_SRC8_HEIGHT,On Port A" line.long 0x54 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x54 16.--26. 1. "PRTA_SRC9_WIDTH,On Port A" hexmask.long.word 0x54 0.--10. 1. "PRTA_SRC9_HEIGHT,On Port A" line.long 0x58 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x58 16.--26. 1. "PRTA_SRC10_WIDTH,On Port A" hexmask.long.word 0x58 0.--10. 1. "PRTA_SRC10_HEIGHT,On Port A" line.long 0x5C "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x5C 16.--26. 1. "PRTA_SRC11_WIDTH,On Port A" hexmask.long.word 0x5C 0.--10. 1. "PRTA_SRC11_HEIGHT,On Port A" line.long 0x60 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x60 16.--26. 1. "PRTA_SRC12_WIDTH,On Port A" hexmask.long.word 0x60 0.--10. 1. "PRTA_SRC12_HEIGHT,On Port A" line.long 0x64 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x64 16.--26. 1. "PRTA_SRC13_WIDTH,On Port A" hexmask.long.word 0x64 0.--10. 1. "PRTA_SRC13_HEIGHT,On Port A" line.long 0x68 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x68 16.--26. 1. "PRTA_SRC14_WIDTH,On Port A" hexmask.long.word 0x68 0.--10. 1. "PRTA_SRC14_HEIGHT,On Port A" line.long 0x6C "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x6C 16.--26. 1. "PRTA_SRC15_WIDTH,On Port A" hexmask.long.word 0x6C 0.--10. 1. "PRTA_SRC15_HEIGHT,On Port A" line.long 0x70 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x70 16.--26. 1. "PRTB_SRC0_WIDTH,On Port B" hexmask.long.word 0x70 0.--10. 1. "PRTB_SRC0_HEIGHT,On Port B" line.long 0x74 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x74 16.--26. 1. "PRTB_SRC1_WIDTH,On Port B" hexmask.long.word 0x74 0.--10. 1. "PRTB_SRC1_HEIGHT,On Port B" line.long 0x78 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x78 16.--26. 1. "PRTB_SRC2_WIDTH,On Port B" hexmask.long.word 0x78 0.--10. 1. "PRTB_SRC2_HEIGHT,On Port B" line.long 0x7C "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x7C 16.--26. 1. "PRTB_SRC3_WIDTH,On Port B" hexmask.long.word 0x7C 0.--10. 1. "PRTB_SRC3_HEIGHT,On Port B" line.long 0x80 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x80 16.--26. 1. "PRTB_SRC4_WIDTH,On Port B" hexmask.long.word 0x80 0.--10. 1. "PRTB_SRC4_HEIGHT,On Port B" line.long 0x84 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x84 16.--26. 1. "PRTB_SRC5_WIDTH,On Port B" hexmask.long.word 0x84 0.--10. 1. "PRTB_SRC5_HEIGHT,On Port B" line.long 0x88 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x88 16.--26. 1. "PRTB_SRC6_WIDTH,On Port B" hexmask.long.word 0x88 0.--10. 1. "PRTB_SRC6_HEIGHT,On Port B" line.long 0x8C "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x8C 16.--26. 1. "PRTB_SRC7_WIDTH,On Port B" hexmask.long.word 0x8C 0.--10. 1. "PRTB_SRC7_HEIGHT,On Port B" line.long 0x90 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x90 16.--26. 1. "PRTB_SRC8_WIDTH,On Port B" hexmask.long.word 0x90 0.--10. 1. "PRTB_SRC8_HEIGHT,On Port B" line.long 0x94 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x94 16.--26. 1. "PRTB_SRC9_WIDTH,On Port B" hexmask.long.word 0x94 0.--10. 1. "PRTB_SRC9_HEIGHT,On Port B" line.long 0x98 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x98 16.--26. 1. "PRTB_SRC10_WIDTH,On Port B" hexmask.long.word 0x98 0.--10. 1. "PRTB_SRC10_HEIGHT,On Port B" line.long 0x9C "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x9C 16.--26. 1. "PRTB_SRC11_WIDTH,On Port B" hexmask.long.word 0x9C 0.--10. 1. "PRTB_SRC11_HEIGHT,On Port B" line.long 0xA0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0xA0 16.--26. 1. "PRTB_SRC12_WIDTH,On Port B" hexmask.long.word 0xA0 0.--10. 1. "PRTB_SRC12_HEIGHT,On Port B" line.long 0xA4 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0xA4 16.--26. 1. "PRTB_SRC13_WIDTH,On Port B" hexmask.long.word 0xA4 0.--10. 1. "PRTB_SRC13_HEIGHT,On Port B" line.long 0xA8 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0xA8 16.--26. 1. "PRTB_SRC14_WIDTH,On Port B" hexmask.long.word 0xA8 0.--10. 1. "PRTB_SRC14_HEIGHT,On Port B" line.long 0xAC "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0xAC 16.--26. 1. "PRTB_SRC15_WIDTH,On Port B" hexmask.long.word 0xAC 0.--10. 1. "PRTB_SRC15_HEIGHT,On Port B" line.long 0xB0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB4 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" line.long 0xB8 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" bitfld.long 0xB8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xB8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xB8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xB8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xBC "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0xBC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xBC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xC0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" bitfld.long 0xC0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xC0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xC4 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0xC4 16.--27. 1. "ACT_USE_NUMLINES,When cropping" hexmask.long.word 0xC4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xC8 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" bitfld.long 0xC8 28.--31. "ANC_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xC8 16.--27. 1. "ANC_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xC8 15. "ANC_BYPASS_N," "0,1" newline hexmask.long.word 0xC8 0.--11. 1. "ANC_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xCC "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0xCC 16.--27. 1. "ANC_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xCC 0.--11. 1. "ANC_SKIP_NUMLINES,The number of lines to crop from the top of the vertical ancillary data region" line.long 0xD0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" bitfld.long 0xD0 28.--31. "ACT_TARGET_SRCNUM,The cropping module can work on only one srcnum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0xD0 16.--27. 1. "ACT_USE_NUMPIX,When cropping the number of pixels to keep after the skip_numpix value" bitfld.long 0xD0 15. "ACT_BYPASS_N," "0,1" newline hexmask.long.word 0xD0 0.--11. 1. "ACT_SKIP_NUMPIX,The number of pixels to crop from the beginning of each line" line.long 0xD4 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0xD4 16.--27. 1. "ACT_USE_NUMLINES,When cropping the number of lines to keep after the skip_numlines value" hexmask.long.word 0xD4 0.--11. 1. "ACT_SKIP_NUMLINES,The number of lines to crop from the top of the vertical active video region" line.long 0xD8 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0xD8 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xD8 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" line.long 0xDC "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0xDC 16.--31. 1. "YUV_SRCNUM_STOP_IMMEDIATELY,For the Active Video Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hexmask.long.word 0xDC 0.--15. 1. "ANC_SRCNUM_STOP_IMMEDIATELY,For the Ancillary Data Port to the VPDMA logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port" hgroup.long 0xE0++0x07 hide.long 0x00 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hide.long 0x04 "VIP_XTRA9_PORT_B,Reserved Register for Port B" tree.end tree "VIP1_Slice0_sc" base ad:0x48975800 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "0,1" bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "0,1" bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "0,1" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "0,1" newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "0,1" bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "0,1" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "0,1" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" tree.end tree "VIP1_Slice1_sc" base ad:0x48975D00 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "0,1" bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "0,1" bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "0,1" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "0,1" newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "0,1" bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "0,1" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "0,1" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" tree.end tree "VIP2_Slice0_sc" base ad:0x48995800 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "0,1" bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "0,1" bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "0,1" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "0,1" newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "0,1" bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "0,1" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "0,1" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" tree.end tree "VIP2_Slice1_sc" base ad:0x48995D00 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "0,1" bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "0,1" bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "0,1" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "0,1" newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "0,1" bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "0,1" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "0,1" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" tree.end tree "VIP3_Slice0_sc" base ad:0x489B5800 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "0,1" bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "0,1" bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "0,1" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "0,1" newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "0,1" bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "0,1" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "0,1" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" tree.end tree "VIP3_Slice1_sc" base ad:0x489B5D00 group.long 0x00++0x1B line.long 0x00 "VIP_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "0,1" bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "0,1" bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by both horizontal and vertical scaling" "0,1" newline bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "0,1" newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by the edge-detection block" "0,1" bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is used by vertical scaling" "0,1" bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is a general purpose" "0,1" newline bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "0,1" line.long 0x04 "VIP_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VIP_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VIP_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VIP_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VIP_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VIP_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VIP_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC9," line.long 0x08 "VIP_CFG_SC10," line.long 0x0C "VIP_CFG_SC11," line.long 0x10 "VIP_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VIP_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VIP_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VIP_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VIP_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VIP_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VIP_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VIP_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VIP_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" tree.end tree "VIP1_top_level" base ad:0x48970000 rgroup.long 0x00++0x03 line.long 0x00 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used" bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,ajor Release Number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3" bitfld.long 0x00 0.--5. "MINOR,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "VIP_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "0,1,2,3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" group.long 0x20++0x3F line.long 0x00 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0" bitfld.long 0x00 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x00 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "0,1" newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "0,1" newline bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "0,1" line.long 0x04 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1" bitfld.long 0x04 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" newline bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "0,1" bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "0,1" bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "0,1" bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "0,1" bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "0,1" line.long 0x08 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x08 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x08 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "0,1" line.long 0x0C "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x0C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" newline bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "0,1" line.long 0x10 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0" bitfld.long 0x10 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "0,1" line.long 0x14 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1" bitfld.long 0x14 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "0,1" line.long 0x18 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0" bitfld.long 0x18 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x1C "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1" bitfld.long 0x1C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x20 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0" bitfld.long 0x20 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x20 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x20 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "0,1" newline bitfld.long 0x20 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "0,1" newline bitfld.long 0x20 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "0,1" line.long 0x24 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1" bitfld.long 0x24 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" newline bitfld.long 0x24 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "0,1" bitfld.long 0x24 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "0,1" newline bitfld.long 0x24 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "0,1" bitfld.long 0x24 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "0,1" bitfld.long 0x24 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "0,1" newline bitfld.long 0x24 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "0,1" bitfld.long 0x24 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "0,1" line.long 0x28 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x28 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x28 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x28 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x28 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x28 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "0,1" line.long 0x2C "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x2C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" newline bitfld.long 0x2C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x2C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x2C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "0,1" line.long 0x30 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0" bitfld.long 0x30 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "0,1" line.long 0x34 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1" bitfld.long 0x34 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "0,1" line.long 0x38 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0" bitfld.long 0x38 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x3C "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1" bitfld.long 0x3C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "0,1" group.long 0xA0++0x03 line.long 0x00 "VIP_INTC_EOI,INTC EOI Register" group.long 0x100++0x13 line.long 0x00 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register" bitfld.long 0x00 17. "VIP2_DP_EN,Video Input Port 2 Data Path Clock Enable " "0,1" bitfld.long 0x00 16. "VIP1_DP_EN,Video Input Port 1 Data Path Clock Enable " "0,1" bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable " "0,1" line.long 0x04 "VIP_CLKC_RST,CLKC Module Reset Register" bitfld.long 0x04 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" bitfld.long 0x04 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" bitfld.long 0x04 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x08 "VIP_CLKC_DPS,CLKC Main Data Path Select Register" bitfld.long 0x08 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" bitfld.long 0x08 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" bitfld.long 0x08 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline bitfld.long 0x08 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x0C "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register" bitfld.long 0x0C 28.--31. "VIP1_DATAPATH_SELECT,VIP1 Datapath Register Field Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 27. "VIP1_TESTPORT_A_SELECT," "0,1" bitfld.long 0x0C 26. "VIP1_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x0C 17. "VIP1_CHR_DS_2_BYPASS,Video Input Port 1 Chroma Downsampler 2 Bypass" "0,1" bitfld.long 0x0C 16. "VIP1_CHR_DS_1_BYPASS,Video Input Port 1 Chroma Downsampler 1 Bypass" "0,1" bitfld.long 0x0C 15. "VIP1_MULTI_CHANNEL_SELECT,Video Input Port 1 Multi Channel Select" "0,1" newline bitfld.long 0x0C 12.--14. "VIP1_CHR_DS_2_SRC_SELECT,Video Input Port 1 Chroma Downsampler 2 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. "VIP1_CHR_DS_1_SRC_SELECT,Video Input Port 1 Chroma Downsampler 1 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8. "VIP1_RGB_OUT_HI_SELECT,Video Input Port 1 HI RGB Output Select" "0,1" newline bitfld.long 0x0C 7. "VIP1_RGB_OUT_LO_SELECT,Video Input Port 1 LO RGB Output Select" "0,1" bitfld.long 0x0C 6. "VIP1_RGB_SRC_SELECT,Video Input Port 1 RGB Output Path Select" "0,1" bitfld.long 0x0C 3.--5. "VIP1_SC_SRC_SELECT,Video Input Port 1 SC_M Source Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 0.--2. "VIP1_CSC_SRC_SELECT,Video Input Port 1 CSC Source Select" "0,1,2,3,4,5,6,7" line.long 0x10 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register" bitfld.long 0x10 28.--31. "VIP2_DATAPATH_SELECT,VIP2 Datapath Register Field Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 27. "VIP2_TESTPORT_A_SELECT," "0,1" bitfld.long 0x10 26. "VIP2_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x10 17. "VIP2_CHR_DS_2_BYPASS,Video Input Port 2 Chroma Downsampler 2 Bypass" "0,1" bitfld.long 0x10 16. "VIP2_CHR_DS_1_BYPASS,Video Input Port 2 Chroma Downsampler 1 Bypass" "0,1" bitfld.long 0x10 15. "VIP2_MULTI_CHANNEL_SELECT,Video Input Port 2 Multi Channel Select" "0,1" newline bitfld.long 0x10 12.--14. "VIP2_CHR_DS_2_SRC_SELECT,Video Input Port 2 Chroma Downsampler 2 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "VIP2_CHR_DS_1_SRC_SELECT,Video Input Port 2 Chroma Downsampler 1 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8. "VIP2_RGB_OUT_HI_SELECT,Video Input Port 2 HI RGB Output Select" "0,1" newline bitfld.long 0x10 7. "VIP2_RGB_OUT_LO_SELECT,Video Input Port 2 LO RGB Output Select" "0,1" bitfld.long 0x10 6. "VIP2_RGB_SRC_SELECT,Video Input Port 2 RGB Output Path Select" "0,1" bitfld.long 0x10 3.--5. "VIP2_SC_SRC_SELECT,Video Input Port 2 SC_M Source Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "VIP2_CSC_SRC_SELECT,Video Input Port 2 CSC Source Select" "0,1,2,3,4,5,6,7" tree.end tree "VIP2_top_level" base ad:0x48990000 rgroup.long 0x00++0x03 line.long 0x00 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used" bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,ajor Release Number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3" bitfld.long 0x00 0.--5. "MINOR,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "VIP_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "0,1,2,3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" group.long 0x20++0x3F line.long 0x00 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0" bitfld.long 0x00 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x00 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "0,1" newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "0,1" newline bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "0,1" line.long 0x04 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1" bitfld.long 0x04 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" newline bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "0,1" bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "0,1" bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "0,1" bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "0,1" bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "0,1" line.long 0x08 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x08 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x08 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "0,1" line.long 0x0C "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x0C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" newline bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "0,1" line.long 0x10 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0" bitfld.long 0x10 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "0,1" line.long 0x14 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1" bitfld.long 0x14 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "0,1" line.long 0x18 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0" bitfld.long 0x18 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x1C "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1" bitfld.long 0x1C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x20 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0" bitfld.long 0x20 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x20 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x20 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "0,1" newline bitfld.long 0x20 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "0,1" newline bitfld.long 0x20 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "0,1" line.long 0x24 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1" bitfld.long 0x24 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" newline bitfld.long 0x24 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "0,1" bitfld.long 0x24 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "0,1" newline bitfld.long 0x24 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "0,1" bitfld.long 0x24 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "0,1" bitfld.long 0x24 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "0,1" newline bitfld.long 0x24 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "0,1" bitfld.long 0x24 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "0,1" line.long 0x28 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x28 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x28 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x28 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x28 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x28 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "0,1" line.long 0x2C "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x2C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" newline bitfld.long 0x2C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x2C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x2C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "0,1" line.long 0x30 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0" bitfld.long 0x30 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "0,1" line.long 0x34 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1" bitfld.long 0x34 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "0,1" line.long 0x38 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0" bitfld.long 0x38 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x3C "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1" bitfld.long 0x3C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "0,1" group.long 0xA0++0x03 line.long 0x00 "VIP_INTC_EOI,INTC EOI Register" group.long 0x100++0x13 line.long 0x00 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register" bitfld.long 0x00 17. "VIP2_DP_EN,Video Input Port 2 Data Path Clock Enable " "0,1" bitfld.long 0x00 16. "VIP1_DP_EN,Video Input Port 1 Data Path Clock Enable " "0,1" bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable " "0,1" line.long 0x04 "VIP_CLKC_RST,CLKC Module Reset Register" bitfld.long 0x04 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" bitfld.long 0x04 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" bitfld.long 0x04 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x08 "VIP_CLKC_DPS,CLKC Main Data Path Select Register" bitfld.long 0x08 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" bitfld.long 0x08 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" bitfld.long 0x08 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline bitfld.long 0x08 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x0C "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register" bitfld.long 0x0C 28.--31. "VIP1_DATAPATH_SELECT,VIP1 Datapath Register Field Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 27. "VIP1_TESTPORT_A_SELECT," "0,1" bitfld.long 0x0C 26. "VIP1_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x0C 17. "VIP1_CHR_DS_2_BYPASS,Video Input Port 1 Chroma Downsampler 2 Bypass" "0,1" bitfld.long 0x0C 16. "VIP1_CHR_DS_1_BYPASS,Video Input Port 1 Chroma Downsampler 1 Bypass" "0,1" bitfld.long 0x0C 15. "VIP1_MULTI_CHANNEL_SELECT,Video Input Port 1 Multi Channel Select" "0,1" newline bitfld.long 0x0C 12.--14. "VIP1_CHR_DS_2_SRC_SELECT,Video Input Port 1 Chroma Downsampler 2 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. "VIP1_CHR_DS_1_SRC_SELECT,Video Input Port 1 Chroma Downsampler 1 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8. "VIP1_RGB_OUT_HI_SELECT,Video Input Port 1 HI RGB Output Select" "0,1" newline bitfld.long 0x0C 7. "VIP1_RGB_OUT_LO_SELECT,Video Input Port 1 LO RGB Output Select" "0,1" bitfld.long 0x0C 6. "VIP1_RGB_SRC_SELECT,Video Input Port 1 RGB Output Path Select" "0,1" bitfld.long 0x0C 3.--5. "VIP1_SC_SRC_SELECT,Video Input Port 1 SC_M Source Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 0.--2. "VIP1_CSC_SRC_SELECT,Video Input Port 1 CSC Source Select" "0,1,2,3,4,5,6,7" line.long 0x10 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register" bitfld.long 0x10 28.--31. "VIP2_DATAPATH_SELECT,VIP2 Datapath Register Field Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 27. "VIP2_TESTPORT_A_SELECT," "0,1" bitfld.long 0x10 26. "VIP2_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x10 17. "VIP2_CHR_DS_2_BYPASS,Video Input Port 2 Chroma Downsampler 2 Bypass" "0,1" bitfld.long 0x10 16. "VIP2_CHR_DS_1_BYPASS,Video Input Port 2 Chroma Downsampler 1 Bypass" "0,1" bitfld.long 0x10 15. "VIP2_MULTI_CHANNEL_SELECT,Video Input Port 2 Multi Channel Select" "0,1" newline bitfld.long 0x10 12.--14. "VIP2_CHR_DS_2_SRC_SELECT,Video Input Port 2 Chroma Downsampler 2 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "VIP2_CHR_DS_1_SRC_SELECT,Video Input Port 2 Chroma Downsampler 1 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8. "VIP2_RGB_OUT_HI_SELECT,Video Input Port 2 HI RGB Output Select" "0,1" newline bitfld.long 0x10 7. "VIP2_RGB_OUT_LO_SELECT,Video Input Port 2 LO RGB Output Select" "0,1" bitfld.long 0x10 6. "VIP2_RGB_SRC_SELECT,Video Input Port 2 RGB Output Path Select" "0,1" bitfld.long 0x10 3.--5. "VIP2_SC_SRC_SELECT,Video Input Port 2 SC_M Source Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "VIP2_CSC_SRC_SELECT,Video Input Port 2 CSC Source Select" "0,1,2,3,4,5,6,7" tree.end tree "VIP3_top_level" base ad:0x489B0000 rgroup.long 0x00++0x03 line.long 0x00 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used" bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,ajor Release Number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3" bitfld.long 0x00 0.--5. "MINOR,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "VIP_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE,Configuration of the local initiator state management mode" "0,1,2,3" bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "0,1,2,3" group.long 0x20++0x3F line.long 0x00 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0" bitfld.long 0x00 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x00 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "0,1" newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "0,1" newline bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "0,1" line.long 0x04 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1" bitfld.long 0x04 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" newline bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "0,1" bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "0,1" bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "0,1" bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "0,1" bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "0,1" line.long 0x08 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x08 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x08 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "0,1" line.long 0x0C "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x0C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" newline bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "0,1" line.long 0x10 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0" bitfld.long 0x10 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "0,1" line.long 0x14 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1" bitfld.long 0x14 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "0,1" line.long 0x18 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0" bitfld.long 0x18 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x1C "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1" bitfld.long 0x1C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x20 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0" bitfld.long 0x20 21. "VIP2_PARSER_INT_RAW,VIP2 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x20 20. "VIP1_PARSER_INT_RAW,VIP1 Parser Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x20 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "0,1" newline bitfld.long 0x20 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x20 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x20 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "0,1" newline bitfld.long 0x20 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "0,1" line.long 0x24 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1" bitfld.long 0x24 25. "VIP2_CHR_DS_2_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 24. "VIP2_CHR_DS_1_UV_ERR_INT_RAW,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 23. "VIP1_CHR_DS_2_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status" "0,1" newline bitfld.long 0x24 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x24 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "0,1" bitfld.long 0x24 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "0,1" newline bitfld.long 0x24 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "0,1" bitfld.long 0x24 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "0,1" bitfld.long 0x24 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "0,1" newline bitfld.long 0x24 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "0,1" bitfld.long 0x24 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "0,1" line.long 0x28 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0" bitfld.long 0x28 21. "VIP2_PARSER_INT_ENA,VIP2 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x28 20. "VIP1_PARSER_INT_ENA,VIP1 Parser Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x28 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x28 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x28 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x28 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x28 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "0,1" line.long 0x2C "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1" bitfld.long 0x2C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" newline bitfld.long 0x2C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x2C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x2C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x2C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x2C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "0,1" line.long 0x30 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0" bitfld.long 0x30 21. "VIP2_PARSER_INT_ENA_SET,VIP2 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 20. "VIP1_PARSER_INT_ENA_SET,VIP1 Parser Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x30 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x30 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "0,1" line.long 0x34 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1" bitfld.long 0x34 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_SET,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x34 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x34 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "0,1" line.long 0x38 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0" bitfld.long 0x38 21. "VIP2_PARSER_INT_ENA_CLR,VIP2 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 20. "VIP1_PARSER_INT_ENA_CLR,VIP1 Parser Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x38 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x38 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x3C "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1" bitfld.long 0x3C 25. "VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 24. "VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 23. "VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 6. "VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x3C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x3C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "0,1" group.long 0xA0++0x03 line.long 0x00 "VIP_INTC_EOI,INTC EOI Register" group.long 0x100++0x13 line.long 0x00 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register" bitfld.long 0x00 17. "VIP2_DP_EN,Video Input Port 2 Data Path Clock Enable " "0,1" bitfld.long 0x00 16. "VIP1_DP_EN,Video Input Port 1 Data Path Clock Enable " "0,1" bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable " "0,1" line.long 0x04 "VIP_CLKC_RST,CLKC Module Reset Register" bitfld.long 0x04 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" bitfld.long 0x04 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" bitfld.long 0x04 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x08 "VIP_CLKC_DPS,CLKC Main Data Path Select Register" bitfld.long 0x08 31. "MAIN_RST,Reset for all modules in DSS Main Data Path" "0,1" bitfld.long 0x08 17. "VIP2_DP_RST,Video Input Port 2 Data Path Reset" "0,1" bitfld.long 0x08 16. "VIP1_DP_RST,Video Input Port 1 Data Path Reset" "0,1" newline bitfld.long 0x08 0. "VPDMA_RST,VPDMA Reset" "0,1" line.long 0x0C "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register" bitfld.long 0x0C 28.--31. "VIP1_DATAPATH_SELECT,VIP1 Datapath Register Field Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 27. "VIP1_TESTPORT_A_SELECT," "0,1" bitfld.long 0x0C 26. "VIP1_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x0C 17. "VIP1_CHR_DS_2_BYPASS,Video Input Port 1 Chroma Downsampler 2 Bypass" "0,1" bitfld.long 0x0C 16. "VIP1_CHR_DS_1_BYPASS,Video Input Port 1 Chroma Downsampler 1 Bypass" "0,1" bitfld.long 0x0C 15. "VIP1_MULTI_CHANNEL_SELECT,Video Input Port 1 Multi Channel Select" "0,1" newline bitfld.long 0x0C 12.--14. "VIP1_CHR_DS_2_SRC_SELECT,Video Input Port 1 Chroma Downsampler 2 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 9.--11. "VIP1_CHR_DS_1_SRC_SELECT,Video Input Port 1 Chroma Downsampler 1 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 8. "VIP1_RGB_OUT_HI_SELECT,Video Input Port 1 HI RGB Output Select" "0,1" newline bitfld.long 0x0C 7. "VIP1_RGB_OUT_LO_SELECT,Video Input Port 1 LO RGB Output Select" "0,1" bitfld.long 0x0C 6. "VIP1_RGB_SRC_SELECT,Video Input Port 1 RGB Output Path Select" "0,1" bitfld.long 0x0C 3.--5. "VIP1_SC_SRC_SELECT,Video Input Port 1 SC_M Source Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 0.--2. "VIP1_CSC_SRC_SELECT,Video Input Port 1 CSC Source Select" "0,1,2,3,4,5,6,7" line.long 0x10 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register" bitfld.long 0x10 28.--31. "VIP2_DATAPATH_SELECT,VIP2 Datapath Register Field Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 27. "VIP2_TESTPORT_A_SELECT," "0,1" bitfld.long 0x10 26. "VIP2_TESTPORT_B_SELECT," "0,1" newline bitfld.long 0x10 17. "VIP2_CHR_DS_2_BYPASS,Video Input Port 2 Chroma Downsampler 2 Bypass" "0,1" bitfld.long 0x10 16. "VIP2_CHR_DS_1_BYPASS,Video Input Port 2 Chroma Downsampler 1 Bypass" "0,1" bitfld.long 0x10 15. "VIP2_MULTI_CHANNEL_SELECT,Video Input Port 2 Multi Channel Select" "0,1" newline bitfld.long 0x10 12.--14. "VIP2_CHR_DS_2_SRC_SELECT,Video Input Port 2 Chroma Downsampler 2 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x10 9.--11. "VIP2_CHR_DS_1_SRC_SELECT,Video Input Port 2 Chroma Downsampler 1 Source Select" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8. "VIP2_RGB_OUT_HI_SELECT,Video Input Port 2 HI RGB Output Select" "0,1" newline bitfld.long 0x10 7. "VIP2_RGB_OUT_LO_SELECT,Video Input Port 2 LO RGB Output Select" "0,1" bitfld.long 0x10 6. "VIP2_RGB_SRC_SELECT,Video Input Port 2 RGB Output Path Select" "0,1" bitfld.long 0x10 3.--5. "VIP2_SC_SRC_SELECT,Video Input Port 2 SC_M Source Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "VIP2_CSC_SRC_SELECT,Video Input Port 2 CSC Source Select" "0,1,2,3,4,5,6,7" tree.end tree "VIP1_VPDMA" base ad:0x4897D000 rgroup.long 0x00++0x0F line.long 0x00 "VIP_PID,PID VIP VPDMA register" line.long 0x04 "VIP_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VIP_LIST_ATTR,The attributes of a new list" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located atVIP_LIST_ADDR" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register" "0,1" newline bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" newline rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" newline bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" newline bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x30++0xAF line.long 0x00 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients" bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x10 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x10 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x10 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x10 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x10 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x10 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x10 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x10 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x10 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x10 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x10 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x10 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x10 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x10 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x10 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x10 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x10 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x10 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x10 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x10 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x10 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x10 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x10 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x10 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x10 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x10 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x10 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x10 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x10 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x10 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x10 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x14 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x18 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x18 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x18 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x18 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x18 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x18 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x18 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x18 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x18 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x18 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x18 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x18 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x18 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x18 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x18 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x18 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x18 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x18 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x18 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x18 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x18 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x18 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x18 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x18 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x18 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x18 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x18 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x18 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x18 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x18 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x18 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x1C "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x20 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x20 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x20 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x20 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x20 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x20 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x20 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x20 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x20 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x20 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x20 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x20 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x20 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x20 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x20 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x20 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x20 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x20 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x20 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x24 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x28 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x28 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x28 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x28 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x28 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x28 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x28 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x28 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x28 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x28 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x28 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x28 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x28 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x28 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x28 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x28 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x2C "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x2C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x30 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x30 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x30 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x30 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x30 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x30 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x30 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x30 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x30 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x30 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x30 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x30 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x30 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x30 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x30 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x30 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x30 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x30 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x30 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x30 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x34 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x34 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x38 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x38 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x38 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x38 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x38 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x38 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x38 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x38 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x38 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x38 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x38 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x38 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x38 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x38 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x38 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x38 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x38 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x38 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x38 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x38 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x38 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x38 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x38 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x38 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x3C "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x3C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x40 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x40 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x40 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x40 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x40 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x40 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x40 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x40 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x40 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x40 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x40 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x40 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x40 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x40 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x40 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x40 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x40 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x40 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x40 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x40 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x40 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x40 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x40 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x40 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x40 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x40 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x40 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x40 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x40 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x40 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x40 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x40 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x40 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x44 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x44 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x48 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x48 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x48 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x48 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x48 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x48 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x48 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x48 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x48 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x48 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x48 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x48 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x48 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x48 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x48 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x48 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x48 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x48 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x48 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x48 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x48 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x48 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x48 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x48 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x48 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x48 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x48 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x48 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x48 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x48 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x48 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x48 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x48 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x4C "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x4C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x50 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x50 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x50 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x50 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x50 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x50 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x50 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x50 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x50 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x50 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x50 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x50 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x50 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x50 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x50 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x50 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x50 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x50 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x50 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x50 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x54 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x54 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x58 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x58 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x58 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x58 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x58 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x58 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x58 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x58 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x58 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x58 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x58 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x58 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x58 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x58 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x58 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x58 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x58 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x58 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x58 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x58 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x5C "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x5C 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x60 "VIP_INT2_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x60 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x60 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x60 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x60 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x60 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x60 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x60 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x60 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x60 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x60 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x60 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x60 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x60 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x60 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x60 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x60 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x60 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x60 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x60 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x60 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x60 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x60 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x60 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x60 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x60 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x60 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x60 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x60 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x60 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x60 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x60 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x60 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x64 "VIP_INT2_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x64 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x68 "VIP_INT2_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x68 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x68 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x68 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x68 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x68 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x68 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x68 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x68 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x68 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x68 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x68 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x68 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x68 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x68 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x68 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x68 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x68 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x68 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x68 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x68 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x68 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x68 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x68 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x68 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x68 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x68 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x68 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x68 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x68 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x68 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x68 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x68 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x6C "VIP_INT2_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x6C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x70 "VIP_INT2_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x70 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x70 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x70 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x70 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x70 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x70 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x70 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x70 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x70 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x70 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x70 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x70 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x70 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x70 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x70 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x70 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x70 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x70 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x70 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x70 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x70 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x70 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x70 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x70 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x70 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x70 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x70 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x70 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x70 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x70 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x70 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x70 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x74 "VIP_INT2_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x74 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x78 "VIP_INT2_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x78 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x78 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x78 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x78 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x78 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x78 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x78 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x78 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x78 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x78 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x78 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x78 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x78 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x78 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x78 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x78 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x78 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x78 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x78 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x7C "VIP_INT2_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x7C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x80 "VIP_INT2_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x80 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x80 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x80 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x80 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x80 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x80 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x80 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x80 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x80 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x80 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x80 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x80 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x80 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x80 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x80 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x80 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x80 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x80 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x80 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x84 "VIP_INT2_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x84 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x88 "VIP_INT3_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x88 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x88 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x88 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x88 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x88 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x88 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x88 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x88 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x88 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x88 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x88 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x88 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x88 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x88 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x88 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x88 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x88 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x88 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x88 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x88 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x88 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x88 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x88 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x88 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x88 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x88 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x88 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x88 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x88 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x88 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x88 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x88 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x8C "VIP_INT3_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x8C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0x90 "VIP_INT3_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x90 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x90 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x90 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x90 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x90 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x90 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x90 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x90 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x90 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x90 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x90 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x90 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x90 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x90 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x90 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x90 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x90 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x90 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x90 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x90 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x90 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x90 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x90 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x90 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x90 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x90 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x90 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x90 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x90 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x90 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x90 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x90 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x94 "VIP_INT3_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x94 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0x98 "VIP_INT3_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x98 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x98 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x98 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x98 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x98 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x98 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x98 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x98 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x98 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x98 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x98 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x98 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x98 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x98 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x98 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x98 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x98 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x98 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x98 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x98 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x98 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x98 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x98 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x98 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x98 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x98 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x98 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x98 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x98 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x98 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x98 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x98 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x9C "VIP_INT3_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x9C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0xA0 "VIP_INT3_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0xA0 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0xA0 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0xA0 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0xA0 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0xA0 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0xA0 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0xA0 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0xA0 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0xA0 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0xA0 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0xA0 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0xA0 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0xA0 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0xA0 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0xA0 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0xA0 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0xA0 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0xA0 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0xA0 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0xA4 "VIP_INT3_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0xA4 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0xA8 "VIP_INT3_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0xA8 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0xA8 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0xA8 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0xA8 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0xA8 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0xA8 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0xA8 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0xA8 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0xA8 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0xA8 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0xA8 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0xA8 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0xA8 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0xA8 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0xA8 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0xA8 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0xA8 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0xA8 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0xA8 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0xAC "VIP_INT3_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0xAC 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" group.long 0x200++0x03 line.long 0x00 "VIP_PERF_MON0,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x280++0x2B line.long 0x00 "VIP_PERF_MON32,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON33,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON34,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON35,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x10 "VIP_PERF_MON36,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x10 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x10 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x10 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x10 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x14 "VIP_PERF_MON37,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x14 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x14 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x14 24.--26. "STOP_COUNT," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x14 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x18 "VIP_PERF_MON38,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x18 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x18 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x18 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x18 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x18 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x1C "VIP_PERF_MON39,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x1C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x1C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x1C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x1C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x1C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x20 "VIP_PERF_MON40,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x20 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x20 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x20 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x20 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x20 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x24 "VIP_PERF_MON41,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x24 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x24 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x24 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x24 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x24 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x28 "VIP_PERF_MON42,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x28 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x28 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x28 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x28 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x28 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x2C8++0x0F line.long 0x00 "VIP_PERF_MON50,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON51,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON52,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON53,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x2E0++0x17 line.long 0x00 "VIP_PERF_MON56,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT," "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT," "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON57,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON58,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON59,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x10 "VIP_PERF_MON60,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x10 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x10 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x10 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x10 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x14 "VIP_PERF_MON61,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x14 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x14 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x14 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x14 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x388++0x1F line.long 0x00 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x18 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x18 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x18 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x18 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x18 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x1C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x1C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x1C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x1C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x1C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D0++0x03 line.long 0x00 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3E8++0x0F line.long 0x00 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 8. (list 44. 45. 46. 47. 48. 49. 54. 55. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x28 0x2C ) group.long ($2+0x2B0)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 43. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x68 ) group.long ($2+0x244)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x204)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end tree.end tree "VIP2_VPDMA" base ad:0x4899D000 rgroup.long 0x00++0x0F line.long 0x00 "VIP_PID,PID VIP VPDMA register" line.long 0x04 "VIP_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VIP_LIST_ATTR,The attributes of a new list" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located atVIP_LIST_ADDR" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register" "0,1" newline bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" newline rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" newline bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" newline bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x30++0xAF line.long 0x00 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients" bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x10 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x10 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x10 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x10 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x10 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x10 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x10 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x10 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x10 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x10 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x10 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x10 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x10 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x10 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x10 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x10 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x10 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x10 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x10 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x10 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x10 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x10 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x10 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x10 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x10 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x10 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x10 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x10 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x10 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x10 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x10 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x14 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x18 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x18 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x18 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x18 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x18 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x18 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x18 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x18 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x18 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x18 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x18 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x18 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x18 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x18 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x18 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x18 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x18 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x18 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x18 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x18 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x18 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x18 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x18 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x18 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x18 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x18 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x18 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x18 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x18 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x18 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x18 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x1C "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x20 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x20 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x20 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x20 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x20 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x20 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x20 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x20 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x20 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x20 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x20 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x20 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x20 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x20 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x20 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x20 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x20 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x20 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x20 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x24 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x28 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x28 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x28 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x28 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x28 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x28 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x28 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x28 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x28 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x28 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x28 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x28 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x28 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x28 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x28 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x28 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x2C "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x2C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x30 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x30 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x30 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x30 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x30 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x30 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x30 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x30 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x30 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x30 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x30 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x30 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x30 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x30 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x30 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x30 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x30 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x30 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x30 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x30 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x34 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x34 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x38 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x38 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x38 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x38 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x38 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x38 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x38 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x38 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x38 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x38 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x38 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x38 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x38 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x38 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x38 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x38 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x38 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x38 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x38 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x38 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x38 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x38 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x38 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x38 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x3C "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x3C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x40 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x40 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x40 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x40 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x40 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x40 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x40 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x40 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x40 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x40 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x40 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x40 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x40 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x40 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x40 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x40 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x40 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x40 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x40 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x40 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x40 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x40 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x40 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x40 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x40 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x40 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x40 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x40 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x40 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x40 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x40 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x40 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x40 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x44 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x44 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x48 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x48 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x48 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x48 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x48 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x48 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x48 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x48 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x48 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x48 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x48 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x48 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x48 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x48 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x48 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x48 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x48 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x48 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x48 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x48 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x48 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x48 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x48 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x48 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x48 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x48 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x48 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x48 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x48 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x48 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x48 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x48 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x48 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x4C "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x4C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x50 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x50 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x50 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x50 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x50 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x50 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x50 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x50 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x50 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x50 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x50 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x50 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x50 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x50 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x50 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x50 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x50 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x50 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x50 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x50 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x54 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x54 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x58 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x58 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x58 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x58 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x58 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x58 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x58 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x58 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x58 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x58 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x58 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x58 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x58 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x58 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x58 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x58 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x58 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x58 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x58 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x58 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x5C "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x5C 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x60 "VIP_INT2_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x60 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x60 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x60 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x60 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x60 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x60 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x60 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x60 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x60 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x60 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x60 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x60 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x60 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x60 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x60 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x60 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x60 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x60 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x60 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x60 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x60 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x60 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x60 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x60 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x60 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x60 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x60 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x60 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x60 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x60 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x60 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x60 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x64 "VIP_INT2_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x64 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x68 "VIP_INT2_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x68 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x68 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x68 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x68 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x68 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x68 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x68 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x68 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x68 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x68 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x68 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x68 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x68 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x68 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x68 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x68 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x68 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x68 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x68 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x68 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x68 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x68 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x68 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x68 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x68 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x68 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x68 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x68 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x68 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x68 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x68 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x68 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x6C "VIP_INT2_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x6C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x70 "VIP_INT2_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x70 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x70 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x70 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x70 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x70 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x70 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x70 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x70 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x70 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x70 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x70 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x70 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x70 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x70 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x70 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x70 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x70 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x70 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x70 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x70 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x70 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x70 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x70 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x70 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x70 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x70 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x70 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x70 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x70 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x70 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x70 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x70 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x74 "VIP_INT2_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x74 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x78 "VIP_INT2_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x78 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x78 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x78 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x78 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x78 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x78 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x78 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x78 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x78 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x78 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x78 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x78 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x78 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x78 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x78 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x78 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x78 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x78 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x78 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x7C "VIP_INT2_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x7C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x80 "VIP_INT2_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x80 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x80 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x80 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x80 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x80 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x80 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x80 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x80 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x80 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x80 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x80 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x80 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x80 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x80 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x80 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x80 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x80 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x80 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x80 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x84 "VIP_INT2_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x84 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x88 "VIP_INT3_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x88 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x88 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x88 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x88 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x88 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x88 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x88 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x88 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x88 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x88 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x88 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x88 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x88 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x88 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x88 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x88 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x88 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x88 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x88 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x88 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x88 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x88 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x88 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x88 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x88 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x88 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x88 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x88 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x88 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x88 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x88 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x88 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x8C "VIP_INT3_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x8C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0x90 "VIP_INT3_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x90 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x90 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x90 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x90 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x90 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x90 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x90 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x90 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x90 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x90 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x90 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x90 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x90 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x90 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x90 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x90 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x90 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x90 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x90 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x90 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x90 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x90 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x90 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x90 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x90 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x90 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x90 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x90 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x90 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x90 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x90 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x90 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x94 "VIP_INT3_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x94 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0x98 "VIP_INT3_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x98 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x98 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x98 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x98 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x98 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x98 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x98 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x98 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x98 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x98 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x98 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x98 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x98 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x98 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x98 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x98 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x98 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x98 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x98 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x98 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x98 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x98 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x98 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x98 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x98 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x98 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x98 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x98 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x98 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x98 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x98 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x98 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x9C "VIP_INT3_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x9C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0xA0 "VIP_INT3_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0xA0 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0xA0 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0xA0 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0xA0 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0xA0 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0xA0 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0xA0 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0xA0 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0xA0 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0xA0 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0xA0 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0xA0 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0xA0 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0xA0 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0xA0 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0xA0 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0xA0 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0xA0 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0xA0 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0xA4 "VIP_INT3_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0xA4 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0xA8 "VIP_INT3_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0xA8 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0xA8 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0xA8 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0xA8 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0xA8 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0xA8 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0xA8 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0xA8 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0xA8 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0xA8 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0xA8 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0xA8 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0xA8 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0xA8 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0xA8 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0xA8 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0xA8 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0xA8 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0xA8 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0xAC "VIP_INT3_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0xAC 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" group.long 0x200++0x03 line.long 0x00 "VIP_PERF_MON0,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x280++0x2B line.long 0x00 "VIP_PERF_MON32,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON33,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON34,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON35,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x10 "VIP_PERF_MON36,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x10 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x10 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x10 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x10 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x14 "VIP_PERF_MON37,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x14 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x14 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x14 24.--26. "STOP_COUNT," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x14 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x18 "VIP_PERF_MON38,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x18 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x18 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x18 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x18 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x18 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x1C "VIP_PERF_MON39,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x1C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x1C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x1C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x1C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x1C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x20 "VIP_PERF_MON40,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x20 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x20 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x20 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x20 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x20 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x24 "VIP_PERF_MON41,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x24 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x24 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x24 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x24 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x24 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x28 "VIP_PERF_MON42,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x28 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x28 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x28 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x28 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x28 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x2C8++0x0F line.long 0x00 "VIP_PERF_MON50,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON51,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON52,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON53,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x2E0++0x17 line.long 0x00 "VIP_PERF_MON56,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT," "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT," "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON57,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON58,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON59,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x10 "VIP_PERF_MON60,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x10 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x10 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x10 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x10 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x14 "VIP_PERF_MON61,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x14 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x14 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x14 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x14 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x388++0x1F line.long 0x00 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x18 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x18 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x18 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x18 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x18 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x1C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x1C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x1C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x1C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x1C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D0++0x03 line.long 0x00 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3E8++0x0F line.long 0x00 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 8. (list 44. 45. 46. 47. 48. 49. 54. 55. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x28 0x2C ) group.long ($2+0x2B0)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 43. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x68 ) group.long ($2+0x244)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x204)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end tree.end tree "VIP3_VPDMA" base ad:0x489BD000 rgroup.long 0x00++0x0F line.long 0x00 "VIP_PID,PID VIP VPDMA register" line.long 0x04 "VIP_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VIP_LIST_ATTR,The attributes of a new list" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located atVIP_LIST_ADDR" "0,1,2,3,4,5,6,7" bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register" "0,1" newline bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" newline rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" newline bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" newline bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x30++0xAF line.long 0x00 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients" bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x10 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x10 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x10 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x10 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x10 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x10 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x10 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x10 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x10 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x10 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x10 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x10 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x10 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x10 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x10 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x10 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x10 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x10 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x10 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x10 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x10 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x10 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x10 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x10 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x10 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x10 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x10 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x10 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x10 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x10 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x10 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x14 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x14 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x18 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x18 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x18 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x18 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x18 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x18 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x18 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x18 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x18 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x18 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x18 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x18 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x18 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x18 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x18 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x18 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x18 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x18 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x18 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x18 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x18 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x18 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x18 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x18 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x18 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x18 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x18 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x18 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x18 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x18 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x18 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x1C "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x1C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x20 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x20 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x20 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x20 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x20 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x20 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x20 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x20 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x20 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x20 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x20 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x20 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x20 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x20 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x20 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x20 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x20 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x20 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x20 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x20 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x20 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x20 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x20 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x20 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x20 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x20 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x20 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x20 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x20 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x20 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x20 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x20 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x24 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x24 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x28 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x28 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x28 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x28 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x28 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x28 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x28 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x28 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x28 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x28 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x28 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x28 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x28 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x28 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x28 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x28 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x28 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x28 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x28 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x2C "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x2C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x2C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x2C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x30 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x30 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x30 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x30 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x30 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x30 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x30 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x30 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x30 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x30 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x30 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x30 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x30 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x30 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x30 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x30 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x30 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x30 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x30 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x30 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x30 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x30 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x30 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x34 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x34 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x34 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" bitfld.long 0x34 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x38 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x38 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x38 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x38 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x38 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x38 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x38 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x38 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x38 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x38 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x38 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x38 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x38 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x38 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x38 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x38 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x38 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x38 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x38 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x38 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x38 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x38 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x38 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x38 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x38 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x38 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x38 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x38 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x38 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x38 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x38 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x38 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x38 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x3C "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x3C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x3C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x40 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x40 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x40 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x40 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x40 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x40 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x40 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x40 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x40 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x40 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x40 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x40 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x40 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x40 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x40 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x40 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x40 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x40 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x40 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x40 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x40 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x40 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x40 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x40 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x40 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x40 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x40 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x40 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x40 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x40 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x40 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x40 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x40 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x44 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x44 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x44 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x44 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x48 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x48 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x48 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x48 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x48 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x48 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x48 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x48 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x48 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x48 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x48 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x48 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x48 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x48 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x48 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x48 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x48 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x48 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x48 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x48 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x48 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x48 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x48 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x48 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x48 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x48 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x48 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x48 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x48 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x48 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x48 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x48 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x48 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x4C "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x4C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x4C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x4C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x50 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x50 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x50 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x50 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x50 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x50 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x50 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x50 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x50 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x50 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x50 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x50 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x50 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x50 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x50 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x50 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x50 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x50 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x50 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x50 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x54 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x54 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x54 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x54 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x58 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x58 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x58 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x58 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x58 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x58 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x58 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x58 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x58 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x58 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x58 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x58 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x58 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x58 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x58 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x58 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x58 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x58 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x58 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x58 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x58 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x58 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x58 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x5C "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x5C 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x5C 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" bitfld.long 0x5C 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x60 "VIP_INT2_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x60 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x60 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x60 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x60 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x60 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x60 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x60 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x60 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x60 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x60 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x60 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x60 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x60 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x60 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x60 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x60 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x60 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x60 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x60 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x60 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x60 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x60 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x60 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x60 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x60 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x60 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x60 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x60 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x60 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x60 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x60 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x60 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x64 "VIP_INT2_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x64 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x64 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x64 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x68 "VIP_INT2_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x68 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x68 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x68 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x68 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x68 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x68 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x68 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x68 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x68 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x68 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x68 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x68 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x68 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x68 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x68 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x68 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x68 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x68 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x68 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x68 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x68 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x68 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x68 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x68 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x68 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x68 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x68 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x68 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x68 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x68 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x68 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x68 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x6C "VIP_INT2_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x6C 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x6C 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x6C 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x70 "VIP_INT2_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x70 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x70 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x70 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x70 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x70 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x70 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x70 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x70 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x70 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x70 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x70 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x70 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x70 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x70 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x70 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x70 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x70 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x70 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x70 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x70 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x70 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x70 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x70 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x70 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x70 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x70 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x70 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x70 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x70 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x70 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x70 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x70 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x74 "VIP_INT2_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x74 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x74 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x74 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x78 "VIP_INT2_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x78 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0x78 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0x78 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0x78 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0x78 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0x78 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0x78 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0x78 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0x78 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0x78 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0x78 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0x78 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0x78 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0x78 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0x78 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0x78 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0x78 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0x78 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0x78 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0x7C "VIP_INT2_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x7C 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x7C 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x7C 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x80 "VIP_INT2_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x80 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0x80 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0x80 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x80 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0x80 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0x80 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x80 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0x80 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0x80 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x80 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0x80 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0x80 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x80 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0x80 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0x80 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x80 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0x80 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x80 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x80 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0x80 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x80 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0x80 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x84 "VIP_INT2_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x84 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x84 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" bitfld.long 0x84 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x88 "VIP_INT3_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x88 31. "INT_STAT_VIP1_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip1_mult_ancb_src9" "0,1" bitfld.long 0x88 30. "INT_STAT_VIP1_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip1_mult_ancb_src8" "0,1" bitfld.long 0x88 29. "INT_STAT_VIP1_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip1_mult_ancb_src7" "0,1" newline bitfld.long 0x88 28. "INT_STAT_VIP1_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip1_mult_ancb_src6" "0,1" bitfld.long 0x88 27. "INT_STAT_VIP1_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip1_mult_ancb_src5" "0,1" bitfld.long 0x88 26. "INT_STAT_VIP1_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip1_mult_ancb_src4" "0,1" newline bitfld.long 0x88 25. "INT_STAT_VIP1_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip1_mult_ancb_src3" "0,1" bitfld.long 0x88 24. "INT_STAT_VIP1_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip1_mult_ancb_src2" "0,1" bitfld.long 0x88 23. "INT_STAT_VIP1_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip1_mult_ancb_src1" "0,1" newline bitfld.long 0x88 22. "INT_STAT_VIP1_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip1_mult_ancb_src0" "0,1" bitfld.long 0x88 21. "INT_STAT_VIP1_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip1_mult_anca_src15" "0,1" bitfld.long 0x88 20. "INT_STAT_VIP1_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip1_mult_anca_src14" "0,1" newline bitfld.long 0x88 19. "INT_STAT_VIP1_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip1_mult_anca_src13" "0,1" bitfld.long 0x88 18. "INT_STAT_VIP1_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip1_mult_anca_src12" "0,1" bitfld.long 0x88 17. "INT_STAT_VIP1_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip1_mult_anca_src11" "0,1" newline bitfld.long 0x88 16. "INT_STAT_VIP1_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip1_mult_anca_src10" "0,1" bitfld.long 0x88 15. "INT_STAT_VIP1_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip1_mult_anca_src9" "0,1" bitfld.long 0x88 14. "INT_STAT_VIP1_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip1_mult_anca_src8" "0,1" newline bitfld.long 0x88 13. "INT_STAT_VIP1_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip1_mult_anca_src7" "0,1" bitfld.long 0x88 12. "INT_STAT_VIP1_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip1_mult_anca_src6" "0,1" bitfld.long 0x88 11. "INT_STAT_VIP1_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip1_mult_anca_src5" "0,1" newline bitfld.long 0x88 10. "INT_STAT_VIP1_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip1_mult_anca_src4" "0,1" bitfld.long 0x88 9. "INT_STAT_VIP1_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip1_mult_anca_src3" "0,1" bitfld.long 0x88 8. "INT_STAT_VIP1_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip1_mult_anca_src2" "0,1" newline bitfld.long 0x88 7. "INT_STAT_VIP1_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip1_mult_anca_src1" "0,1" bitfld.long 0x88 6. "INT_STAT_VIP1_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip1_mult_anca_src0" "0,1" bitfld.long 0x88 5. "INT_STAT_VIP1_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip1_mult_portb_src15" "0,1" newline bitfld.long 0x88 4. "INT_STAT_VIP1_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip1_mult_portb_src14" "0,1" bitfld.long 0x88 3. "INT_STAT_VIP1_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip1_mult_portb_src13" "0,1" bitfld.long 0x88 2. "INT_STAT_VIP1_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip1_mult_portb_src12" "0,1" newline bitfld.long 0x88 1. "INT_STAT_VIP1_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip1_mult_portb_src11" "0,1" bitfld.long 0x88 0. "INT_STAT_VIP1_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip1_mult_portb_src10" "0,1" line.long 0x8C "VIP_INT3_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x8C 31. "INT_MASK_VIP1_MULT_ANCB_SRC9,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 30. "INT_MASK_VIP1_MULT_ANCB_SRC8,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 29. "INT_MASK_VIP1_MULT_ANCB_SRC7,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 28. "INT_MASK_VIP1_MULT_ANCB_SRC6,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 27. "INT_MASK_VIP1_MULT_ANCB_SRC5,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 26. "INT_MASK_VIP1_MULT_ANCB_SRC4,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 25. "INT_MASK_VIP1_MULT_ANCB_SRC3,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 24. "INT_MASK_VIP1_MULT_ANCB_SRC2,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 23. "INT_MASK_VIP1_MULT_ANCB_SRC1,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 22. "INT_MASK_VIP1_MULT_ANCB_SRC0,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 21. "INT_MASK_VIP1_MULT_ANCA_SRC15,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 20. "INT_MASK_VIP1_MULT_ANCA_SRC14,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 19. "INT_MASK_VIP1_MULT_ANCA_SRC13,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 18. "INT_MASK_VIP1_MULT_ANCA_SRC12,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 17. "INT_MASK_VIP1_MULT_ANCA_SRC11,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 16. "INT_MASK_VIP1_MULT_ANCA_SRC10,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 15. "INT_MASK_VIP1_MULT_ANCA_SRC9,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 14. "INT_MASK_VIP1_MULT_ANCA_SRC8,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 13. "INT_MASK_VIP1_MULT_ANCA_SRC7,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 12. "INT_MASK_VIP1_MULT_ANCA_SRC6,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 11. "INT_MASK_VIP1_MULT_ANCA_SRC5,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 10. "INT_MASK_VIP1_MULT_ANCA_SRC4,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 9. "INT_MASK_VIP1_MULT_ANCA_SRC3,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 8. "INT_MASK_VIP1_MULT_ANCA_SRC2,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 7. "INT_MASK_VIP1_MULT_ANCA_SRC1,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 6. "INT_MASK_VIP1_MULT_ANCA_SRC0,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 5. "INT_MASK_VIP1_MULT_PORTB_SRC15,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 4. "INT_MASK_VIP1_MULT_PORTB_SRC14,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 3. "INT_MASK_VIP1_MULT_PORTB_SRC13,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 2. "INT_MASK_VIP1_MULT_PORTB_SRC12,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x8C 1. "INT_MASK_VIP1_MULT_PORTB_SRC11,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x8C 0. "INT_MASK_VIP1_MULT_PORTB_SRC10,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0x90 "VIP_INT3_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x90 31. "INT_STAT_VIP2_MULT_PORTB_SRC3,The last write DMA transaction has completed for channel vip2_mult_portb_src3" "0,1" bitfld.long 0x90 30. "INT_STAT_VIP2_MULT_PORTB_SRC2,The last write DMA transaction has completed for channel vip2_mult_portb_src2" "0,1" bitfld.long 0x90 29. "INT_STAT_VIP2_MULT_PORTB_SRC1,The last write DMA transaction has completed for channel vip2_mult_portb_src1" "0,1" newline bitfld.long 0x90 28. "INT_STAT_VIP2_MULT_PORTB_SRC0,The last write DMA transaction has completed for channel vip2_mult_portb_src0" "0,1" bitfld.long 0x90 27. "INT_STAT_VIP2_MULT_PORTA_SRC15,The last write DMA transaction has completed for channel vip2_mult_porta_src15" "0,1" bitfld.long 0x90 26. "INT_STAT_VIP2_MULT_PORTA_SRC14,The last write DMA transaction has completed for channel vip2_mult_porta_src14" "0,1" newline bitfld.long 0x90 25. "INT_STAT_VIP2_MULT_PORTA_SRC13,The last write DMA transaction has completed for channel vip2_mult_porta_src13" "0,1" bitfld.long 0x90 24. "INT_STAT_VIP2_MULT_PORTA_SRC12,The last write DMA transaction has completed for channel vip2_mult_porta_src12" "0,1" bitfld.long 0x90 23. "INT_STAT_VIP2_MULT_PORTA_SRC11,The last write DMA transaction has completed for channel vip2_mult_porta_src11" "0,1" newline bitfld.long 0x90 22. "INT_STAT_VIP2_MULT_PORTA_SRC10,The last write DMA transaction has completed for channel vip2_mult_porta_src10" "0,1" bitfld.long 0x90 21. "INT_STAT_VIP2_MULT_PORTA_SRC9,The last write DMA transaction has completed for channel vip2_mult_porta_src9" "0,1" bitfld.long 0x90 20. "INT_STAT_VIP2_MULT_PORTA_SRC8,The last write DMA transaction has completed for channel vip2_mult_porta_src8" "0,1" newline bitfld.long 0x90 19. "INT_STAT_VIP2_MULT_PORTA_SRC7,The last write DMA transaction has completed for channel vip2_mult_porta_src7" "0,1" bitfld.long 0x90 18. "INT_STAT_VIP2_MULT_PORTA_SRC6,The last write DMA transaction has completed for channel vip2_mult_porta_src6" "0,1" bitfld.long 0x90 17. "INT_STAT_VIP2_MULT_PORTA_SRC5,The last write DMA transaction has completed for channel vip2_mult_porta_src5" "0,1" newline bitfld.long 0x90 16. "INT_STAT_VIP2_MULT_PORTA_SRC4,The last write DMA transaction has completed for channel vip2_mult_porta_src4" "0,1" bitfld.long 0x90 15. "INT_STAT_VIP2_MULT_PORTA_SRC3,The last write DMA transaction has completed for channel vip2_mult_porta_src3" "0,1" bitfld.long 0x90 14. "INT_STAT_VIP2_MULT_PORTA_SRC2,The last write DMA transaction has completed for channel vip2_mult_porta_src2" "0,1" newline bitfld.long 0x90 13. "INT_STAT_VIP2_MULT_PORTA_SRC1,The last write DMA transaction has completed for channel vip2_mult_porta_src1" "0,1" bitfld.long 0x90 12. "INT_STAT_VIP2_MULT_PORTA_SRC0,The last write DMA transaction has completed for channel vip2_mult_porta_src0" "0,1" bitfld.long 0x90 11. "INT_STAT_VIP1_PORTB_RGB,The last write DMA transaction has completed for channel vip1_portb_rgb" "0,1" newline bitfld.long 0x90 10. "INT_STAT_VIP1_PORTA_RGB,The last write DMA transaction has completed for channel vip1_porta_rgb" "0,1" bitfld.long 0x90 9. "INT_STAT_VIP1_PORTB_CHROMA,The last write DMA transaction has completed for channel vip1_portb_chroma" "0,1" bitfld.long 0x90 8. "INT_STAT_VIP1_PORTB_LUMA,The last write DMA transaction has completed for channel vip1_portb_luma" "0,1" newline bitfld.long 0x90 7. "INT_STAT_VIP1_PORTA_CHROMA,The last write DMA transaction has completed for channel vip1_porta_chroma" "0,1" bitfld.long 0x90 6. "INT_STAT_VIP1_PORTA_LUMA,The last write DMA transaction has completed for channel vip1_porta_luma" "0,1" bitfld.long 0x90 5. "INT_STAT_VIP1_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip1_mult_ancb_src15" "0,1" newline bitfld.long 0x90 4. "INT_STAT_VIP1_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip1_mult_ancb_src14" "0,1" bitfld.long 0x90 3. "INT_STAT_VIP1_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip1_mult_ancb_src13" "0,1" bitfld.long 0x90 2. "INT_STAT_VIP1_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip1_mult_ancb_src12" "0,1" newline bitfld.long 0x90 1. "INT_STAT_VIP1_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip1_mult_ancb_src11" "0,1" bitfld.long 0x90 0. "INT_STAT_VIP1_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip1_mult_ancb_src10" "0,1" line.long 0x94 "VIP_INT3_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x94 31. "INT_MASK_VIP2_MULT_PORTB_SRC3,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 30. "INT_MASK_VIP2_MULT_PORTB_SRC2,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 29. "INT_MASK_VIP2_MULT_PORTB_SRC1,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 28. "INT_MASK_VIP2_MULT_PORTB_SRC0,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 27. "INT_MASK_VIP2_MULT_PORTA_SRC15,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 26. "INT_MASK_VIP2_MULT_PORTA_SRC14,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 25. "INT_MASK_VIP2_MULT_PORTA_SRC13,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 24. "INT_MASK_VIP2_MULT_PORTA_SRC12,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 23. "INT_MASK_VIP2_MULT_PORTA_SRC11,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 22. "INT_MASK_VIP2_MULT_PORTA_SRC10,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 21. "INT_MASK_VIP2_MULT_PORTA_SRC9,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 20. "INT_MASK_VIP2_MULT_PORTA_SRC8,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 19. "INT_MASK_VIP2_MULT_PORTA_SRC7,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 18. "INT_MASK_VIP2_MULT_PORTA_SRC6,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 17. "INT_MASK_VIP2_MULT_PORTA_SRC5,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 16. "INT_MASK_VIP2_MULT_PORTA_SRC4,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 15. "INT_MASK_VIP2_MULT_PORTA_SRC3,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 14. "INT_MASK_VIP2_MULT_PORTA_SRC2,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 13. "INT_MASK_VIP2_MULT_PORTA_SRC1,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 12. "INT_MASK_VIP2_MULT_PORTA_SRC0,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 11. "INT_MASK_VIP1_PORTB_RGB,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 10. "INT_MASK_VIP1_PORTA_RGB,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 9. "INT_MASK_VIP1_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 8. "INT_MASK_VIP1_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 7. "INT_MASK_VIP1_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 6. "INT_MASK_VIP1_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 5. "INT_MASK_VIP1_MULT_ANCB_SRC15,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 4. "INT_MASK_VIP1_MULT_ANCB_SRC14,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 3. "INT_MASK_VIP1_MULT_ANCB_SRC13,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 2. "INT_MASK_VIP1_MULT_ANCB_SRC12,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x94 1. "INT_MASK_VIP1_MULT_ANCB_SRC11,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x94 0. "INT_MASK_VIP1_MULT_ANCB_SRC10,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0x98 "VIP_INT3_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x98 31. "INT_STAT_VIP2_MULT_ANCB_SRC3,The last write DMA transaction has completed for channel vip2_mult_ancb_src3" "0,1" bitfld.long 0x98 30. "INT_STAT_VIP2_MULT_ANCB_SRC2,The last write DMA transaction has completed for channel vip2_mult_ancb_src2" "0,1" bitfld.long 0x98 29. "INT_STAT_VIP2_MULT_ANCB_SRC1,The last write DMA transaction has completed for channel vip2_mult_ancb_src1" "0,1" newline bitfld.long 0x98 28. "INT_STAT_VIP2_MULT_ANCB_SRC0,The last write DMA transaction has completed for channel vip2_mult_ancb_src0" "0,1" bitfld.long 0x98 27. "INT_STAT_VIP2_MULT_ANCA_SRC15,The last write DMA transaction has completed for channel vip2_mult_anca_src15" "0,1" bitfld.long 0x98 26. "INT_STAT_VIP2_MULT_ANCA_SRC14,The last write DMA transaction has completed for channel vip2_mult_anca_src14" "0,1" newline bitfld.long 0x98 25. "INT_STAT_VIP2_MULT_ANCA_SRC13,The last write DMA transaction has completed for channel vip2_mult_anca_src13" "0,1" bitfld.long 0x98 24. "INT_STAT_VIP2_MULT_ANCA_SRC12,The last write DMA transaction has completed for channel vip2_mult_anca_src12" "0,1" bitfld.long 0x98 23. "INT_STAT_VIP2_MULT_ANCA_SRC11,The last write DMA transaction has completed for channel vip2_mult_anca_src11" "0,1" newline bitfld.long 0x98 22. "INT_STAT_VIP2_MULT_ANCA_SRC10,The last write DMA transaction has completed for channel vip2_mult_anca_src10" "0,1" bitfld.long 0x98 21. "INT_STAT_VIP2_MULT_ANCA_SRC9,The last write DMA transaction has completed for channel vip2_mult_anca_src9" "0,1" bitfld.long 0x98 20. "INT_STAT_VIP2_MULT_ANCA_SRC8,The last write DMA transaction has completed for channel vip2_mult_anca_src8" "0,1" newline bitfld.long 0x98 19. "INT_STAT_VIP2_MULT_ANCA_SRC7,The last write DMA transaction has completed for channel vip2_mult_anca_src7" "0,1" bitfld.long 0x98 18. "INT_STAT_VIP2_MULT_ANCA_SRC6,The last write DMA transaction has completed for channel vip2_mult_anca_src6" "0,1" bitfld.long 0x98 17. "INT_STAT_VIP2_MULT_ANCA_SRC5,The last write DMA transaction has completed for channel vip2_mult_anca_src5" "0,1" newline bitfld.long 0x98 16. "INT_STAT_VIP2_MULT_ANCA_SRC4,The last write DMA transaction has completed for channel vip2_mult_anca_src4" "0,1" bitfld.long 0x98 15. "INT_STAT_VIP2_MULT_ANCA_SRC3,The last write DMA transaction has completed for channel vip2_mult_anca_src3" "0,1" bitfld.long 0x98 14. "INT_STAT_VIP2_MULT_ANCA_SRC2,The last write DMA transaction has completed for channel vip2_mult_anca_src2" "0,1" newline bitfld.long 0x98 13. "INT_STAT_VIP2_MULT_ANCA_SRC1,The last write DMA transaction has completed for channel vip2_mult_anca_src1" "0,1" bitfld.long 0x98 12. "INT_STAT_VIP2_MULT_ANCA_SRC0,The last write DMA transaction has completed for channel vip2_mult_anca_src0" "0,1" bitfld.long 0x98 11. "INT_STAT_VIP2_MULT_PORTB_SRC15,The last write DMA transaction has completed for channel vip2_mult_portb_src15" "0,1" newline bitfld.long 0x98 10. "INT_STAT_VIP2_MULT_PORTB_SRC14,The last write DMA transaction has completed for channel vip2_mult_portb_src14" "0,1" bitfld.long 0x98 9. "INT_STAT_VIP2_MULT_PORTB_SRC13,The last write DMA transaction has completed for channel vip2_mult_portb_src13" "0,1" bitfld.long 0x98 8. "INT_STAT_VIP2_MULT_PORTB_SRC12,The last write DMA transaction has completed for channel vip2_mult_portb_src12" "0,1" newline bitfld.long 0x98 7. "INT_STAT_VIP2_MULT_PORTB_SRC11,The last write DMA transaction has completed for channel vip2_mult_portb_src11" "0,1" bitfld.long 0x98 6. "INT_STAT_VIP2_MULT_PORTB_SRC10,The last write DMA transaction has completed for channel vip2_mult_portb_src10" "0,1" bitfld.long 0x98 5. "INT_STAT_VIP2_MULT_PORTB_SRC9,The last write DMA transaction has completed for channel vip2_mult_portb_src9" "0,1" newline bitfld.long 0x98 4. "INT_STAT_VIP2_MULT_PORTB_SRC8,The last write DMA transaction has completed for channel vip2_mult_portb_src8" "0,1" bitfld.long 0x98 3. "INT_STAT_VIP2_MULT_PORTB_SRC7,The last write DMA transaction has completed for channel vip2_mult_portb_src7" "0,1" bitfld.long 0x98 2. "INT_STAT_VIP2_MULT_PORTB_SRC6,The last write DMA transaction has completed for channel vip2_mult_portb_src6" "0,1" newline bitfld.long 0x98 1. "INT_STAT_VIP2_MULT_PORTB_SRC5,The last write DMA transaction has completed for channel vip2_mult_portb_src5" "0,1" bitfld.long 0x98 0. "INT_STAT_VIP2_MULT_PORTB_SRC4,The last write DMA transaction has completed for channel vip2_mult_portb_src4" "0,1" line.long 0x9C "VIP_INT3_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x9C 31. "INT_MASK_VIP2_MULT_ANCB_SRC3,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 30. "INT_MASK_VIP2_MULT_ANCB_SRC2,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 29. "INT_MASK_VIP2_MULT_ANCB_SRC1,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 28. "INT_MASK_VIP2_MULT_ANCB_SRC0,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 27. "INT_MASK_VIP2_MULT_ANCA_SRC15,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 26. "INT_MASK_VIP2_MULT_ANCA_SRC14,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 25. "INT_MASK_VIP2_MULT_ANCA_SRC13,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 24. "INT_MASK_VIP2_MULT_ANCA_SRC12,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 23. "INT_MASK_VIP2_MULT_ANCA_SRC11,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 22. "INT_MASK_VIP2_MULT_ANCA_SRC10,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 21. "INT_MASK_VIP2_MULT_ANCA_SRC9,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 20. "INT_MASK_VIP2_MULT_ANCA_SRC8,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 19. "INT_MASK_VIP2_MULT_ANCA_SRC7,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 18. "INT_MASK_VIP2_MULT_ANCA_SRC6,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 17. "INT_MASK_VIP2_MULT_ANCA_SRC5,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 16. "INT_MASK_VIP2_MULT_ANCA_SRC4,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 15. "INT_MASK_VIP2_MULT_ANCA_SRC3,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 14. "INT_MASK_VIP2_MULT_ANCA_SRC2,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 13. "INT_MASK_VIP2_MULT_ANCA_SRC1,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 12. "INT_MASK_VIP2_MULT_ANCA_SRC0,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 11. "INT_MASK_VIP2_MULT_PORTB_SRC15,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 10. "INT_MASK_VIP2_MULT_PORTB_SRC14,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 9. "INT_MASK_VIP2_MULT_PORTB_SRC13,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 8. "INT_MASK_VIP2_MULT_PORTB_SRC12,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 7. "INT_MASK_VIP2_MULT_PORTB_SRC11,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 6. "INT_MASK_VIP2_MULT_PORTB_SRC10,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 5. "INT_MASK_VIP2_MULT_PORTB_SRC9,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 4. "INT_MASK_VIP2_MULT_PORTB_SRC8,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 3. "INT_MASK_VIP2_MULT_PORTB_SRC7,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 2. "INT_MASK_VIP2_MULT_PORTB_SRC6,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x9C 1. "INT_MASK_VIP2_MULT_PORTB_SRC5,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0x9C 0. "INT_MASK_VIP2_MULT_PORTB_SRC4,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0xA0 "VIP_INT3_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0xA0 18. "INT_STAT_OTHER,This event will cause a one to be set in this register until cleared by software" "0,1" bitfld.long 0xA0 17. "INT_STAT_VIP2_PORTB_RGB,The last write DMA transaction has completed for channel vip2_portb_rgb" "0,1" bitfld.long 0xA0 16. "INT_STAT_VIP2_PORTA_RGB,The last write DMA transaction has completed for channel vip2_porta_rgb" "0,1" newline bitfld.long 0xA0 15. "INT_STAT_VIP2_PORTB_CHROMA,The last write DMA transaction has completed for channel vip2_portb_chroma" "0,1" bitfld.long 0xA0 14. "INT_STAT_VIP2_PORTB_LUMA,The last write DMA transaction has completed for channel vip2_portb_luma" "0,1" bitfld.long 0xA0 13. "INT_STAT_VIP2_PORTA_CHROMA,The last write DMA transaction has completed for channel vip2_porta_chroma" "0,1" newline bitfld.long 0xA0 12. "INT_STAT_VIP2_PORTA_LUMA,The last write DMA transaction has completed for channel vip2_porta_luma" "0,1" bitfld.long 0xA0 11. "INT_STAT_VIP2_MULT_ANCB_SRC15,The last write DMA transaction has completed for channel vip2_mult_ancb_src15" "0,1" bitfld.long 0xA0 10. "INT_STAT_VIP2_MULT_ANCB_SRC14,The last write DMA transaction has completed for channel vip2_mult_ancb_src14" "0,1" newline bitfld.long 0xA0 9. "INT_STAT_VIP2_MULT_ANCB_SRC13,The last write DMA transaction has completed for channel vip2_mult_ancb_src13" "0,1" bitfld.long 0xA0 8. "INT_STAT_VIP2_MULT_ANCB_SRC12,The last write DMA transaction has completed for channel vip2_mult_ancb_src12" "0,1" bitfld.long 0xA0 7. "INT_STAT_VIP2_MULT_ANCB_SRC11,The last write DMA transaction has completed for channel vip2_mult_ancb_src11" "0,1" newline bitfld.long 0xA0 6. "INT_STAT_VIP2_MULT_ANCB_SRC10,The last write DMA transaction has completed for channel vip2_mult_ancb_src10" "0,1" bitfld.long 0xA0 5. "INT_STAT_VIP2_MULT_ANCB_SRC9,The last write DMA transaction has completed for channel vip2_mult_ancb_src9" "0,1" bitfld.long 0xA0 4. "INT_STAT_VIP2_MULT_ANCB_SRC8,The last write DMA transaction has completed for channel vip2_mult_ancb_src8" "0,1" newline bitfld.long 0xA0 3. "INT_STAT_VIP2_MULT_ANCB_SRC7,The last write DMA transaction has completed for channel vip2_mult_ancb_src7" "0,1" bitfld.long 0xA0 2. "INT_STAT_VIP2_MULT_ANCB_SRC6,The last write DMA transaction has completed for channel vip2_mult_ancb_src6" "0,1" bitfld.long 0xA0 1. "INT_STAT_VIP2_MULT_ANCB_SRC5,The last write DMA transaction has completed for channel vip2_mult_ancb_src5" "0,1" newline bitfld.long 0xA0 0. "INT_STAT_VIP2_MULT_ANCB_SRC4,The last write DMA transaction has completed for channel vip2_mult_ancb_src4" "0,1" line.long 0xA4 "VIP_INT3_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0xA4 18. "INT_MASK_OTHER,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 17. "INT_MASK_VIP2_PORTB_RGB,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 16. "INT_MASK_VIP2_PORTA_RGB,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 15. "INT_MASK_VIP2_PORTB_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 14. "INT_MASK_VIP2_PORTB_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 13. "INT_MASK_VIP2_PORTA_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 12. "INT_MASK_VIP2_PORTA_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 11. "INT_MASK_VIP2_MULT_ANCB_SRC15,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 10. "INT_MASK_VIP2_MULT_ANCB_SRC14,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 9. "INT_MASK_VIP2_MULT_ANCB_SRC13,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 8. "INT_MASK_VIP2_MULT_ANCB_SRC12,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 7. "INT_MASK_VIP2_MULT_ANCB_SRC11,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 6. "INT_MASK_VIP2_MULT_ANCB_SRC10,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 5. "INT_MASK_VIP2_MULT_ANCB_SRC9,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 4. "INT_MASK_VIP2_MULT_ANCB_SRC8,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 3. "INT_MASK_VIP2_MULT_ANCB_SRC7,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 2. "INT_MASK_VIP2_MULT_ANCB_SRC6,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xA4 1. "INT_MASK_VIP2_MULT_ANCB_SRC5,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xA4 0. "INT_MASK_VIP2_MULT_ANCB_SRC4,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0xA8 "VIP_INT3_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0xA8 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" bitfld.long 0xA8 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" bitfld.long 0xA8 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0xA8 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" bitfld.long 0xA8 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" bitfld.long 0xA8 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0xA8 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" bitfld.long 0xA8 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" bitfld.long 0xA8 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0xA8 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" bitfld.long 0xA8 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" bitfld.long 0xA8 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0xA8 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" bitfld.long 0xA8 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" bitfld.long 0xA8 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0xA8 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" bitfld.long 0xA8 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0xA8 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0xA8 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" bitfld.long 0xA8 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0xA8 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" bitfld.long 0xA8 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0xAC "VIP_INT3_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0xAC 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0xAC 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" bitfld.long 0xAC 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" group.long 0x200++0x03 line.long 0x00 "VIP_PERF_MON0,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x280++0x2B line.long 0x00 "VIP_PERF_MON32,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON33,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON34,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON35,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x10 "VIP_PERF_MON36,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x10 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x10 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x10 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x10 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x14 "VIP_PERF_MON37,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x14 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x14 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x14 24.--26. "STOP_COUNT," "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x14 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x18 "VIP_PERF_MON38,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x18 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x18 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x18 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x18 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x18 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x1C "VIP_PERF_MON39,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x1C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x1C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x1C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x1C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x1C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x20 "VIP_PERF_MON40,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x20 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x20 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x20 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x20 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x20 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x24 "VIP_PERF_MON41,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x24 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x24 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x24 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x24 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x24 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x28 "VIP_PERF_MON42,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x28 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x28 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x28 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x28 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x28 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x2C8++0x0F line.long 0x00 "VIP_PERF_MON50,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON51,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON52,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON53,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x2E0++0x17 line.long 0x00 "VIP_PERF_MON56,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT," "0,1,2,3" bitfld.long 0x00 24.--26. "STOP_COUNT," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--21. "START_CLIENT," "0,1,2,3" bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x04 "VIP_PERF_MON57,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x04 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x04 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x04 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x04 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x04 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x04 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x08 "VIP_PERF_MON58,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x08 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x08 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x08 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x08 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x08 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x0C "VIP_PERF_MON59,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x0C 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x0C 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0C 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x0C 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x10 "VIP_PERF_MON60,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x10 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x10 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x10 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x10 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" line.long 0x14 "VIP_PERF_MON61,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x14 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x14 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" bitfld.long 0x14 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" bitfld.long 0x14 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" group.long 0x388++0x1F line.long 0x00 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x18 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x18 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x18 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x18 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x18 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x1C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x1C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x1C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x1C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x1C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D0++0x03 line.long 0x00 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3E8++0x0F line.long 0x00 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0C "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" repeat 8. (list 44. 45. 46. 47. 48. 49. 54. 55. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x28 0x2C ) group.long ($2+0x2B0)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 43. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x68 ) group.long ($2+0x244)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x204)++0x03 line.long 0x00 "VIP_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA\\n" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "0,1,2,3" bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end tree.end tree.end tree.open "VPE" repeat 3. (list 0. 1. 2. )(list ad:0x489D0300 ad:0x489D0400 ad:0x489D0500 ) tree "VPE_CHR_US_INST_$1" base $2 rgroup.long 0x00++0x23 line.long 0x00 "VPE_PID," line.long 0x04 "VPE_REG0," hexmask.long.word 0x04 18.--31. 1. "ANCHOR_FID0_C0,C0 coefficient for Anchor Pixel" bitfld.long 0x04 16.--17. "CFG_MODE," "?,CFG_MODE_1,?,?" hexmask.long.word 0x04 2.--15. 1. "ANCHOR_FID0_C1,C1 coefficient for Anchor Pixel" line.long 0x08 "VPE_REG1," hexmask.long.word 0x08 18.--31. 1. "ANCHOR_FID0_C2,C2 coefficient for Anchor Pixel" hexmask.long.word 0x08 2.--15. 1. "ANCHOR_FID0_C3,C3 coefficient for Anchor Pixel" line.long 0x0C "VPE_REG2," hexmask.long.word 0x0C 18.--31. 1. "INTERP_FID0_C0,C0 coefficient for Interpolated Pixel" hexmask.long.word 0x0C 2.--15. 1. "INTERP_FID0_C1,C1 coefficient for Interpolated Pixel" line.long 0x10 "VPE_REG3," hexmask.long.word 0x10 18.--31. 1. "INTERP_FID0_C2,C2 coefficient for Interpolated Pixel" hexmask.long.word 0x10 2.--15. 1. "INTERP_FID0_C3,C3 coefficient for Interpolated Pixel" line.long 0x14 "VPE_REG4," hexmask.long.word 0x14 18.--31. 1. "ANCHOR_FID1_C0,C0 coefficient for Anchor Pixel" hexmask.long.word 0x14 2.--15. 1. "ANCHOR_FID1_C1,C1 coefficient for Anchor Pixel" line.long 0x18 "VPE_REG5," hexmask.long.word 0x18 18.--31. 1. "ANCHOR_FID1_C2,C2 coefficient for Anchor Pixel" hexmask.long.word 0x18 2.--15. 1. "ANCHOR_FID1_C3,C3 coefficient for Anchor Pixel" line.long 0x1C "VPE_REG6," hexmask.long.word 0x1C 18.--31. 1. "INTERP_FID1_C0,C0 coefficient for Interpolated Pixel" hexmask.long.word 0x1C 2.--15. 1. "INTERP_FID1_C1,C1 coefficient for Interpolated Pixel" line.long 0x20 "VPE_REG7," hexmask.long.word 0x20 18.--31. 1. "INTERP_FID1_C2,C2 coefficient for Interpolated Pixel" hexmask.long.word 0x20 2.--15. 1. "INTERP_FID1_C3,C3 coefficient for Interpolated Pixel" tree.end repeat.end tree "VPE_CSC" base ad:0x489D5700 group.long 0x00++0x17 line.long 0x00 "VPE_CSC00," hexmask.long.word 0x00 16.--28. 1. "B0,Coefficients of color space converter" hexmask.long.word 0x00 0.--12. 1. "A0,Its is represented as Q3.10 number" line.long 0x04 "VPE_CSC01," hexmask.long.word 0x04 16.--28. 1. "A1,Coefficients of color space converter" hexmask.long.word 0x04 0.--12. 1. "C0,Coefficients of color space converter" line.long 0x08 "VPE_CSC02," hexmask.long.word 0x08 16.--28. 1. "C1,Coefficients of color space converter" hexmask.long.word 0x08 0.--12. 1. "B1,Coefficients of color space converter" line.long 0x0C "VPE_CSC03," hexmask.long.word 0x0C 16.--28. 1. "B2,Coefficients of color space converter" hexmask.long.word 0x0C 0.--12. 1. "A2,Coefficients of color space converter" line.long 0x10 "VPE_CSC04," hexmask.long.word 0x10 16.--27. 1. "D0,Coefficients of color space converter" hexmask.long.word 0x10 0.--12. 1. "C2,Coefficients of color space converter" line.long 0x14 "VPE_CSC05," bitfld.long 0x14 28. "BYPASS,Full CSC bypass mode" "0,1" hexmask.long.word 0x14 16.--27. 1. "D2,Coefficients of color space converter" hexmask.long.word 0x14 0.--11. 1. "D1,Coefficients of color space converter" tree.end tree "VPE_DEI" base ad:0x489D0600 group.long 0x00++0x0F line.long 0x00 "VPE_DEI_REG0," bitfld.long 0x00 31. "PROGRESSIVE_BYPASS,Progressive Mode" "PROGRESSIVE_BYPASS_0,PROGRESSIVE_BYPASS_1" bitfld.long 0x00 30. "FIELD_FLUSH,Field Flush Mode" "FIELD_FLUSH_0,FIELD_FLUSH_1" bitfld.long 0x00 29. "INTERLACE_BYPASS,Interlace Bypass Mode" "INTERLACE_BYPASS_0,INTERLACE_BYPASS_1" newline hexmask.long.word 0x00 16.--26. 1. "HEIGHT,Frame Height" hexmask.long.word 0x00 0.--10. 1. "WIDTH,Frame Width" line.long 0x04 "VPE_DEI_REG1," bitfld.long 0x04 1. "MDT_SPATMAX_BYPASS,Spatial Maximum Filtering Bypass for motion values used in EDI" "MDT_SPATMAX_BYPASS_0,MDT_SPATMAX_BYPASS_1" bitfld.long 0x04 0. "MDT_TEMPMAX_BYPASS,Spatio-temporal Maximum Filtering Bypass for motion valued used in EDI" "MDT_TEMPMAX_BYPASS_0,MDT_TEMPMAX_BYPASS_1" line.long 0x08 "VPE_DEI_REG2," bitfld.long 0x08 28.--31. "MDT_MVSTMAX_COR_THR,This is used for increasing noise robustness" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. "MDT_MV_COR_THR,This threshold is for the coring for motion value mv" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 16.--23. 1. "MDT_SF_SC_THR3,Spatial frequency threshold 3" newline hexmask.long.byte 0x08 8.--15. 1. "MDT_SF_SC_THR2,Spatial frequency threshold 2" hexmask.long.byte 0x08 0.--7. 1. "MDT_SF_SC_THR1,Spatial frequency threshold It is used for adaptive scaling of motion values according to how busy the texture is" line.long 0x0C "VPE_DEI_REG3," hexmask.long.byte 0x0C 24.--31. 1. "EDI_COR_SCALE_FACTOR,Scaling factor for correlation along detected edge" hexmask.long.byte 0x0C 16.--23. 1. "EDI_DIR_COR_LOWER_THR,Lower threshold used for correlation along detected edge" hexmask.long.byte 0x0C 8.--15. 1. "EDI_CHROMA3D_COR_THR,Correlation threshold used in 3D processing for chroma" newline bitfld.long 0x0C 3. "EDI_CHROMA_3D_ENABLE,3D Chroma Enable" "EDI_CHROMA_3D_ENABLE_0,EDI_CHROMA_3D_ENABLE_1" bitfld.long 0x0C 2. "EDI_ENABLE_3D,3D Enable" "EDI_ENABLE_3D_0,EDI_ENABLE_3D_1" bitfld.long 0x0C 0.--1. "EDI_INP_MODE,Interpolation mode" "EDI_INP_MODE_0,EDI_INP_MODE_1,EDI_INP_MODE_2,EDI_INP_MODE_3" group.long 0x20++0x1B line.long 0x00 "VPE_DEI_REG8," bitfld.long 0x00 31. "FMD_WINDOW_ENABLE,Enable FMD operation window" "0,1" hexmask.long.word 0x00 16.--26. 1. "FMD_WINDOW_MAXX,Right boundary of FMD operation window Must be less than width" hexmask.long.word 0x00 0.--10. 1. "FMD_WINDOW_MINX,Left boundary of FMD operation window" line.long 0x04 "VPE_DEI_REG9," hexmask.long.word 0x04 16.--26. 1. "FMD_WINDOW_MAXY,Bottom boundary of FMD operation window Must be less than height/2" hexmask.long.word 0x04 0.--10. 1. "FMD_WINDOW_MINY,Top boundary of FMD operation window" line.long 0x08 "VPE_DEI_REG10," hexmask.long.byte 0x08 24.--31. 1. "FMD_CAF_LINE_THR,CAF threshold used for the pixels from two lines in one field This is the threshold used for combing artifacts detection" hexmask.long.byte 0x08 16.--23. 1. "FMD_CAF_FIELD_THR,CAF threshold used for the pixels from two fields This is the threshold used for combing artifacts detection" bitfld.long 0x08 3. "FMD_BED_ENABLE,Film Mode Bad Edit Detection" "FMD_BED_ENABLE_0,FMD_BED_ENABLE_1" newline bitfld.long 0x08 2. "FMD_JAM_DIR,Film Mode Field Jamming Direction" "FMD_JAM_DIR_0,FMD_JAM_DIR_1" bitfld.long 0x08 1. "FMD_LOCK,Film Mode Field Jamming Direction" "FMD_LOCK_0,FMD_LOCK_1" bitfld.long 0x08 0. "FMD_ENABLE,Enable film mode processing" "FMD_ENABLE_0,FMD_ENABLE_1" line.long 0x0C "VPE_DEI_REG11," hexmask.long.tbyte 0x0C 0.--19. 1. "FMD_CAF_THR,CAF threshold used for leaving film mode: If the combing artifacts is greater than this threshold CAF is detected and thus the state machine will be forced to leave the film mode" line.long 0x10 "VPE_DEI_REG12," bitfld.long 0x10 24. "FMD_RESET,When '1' the film mode detection module needs to be reset by the software" "0,1" hexmask.long.tbyte 0x10 0.--20. 1. "FMD_CAF,Detected combing artifacts" line.long 0x14 "VPE_DEI_REG13," hexmask.long 0x14 0.--27. 1. "FMD_FIELD_DIFF,Field difference (difference between two neighboring fields one top and one bottom)" line.long 0x18 "VPE_DEI_REG14," hexmask.long.tbyte 0x18 0.--19. 1. "FMD_FRAME_DIFF,Frame difference (difference between two top or two bottom fields)" repeat 4. (list 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x10)++0x03 line.long 0x00 "VPE_DEI_REG$1," bitfld.long 0x00 24.--28. "EDI_LUT3,EDI Lookup Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. "EDI_LUT2,EDI Lookup Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--12. "EDI_LUT1,EDI Lookup Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. "EDI_LUT0,EDI Lookup Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" repeat.end tree.end tree "VPE_SC" base ad:0x489D0700 group.long 0x00++0x1B line.long 0x00 "VPE_CFG_SC0," bitfld.long 0x00 16. "CFG_FID_SELFGEN,FID self generate enable" "0,1" bitfld.long 0x00 15. "CFG_TRIM,Trimming enable" "CFG_TRIM_0,CFG_TRIM_1" bitfld.long 0x00 14. "CFG_Y_PK_EN,This parameter is used by peaking block" "0,1" newline bitfld.long 0x00 11. "CFG_ENABLE_SIN2_VER_INTP,This parameter is used by both horizontal and vertical scaling" "CFG_ENABLE_SIN2_VER_INTP_0,CFG_ENABLE_SIN2_VER_INTP_1" bitfld.long 0x00 10. "CFG_INTERLACE_I,This parameter is used by horizontal scaling" "CFG_INTERLACE_I_0,CFG_INTERLACE_I_1" bitfld.long 0x00 9. "CFG_HP_BYPASS,This parameter is used by horizontal scaling" "0,1" newline bitfld.long 0x00 8. "CFG_DCM_4X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 7. "CFG_DCM_2X,This parameter is used by horizontal scaling" "0,1" bitfld.long 0x00 6. "CFG_AUTO_HS,This parameter is used by horizontal scaling" "CFG_AUTO_HS_0,CFG_AUTO_HS_1" newline bitfld.long 0x00 5. "CFG_ENABLE_EV,This parameter is used by vertical scaling" "CFG_ENABLE_EV_0,CFG_ENABLE_EV_1" bitfld.long 0x00 4. "CFG_USE_RAV,This parameter is used by vertical scaling" "CFG_USE_RAV_0,CFG_USE_RAV_1" bitfld.long 0x00 3. "CFG_INVT_FID,This parameter is a general purpose" "CFG_INVT_FID_0,CFG_INVT_FID_1" newline bitfld.long 0x00 2. "CFG_SC_BYPASS,This parameter is used by horizontal scaling" "CFG_SC_BYPASS_0,CFG_SC_BYPASS_1" bitfld.long 0x00 1. "CFG_LINEAR,This parameter is used by vertical scaling" "CFG_LINEAR_0,CFG_LINEAR_1" bitfld.long 0x00 0. "CFG_INTERLACE_O,This parameter is used by vertical scaling" "CFG_INTERLACE_O_0,CFG_INTERLACE_O_1" line.long 0x04 "VPE_CFG_SC1," hexmask.long 0x04 0.--26. 1. "CFG_ROW_ACC_INC,This parameter is used by vertical scaling" line.long 0x08 "VPE_CFG_SC2," hexmask.long 0x08 0.--27. 1. "CFG_ROW_ACC_OFFSET,This parameter is used by vertical scaling" line.long 0x0C "VPE_CFG_SC3," hexmask.long 0x0C 0.--27. 1. "CFG_ROW_ACC_OFFSET_B,This parameter is used by vertical scaling" line.long 0x10 "VPE_CFG_SC4," bitfld.long 0x10 28.--30. "CFG_NLIN_ACC_INIT_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" bitfld.long 0x10 24.--26. "CFG_LIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 12.--22. 1. "CFG_TAR_W,This parameter is a general purpose" newline hexmask.long.word 0x10 0.--10. 1. "CFG_TAR_H,This parameter is a general purpose" line.long 0x14 "VPE_CFG_SC5," bitfld.long 0x14 24.--26. "CFG_NLIN_ACC_INC_U,This parameter is used by horizontal scaling" "0,1,2,3,4,5,6,7" hexmask.long.word 0x14 12.--22. 1. "CFG_SRC_W,This parameter is a general purpose" hexmask.long.word 0x14 0.--10. 1. "CFG_SRC_H,This parameter is a general purpose" line.long 0x18 "VPE_CFG_SC6," hexmask.long.word 0x18 10.--19. 1. "CFG_ROW_ACC_INIT_RAV_B,This parameter is used by vertical scaling" hexmask.long.word 0x18 0.--9. 1. "CFG_ROW_ACC_INIT_RAV,This parameter is used by vertical scaling" group.long 0x20++0x17 line.long 0x00 "VPE_CFG_SC8," hexmask.long.word 0x00 12.--22. 1. "CFG_NLIN_RIGHT,This parameter is used by horizontal scaling" hexmask.long.word 0x00 0.--10. 1. "CFG_NLIN_LEFT,This parameter is used by horizontal scaling" line.long 0x04 "VPE_CFG_SC9," line.long 0x08 "VPE_CFG_SC10," line.long 0x0C "VPE_CFG_SC11," line.long 0x10 "VPE_CFG_SC12," hexmask.long 0x10 0.--24. 1. "CFG_COL_ACC_OFFSET,This parameter is used in horizontal scaling" line.long 0x14 "VPE_CFG_SC13," hexmask.long.word 0x14 0.--9. 1. "CFG_SC_FACTOR_RAV,This parameter is used by vertical scaling" group.long 0x48++0x13 line.long 0x00 "VPE_CFG_SC18," hexmask.long.word 0x00 0.--9. 1. "CFG_HS_FACTOR,This parameter is used by horizontal scaling" line.long 0x04 "VPE_CFG_SC19," hexmask.long.byte 0x04 24.--31. 1. "CFG_HPF_COEF3,This parameter is used by the peaking block" hexmask.long.byte 0x04 16.--23. 1. "CFG_HPF_COEF2,This parameter is used by the peaking block" hexmask.long.byte 0x04 8.--15. 1. "CFG_HPF_COEF1,This parameter is used by the peaking block" newline hexmask.long.byte 0x04 0.--7. 1. "CFG_HPF_COEF0,This parameter is used by the peaking block" line.long 0x08 "VPE_CFG_SC20," hexmask.long.word 0x08 20.--28. 1. "CFG_NL_LIMIT,This parameter is used by the peaking block" bitfld.long 0x08 16.--18. "CFG_HPF_NORM_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x08 8.--15. 1. "CFG_HPF_COEF5,This parameter is used by the peaking block" newline hexmask.long.byte 0x08 0.--7. 1. "CFG_HPF_COEF4,This parameter is used by the peaking block" line.long 0x0C "VPE_CFG_SC21," hexmask.long.byte 0x0C 16.--23. 1. "CFG_NL_LO_SLOPE,This parameter is used by the peaking block" hexmask.long.word 0x0C 0.--8. 1. "CFG_NL_LO_THR,This parameter is used by the peaking block" line.long 0x10 "VPE_CFG_SC22," bitfld.long 0x10 16.--18. "CFG_NL_HI_SLOPE_SHIFT,This parameter is used by the peaking block" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 0.--8. 1. "CFG_NL_HI_THR,This parameter is used by the peaking block" group.long 0x60++0x07 line.long 0x00 "VPE_CFG_SC24," hexmask.long.word 0x00 16.--26. 1. "CFG_ORG_W,This parameter is used by the trimmer" hexmask.long.word 0x00 0.--10. 1. "CFG_ORG_H,This parameter is used by the trimmer" line.long 0x04 "VPE_CFG_SC25," hexmask.long.word 0x04 16.--26. 1. "CFG_OFF_W,This parameter is used by the trimmer" hexmask.long.word 0x04 0.--10. 1. "CFG_OFF_H,This parameter is used by the trimmer" tree.end tree "VPE_TOP_LEVEL" base ad:0x489D0000 rgroup.long 0x00++0x03 line.long 0x00 "VPE_CLKC_PID," group.long 0x10++0x03 line.long 0x00 "VPE_SYSCONFIG," bitfld.long 0x00 4.--5. "STANDBYMODE,Standymode setting for PWRSTNDBY IPGeneric" "0,1,2,3" bitfld.long 0x00 2.--3. "IDLEMODE,Idlemode setting for PWRIDLE IPGenerc" "0,1,2,3" group.long 0x20++0x1F line.long 0x00 "VPE_INTC_INTR0_STATUS_RAW0," bitfld.long 0x00 18. "DEI_FMD_INT_RAW,DEI Film Mode Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x00 16. "VPDMA_INT0_DESCRIPTOR_RAW,VPDMA INT0 Descriptor Status Read indicates raw status" "0,1" newline bitfld.long 0x00 15. "VPDMA_INT0_LIST7_NOTIFY_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 14. "VPDMA_INT0_LIST7_COMPLETE_RAW,VPDMA INT0 List7 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 13. "VPDMA_INT0_LIST6_NOTIFY_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 12. "VPDMA_INT0_LIST6_COMPLETE_RAW,VPDMA INT0 List6 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 11. "VPDMA_INT0_LIST5_NOTIFY_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 10. "VPDMA_INT0_LIST5_COMPLETE_RAW,VPDMA INT0 List5 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 9. "VPDMA_INT0_LIST4_NOTIFY_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 8. "VPDMA_INT0_LIST4_COMPLETE_RAW,VPDMA INT0 List4 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 7. "VPDMA_INT0_LIST3_NOTIFY_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 6. "VPDMA_INT0_LIST3_COMPLETE_RAW,VPDMA INT0 List3 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 5. "VPDMA_INT0_LIST2_NOTIFY_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 4. "VPDMA_INT0_LIST2_COMPLETE_RAW,VPDMA INT0 List2 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 3. "VPDMA_INT0_LIST1_NOTIFY_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" bitfld.long 0x00 2. "VPDMA_INT0_LIST1_COMPLETE_RAW,VPDMA INT0 List1 Complete Status Read indicates raw status" "0,1" newline bitfld.long 0x00 1. "VPDMA_INT0_LIST0_NOTIFY_RAW,VPDMA INT0 List0 Notify Status Read indicates raw status" "0,1" bitfld.long 0x00 0. "VPDMA_INT0_LIST0_COMPLETE_RAW,VPDMA INT0 List0 Complete Status Read indicates raw status" "0,1" line.long 0x04 "VPE_INTC_INTR0_STATUS_RAW1," bitfld.long 0x04 22. "VIP1_CHR_DS_1_UV_ERR_INT_RAW,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status" "0,1" bitfld.long 0x04 16. "DEI_ERROR_INT_RAW,DEI Error Interrupt Status Read indicates raw status" "0,1" newline bitfld.long 0x04 7. "VPDMA_INT0_CLIENT_RAW,VPDMA INT0 Client Status Read indicates raw status" "0,1" bitfld.long 0x04 5. "VPDMA_INT0_CHANNEL_GROUP5_RAW,VPDMA INT0 Channel Group5 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 4. "VPDMA_INT0_CHANNEL_GROUP4_RAW,VPDMA INT0 Channel Group4 Status Read indicates raw status" "0,1" bitfld.long 0x04 3. "VPDMA_INT0_CHANNEL_GROUP3_RAW,VPDMA INT0 Channel Group3 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 2. "VPDMA_INT0_CHANNEL_GROUP2_RAW,VPDMA INT0 Channel Group2 Status Read indicates raw status" "0,1" bitfld.long 0x04 1. "VPDMA_INT0_CHANNEL_GROUP1_RAW,VPDMA INT0 Channel Group1 Status Read indicates raw status" "0,1" newline bitfld.long 0x04 0. "VPDMA_INT0_CHANNEL_GROUP0_RAW,VPDMA INT0 Channel Group0 Status Read indicates raw status" "0,1" line.long 0x08 "VPE_INTC_INTR0_STATUS_ENA0," bitfld.long 0x08 18. "DEI_FMD_INT_ENA,DEI Film Mode Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 16. "VPDMA_INT0_DESCRIPTOR_ENA,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 15. "VPDMA_INT0_LIST7_NOTIFY_ENA,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 14. "VPDMA_INT0_LIST7_COMPLETE_ENA,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 13. "VPDMA_INT0_LIST6_NOTIFY_ENA,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 12. "VPDMA_INT0_LIST6_COMPLETE_ENA,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 11. "VPDMA_INT0_LIST5_NOTIFY_ENA,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 10. "VPDMA_INT0_LIST5_COMPLETE_ENA,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 9. "VPDMA_INT0_LIST4_NOTIFY_ENA,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x08 8. "VPDMA_INT0_LIST4_COMPLETE_ENA,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 7. "VPDMA_INT0_LIST3_NOTIFY_ENA,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 6. "VPDMA_INT0_LIST3_COMPLETE_ENA,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 5. "VPDMA_INT0_LIST2_NOTIFY_ENA,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable" "0,1" bitfld.long 0x08 4. "VPDMA_INT0_LIST2_COMPLETE_ENA,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 3. "VPDMA_INT0_LIST1_NOTIFY_ENA,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 2. "VPDMA_INT0_LIST1_COMPLETE_ENA,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable" "0,1" newline bitfld.long 0x08 1. "VPDMA_INT0_LIST0_NOTIFY_ENA,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable" "0,1" bitfld.long 0x08 0. "VPDMA_INT0_LIST0_COMPLETE_ENA,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable" "0,1" line.long 0x0C "VPE_INTC_INTR0_STATUS_ENA1," bitfld.long 0x0C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status" "0,1" bitfld.long 0x0C 16. "DEI_ERROR_INT_ENA,DEI Error Enabled Interrupt Status Read indicates enabled status" "0,1" newline bitfld.long 0x0C 7. "VPDMA_INT0_CLIENT_ENA,VPDMA INT0 Client Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status" "0,1" bitfld.long 0x0C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status" "0,1" newline bitfld.long 0x0C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status" "0,1" line.long 0x10 "VPE_INTC_INTR0_ENA_SET0," bitfld.long 0x10 18. "DEI_FMD_INT_ENA_SET,DEI Film Mode Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 16. "VPDMA_INT0_DESCRIPTOR_ENA_SET,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_SET,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_SET,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_SET,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_SET,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_SET,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_SET,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_SET,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_SET,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_SET,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_SET,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_SET,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_SET,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_SET,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_SET,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x10 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_SET,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x10 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_SET,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable" "0,1" line.long 0x14 "VPE_INTC_INTR0_ENA_SET1," bitfld.long 0x14 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 16. "DEI_ERROR_INT_ENA_SET,DEI Error Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 7. "VPDMA_INT0_CLIENT_ENA_SET,VPDMA INT0 Client Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_SET,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_SET,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_SET,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_SET,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable" "0,1" bitfld.long 0x14 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_SET,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable" "0,1" newline bitfld.long 0x14 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_SET,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable" "0,1" line.long 0x18 "VPE_INTC_INTR0_ENA_CLR0," bitfld.long 0x18 18. "DEI_FMD_INT_ENA_CLR,DEI Film Mode Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 16. "VPDMA_INT0_DESCRIPTOR_ENA_CLR,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 15. "VPDMA_INT0_LIST7_NOTIFY_ENA_CLR,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 14. "VPDMA_INT0_LIST7_COMPLETE_ENA_CLR,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 13. "VPDMA_INT0_LIST6_NOTIFY_ENA_CLR,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 12. "VPDMA_INT0_LIST6_COMPLETE_ENA_CLR,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 11. "VPDMA_INT0_LIST5_NOTIFY_ENA_CLR,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 10. "VPDMA_INT0_LIST5_COMPLETE_ENA_CLR,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 9. "VPDMA_INT0_LIST4_NOTIFY_ENA_CLR,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 8. "VPDMA_INT0_LIST4_COMPLETE_ENA_CLR,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 7. "VPDMA_INT0_LIST3_NOTIFY_ENA_CLR,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 6. "VPDMA_INT0_LIST3_COMPLETE_ENA_CLR,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 5. "VPDMA_INT0_LIST2_NOTIFY_ENA_CLR,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 4. "VPDMA_INT0_LIST2_COMPLETE_ENA_CLR,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 3. "VPDMA_INT0_LIST1_NOTIFY_ENA_CLR,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 2. "VPDMA_INT0_LIST1_COMPLETE_ENA_CLR,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x18 1. "VPDMA_INT0_LIST0_NOTIFY_ENA_CLR,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x18 0. "VPDMA_INT0_LIST0_COMPLETE_ENA_CLR,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable" "0,1" line.long 0x1C "VPE_INTC_INTR0_ENA_CLR1," bitfld.long 0x1C 22. "VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 16. "DEI_ERROR_INT_ENA_CLR,DEI Error Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 7. "VPDMA_INT0_CLIENT_ENA_CLR,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 5. "VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 4. "VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 3. "VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 2. "VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable" "0,1" bitfld.long 0x1C 1. "VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable" "0,1" newline bitfld.long 0x1C 0. "VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable" "0,1" group.long 0xA0++0x03 line.long 0x00 "VPE_INTC_EOI,INTC EOI Register" group.long 0x100++0x07 line.long 0x00 "VPE_CLKC_CLKEN," bitfld.long 0x00 1. "PRIM_DP_EN,Primary Video Data Path Clock Enable" "PRIM_DP_EN_0,PRIM_DP_EN_1" bitfld.long 0x00 0. "VPDMA_EN,VPDMA Clock Enable" "VPDMA_EN_0,VPDMA_EN_1" line.long 0x04 "VPE_CLKC_RST," bitfld.long 0x04 31. "MAIN_RST,Reset for entire data path in VPE0" "0,1" bitfld.long 0x04 1. "PRIM_DP_RST,Primary Video Data Path Reset" "0,1" newline bitfld.long 0x04 0. "VPDMA_RST,VPDMA Reset" "0,1" group.long 0x10C++0x03 line.long 0x00 "VPE_CLKC_DPS," bitfld.long 0x00 18. "COLOR_SEPARATE_422,422 Color Separate Select" "COLOR_SEPARATE_422_0,COLOR_SEPARATE_422_1" bitfld.long 0x00 16. "CHR_DS_BYPASS,Chroma Downsampler Bypass" "CHR_DS_BYPASS_0,CHR_DS_BYPASS_1" newline bitfld.long 0x00 9.--11. "CHR_DS_SRC_SELECT,Chroma Downsampler Source Select" "CHR_DS_SRC_SELECT_0,CHR_DS_SRC_SELECT_1,?,?,?,?,?,?" bitfld.long 0x00 8. "RGB_OUT_SELECT,RGB Output Select" "RGB_OUT_SELECT_0,RGB_OUT_SELECT_1" newline bitfld.long 0x00 0.--2. "CSC_SRC_SELECT,CSC Source Select" "CSC_SRC_SELECT_0,CSC_SRC_SELECT_1,?,?,?,?,?,?" group.long 0x11C++0x03 line.long 0x00 "VPE_RANGE_MAP," bitfld.long 0x00 28. "RANGE_REDUCTION_PRIM_ON,Range Reduction ON for Primary input" "0,1" bitfld.long 0x00 6. "RANGE_MAP_PRIM_ON,Range Mapping ON for Primary input" "0,1" newline bitfld.long 0x00 3.--5. "RANGE_MAPUV_PRIM,Range Map UV for Primary input" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "RANGE_MAPY_PRIM,Range Map Y for Primary input" "0,1,2,3,4,5,6,7" tree.end tree "VPE_VPDMA" base ad:0x489DD000 rgroup.long 0x00++0x0F line.long 0x00 "VPE_VPDMA_PID,This register follows the format described in PDR3.5" bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3" newline hexmask.long.word 0x00 16.--29. 1. "FUNC,The funcition of the module being used" newline bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. "MAJOR,Major Release Number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "VPDMA_LOAD_COMPLETE,This bit will be 1 when the VPDMA state machines image and data image have successfuly been fetched and loaded" "0,1" newline bitfld.long 0x00 6. "VPDMA_ACCESS_TYPE,After bootup this bit states how DMA transaction are setup by lists or through register access" "VPDMA_ACCESS_TYPE_0,VPDMA_ACCESS_TYPE_1" newline bitfld.long 0x00 0.--5. "MINOR,Minor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "VPE_LIST_ADDR,The location of a new list to begin processing" line.long 0x08 "VPE_LIST_ATTR,The attributes of a new list" bitfld.long 0x08 24.--26. "LIST_NUM,The list number that should be assigned to the list located at LIST_ADDR" "0,1,2,3,4,5,6,7" newline bitfld.long 0x08 20. "STOP,This bit is written with the LIST_NUMBER field to stop a self-modifying list" "0,1" newline rbitfld.long 0x08 19. "RDY,This bit is low when a new list cannot be written to theVPE_LIST_ADDR register" "0,1" newline bitfld.long 0x08 16.--18. "LIST_TYPE,The type of list that has been generated" "LIST_TYPE_0,LIST_TYPE_1,LIST_TYPE_2,?,?,?,?,?" newline hexmask.long.word 0x08 0.--15. 1. "LIST_SIZE,Number of 128 bit word in the new list of descriptors" line.long 0x0C "VPE_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list" rbitfld.long 0x0C 23. "LIST7_BUSY,The list 7 is currently running" "0,1" newline rbitfld.long 0x0C 22. "LIST6_BUSY,The list 6 is currently running" "0,1" newline rbitfld.long 0x0C 21. "LIST5_BUSY,The list 5 is currently running" "0,1" newline rbitfld.long 0x0C 20. "LIST4_BUSY,The list 4 is currently running" "0,1" newline rbitfld.long 0x0C 19. "LIST3_BUSY,The list 3 is currently running" "0,1" newline rbitfld.long 0x0C 18. "LIST2_BUSY,The list 2 is currently running" "0,1" newline rbitfld.long 0x0C 17. "LIST1_BUSY,The list 1 is currently running" "0,1" newline rbitfld.long 0x0C 16. "LIST0_BUSY,The list 0 is currently running" "0,1" newline bitfld.long 0x0C 7. "SYNC_LISTS7,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it" "0,1" newline bitfld.long 0x0C 6. "SYNC_LISTS6,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it" "0,1" newline bitfld.long 0x0C 5. "SYNC_LISTS5,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it" "0,1" newline bitfld.long 0x0C 4. "SYNC_LISTS4,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it" "0,1" newline bitfld.long 0x0C 3. "SYNC_LISTS3,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it" "0,1" newline bitfld.long 0x0C 2. "SYNC_LISTS2,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it" "0,1" newline bitfld.long 0x0C 1. "SYNC_LISTS1,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it" "0,1" newline bitfld.long 0x0C 0. "SYNC_LISTS0,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it" "0,1" group.long 0x18++0x07 line.long 0x00 "VPE_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x00 24.--31. 1. "RED,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 16.--23. 1. "GREEN,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 8.--15. 1. "BLUE,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x00 0.--7. 1. "BLEND,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" line.long 0x04 "VPE_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x04 16.--23. 1. "Y,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x04 8.--15. 1. "CR,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" newline hexmask.long.byte 0x04 0.--7. 1. "CB,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" group.long 0x30++0x6F line.long 0x00 "VPE_VPDMA_SETUP,Configures global parameters that are shared by all clients" bitfld.long 0x00 0. "SEC_BASE_CH,Use Secondary Channels for Mosaic mode" "0,1" line.long 0x04 "VPE_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor" hexmask.long.word 0x04 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 1 in a write descriptor" newline hexmask.long.word 0x04 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 1 in a write descriptor" line.long 0x08 "VPE_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor" hexmask.long.word 0x08 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 2 in a write descriptor" newline hexmask.long.word 0x08 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 2 in a write descriptor" line.long 0x0C "VPE_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor" hexmask.long.word 0x0C 16.--31. 1. "MAX_WIDTH,The maximum width to use for setting of max_width 3 in a write descriptor" newline hexmask.long.word 0x0C 0.--15. 1. "MAX_HEIGHT,The maximum height to use for setting of max_height 3 in a write descriptor" line.long 0x10 "VPE_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x10 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline bitfld.long 0x10 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x10 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x10 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" newline bitfld.long 0x10 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x10 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" newline bitfld.long 0x10 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x10 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x14 "VPE_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x14 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x14 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x18 "VPE_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x18 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x18 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x18 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x18 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x18 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x18 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x18 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x18 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x1C "VPE_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x1C 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x1C 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x20 "VPE_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0" bitfld.long 0x20 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" newline bitfld.long 0x20 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x20 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x20 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x20 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" newline bitfld.long 0x20 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x20 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" newline bitfld.long 0x20 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x20 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x20 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x20 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" newline bitfld.long 0x20 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x20 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" newline bitfld.long 0x20 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x20 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x20 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x20 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x20 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x20 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x20 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x20 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x20 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x20 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x20 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x20 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x20 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x20 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x20 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x20 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x20 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x20 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x20 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x24 "VPE_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0" bitfld.long 0x24 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" newline bitfld.long 0x24 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int0" "0,1" line.long 0x28 "VPE_INT1_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x28 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline bitfld.long 0x28 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x28 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x28 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" newline bitfld.long 0x28 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x28 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" newline bitfld.long 0x28 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x28 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x2C "VPE_INT1_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x2C 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x2C 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x30 "VPE_INT1_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x30 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x30 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x30 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x30 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x30 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x30 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x30 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x30 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x34 "VPE_INT1_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x34 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x34 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x38 "VPE_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1" bitfld.long 0x38 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" newline bitfld.long 0x38 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x38 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x38 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x38 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" newline bitfld.long 0x38 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x38 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" newline bitfld.long 0x38 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x38 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x38 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x38 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" newline bitfld.long 0x38 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x38 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" newline bitfld.long 0x38 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x38 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x38 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x38 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x38 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x38 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x38 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x38 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x38 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x38 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x38 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x38 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x38 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x38 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x38 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x38 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x38 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x38 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x38 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x3C "VPE_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1" bitfld.long 0x3C 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" newline bitfld.long 0x3C 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int1" "0,1" line.long 0x40 "VPE_INT2_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x40 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline bitfld.long 0x40 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x40 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x40 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" newline bitfld.long 0x40 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x40 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" newline bitfld.long 0x40 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x40 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x44 "VPE_INT2_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x44 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x44 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x44 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x44 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x44 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x44 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x44 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x44 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x48 "VPE_INT2_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x48 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x48 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x48 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x48 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x48 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x48 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x48 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x48 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x4C "VPE_INT2_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x4C 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x4C 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x4C 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x4C 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x4C 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x4C 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x4C 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x4C 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x50 "VPE_INT2_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int2" bitfld.long 0x50 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" newline bitfld.long 0x50 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x50 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x50 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x50 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" newline bitfld.long 0x50 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x50 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" newline bitfld.long 0x50 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x50 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x50 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x50 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" newline bitfld.long 0x50 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x50 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" newline bitfld.long 0x50 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x50 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x50 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x50 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x50 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x50 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x50 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x50 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x50 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x50 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x50 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x50 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x50 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x50 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x50 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x50 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x50 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x50 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x50 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x54 "VPE_INT2_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int2" bitfld.long 0x54 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" newline bitfld.long 0x54 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int2" "0,1" line.long 0x58 "VPE_INT3_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x58 15. "INT_STAT_HQ_MV_OUT,The last write DMA transaction has completed for channel hq_mv_out" "0,1" newline bitfld.long 0x58 12. "INT_STAT_HQ_MV,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer" "0,1" newline bitfld.long 0x58 5. "INT_STAT_HQ_VID3_CHROMA,The last write DMA transaction has completed for channel hq_vid3_chroma" "0,1" newline bitfld.long 0x58 4. "INT_STAT_HQ_VID3_LUMA,The last write DMA transaction has completed for channel hq_vid3_luma" "0,1" newline bitfld.long 0x58 3. "INT_STAT_HQ_VID2_CHROMA,The last write DMA transaction has completed for channel hq_vid2_chroma" "0,1" newline bitfld.long 0x58 2. "INT_STAT_HQ_VID2_LUMA,The last write DMA transaction has completed for channel hq_vid2_luma" "0,1" newline bitfld.long 0x58 1. "INT_STAT_HQ_VID1_CHROMA,The last write DMA transaction has completed for channel hq_vid1_chroma" "0,1" newline bitfld.long 0x58 0. "INT_STAT_HQ_VID1_LUMA,The last write DMA transaction has completed for channel hq_vid1_luma" "0,1" line.long 0x5C "VPE_INT3_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x5C 15. "INT_MASK_HQ_MV_OUT,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x5C 12. "INT_MASK_HQ_MV,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x5C 5. "INT_MASK_HQ_VID3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x5C 4. "INT_MASK_HQ_VID3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x5C 3. "INT_MASK_HQ_VID2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x5C 2. "INT_MASK_HQ_VID2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x5C 1. "INT_MASK_HQ_VID1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x5C 0. "INT_MASK_HQ_VID1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0x60 "VPE_INT3_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x60 15. "INT_STAT_DEI_HQ_MV_OUT,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x60 12. "INT_STAT_DEI_HQ_MV_IN,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x60 5. "INT_STAT_DEI_HQ_3_CHROMA,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x60 4. "INT_STAT_DEI_HQ_3_LUMA,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x60 3. "INT_STAT_DEI_HQ_2_CHROMA,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x60 2. "INT_STAT_DEI_HQ_2_LUMA,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x60 1. "INT_STAT_DEI_HQ_1_LUMA,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" newline bitfld.long 0x60 0. "INT_STAT_DEI_HQ_1_CHROMA,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client" "0,1" line.long 0x64 "VPE_INT3_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x64 15. "INT_MASK_DEI_HQ_MV_OUT,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x64 12. "INT_MASK_DEI_HQ_MV_IN,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x64 5. "INT_MASK_DEI_HQ_3_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x64 4. "INT_MASK_DEI_HQ_3_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x64 3. "INT_MASK_DEI_HQ_2_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x64 2. "INT_MASK_DEI_HQ_2_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x64 1. "INT_MASK_DEI_HQ_1_LUMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x64 0. "INT_MASK_DEI_HQ_1_CHROMA,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" line.long 0x68 "VPE_INT3_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int3" bitfld.long 0x68 31. "INT_STAT_CONTROL_DESCRIPTOR_INT15,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15" "0,1" newline bitfld.long 0x68 30. "INT_STAT_CONTROL_DESCRIPTOR_INT14,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14" "0,1" newline bitfld.long 0x68 29. "INT_STAT_CONTROL_DESCRIPTOR_INT13,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13" "0,1" newline bitfld.long 0x68 28. "INT_STAT_CONTROL_DESCRIPTOR_INT12,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12" "0,1" newline bitfld.long 0x68 27. "INT_STAT_CONTROL_DESCRIPTOR_INT11,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11" "0,1" newline bitfld.long 0x68 26. "INT_STAT_CONTROL_DESCRIPTOR_INT10,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10" "0,1" newline bitfld.long 0x68 25. "INT_STAT_CONTROL_DESCRIPTOR_INT9,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9" "0,1" newline bitfld.long 0x68 24. "INT_STAT_CONTROL_DESCRIPTOR_INT8,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8" "0,1" newline bitfld.long 0x68 23. "INT_STAT_CONTROL_DESCRIPTOR_INT7,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7" "0,1" newline bitfld.long 0x68 22. "INT_STAT_CONTROL_DESCRIPTOR_INT6,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6" "0,1" newline bitfld.long 0x68 21. "INT_STAT_CONTROL_DESCRIPTOR_INT5,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5" "0,1" newline bitfld.long 0x68 20. "INT_STAT_CONTROL_DESCRIPTOR_INT4,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4" "0,1" newline bitfld.long 0x68 19. "INT_STAT_CONTROL_DESCRIPTOR_INT3,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3" "0,1" newline bitfld.long 0x68 18. "INT_STAT_CONTROL_DESCRIPTOR_INT2,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2" "0,1" newline bitfld.long 0x68 17. "INT_STAT_CONTROL_DESCRIPTOR_INT1,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1" "0,1" newline bitfld.long 0x68 16. "INT_STAT_CONTROL_DESCRIPTOR_INT0,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0" "0,1" newline bitfld.long 0x68 15. "INT_STAT_LIST7_NOTIFY,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x68 14. "INT_STAT_LIST7_COMPLETE,List 7 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x68 13. "INT_STAT_LIST6_NOTIFY,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x68 12. "INT_STAT_LIST6_COMPLETE,List 6 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x68 11. "INT_STAT_LIST5_NOTIFY,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x68 10. "INT_STAT_LIST5_COMPLETE,List 5 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x68 9. "INT_STAT_LIST4_NOTIFY,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x68 8. "INT_STAT_LIST4_COMPLETE,List 4 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x68 7. "INT_STAT_LIST3_NOTIFY,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x68 6. "INT_STAT_LIST3_COMPLETE,List 3 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x68 5. "INT_STAT_LIST2_NOTIFY,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x68 4. "INT_STAT_LIST2_COMPLETE,List 2 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x68 3. "INT_STAT_LIST1_NOTIFY,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x68 2. "INT_STAT_LIST1_COMPLETE,List 1 has completed and a new list can be loaded" "0,1" newline bitfld.long 0x68 1. "INT_STAT_LIST0_NOTIFY,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel" "0,1" newline bitfld.long 0x68 0. "INT_STAT_LIST0_COMPLETE,List 0 has completed and a new list can be loaded" "0,1" line.long 0x6C "VPE_INT3_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int3" bitfld.long 0x6C 31. "INT_MASK_CONTROL_DESCRIPTOR_INT15,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 30. "INT_MASK_CONTROL_DESCRIPTOR_INT14,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 29. "INT_MASK_CONTROL_DESCRIPTOR_INT13,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 28. "INT_MASK_CONTROL_DESCRIPTOR_INT12,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 27. "INT_MASK_CONTROL_DESCRIPTOR_INT11,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 26. "INT_MASK_CONTROL_DESCRIPTOR_INT10,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 25. "INT_MASK_CONTROL_DESCRIPTOR_INT9,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 24. "INT_MASK_CONTROL_DESCRIPTOR_INT8,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 23. "INT_MASK_CONTROL_DESCRIPTOR_INT7,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 22. "INT_MASK_CONTROL_DESCRIPTOR_INT6,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 21. "INT_MASK_CONTROL_DESCRIPTOR_INT5,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 20. "INT_MASK_CONTROL_DESCRIPTOR_INT4,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 19. "INT_MASK_CONTROL_DESCRIPTOR_INT3,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 18. "INT_MASK_CONTROL_DESCRIPTOR_INT2,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 17. "INT_MASK_CONTROL_DESCRIPTOR_INT1,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 16. "INT_MASK_CONTROL_DESCRIPTOR_INT0,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 15. "INT_MASK_LIST7_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 14. "INT_MASK_LIST7_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 13. "INT_MASK_LIST6_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 12. "INT_MASK_LIST6_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 11. "INT_MASK_LIST5_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 10. "INT_MASK_LIST5_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 9. "INT_MASK_LIST4_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 8. "INT_MASK_LIST4_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 7. "INT_MASK_LIST3_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 6. "INT_MASK_LIST3_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 5. "INT_MASK_LIST2_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 4. "INT_MASK_LIST2_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 3. "INT_MASK_LIST1_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 2. "INT_MASK_LIST1_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 1. "INT_MASK_LIST0_NOTIFY,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" newline bitfld.long 0x6C 0. "INT_MASK_LIST0_COMPLETE,The interrupt for should generate an interrupt on interrupt vpdma_int3" "0,1" group.long 0x300++0x17 line.long 0x00 "VPE_PRI_CHROMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" newline bitfld.long 0x00 8.--9. "LINE_MODE,Selects the output mode of the line buffer" "LINE_MODE_0,LINE_MODE_1,LINE_MODE_2,LINE_MODE_3" line.long 0x04 "VPE_PRI_LUMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" line.long 0x08 "VPE_PRI_FLD1_LUMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x08 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x08 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x08 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x08 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x08 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" line.long 0x0C "VPE_PRI_FLD1_CHROMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x0C 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x0C 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x0C 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x0C 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x0C 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" newline bitfld.long 0x0C 8.--9. "LINE_MODE,Selects the output mode of the line buffer" "LINE_MODE_0,LINE_MODE_1,LINE_MODE_2,LINE_MODE_3" newline hexmask.long.byte 0x0C 0.--7. 1. "3: each line once only on one line. Each data line gets number of frame lines divided by number of buffered lines.," line.long 0x10 "VPE_PRI_FLD2_LUMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x10 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x10 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x10 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x10 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x10 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" line.long 0x14 "VPE_PRI_FLD2_CHROMA_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x14 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x14 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x14 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x14 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x14 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" newline bitfld.long 0x14 8.--9. "LINE_MODE,Selects the output mode of the line buffer" "LINE_MODE_0,LINE_MODE_1,LINE_MODE_2,LINE_MODE_3" group.long 0x330++0x03 line.long 0x00 "VPE_PRI_MV0_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" group.long 0x33C++0x03 line.long 0x00 "VPE_PRI_MV_OUT_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" group.long 0x390++0x07 line.long 0x00 "VPE_VIP0_UP_Y_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" line.long 0x04 "VPE_VIP0_UP_UV_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x04 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x04 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x04 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x04 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x04 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" group.long 0x3D0++0x03 line.long 0x00 "VPE_VPI_CTL_CSTAT,The register holds status information and control for the client" hexmask.long.byte 0x00 24.--31. 1. "REQ_DELAY,The minimum number of clock cycles between requests being issued" newline hexmask.long.byte 0x00 16.--23. 1. "REQ_RATE,The number of clock cycles between the last two requests issued" newline rbitfld.long 0x00 15. "BUSY,Signals if the client is currently active" "0,1" newline rbitfld.long 0x00 14. "DMA_ACTIVE,Signals if the client is currently actively sending DMA requests" "0,1" newline bitfld.long 0x00 10.--13. "FRAME_START,The source of the start frame event for the client" "FRAME_START_0,FRAME_START_1,FRAME_START_2,FRAME_START_3,FRAME_START_4,FRAME_START_5,FRAME_START_6,FRAME_START_7,?,?,?,?,?,?,?,?" repeat 11. (list 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 ) group.long ($2+0x29C)++0x03 line.long 0x00 "VPE_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "0,1,2,3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 10. (list 32. 33. 34. 35. 36. 37. 38. 50. 51. 52. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x48 0x4C 0x50 ) group.long ($2+0x280)++0x03 line.long 0x00 "VPE_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x240)++0x03 line.long 0x00 "VPE_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x03 line.long 0x00 "VPE_PERF_MON$1,The register can be used to capture timing differences between events in the VPDMA" bitfld.long 0x00 30.--31. "CAPTURE_MODE,Sets how the counter should be updated" "CAPTURE_MODE_0,CAPTURE_MODE_1,CAPTURE_MODE_2,CAPTURE_MODE_3" newline bitfld.long 0x00 28.--29. "STOP_CLIENT,Sets the client whose event stops the performance monitor counter" "STOP_CLIENT_0,STOP_CLIENT_1,STOP_CLIENT_2,STOP_CLIENT_3" newline bitfld.long 0x00 24.--26. "STOP_COUNT,Sets the value that stops the performance monitor counter" "STOP_COUNT_0,STOP_COUNT_1,STOP_COUNT_2,STOP_COUNT_3,STOP_COUNT_4,STOP_COUNT_5,STOP_COUNT_6,STOP_COUNT_7" newline bitfld.long 0x00 20.--21. "START_CLIENT,Sets the client whose event starts the performance monitor counter" "START_CLIENT_0,START_CLIENT_1,START_CLIENT_2,START_CLIENT_3" newline bitfld.long 0x00 16.--18. "START_COUNT,Sets the value that starts the performance monitor counter" "START_COUNT_0,START_COUNT_1,START_COUNT_2,START_COUNT_3,START_COUNT_4,START_COUNT_5,START_COUNT_6,START_COUNT_7" newline hexmask.long.word 0x00 0.--15. 1. "CURR_COUNT,The current value of the perfomance monitor counter" repeat.end tree.end tree.end tree.open "Watchdog_Timers" tree "WD_TIMER2" base ad:0x4AE14000 rgroup.long 0x00++0x03 line.long 0x00 "WIDR,IP revision identifier" group.long 0x10++0x27 line.long 0x00 "WDSC,This register controls the various parameters of the L4 interface" bitfld.long 0x00 5. "EMUFREE,Emulation mode - Disabled" "EMUFREE_0,EMUFREE_1" bitfld.long 0x00 3.--4. "IDLEMODE,Configuration of the local target state management mode" "IDLEMODE_0,IDLEMODE_1,IDLEMODE_2,IDLEMODE_3" bitfld.long 0x00 1. "SOFTRESET,Software reset" "SOFTRESET_0_w,SOFTRESET_1_r" line.long 0x04 "WDST,This register provides status information about the module" bitfld.long 0x04 0. "RESETDONE,Internal module reset monitoring - Ongoing" "RESETDONE_0_r,RESETDONE_1_r" line.long 0x08 "WISR,This register shows which interrupt events are pending inside the module" bitfld.long 0x08 1. "DLY_IT_FLAG,Pending delay interrupt status" "DLY_IT_FLAG_0_w,DLY_IT_FLAG_1_r" bitfld.long 0x08 0. "OVF_IT_FLAG,Pending overflow interrupt status" "OVF_IT_FLAG_0_w,OVF_IT_FLAG_1_r" line.long 0x0C "WIER,This register controls (enable/disable) the interrupt events" bitfld.long 0x0C 1. "DLY_IT_ENA,Delay interrupt enable/disable - Disabled" "DLY_IT_ENA_0,DLY_IT_ENA_1" bitfld.long 0x0C 0. "OVF_IT_ENA,Overflow interrupt enable/disable - Disabled" "OVF_IT_ENA_0,OVF_IT_ENA_1" line.long 0x10 "WWER,This register controls (enable/disable) the wake-up events" bitfld.long 0x10 1. "DLY_WK_ENA,Delay wake-up enable - Disabled" "DLY_WK_ENA_0,DLY_WK_ENA_1" bitfld.long 0x10 0. "OVF_WK_ENA,Overflow wake-up enable - Disabled" "OVF_WK_ENA_0,OVF_WK_ENA_1" line.long 0x14 "WCLR,This register controls the prescaler stage of the counter" bitfld.long 0x14 5. "PRE,Prescaler enable/disable configuration - Disabled" "PRE_0,PRE_1" bitfld.long 0x14 2.--4. "PTV,Prescaler value The timer counter is prescaled with the value: 2" "PTV_0,PTV_1,PTV_2,PTV_3,PTV_4,PTV_5,PTV_6,PTV_7" line.long 0x18 "WCRR,This register holds the value of the internal counter" line.long 0x1C "WLDR,This register holds the timer load value" line.long 0x20 "WTGR,Writing a different value than the one already written in this register does a watchdog counter reload" line.long 0x24 "WWPS,This register contains the write posting bits for all writeable functional registers" bitfld.long 0x24 5. "W_PEND_WDLY,Write pending for registerWDLY - Ready" "W_PEND_WDLY_0_r,W_PEND_WDLY_1_r" bitfld.long 0x24 4. "W_PEND_WSPR,Write pending for registerWSPR - Ready" "W_PEND_WSPR_0_r,W_PEND_WSPR_1_r" bitfld.long 0x24 3. "W_PEND_WTGR,Write pending for registerWTGR - Ready" "W_PEND_WTGR_0_r,W_PEND_WTGR_1_r" bitfld.long 0x24 2. "W_PEND_WLDR,Write pending for registerWLDR - Ready" "W_PEND_WLDR_0_r,W_PEND_WLDR_1_r" newline bitfld.long 0x24 1. "W_PEND_WCRR,Write pending for registerWCRR - Ready" "W_PEND_WCRR_0_r,W_PEND_WCRR_1_r" bitfld.long 0x24 0. "W_PEND_WCLR,Write pending for registerWCLR - Ready" "W_PEND_WCLR_0_r,W_PEND_WCLR_1_r" group.long 0x44++0x07 line.long 0x00 "WDLY,This register holds the delay value that controls the internal pre-overflow event detection" line.long 0x04 "WSPR,This register holds the start-stop value that controls the internal start-stop FSM" group.long 0x50++0x17 line.long 0x00 "WIRQEOI,Software End Of Interrupt" bitfld.long 0x00 0. "LINE_NUMBER,EOI for interrupt output line Reads always 0 (no EOI memory)" "LINE_NUMBER_0,LINE_NUMBER_1" line.long 0x04 "WIRQSTATRAW,IRQ unmasked status. status set per-event raw interrupt status vector. line 0" bitfld.long 0x04 1. "EVENT_DLY,Settable raw status for delay event - Read_0" "EVENT_DLY_0_w,EVENT_DLY_1_r" bitfld.long 0x04 0. "EVENT_OVF,Settable raw status for overflow event - Read_0" "EVENT_OVF_0_w,EVENT_OVF_1_r" line.long 0x08 "WIRQSTAT,IRQ masked status. status clear per-event enabled interrupt status vector. line 0" bitfld.long 0x08 1. "EVENT_DLY,Clearable enabled status for delay event - Read_0" "EVENT_DLY_0_w,EVENT_DLY_1_r" bitfld.long 0x08 0. "EVENT_OVF,Clearable enabled status for overflow event - Read_0" "EVENT_OVF_0_w,EVENT_OVF_1_r" line.long 0x0C "WIRQENSET,IRQ enable set per-event interrupt enable bit vector. line 0" bitfld.long 0x0C 1. "ENABLE_DLY,Enable for delay event - Read_0" "ENABLE_DLY_0_w,ENABLE_DLY_1_r" bitfld.long 0x0C 0. "ENABLE_OVF,Enable for overflow event - Read_0" "ENABLE_OVF_0_w,ENABLE_OVF_1_r" line.long 0x10 "WIRQENCLR,IRQ enable clear per-event interrupt enable bit vector. line 0" bitfld.long 0x10 1. "ENABLE_DLY,Enable for delay event - Read_0" "ENABLE_DLY_0_w,ENABLE_DLY_1_r" bitfld.long 0x10 0. "ENABLE_OVF,Enable for overflow event - Read_0" "ENABLE_OVF_0_w,ENABLE_OVF_1_r" line.long 0x14 "WIRQWAKEEN,This register controls (enable/disable) the wake-up events" bitfld.long 0x14 1. "DLY_WK_ENA,Enable delay wake-up - Disabled" "DLY_WK_ENA_0,DLY_WK_ENA_1" bitfld.long 0x14 0. "OVF_WK_ENA,Enable overflow wakeup - Disabled" "OVF_WK_ENA_0,OVF_WK_ENA_1" tree.end tree.end autoindent.off newline