; --------------------------------------------------------------------------------
; @Title: TMS570LS20216 Specific Menu
; @Props: Released
; @Author: ADI
; @Changelog: 2008-10-22 ADI
; @Manufacturer: TI - Texas Instruments
; @Core: Cortex-R4F
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: mentms570ls20216.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-R4F)"
(
menuitem "[:chip]ID Registers"                      "per , ""Core Registers (Cortex-R4F),ID Registers"""
menuitem "[:chip]System Control and Configuration"  "per , ""Core Registers (Cortex-R4F),System Control and Configuration"""
menuitem "[:chip]MPU Control and Configuration"     "per , ""Core Registers (Cortex-R4F),MPU Control and Configuration"""
menuitem "[:chip]Cache Control and Configuration"   "per , ""Core Registers (Cortex-R4F),Cache Control and Configuration"""
menuitem "[:chip]TCM Control and Configuration"     "per , ""Core Registers (Cortex-R4F),TCM Control and Configuration"""
menuitem "[:chip]System Performance Monitor"        "per , ""Core Registers (Cortex-R4F),System Performance Monitor"""
separator
menuitem "[:chip]Debug Registers"                   "per , ""Core Registers (Cortex-R4F),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"              "per , ""Core Registers (Cortex-R4F),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"      "per , ""Core Registers (Cortex-R4F),Watchpoint Control Registers"""
)
separator
popup "ADC"
(
menuitem "MIBADC1"                            "per , ""ADC (Analog to Digital Converter),MIBADC1"""
menuitem "MIBADC2"                            "per , ""ADC (Analog to Digital Converter),MIBADC2"""
)
popup "DCAN"
(
menuitem "DCAN1"                              "per , ""DCAN (Controller Area Network),DCAN1"""
menuitem "DCAN2"                              "per , ""DCAN (Controller Area Network),DCAN2"""
menuitem "DCAN3"                              "per , ""DCAN (Controller Area Network),DCAN3"""
)
menuitem "Flexray"                                "per , ""Flexray"""
menuitem "FlexrayTU"                              "per , ""FlexrayTU"""
popup "GPIO"
(
menuitem "GIO"                                "per , ""GPIO (General-Purpose Input/Output),GIO"""
menuitem "GIOA"                               "per , ""GPIO (General-Purpose Input/Output),GIOA"""
menuitem "GIOB"                               "per , ""GPIO (General-Purpose Input/Output),GIOB"""
)
menuitem "NHET"                                   "per , ""NHET (New High End Timer)"""
menuitem "HTU"                                    "per , ""HTU (High End Timer Transfer Unit)"""
popup "SPI"
(
menuitem "MIBSPI1"                            "per , ""SPI (Serial Peripheral Interface),MIBSPI1"""
menuitem "MIBSPI3"                            "per , ""SPI (Serial Peripheral Interface),MIBSPI3"""
menuitem "MIBSPIP5"                           "per , ""SPI (Serial Peripheral Interface),MIPSPIP5"""
)
popup "SCI"
(
menuitem "LIN1"                               "per , ""SCI (Serial Communication Interface),LIN1"""
menuitem "LIN2"                               "per , ""SCI (Serial Communication Interface),LIN2"""
)
menuitem "CCMR4"                                  "per , ""CCMR4 (CPU Compare Module - CortexR4)"""
menuitem "CRC"                                    "per , ""CRC"""
menuitem "DMA"                                    "per , ""DMA (Direct Memory Access)"""
menuitem "DMM"                                    "per , ""DMM (Data Modification Module)"""
menuitem "ESM"                                    "per , ""ESM (Error Signaling Module)"""
menuitem "Flash Wrapper"                          "per , ""Flash_Wrapper"""
menuitem "PBIST"                                  "per , ""PBIST (Programmable Built-In Self-Test)"""
menuitem "RTP"                                    "per , ""RTP (RAM Trace Port)"""
menuitem "RTI"                                    "per , ""RTI (Real Time Interrupt)"""
menuitem "STC"                                    "per , ""STC (Self-Test Controller)"""
menuitem "SYS"                                    "per , ""SYS (System Registers)"""
popup "VIM"
(
menuitem "VIM"                                "per , ""VIM (Vectored Interrupt Manager),VIM"""
menuitem "VIMPAR"                             "per , ""VIM (Vectored Interrupt Manager),VIMPAR"""
)
menuitem "POM"                                    "per , ""POM (Parameter Overlay Module)"""
menuitem "EMIF"                                   "per , ""EMIF (Asynchronous External Memory Interface)"""
menuitem "PCR"                                    "per , ""PCR (Peripheral Central Resource)"""
popup "RAM Wrapper"
(
menuitem "RAM Wrapper Even"                   "per , ""RAM Wrapper,RAM_Wrapper_even"""
menuitem "RAM Wrapper Odd"                    "per , ""RAM Wrapper,RAM_Wrapper_odd"""
)
)
)