; --------------------------------------------------------------------------------
; @Title: TDA2x Specific Menu
; @Props: Released
; @Author: ASK
; @Changelog: 2016-03-29 ASK
; @Manufacturer: TI - Texas Instruments
; @Core: Cortex-A15, Cortex-M4, ARM9, C646X
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: mentda2x.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
if (CPUFAMILY()=="C6000")
(
popup "&CPU"
(
after "FPU Registers"
separator
popup "[:cache]Cache"
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
popup "&Trace"
(
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("AET")
(
menuitem "[:oconfig]AET settings..." "AET.state"
)
)
popup "&Perf"
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
else
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
)
popup "Peripherals"
(
if (cpuis("TDA2x"))
(
popup "[:chip]Core Registers (Cortex-A15MPCore)"
(
menuitem "[:chip]ID Registers"                      "per , ""Core Registers (Cortex-A15MPCore),ID Registers"""
menuitem "[:chip]System Control and Configuration"  "per , ""Core Registers (Cortex-A15MPCore),System Control and Configuration"""
menuitem "[:chip]Memory Management Unit"            "per , ""Core Registers (Cortex-A15MPCore),Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions"         "per , ""Core Registers (Cortex-A15MPCore),Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration"   "per , ""Core Registers (Cortex-A15MPCore),Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor"        "per , ""Core Registers (Cortex-A15MPCore),System Performance Monitor"""
menuitem "[:chip]System Timer Register"             "per , ""Core Registers (Cortex-A15MPCore),System Timer Register"""
separator
menuitem "[:chip]Debug Registers"                   "per , ""Core Registers (Cortex-A15MPCore),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"              "per , ""Core Registers (Cortex-A15MPCore),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"      "per , ""Core Registers (Cortex-A15MPCore),Watchpoint Control Registers"""
separator
menuitem "[:chip]Interrupt Controller"              "per , ""Core Registers (Cortex-A15MPCore),Interrupt Controller"""
)
)
else if (cpuis("TDA2XIPU*"))||(cpuis("TDA2XIPU*"))
(
popup "[:chip]Core Registers (Cortex-M4)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M4),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M4),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M4),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
else if (cpuis("TDA2XIVA"))
(
menuitem "[:chip]Core Registers (ARM966)"           "per , ""Core Registers (ARM966)"""
)
else if (cpuis("TDA2XDSP?"))
(
popup "[:chip]Core Registers (c66x)"
(
menuitem "[:chip]L1P;L1P Registers"                    "per , ""Core Registers (c66x),Cache,L1P Cache"""
menuitem "[:chip]L1D;L1D Registers"                    "per , ""Core Registers (c66x),Cache,L1D Cache"""
menuitem "[:chip]L2;L2 Registers"                      "per , ""Core Registers (c66x),Cache,L2 Cache"""
menuitem "[:chip]IDMA;IDMA Registers"                  "per , ""Core Registers (c66x),IDMA (Internal Direct Memory Access Controller)"""
menuitem "[:chip]XMC;XMC Registers"                    "per , ""Core Registers (c66x),XMC (Extended Memory Controller)"""
menuitem "[:chip]BM;BM Registers"                      "per , ""Core Registers (c66x),Bandwith Management"""
menuitem "[:chip]IC;IC Registers"                      "per , ""Core Registers (c66x),Interrupt Controller"""
menuitem "[:chip]PD;PD Registers"                      "per , ""Core Registers (c66x),Power-Down Controller"""
)
)
separator
menuitem "PRCM"                                         "PER , ""PRCM"""
menuitem "Dual_Cortex_A15_MPU_Subsystem"                "PER , ""Dual_Cortex_A15_MPU_Subsystem"""
menuitem "DSP_Subsystem"                                "PER , ""DSP_Subsystem"""
if cpuis("TDA2XIVA")
(
menuitem "IVA_Imaging_Controller"                   "PER , ""IVA_Imaging_Controller"""
)
menuitem "IVA_Video_Direct_Memory_Access"               "PER , ""IVA_Video_Direct_Memory_Access"""
menuitem "IVA_Synchronization_Box"                      "PER , ""IVA_Synchronization_Box"""
menuitem "IVA_Load_and_Store_Engine"                    "PER , ""IVA_Load_and_Store_Engine"""
menuitem "IVA_Motion_Estimation"                        "PER , ""IVA_Motion_Estimation"""
menuitem "IVA_Intra_Prediction_Estimation"              "PER , ""IVA_Intra_Prediction_Estimation"""
menuitem "IVA_Loop_Filter"                              "PER , ""IVA_Loop_Filter"""
menuitem "IVA_Motion_Compensation"                      "PER , ""IVA_Motion_Compensation"""
menuitem "IVA_CALCulation_Engine_3"                     "PER , ""IVA_CALCulation_Engine_3"""
menuitem "IVA_Entropy_Coder_Decoder"                    "PER , ""IVA_Entropy_Coder_Decoder"""
menuitem "Dual_Cortex_M4_IPU_Subsystem"                 "PER , ""Dual_Cortex_M4_IPU_Subsystem"""
menuitem "VIP"                                          "PER , ""VIP"""
menuitem "VPE"                                          "PER , ""VPE"""
menuitem "Display_Subsystem_Overview"                   "PER , ""Display_Subsystem_Overview"""
menuitem "Display_Controller"                           "PER , ""Display_Controller"""
menuitem "GPU"                                          "PER , ""GPU"""
menuitem "L3_MAIN_Interconnect"                         "PER , ""L3_MAIN_Interconnect"""
menuitem "L4_Interconnects"                             "PER , ""L4_Interconnects"""
menuitem "BB2D"                                         "PER , ""BB2D"""
menuitem "Dynamic_Memory_Manager"                       "PER , ""Dynamic_Memory_Manager"""
menuitem "EMIF_Controller"                              "PER , ""EMIF_Controller"""
menuitem "General_Purpose_Memory_Controller"            "PER , ""General_Purpose_Memory_Controller"""
menuitem "Error_Location_Module"                        "PER , ""Error_Location_Module"""
menuitem "On_Chip_Memory_OCM"                           "PER , ""On_Chip_Memory_OCM"""
menuitem "Enhanced_DMA"                                 "PER , ""Enhanced_DMA"""
menuitem "System_DMA"                                   "PER , ""System_DMA"""
menuitem "IODELAYCONFIG_Module"                         "PER , ""IODELAYCONFIG_Module"""
menuitem "Control_Module"                               "PER , ""Control_Module"""
menuitem "Mailbox"                                      "PER , ""Mailbox"""
menuitem "MMU"                                          "PER , ""MMU"""
menuitem "Spinlock"                                     "PER , ""Spinlock"""
menuitem "General_Purpose_Timers"                       "PER , ""General_Purpose_Timers"""
menuitem "Watchdog_Timer"                               "PER , ""Watchdog_Timer"""
menuitem "_32_kHz_Synchronized_Timer_COUNTER_32K"       "PER , ""_32_kHz_Synchronized_Timer_COUNTER_32K"""
menuitem "RTC"                                          "PER , ""RTC"""
menuitem "Multimaster_High_Speed_I2C_Controller"        "PER , ""Multimaster_High_Speed_I2C_Controller"""
menuitem "UART_IrDA_CIR"                                "PER , ""UART_IrDA_CIR"""
menuitem "Multichannel_Serial_Peripheral_Interface"     "PER , ""Multichannel_Serial_Peripheral_Interface"""
menuitem "Quad_Serial_Peripheral_Interface"             "PER , ""Quad_Serial_Peripheral_Interface"""
menuitem "Multichannel_Audio_Serial_Port"               "PER , ""Multichannel_Audio_Serial_Port"""
menuitem "SuperSpeed_USB_DRD"                           "PER , ""SuperSpeed_USB_DRD"""
menuitem "SATA_Controller"                              "PER , ""SATA_Controller"""
menuitem "PCIe_Controller"                              "PER , ""PCIe_Controller"""
menuitem "DCAN"                                         "PER , ""DCAN"""
menuitem "Gigabit_Ethernet_Switch_GMAC_SW"              "PER , ""Gigabit_Ethernet_Switch_GMAC_SW"""
menuitem "eMMC_SD_SDIO"                                 "PER , ""eMMC_SD_SDIO"""
menuitem "USB3_PHY_and_SATA_PHY_Subsystems__Manual"     "PER , ""USB3_PHY_and_SATA_PHY_Subsystems__Manual"""
menuitem "PCIe_PHY_Subsystem"                           "PER , ""PCIe_PHY_Subsystem"""
menuitem "General_Purpose_Interface_Overview"           "PER , ""General_Purpose_Interface_Overview"""
menuitem "PWM_Subsystem_Resources"                      "PER , ""PWM_Subsystem_Resources"""
menuitem "On_Chip_Debug_Support"                        "PER , ""On_Chip_Debug_Support"""
menuitem "Embedded_Vision_Engine_EVE_Subsystem"         "PER , ""Embedded_Vision_Engine_EVE_Subsystem"""
menuitem "VCOP_CPU_and_Instruction_Set"                 "PER , ""VCOP_CPU_and_Instruction_Set"""
)
)