; --------------------------------------------------------------------------------
; @Title: Stratix 10 Specific Menu
; @Props: Released
; @Author: CEZ, MKO, MRO, DLI, PID, KRZ
; @Changelog: 2019-10-10 MKO
; @Manufacturer: INTEL - Intel Corporation
; @Core: Cortex-A53
; @Chip: STRATIX10SX
; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menstratix10.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-A53)"
(
menuitem "[:chip]ID Registers[AArch64]"                                     "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch64]"                 "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch64]"                           "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]"                        "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch64]"                  "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]"                       "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]"                           "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]"       "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch64]"                                  "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch64]"                             "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch64]"                     "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
separator
menuitem "[:chip]ID Registers[AArch32]"                                     "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch32]"                 "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch32]"                           "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch32]"                        "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch32]"                  "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch32]"                       "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]"                           "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]"       "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch32]"                                  "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch32]"                             "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch32]"                     "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
separator
menuitem "[:chip]Interrupt Controller (GIC-400)"                            "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-400)"""
)
separator
menuitem "CCU;Cache Coherency Unit"                                     "per , ""CCU (Cache Coherency Unit)"""
; menuitem "SMMU;System Memory Management Unit"                                       "per , ""SMMU (System Memory Management Unit)"""
popup "SDRAML3INT;SDRAM L3 Interconnect"
(
menuitem "DDR_T_MAIN_PROBE"                                         "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_T_MAIN_PROBE"""
menuitem "DDR_SCHEDULER_DDR_T_MAIN_SCHEDULER"                       "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_DDR_T_MAIN_SCHEDULER"""
menuitem "IOHMC_CTRL_MMR_TOP_INST"                                  "per , ""SDRAML3INT (SDRAM L3 Interconnect),IOHMC_CTRL_MMR_TOP_INST"""
menuitem "HMC_ADP_CSR_OCP_SLV"                                      "per , ""SDRAML3INT (SDRAM L3 Interconnect),HMC_ADP_CSR_OCP_SLV"""
menuitem "FIREWALL_DDR_SCHEDULER_MPFE_SCR"                          "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_DDR_SCHEDULER_MPFE_SCR"""
menuitem "FIREWALL_MPU_DDR_SCR"                                     "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_MPU_DDR_SCR"""
menuitem "FIREWALL_DDR_FPGA2SDRAM_INST_0_SCR"                       "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_DDR_FPGA2SDRAM_INST_0_SCR"""
menuitem "FIREWALL_DDR_FPGA2SDRAM_INST_1_DDR_SCR"                   "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_DDR_FPGA2SDRAM_INST_1_DDR_SCR"""
menuitem "FIREWALL_DDR_FPGA2SDRAM_INST_2_SCR"                       "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_DDR_FPGA2SDRAM_INST_2_SCR"""
menuitem "DDR_SCHEDULER_CS_OBS_AT_MAIN_ATBENDPOINT"                 "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_CS_OBS_AT_MAIN_ATBENDPOINT"""
menuitem "DDR_SCHEDULER_CCU_MEM0_I_MAIN_QOSGENERATOR"               "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_CCU_MEM0_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR"     "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM0_AXI132_I_MAIN_QOSGENERATOR"     "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM0_AXI132_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR"      "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR"     "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM1_AXI132_I_MAIN_QOSGENERATOR"     "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM1_AXI132_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR"      "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR"     "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM2_AXI132_I_MAIN_QOSGENERATOR"     "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM2_AXI132_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR"      "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR"""
menuitem "DDR_SCHEDULER_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER"    "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER"""
)
menuitem "FPGA_BRIDGE_SOC2FPGA;FPGA Bridge SOC 2 FPGA"                  "per , ""FPGA_BRIDGE_SOC2FPGA (FPGA Bridge SOC 2 FPGA)"""
menuitem "FPGA_BRIDGE_SOC2FPGA_DEF;FPGA Bridge SOC 2 FPGA Default"      "per , ""FPGA_BRIDGE_SOC2FPGA_DEF (FPGA Bridge SOC 2 FPGA Default)"""
menuitem "FPGA_BRIDGE_LWSOC2FPGA;FPGA Bridge LWSOC 2 FPGA"              "per , ""FPGA_BRIDGE_LWSOC2FPGA (FPGA Bridge LWSOC 2 FPGA)"""
menuitem "DMA;Direct Memory Access"                                     "per , ""DMA (Direct Memory Access)"""
menuitem "OC_RAM;OnChip RAM"                                            "per , ""OC_RAM (OnChip RAM)"""
popup "ECC;ECC Address Block Group"
(
menuitem "EMAC0 RX"                                                 "per , ""ECC (ECC Address Block Group),EMAC0 RX"""
menuitem "EMAC0 TX"                                                 "per , ""ECC (ECC Address Block Group),EMAC0 TX"""
menuitem "EMAC1 RX"                                                 "per , ""ECC (ECC Address Block Group),EMAC1 RX"""
menuitem "EMAC1 TX"                                                 "per , ""ECC (ECC Address Block Group),EMAC1 TX"""
menuitem "EMAC2 RX"                                                 "per , ""ECC (ECC Address Block Group),EMAC2 RX"""
menuitem "EMAC2 TX"                                                 "per , ""ECC (ECC Address Block Group),EMAC2 TX"""
menuitem "USB0"                                                     "per , ""ECC (ECC Address Block Group),USB0"""
menuitem "USB1"                                                     "per , ""ECC (ECC Address Block Group),USB1"""
menuitem "NANDe"                                                    "per , ""ECC (ECC Address Block Group),NANDe"""
menuitem "NANDr"                                                    "per , ""ECC (ECC Address Block Group),NANDr"""
menuitem "NANDw"                                                    "per , ""ECC (ECC Address Block Group),NANDw"""
menuitem "SDMMC"                                                    "per , ""ECC (ECC Address Block Group),SDMMC"""
menuitem "DMAC"                                                     "per , ""ECC (ECC Address Block Group),DMAC"""
menuitem "OnChip RAM"                                               "per , ""ECC (ECC Address Block Group),OnChip RAM"""
)
popup "CLK_MGR;Clock Manager"
(
menuitem "CLK_MGR_CTRL;Control Status"                              "per , ""CLK_MGR (Clock Manager),CLK_MGR_CTRL (Control Status)"""
menuitem "MAINPLL_GRP;Control Status"                               "per , ""CLK_MGR (Clock Manager),MAINPLL_GRP (Control Status)"""
menuitem "PERIPHPLL_GRP;Settings for the Peripheral PLL"            "per , ""CLK_MGR (Clock Manager),PERIPHPLL_GRP (Settings for the Peripheral PLL)"""
)
popup "SDM;SDM Address Block Group"
(
menuitem "SDM SDMMC"                                                "per , ""SDM (SDM Address Block Group),SDM SDMMC"""
menuitem "SDM QSPI"                                                 "per , ""SDM (SDM Address Block Group),SDM QSPI"""
)
menuitem "RESET_MGR;Reset Manager"                                      "per , ""RESET_MGR (Reset Manager)"""
menuitem "SYSTEM_MGR;System Manager"                                    "per , ""SYSTEM_MGR (System Manager)"""
menuitem "DEDICATED_PINMUX;HPS Pinmux CSR"                              "per , ""DEDICATED_PINMUX (HPS Pinmux CSR)"""
popup "NAND"
(
menuitem "NAND_CONFIG;NAND Configuration Registers"                  "per , ""NAND,NAND_CONFIG (NAND Configuration Registers)"""
menuitem "NAND_PARAM;NAND Parameters Registers"                     "per , ""NAND,NAND_PARAM (NAND Parameters Registers)"""
menuitem "NAND_STATUS;NAND Status Registers"                        "per , ""NAND,NAND_STATUS (NAND Status Registers)"""
menuitem "NAND_ECC;NAND ECC Registers"                              "per , ""NAND,NAND_ECC (NAND ECC Registers)"""
menuitem "NAMD_DMA;NAND DMA Registers"                              "per , ""NAND,NAMD_DMA (NAND DMA Registers)"""
menuitem "NAND_DATA;NAND DATA Registers"                            "per , ""NAND,NAND_DATA (NAND DATA Registers)"""
)
menuitem "SDMMC;SD/MMC Controller"                                      "per , ""SDMMC (SD/MMC Controller)"""
popup "EMAC;Ethernet Media Access Controller"
(
menuitem "EMAC0"                                                    "per , ""EMAC (Ethernet Media Access Controller),EMAC0"""
menuitem "EMAC1"                                                    "per , ""EMAC (Ethernet Media Access Controller),EMAC1"""
menuitem "EMAC2"                                                    "per , ""EMAC (Ethernet Media Access Controller),EMAC2"""
)
popup "USB;Universal Serial Bus"
(
menuitem "USBOTG 0"                                                 "per , ""USB (Universal Serial Bus),USBOTG 0"""
menuitem "USBOTG 1"                                                 "per , ""USB (Universal Serial Bus),USBOTG 1"""
)
popup "SPI;Serial Peripheral Interface"
(
popup "SPI Slave"
(
menuitem "SPIS_0"                                               "per , ""SPI (Serial Peripheral Interface),SPI Slave,SPIS_0"""
menuitem "SPIS_1"                                               "per , ""SPI (Serial Peripheral Interface),SPI Slave,SPIS_1"""
)
popup "SPI Master"
(
menuitem "SPIM_0"                                               "per , ""SPI (Serial Peripheral Interface),SPI Master,SPIM_0"""
menuitem "SPIM_1"                                               "per , ""SPI (Serial Peripheral Interface),SPI Master,SPIM_1"""
)
)
popup "I2C;Inter-Integrated Circuit"
(
menuitem "I2C_0"                                                    "per , ""I2C (Inter-Integrated Circuit),I2C_0"""
menuitem "I2C_1"                                                    "per , ""I2C (Inter-Integrated Circuit),I2C_1"""
)
popup "I2C_EMAC;Inter-Integrated Circuit EMAC"
(
menuitem "I2C_EMAC_0"                                               "per , ""I2C_EMAC (Inter-Integrated Circuit EMAC),I2C_EMAC_0"""
menuitem "I2C_EMAC_1"                                               "per , ""I2C_EMAC (Inter-Integrated Circuit EMAC),I2C_EMAC_1"""
menuitem "I2C_EMAC_2"                                               "per , ""I2C_EMAC (Inter-Integrated Circuit EMAC),I2C_EMAC_2"""
)
menuitem "UART;Universal Asynchronous Receiver-Transmitter"             "per , ""UART (Universal Asynchronous Receiver-Transmitter)"""
popup "GPIO;General-Purpose I/O Interface"
(
menuitem "GPIO 0"                                                   "per , ""GPIO (General-Purpose I/O Interface),GPIO 0"""
menuitem "GPIO 1"                                                   "per , ""GPIO (General-Purpose I/O Interface),GPIO 1"""
)
popup "TIMER;Timer System"
(
menuitem "TIMER 0"                                                  "per , ""TIMER (Timer System),TIMER 0"""
menuitem "TIMER 1"                                                  "per , ""TIMER (Timer System),TIMER 1"""
)
popup "TIMER_SP;Timer SP"
(
menuitem "TIMER_SP0"                                                "per , ""TIMER_SP (Timer SP),TIMER_SP0"""
menuitem "TIMER_SP1"                                                "per , ""TIMER_SP (Timer SP),TIMER_SP1"""
)
popup "WDT;Watchdog Timer"
(
menuitem "WDT 0"                                                    "per , ""WDT (Watchdog Timer),WDT 0"""
menuitem "WDT 1"                                                    "per , ""WDT (Watchdog Timer),WDT 1"""
menuitem "WDT 2"                                                    "per , ""WDT (Watchdog Timer),WDT 2"""
menuitem "WDT 3"                                                    "per , ""WDT (Watchdog Timer),WDT 3"""
)
popup "L3IC;L3interconnect"
(
menuitem "Per-Master Security"                                      "per , ""L3IC (L3interconnect),Per-Master Security"""
menuitem "CoreSight Observer Main ATB Endpoint"                     "per , ""L3IC (L3interconnect),CoreSight Observer Main ATB Endpoint"""
menuitem "CoreSight Observer Main Error Logger 0"                   "per , ""L3IC (L3interconnect),CoreSight Observer Main Error Logger 0"""
menuitem "CCU Probe"                                                "per , ""L3IC (L3interconnect),CCU Probe"""
menuitem "EMAC Probe"                                               "per , ""L3IC (L3interconnect),EMAC Probe"""
menuitem "SOC2FPGA Probe"                                           "per , ""L3IC (L3interconnect),SOC2FPGA Probe"""
menuitem "EMAC Probe Transaction Statistics Profiler"               "per , ""L3IC (L3interconnect),EMAC Probe Transaction Statistics Profiler"""
menuitem "CCU IOS QoS Generator"                                    "per , ""L3IC (L3interconnect),CCU IOS QoS Generator"""
menuitem "DMA TBU QoS Generator"                                    "per , ""L3IC (L3interconnect),DMA TBU QoS Generator"""
menuitem "EMAC TBU QoS Generator"                                   "per , ""L3IC (L3interconnect),EMAC TBU QoS Generator"""
menuitem "IO TBU QoS Generator"                                     "per , ""L3IC (L3interconnect),IO TBU QoS Generator"""
menuitem "SDM TBU QoS Generator"                                    "per , ""L3IC (L3interconnect),SDM TBU QoS Generator"""
menuitem "EMAC TBU Transaction Statistics Filter"                   "per , ""L3IC (L3interconnect),EMAC TBU Transaction Statistics Filter"""
menuitem "Privilege"                                                "per , ""L3IC (L3interconnect),Privilege"""
menuitem "L4 Link Responder Rate Adapter"                           "per , ""L3IC (L3interconnect),L4 Link Responder Rate Adapter"""
)
menuitem "NOC_CACHE_CLEAN;NOC Cache Clean"                              "per , ""NOC_CACHE_CLEAN (NOC Cache Clean)"""
menuitem "MBOX;Mailbox Registers"                                       "per , ""MBOX (Mailbox Registers)"""
)
)