; -------------------------------------------------------------------------------- ; @Title: SSE-300 (AN552) Specific Menu ; @Props: Released ; @Author: KRZ ; @Changelog: 2022-08-16 KRZ ; @Manufacturer: ARM - ARM Ltd. ; @Core: Cortex-M55 ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: mensse300an552.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-M55)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M55),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M55),Memory Protection Unit""" menuitem "[:chip]SAU;Security Attribution Unit" "per , ""Core Registers (Cortex-M55),Security Attribution Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M55),Nested Vectored Interrupt Controller""" menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M55),Floating-point Unit (FPU)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M55),Debug,Core Debug""" menuitem "[:chip]BPU;BreakPoint Unit" "per , ""Core Registers (Cortex-M55),Debug,BreakPoint Unit (BPU)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M55),Debug,Data Watchpoint and Trace Unit (DWT)""" menuitem "[:chip]PMU;Performance Monitoring Unit Extension" "per , ""Core Registers (Cortex-M55),Debug,Performance Monitoring Unit Extension (PMU)""" ) ) separator menuitem "AUDIOI2S" "per , ""AUDIOI2S""" menuitem "ETHERNET" "per , ""ETHERNET""" menuitem "FPGAIO;FPGA System Control I/O" "per , ""FPGAIO (FPGA System Control I/O)""" menuitem "FPGAIO_SECURE;FPGA System Control I/O (Secure)" "per , ""FPGAIO_SECURE (FPGA System Control I/O (Secure))""" popup "GPIO;General Purpose I/O Ports And Peripheral I/O Lines" ( menuitem "GPIO0" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO0""" menuitem "GPIO1" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO1""" menuitem "GPIO2" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO2""" menuitem "GPIO3" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIO3""" ) popup "GPIO_SECURE;General Purpose I/O Ports And Peripheral I/O Lines(Secure)" ( menuitem "GPIO0_SECURE" "per , ""GPIO_SECURE (General Purpose I/O Ports And Peripheral I/O Lines (Secure)),GPIO0_SECURE""" menuitem "GPIO1_SECURE" "per , ""GPIO_SECURE (General Purpose I/O Ports And Peripheral I/O Lines (Secure)),GPIO1_SECURE""" menuitem "GPIO2_SECURE" "per , ""GPIO_SECURE (General Purpose I/O Ports And Peripheral I/O Lines (Secure)),GPIO2_SECURE""" menuitem "GPIO3_SECURE" "per , ""GPIO_SECURE (General Purpose I/O Ports And Peripheral I/O Lines (Secure)),GPIO3_SECURE""" ) popup "I2C;Inter-Integrated Circuit" ( menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0""" menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1""" ) popup "I2C_SECURE;Inter-Integrated Circuit (Secure)" ( menuitem "I2C0_SECURE" "per , ""I2C_SECURE (Inter-Integrated Circuit (Secure)),I2C0_SECURE""" menuitem "I2C1_SECURE" "per , ""I2C_SECURE (Inter-Integrated Circuit (Secure)),I2C1_SECURE""" ) popup "ISRAM_MPC;ISRAM Memory Protection Controller" ( menuitem "ISRAM0MPC" "per , ""ISRAM_MPC (ISRAM Memory Protection Controller),ISRAM0MPC""" menuitem "ISRAM1MPC" "per , ""ISRAM_MPC (ISRAM Memory Protection Controller),ISRAM1MPC""" ) menuitem "NSACRB;Non-secure Access Configuration Register Block" "per , ""NSACRB (Non-secure Access Configuration Register Block)""" menuitem "SACRB;Secure Access Configuration Register Block" "per , ""SACRB (Secure Access Configuration Register Block)""" menuitem "SAU;Security Attribution Unit" "per , ""SAU (Security Attribution Unit)""" menuitem "SCC;Serial Communication Controller" "per , ""SCC (Serial Communication Controller)""" menuitem "SCC_SECURE;Serial Communication Controller (Secure)" "per , ""SCC_SECURE (Serial Communication Controller (Secure))""" popup "SPI;SPI" ( menuitem "SSP0" "per , ""SPI (SPI),SSP0""" menuitem "SSP1" "per , ""SPI (SPI),SSP1""" menuitem "SSP2" "per , ""SPI (SPI),SSP2""" ) popup "SPI_SECURE;SPI (Secure)" ( menuitem "SSP0_SECURE" "per , ""SPI_SECURE (SPI (Secure)),SSP0_SECURE""" menuitem "SSP1_SECURE" "per , ""SPI_SECURE (SPI (Secure)),SSP1_SECURE""" menuitem "SSP2_SECURE" "per , ""SPI_SECURE (SPI (Secure)),SSP2_SECURE""" ) menuitem "SYSCOUNTER_CNTRL;System Counter Control" "per , ""SYSCOUNTER_CNTRL (System Counter Control)""" menuitem "SYSCOUNTER_READ;System Counter Read" "per , ""SYSCOUNTER_READ (System Counter Read)""" menuitem "SYSCOUNTER_READ_SECURE;System Counter Read (Secure)" "per , ""SYSCOUNTER_READ_SECURE (System Counter Read (Secure))""" menuitem "SYSCONTROL;System Control" "per , ""SYSCTRL (System Control)""" menuitem "SYSINFO;System Information" "per , ""SYSINFO (System Information)""" menuitem "SYSINFO_SECURE;System Information (Secure)" "per , ""SYSINFO_SECURE (System Information (Secure))""" popup "TIMER;Timer/Counter" ( menuitem "SLOWCLK" "per , ""TIMER (Timer/Counter),SLOWCLK""" menuitem "TIMER0" "per , ""TIMER (Timer/Counter),TIMER0""" menuitem "TIMER1" "per , ""TIMER (Timer/Counter),TIMER1""" menuitem "TIMER2" "per , ""TIMER (Timer/Counter),TIMER2""" menuitem "TIMER3" "per , ""TIMER (Timer/Counter),TIMER3""" ) popup "TIMER_SECURE;Timer/Counter (Secure)" ( menuitem "SLOWCLK_SECURE" "per , ""TIMER_SECURE (Timer/Counter (Secure)),SLOWCLK_SECURE""" menuitem "TIMER0_SECURE" "per , ""TIMER_SECURE (Timer/Counter (Secure)),TIMER0_SECURE""" menuitem "TIMER1_SECURE" "per , ""TIMER_SECURE (Timer/Counter (Secure)),TIMER1_SECURE""" menuitem "TIMER2_SECURE" "per , ""TIMER_SECURE (Timer/Counter (Secure)),TIMER2_SECURE""" menuitem "TIMER3_SECURE" "per , ""TIMER_SECURE (Timer/Counter (Secure)),TIMER3_SECURE""" ) popup "UART;Universal Asynchronous Receiver/Transmitter" ( menuitem "UART0" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART0""" menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1""" menuitem "UART2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART2""" menuitem "UART3" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART3""" menuitem "UART4" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART4""" menuitem "UART5" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART5""" ) popup "UART_SECURE;Universal Asynchronous Receiver/Transmitter (Secure)" ( menuitem "UART0_SECURE" "per , ""UART_SECURE (Universal Asynchronous Receiver/Transmitter (Secure)),UART0_SECURE""" menuitem "UART1_SECURE" "per , ""UART_SECURE (Universal Asynchronous Receiver/Transmitter (Secure)),UART1_SECURE""" menuitem "UART2_SECURE" "per , ""UART_SECURE (Universal Asynchronous Receiver/Transmitter (Secure)),UART2_SECURE""" menuitem "UART3_SECURE" "per , ""UART_SECURE (Universal Asynchronous Receiver/Transmitter (Secure)),UART3_SECURE""" menuitem "UART4_SECURE" "per , ""UART_SECURE (Universal Asynchronous Receiver/Transmitter (Secure)),UART4_SECURE""" menuitem "UART5_SECURE" "per , ""UART_SECURE (Universal Asynchronous Receiver/Transmitter (Secure)),UART5_SECURE""" ) menuitem "USB;Universal Serial Bus" "per , ""USB (Universal Serial Bus)""" menuitem "WATCHDOG;Watchdog Timer" "per , ""WATCHDOG (Watchdog Timer)""" popup "WATCHDOG_SECURE;Watchdog Timer (Secure)" ( menuitem "SLOWCLKWATCHDOG" "per , ""WATCHDOG_SECURE (Watchdog Timer (Secure)),SLOWCLKWATCHDOG""" menuitem "WATCHDOG_SECURE" "per , ""WATCHDOG_SECURE (Watchdog Timer (Secure)),WATCHDOG_SECURE""" ) ) )