; --------------------------------------------------------------------------------
; @Title: S3C2416 Specific Menu
; @Props: Released
; @Author: MAV
; @Changelog: 2010-01-07 MAV
; @Manufacturer: SAMSUNG - Samsung Semiconductor
; @Core: ARM926EJ
; @Chip: S3C2416
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: mens3c2416.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
menuitem "[:chip]ID Registers"                      "per , ""ARM Core Registers,ID Registers"""
menuitem "[:chip]MMU Control and Configuration"     "per , ""ARM Core Registers,MMU Control and Configuration"""
menuitem "[:chip]Cache Control and Configuration"   "per , ""ARM Core Registers,Cache Control and Configuration"""
menuitem "[:chip]TCM Control and Configuration"     "per , ""ARM Core Registers,TCM Control and Configuration"""
menuitem "[:chip]Test and Debug"                    "per , ""ARM Core Registers,Test and Debug"""
menuitem "[:chip]ICEbreaker"                        "per , ""ARM Core Registers,ICEbreaker"""
separator
menuitem "SYSCON"                                   "per , ""SYSCON (System Controller)"""
menuitem "MATRIX & EBI"                             "per , ""MATRIX & EBI"""
popup "SMC"
(
menuitem "Bank 0"                               "per , ""SMC (Static Memory Controller),Bank 0"""
menuitem "Bank 1"                               "per , ""SMC (Static Memory Controller),Bank 1"""
menuitem "Bank 2"                               "per , ""SMC (Static Memory Controller),Bank 2"""
menuitem "Bank 3"                               "per , ""SMC (Static Memory Controller),Bank 3"""
menuitem "Bank 4"                               "per , ""SMC (Static Memory Controller),Bank 4"""
menuitem "Bank 5"                               "per , ""SMC (Static Memory Controller),Bank 5"""
menuitem "Control And Status"                   "per , ""SMC (Static Memory Controller),Control And Status"""
)
menuitem "DRAMC"                                    "per , ""DRAMC (Mobile DRAM Controller)"""
menuitem "NAND"                                     "per , ""NAND Flash Controller"""
popup "DMA"
(
menuitem "Channel 0"                            "per , ""DMA Controller,Channel 0"""
menuitem "Channel 1"                            "per , ""DMA Controller,Channel 1"""
menuitem "Channel 2"                            "per , ""DMA Controller,Channel 2"""
menuitem "Channel 3"                            "per , ""DMA Controller,Channel 3"""
menuitem "Channel 4"                            "per , ""DMA Controller,Channel 4"""
menuitem "Channel 5"                            "per , ""DMA Controller,Channel 5"""
)
menuitem "INTC"                                     "per , ""INTC (Interrupt Controller)"""
popup "I/O Ports"
(
menuitem "Port A"                               "per , ""I/O Ports,Port A"""
menuitem "Port B"                               "per , ""I/O Ports,Port B"""
menuitem "Port C"                               "per , ""I/O Ports,Port C"""
menuitem "Port D"                               "per , ""I/O Ports,Port D"""
menuitem "Port E"                               "per , ""I/O Ports,Port E"""
menuitem "Port F"                               "per , ""I/O Ports,Port F"""
menuitem "Port G"                               "per , ""I/O Ports,Port G"""
menuitem "Port H"                               "per , ""I/O Ports,Port H"""
menuitem "Port K"                               "per , ""I/O Ports,Port K"""
menuitem "Port L"                               "per , ""I/O Ports,Port L"""
menuitem "Port M"                               "per , ""I/O Ports,Port M"""
menuitem "Miscellaneous Registers"              "per , ""I/O Ports,Miscellaneous Registers"""
)
menuitem "WDT"                                      "per , ""WDT (Watchdog Timer)"""
menuitem "PWM"                                      "per , ""PWM (Pulse Width Modulation Timer)"""
menuitem "RTC"                                      "per , ""RTC (Real Time Clock)"""
popup "UART"
(
menuitem "UART 0"                               "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART 0"""
menuitem "UART 1"                               "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART 1"""
menuitem "UART 2"                               "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART 2"""
menuitem "UART 3"                               "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART 3"""
)
popup "USB"
(
menuitem "USBH"                                 "per , ""USB (Universal Serial Bus),USB Host Controller"""
menuitem "USBD"                                 "per , ""USB (Universal Serial Bus),USB Device Controller"""
)
menuitem "IIC"                                      "per , ""IIC (Inter-Intergrated Circuit)"""
menuitem "2D"                                       "per , ""2D (2D Graphics Accelerator)"""
menuitem "HSSPI"                                    "per , ""HSSPI (High Speed Serial Peripheral Interface)"""
popup "HSMMC"
(
menuitem "HSMMC 0"                              "per , ""HSMMC (High-speed MMC),HSMMC 0"""
menuitem "HSMMC 1"                              "per , ""HSMMC (High-speed MMC),HSMMC 1"""
)
menuitem "LCD"                                      "per , ""LCD Controller"""
menuitem "ADC"                                      "per , ""ADC & Touch Screen Interface"""
menuitem "IIS"                                      "per , ""IIS Multi Audio Interface"""
menuitem "AC97"                                     "per , ""AC97 Controller"""
menuitem "PCM"                                      "per , ""PCM Audio Interface"""
)
)