; --------------------------------------------------------------------------------
; @Title: RCARH1 Specific Menu
; @Props: Released
; @Author: CNA, STR
; @Changelog: 2012-08-07
; @Manufacturer: RENESAS - Renesas Technology, Corp.
; @Core: Cortex-A9
; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menrcarh1.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-A9MPCore)"
(
menuitem "[:chip]ID Registers"                        "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
menuitem "[:chip]System Control and Configuration"    "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
menuitem "[:chip]Memory Management Unit"              "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
menuitem "[:chip]Cache Control and Configuration"     "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor"          "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
menuitem "[:chip]Preload Engine"                      "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
menuitem "[:chip]NEON"                                "per , ""Core Registers (Cortex-A9MPCore),NEON"""
separator
menuitem "[:chip]Debug Registers"                     "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"                "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"        "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
separator
menuitem "[:chip]Snoop Control Unit (SCU)"            "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
menuitem "[:chip]Timer and Watchdog Blocks"           "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
menuitem "[:chip]Interrupt Controller (PL-390)"       "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (PL-390)"""
)
separator
menuitem "GPIO"                 " per , ""GPIO (General-Purpose Input/Output)"""
menuitem "CPG"                  " per , ""CPG (Clock Pulse Generator)"""
menuitem "RESET/WDT"            " per , ""RESET/WDT (Resets and Watchdog Timer)"""
menuitem "HPBREG"               " per , ""HPBREG"""
menuitem "INTC/INTC2"           " per , ""INTC/INTC2 (Interrupt Controllers)"""
menuitem "LBSC"                 " per , ""LBSC within Bus Bridge"""
menuitem "DBSC3"                " per , ""DBSC3 (DDR3-SDRAM Interface)"""
menuitem "SuperHyway-DMAC"      " per , ""SuperHyway-DMAC (Direct Memory Access Controller)"""
menuitem "LBSC-DMAC/HPB-DMAC"   " per , ""LBSC-DMAC/HPB-DMAC (DMAC within Bus Bridge)"""
menuitem "R-GP2D"               " per , ""R-GP2D (2D graphics rendering module)"""
menuitem "SGX"                  " per , ""SGX (3D Graphics Engine)"""
menuitem "DU"                   " per , ""DU (Display Unit)"""
menuitem "VIN"                  " per , ""VIN (Video Input Module)"""
menuitem "IMR-X"                " per , ""IMR-X (Distortion Correction Engine)"""
menuitem "IMR-LSX"              " per , ""IMR-LSX (Distortion Correction Engine)"""
menuitem "SRU"                  " per , ""SRU (Sound Routing Unit)"""
menuitem "SSI"                  " per , ""SSI (Serial Sound Interface)"""
menuitem "ADG"                  " per , ""ADG (Audio Clock Generator)"""
menuitem "SPU2F"                " per , ""SPU2F (Sound Processing Unit 2)"""
menuitem "Ether"                " per , ""Ether (Ethernet MAC Controller)"""
menuitem "CAN"                  " per , ""CAN (Controller Area Network)"""
menuitem "MIMLCP"               " per , ""MIMLCP (MOST Interface Module Light for Content Protection)"""
menuitem "MLP"                  " per , ""MLP (MediaLB+)"""
menuitem "SLM"                  " per , ""SLM (SRU Local Memory)"""
menuitem "IEB"                  " per , ""IEB (IE Bus)"""
menuitem "SCIF"                 " per , ""SCIF (Serial Communication Interface with FIFO)"""
menuitem "HSCIF"                " per , ""HSCIF (High Speed Serial Communication Interface with FIFO)"""
menuitem "I2C Bus Interface"    " per , ""I2C Bus Interface"""
menuitem "HSPI"                 " per , ""HSPI (Serial Peripheral Interface)"""
menuitem "MMC"                  " per , ""MMC (Multi Media Card interface)"""
menuitem "SATA"                 " per , ""SATA (Serial-ATA)"""
menuitem "USB"                  " per , ""USB (Universal Serial Bus)"""
menuitem "USB 2.0"              " per , ""USB 2.0 (Universal Serial Bus 2.0)"""
menuitem "USB 1.1"              " per , ""USB 1.1 (Universal Serial Bus 1.1)"""
menuitem "TMU"                  " per , ""TMU (Timer Unit)"""
menuitem "PWM Timer"            " per , ""PWM Timer"""
menuitem "GPS"                  " per , ""GPS"""
menuitem "Gyro-ADC IF"          " per , ""Gyro-ADC IF"""
menuitem "Speed-Pulse IF"       " per , ""Speed-Pulse IF"""
menuitem "IR"                   " per , ""IR (IR Receiver)"""
menuitem "THS/TSC"              " per , ""HS/TSC (Thermal Sensor)"""
menuitem "SYSC"                 " per , ""SYSC (System Controller)"""
menuitem "Coresight ICEReg"     " per , ""Coresight ICEReg"""
)
)