; -------------------------------------------------------------------------------- ; @Title: IMX50 Specific Menu ; @Props: Released ; @Author: TPP, ZAK ; @Changelog: 2013-03-23 ; @Manufacturer: NXP ; @Core: Cortex-A8 ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menmcimx50.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-A8)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A8),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A8),System Control and Configuration""" menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A8),Memory Management Unit""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A8),Cache Control and Configuration""" menuitem "[:chip]L2 Cache Control and Configuration" "per , ""Core Registers (Cortex-A8),L2 Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A8),System Performance Monitor""" menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A8),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A8),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A8),Watchpoint Control Registers""" ) separator menuitem "CCM" "per , ""CCM (Clock Controller Module)""" menuitem "CCM Analog" "per , ""CCM Analog""" menuitem "ARM CORTEX Platform Control" "per , ""ARM CORTEX Platform Control""" menuitem "MAX" "per , ""MAX (Multi-Layer AHB Crossbar Switch)""" menuitem "APBH-Bridge-DMA" "per , ""APBH-Bridge-DMA (AHB-to-APBH Bridge with DMA)""" menuitem "AUDMUX" "per , ""AUDMUX (Digital Audio Multiplexer)""" menuitem "BCH" "per , ""BCH (32-Bit Correcting ECC Accelerator)""" menuitem "CSPI" "per , ""CSPI (Configurable Serial Peripheral Interface)""" menuitem "DCP" "per , ""DCP (Data Co-Processor)""" menuitem "DIGCTL" "per , ""DIGCTL (Digital Control)""" menuitem "DPLLC " "per , ""DPLLC (DPLL Controller)""" menuitem "DRAM MC" "per , ""DRAM MC (DRAM Memory Controller)""" menuitem "DVFSC" "per , ""DVFSC (Dynamic Voltage Frequency Scaling)""" menuitem "eCSPI" "per , ""eCSPI (Enhanced Configurable Serial Peripheral Interface)""" menuitem "EIM" "per , ""EIM (External Interface Module)""" menuitem "EPDC" "per , ""EPDC (Electrophoretic Display Controller)""" menuitem "EPIT" "per , ""EPIT (Enhanced Periodic Interrupt Timer)""" menuitem "eSDHC" "per , ""eSDHC (Enhanced Secure Digital Host Controller)""" menuitem "FEC" "per , ""FEC (Fast Ethernet Controller)""" menuitem "GPIO" "per , ""GPIO (General-Purpose Input/Output)""" menuitem "GPMI" "per , ""GPMI (General-Purpose Media Interface)""" menuitem "GPT" "per , ""GPT (General Purpose Timer)""" menuitem "I2C" "per , ""I2C (Inter IC)""" menuitem "IOMUXC" "per , ""IOMUXC (IOMUX Controller)""" menuitem "KPP" "per , ""KPP (Keypad Port)""" menuitem "eLCDIF" "per , ""eLCDIF (Enhanced LCD Interface)""" menuitem "OCOTP" "per , ""OCOTP (On-Chip OTP Controller)""" menuitem "OWIRE" "per , ""OWIRE (1-Wire Block)""" menuitem "PERFMON" "per , ""PERFMON (Performance Monitor)""" menuitem "PWM" "per , ""PWM (Pulse Width Modulation)""" menuitem "ePXP" "per , ""ePXP (Enhanced Pixel Pipeline)""" menuitem "QOSC" "per , ""QOSC (Quality Of Service Controller)""" menuitem "ROMCP" "per , ""ROMCP (Read Only Memory Controller Patch)""" menuitem "SDMA" "per , ""SDMA (Smart Direct Memory Access Controller)""" menuitem "SPBA" "per , ""SPBA (Shared Peripheral Bus Arbiter)""" menuitem "SRC" "per , ""SRC (System Reset Controller)""" menuitem "SRPGC" "per , ""SRPGC (State Retention Power Gating Controller)""" menuitem "SRTC" "per , ""SRTC (Secure Real Time Clock)""" menuitem "SSI" "per , ""SSI (Synchronous Serial Interface)""" menuitem "TEMPSENSOR" "per , ""TEMPSENSOR (Temperature Sensor)""" menuitem "TZIC" "per , ""TZIC (Interrupt Controller)""" menuitem "UART" "per , ""UART (Universal Asynchronous Receiver/Transmitter)""" menuitem "USBOH1" "per , ""USBOH1 (Universal Serial Bus Controller OTG HOST1)""" menuitem "WDOG" "per , ""WDOG (Watchdog Timer)""" ) )