; --------------------------------------------------------------------------------
; @Title: Apollo 2 Specific Menu
; @Props: Released
; @Author: STR, KWI, KRZ, JDU
; @Changelog: 2017-12-13 STR
;             2020-07-24 KWI
;             2022-02-15 KRZ
;             2023-02-23 JDU
; @Manufacturer: AMBIQ - Ambiq Micro, Inc.
; @Core: Cortex-M4F
; @Chip: AMAPH1KK, AMA2B1KK
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menapollo2.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit"                       "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
if cpuis("AMAPH1KK")
(
menuitem "PWRCTRL;PWR Controller Register Bank"         "per , ""PWRCTRL (PWR Controller Register Bank)"""
menuitem "ITM;Instrumentation Trace Macrocell"          "per , ""ITM (Instrumentation Trace Macrocell)"""
menuitem "MCUCTRL;MCU Miscellaneous Control Logic"      "per , ""MCUCTRL (MCU Miscellaneous Control Logic)"""
menuitem "CACHECTRL;Flash Cache Controller"             "per , ""CACHECTRL (Flash Cache Controller)"""
menuitem "FLASHCTRL;Flash Memory Controller"            "per , ""FLASHCTRL (Flash Memory Controller)"""
popup "I2C Master;I2C/SPI Master"
(
menuitem "I2C0 Master"                              "per , ""I2C Master (I2C/SPI Master),I2C0 Master"""
menuitem "I2C1 Master"                              "per , ""I2C Master (I2C/SPI Master),I2C1 Master"""
menuitem "I2C2 Master"                              "per , ""I2C Master (I2C/SPI Master),I2C2 Master"""
menuitem "I2C3 Master"                              "per , ""I2C Master (I2C/SPI Master),I2C3 Master"""
menuitem "I2C4 Master"                              "per , ""I2C Master (I2C/SPI Master),I2C4 Master"""
menuitem "I2C5 Master"                              "per , ""I2C Master (I2C/SPI Master),I2C5 Master"""
)
menuitem "I2C Slave;I2C/SPI Slave"                      "per , ""I2C Slave (I2C/SPI Slave)"""
menuitem "PDM;PDM Audio"                                "per , ""PDM (PDM Audio)"""
menuitem "GPIO;General Purpose IO"                      "per , ""GPIO (General Purpose IO)"""
menuitem "CLKGEN;Clock Generator"                       "per , ""CLKGEN (Clock Generator)"""
menuitem "RTC;Real Time Clock"                          "per , ""RTC (Real Time Clock)"""
menuitem "CTIMER;Counter/Timer"                         "per , ""CTIMER (Counter/Timer)"""
menuitem "STIMER;System Timer"                          "per , ""STIMER (System Timer)"""
menuitem "WDT;Watchdog Timer"                           "per , ""WDT (Watchdog Timer)"""
menuitem "RSTGEN;MCU Reset Generator"                   "per , ""RSTGEN (MCU Reset Generator)"""
popup "UART;Serial UART"
(
menuitem "UART0"                                    "per , ""UART (Serial UART),UART0"""
menuitem "UART1"                                    "per , ""UART (Serial UART),UART1"""
)
menuitem "ADC;Analog to Digital Converter"              "per , ""ADC (Analog to Digital Converter)"""
menuitem "VCOMP;Voltage Comparator Module"              "per , ""VCOMP (Voltage Comparator Module)"""
)
else if cpuis("AMA2B1KK")
(
menuitem "ADC"              "per , ""ADC (Analog Digital Converter Control)"""
menuitem "CACHECTRL"        "per , ""CACHECTRL (Flash Cache Controller)"""
menuitem "CLKGEN"           "per , ""CLKGEN (Clock Generator)"""
menuitem "CTIMER"           "per , ""CTIMER (Counter/Timer)"""
menuitem "GPIO"             "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
popup "IOMSTR (I2C/SPI Master)"
(
menuitem "IOMSTR0"      "per , ""IOMSTR (I2C/SPI Master),IOMSTR0"""
menuitem "IOMSTR1"      "per , ""IOMSTR (I2C/SPI Master),IOMSTR1"""
menuitem "IOMSTR2"      "per , ""IOMSTR (I2C/SPI Master),IOMSTR2"""
menuitem "IOMSTR3"      "per , ""IOMSTR (I2C/SPI Master),IOMSTR3"""
menuitem "IOMSTR4"      "per , ""IOMSTR (I2C/SPI Master),IOMSTR4"""
menuitem "IOMSTR5"      "per , ""IOMSTR (I2C/SPI Master),IOMSTR5"""
)
menuitem "IOSLAVE"          "per , ""IOSLAVE (I2C/SPI Slave)"""
menuitem "MCUCTRL"          "per , ""MCUCTRL (MCU Miscellaneous Control Logic)"""
menuitem "PDM"              "per , ""PDM (Pulse Density Modulation (Digital Microphone) Interface)"""
menuitem "PWRCTRL"          "per , ""PWRCTRL (PWR Controller Register Bank)"""
menuitem "RSTGEN"           "per , ""RSTGEN (MCU Reset Generator)"""
menuitem "RTC"              "per , ""RTC (Real-time Counter)"""
popup "UART (Universal Asynchronous Receiver/Transmitter)"
(
menuitem "UART0"        "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART0"""
menuitem "UART1"        "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
)
menuitem "VCOMP"            "per , ""VCOMP (Voltage Comparator)"""
menuitem "WDT"              "per , ""WDT (Watchdog Timer Unit)"""
)
)
)