; --------------------------------------------------------------------------------
; @Title: Freescale QorIQ LS1043A RDB NAND FLASH Programming Template
; @Description:
; NAND FLASH(MT29F4G08) is connected to CS0
; The board RCW_SRC[0:8] selects : 1_0000_0110: 8-bit NAND flash, 2 KB  page,
; 64 pages/block
; The RCW_SRC field (9 bits) is spread over SW4[1-8] and SW5[1].
; This script uses SYStem.Option.HRCWOVerRide to set a custom RCW for the flash
; programming phase. This should allow access to the SoC even if the flash is
; empty/corrupted and the RCW/PBL is not valid. The RCW is a template and is not
; guaranteed to work on every board.
;
; Internal SRAM    : 0x10001000
; IFC base : 0x01530000
; IFC_SRAM : 0x7e800000
; CS#    : 0
;
; @Author: jjeong
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; @Chip: LS1043A
; @Keywords: Flash NAND
; --------------------------------------------------------------------------------
; $Id: ls1043-nand2g08-rcwovr.cmm 11733 2023-01-16 08:55:12Z bschroefel $

LOCAL &arg1
ENTRY &arg1
&arg1=STRing.UPpeR("&arg1")  // for example "PREPAREONLY"

&BASE=A:0x1530000

RESet
SYStem.RESet
SYStem.CPU LS1043A
SYStem.Option HRCWOVerRide OFF
SYStem.Option TRST OFF
SYStem.Option EnReset ON
CORE.ASSIGN 1. ; select only master core
Trace.DISable
SYStem.JtagClock CTCK 10MHz

; <temporarily override the RCW>
; temporarily override the RCW. The RCW is fetched while the boot phase and defines initial
; pinmux/serdes/qspi/nor/nand/... configurations.
; The RCW override requires to reset the SoC. Two methods are supported.
;   Method 1: EnReset OFF && HRCWOVerRide ON /PORESET - do not assert the nReset line, issue a JTAG based PORESET
;   Method 2: EnReset ON  && HRCWOVerRide ON          - assert the nReset line
; Steps - Override RCW_SRC only
;   * set EnReset & HRCWOVerRide - Method 1/2
;   * switch to SYStem.Mode Prepare
;   * write the RCW_SRC value to EDBG:0x42000040
;   * switch to SYStem.Up
; Steps - Override RCW completely
;   * set EnReset & HRCWOVerRide - Method 1/2
;   * switch to SYStem.Mode Prepare
;   * write the RCW_SRC value HARDCODED to EDBG:0x42000040
;   * write the RCW itself to EDBG:0x42000000 onwards
;   * ensure in RCW[6]/EDBG:0x42000018 the PBL_SRC is reserved e.g. 0xfb8?????
;   * switch to SYStem.Up

; The following RCW is used to connect to the device even with a empty flash.
; The pinmux is configured to map the NAND pins.
SYStem.Option EnReset OFF
SYStem.Option HRCWOVerRide ON /PORESET

SYStem.Mode.Prepare
; override RCW_SRC = Hardcoded
Data.Set EDBG:0x42000040 %Long 0x9e

; override the RCW itself - values as in uboot mainline LS1043A RDB NAND
Data.Set EDBG:0x42000000 %Long 0x08100010
Data.Set EDBG:0x42000004 %Long 0x0A000000
Data.Set EDBG:0x42000008 %Long 0x00000000
Data.Set EDBG:0x4200000c %Long 0x00000000
Data.Set EDBG:0x42000010 %Long 0x14550002
Data.Set EDBG:0x42000014 %Long 0x80004012
;Data.Set EDBG:0x42000018 %Long 0xE0106000 ; PBL=IFC, IFC=0x106
Data.Set EDBG:0x42000018 %Long 0xfb800a00 ; PBL_SRC=reserved, IFC=0xa
Data.Set EDBG:0x4200001C %Long 0xC1002000
Data.Set EDBG:0x42000020 %Long 0x00000000
Data.Set EDBG:0x42000024 %Long 0x00000000
Data.Set EDBG:0x42000028 %Long 0x00000000
Data.Set EDBG:0x4200002C %Long 0x00038800
Data.Set EDBG:0x42000030 %Long 0x00000000
Data.Set EDBG:0x42000034 %Long 0x00001100
Data.Set EDBG:0x42000038 %Long 0x00000096
Data.Set EDBG:0x4200003C %Long 0x00000001
; </temporarily override the RCW>

SYStem.Up

Register.Set M 0x5 ;EL1h

Data.Set AZD:0x1530010 %LE %Long 0x8300807E  ;Chip-select Property register n (IFC_CSPR0)
Data.Set AZD:0x15301C0 %LE %Long 0x0a07180e  ;Flash Timing register 0 for Chip Select 0
Data.Set AZD:0x15301C4 %LE %Long 0x180e3932  ;Flash Timing register 1 for Chip Select 0
Data.Set AZD:0x15301C8 %LE %Long 0x1e50e001  ;Flash Timing register 2 for Chip Select 0
Data.Set AZD:0x15301CC %LE %Long 0x0         ;Flash Timing register 3 for Chip Select 0

GOSUB READ_ID

LOCAL &pdd
&pdd=OS.PresentDemoDirectory()

Break.RESet

FLASHFILE.RESet

; FLASHFILE.CONFIG <IFC base address> <0x0> <NFC buffer RAM address> <chip select>
FLASHFILE.CONFIG   &BASE              0x0    A:0x7E800000             0x0

; FLASHFILE.TARGET <code_range>       <data_range>       <algorithm file>
FLASHFILE.TARGET 0x10001000++0x1FFF 0x10004000++0x3FFF  &pdd/flash/byte/nand2g08_lsifc.bin  /KEEP /STACKSIZE 0x200

; Read FLASH Manufacturer and Device ID
  FLASHFILE.GETID

//End of the test prepareonly
IF "&arg1"=="PREPAREONLY"
  ENDDO

//Read FLASH
  FLASHFILE.DUMP 0x0

//Erase FLASH
; FLASHFILE.ERASE 0x0--0xFFFFF /EraseBadBlocks

//Write FLASH
; FLASHFILE.LOAD  * 0x0 /WriteBadBlocks
; FLASHFILE.LOAD  * 0x0 /WriteBadBlocks /ComPare   ;verify

ENDDO


READ_ID:
(
  SCREEN.OFF

  Data.Set &BASE+0x1014 %BE %Long 0x90000000  ; FCR0 0x90
  Data.Set &BASE+0x1018 %BE %Long 0x00000000  ; FCR1

  Data.Set &BASE+0x1110 %BE %Long 0x46084000  ; FIR0
  Data.Set &BASE+0x1114 %BE %Long 0x0  ; FIR1
  Data.Set &BASE+0x1118 %BE %Long 0x0  ; FIR2

  Data.Set &BASE+0x115C %BE %Long 0x00000000   ; CS0 select
  ;Data.Set &BASE+0x115C %BE %Long 0x04000000  ; CS1 select
  Data.Set &BASE+0x1108 %BE %Long 0x00000010   ; Byte count

  Data.Set &BASE+0x116C %BE %Long 0x00000000   ; state clear

  Data.Set &BASE+0x103C %BE %Long 0x00000000   ; IFC_ROW0
  Data.Set &BASE+0x1044 %BE %Long 0x00000000   ; IFC_COL0

  Data.Set &BASE+0x1164 %BE %Long 0x80000000  ; IFC operation start

  &temp=Data.Long(A:0x7e800000)
  PRINT "1st: 0x" &temp&0xFF  " (manufacture id)"
  PRINT "2nd: 0x" (&temp>>8.)&0xFF  " (device id)"
  PRINT "3rd: 0x" (&temp>>16.)&0xFF
  PRINT "4th: 0x" (&temp>>24.)&0xFF

  SCREEN.ON

  RETURN
)