; -------------------------------------------------------------------------------- ; @Title: Manitoba with XScale-Core On Chip Peripherals ; @Props: ; @Description: Rev. 0.75 ; @Author: - ; @Changelog: ; @Manufacturer: ; @Doc: ; @Core: ; @Chip: ; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perpxa800.per 15983 2023-04-17 10:35:39Z bschroefel $ ; -------------------------------------------------------------------------------- ; On Chip Peripherals for Manitoba with XScale-Core ; Lot's of inconsistencies in EAS Rev. 0.75 ; State: preliminary ; -------------------------------------------------------------------------------- config 16. 8. width 8. ;begin include file xscale/cp15.ph ;parameters: ; -------------------------------------------------------------------------------- ; 80200, 80321, IXP2400, IXP2800, PXA210, PXA250, PXA800F ; not impl.: IXP425, IXP2850, IXC1100, Bulverde tree "CP15" ; State: ok ; -------------------------------------------------------------------------------- ; -------------------------------------------------------------------------------- ; *** Intel 80200 *** ; -------------------------------------------------------------------------------- if (d.l(c15:0x0)&0xffffe3f0)==0x69052000 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x0 4.--4. "ProdNum ,Product Number" "80200,80200" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,A-1,B-0,C-0,D-0,res,res,res,res,res,res,res,res,res,res,res" ; -------------------------------------------------------------------------------- ; *** Intel 80321 or IOP321 (Verde) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69052020||(d.l(c15:0x0)&0xffffe3f0)==0x69052030 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x0 4.--4. "ProdNum ,Product Number" "80321 (400MHz),80321 (600MHz)" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,B-0,B-1,res,res,res,res,res,res,res,res,res,res,res,res,res" ; -------------------------------------------------------------------------------- ; *** Intel 80331 or IOP331 (Dobson) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69054090 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x0 4.--4. "ProdNum ,Product Number" "80331,80331" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-1,res,res,res,B-0,res,C-0,C-1,res,res,D-0,res,res,res,res,res" ; -------------------------------------------------------------------------------- ; *** Intel 80332 or IOP332 *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69054010 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x0 4.--4. "ProdNum ,Product Number" "80332,80332" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-1/A-2,res,res,res,B-0,res,C-0,C-1,res,res,D-0,res,res,res,res,res" ; -------------------------------------------------------------------------------- ; *** Intel PXA210 (Sabinal), PXA250 (Cotulla) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100||(d.l(c15:0x0)&0xffffe3f0)==0x69052120 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x0 5.--5. "ProdNum ,Product Number" "PXA250,PXA210" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,A-1,B-0,B-1,B-2,C-0,res,res,res,res,res,res,res,res,res,res" ; -------------------------------------------------------------------------------- ; *** Intel PXA27x (Bulverde) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69054110 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x0 5.--5. "ProdNum ,Product Number" "PXA27x,PXA27x" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,A-1,B-0,B-1,C-0,res,res,C-5,res,res,res,res,res,res,res,res" ; -------------------------------------------------------------------------------- ; *** Intel IXP2400 (Sausolito), IXP2800 (Castine) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69054190||(d.l(c15:0x0)&0xffffe3f0)==0x690541a0 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 12.--15. "CoreGen ,Core Generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 4.--7. "ProdNum ,Product Number" "res,res,res,res,res,res,res,res,res,IXP2400,IXP2800,res,res,res,res,res" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" ; -------------------------------------------------------------------------------- ; *** Intel PXA800F (Manitoba) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x690540a0 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x0 5.--5. "ProdNum ,Product Number" "PXA800F,PXA800F" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A,res,res,res,res,res,res,res,res,res,res,res,res,res,res,res" ; -------------------------------------------------------------------------------- ; *** Intel IXP4xx, IXC1100 *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x690541f0 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--18. " Arch ,Architecture Version" "res,V4,V4T,V5,V5T,V5TE,res,res" textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " bitfld.long 0x0 5.--5. "ProdNum ,Product Number" "IXP4xx/IXC1100,IXP4xx/IXC1100" bitfld.long 0x0 0.--3. " ProdRev ,Product Revision" "A-0,res,res,res,res,res,res,res,res,res,res,res,res,res,res,res" ; -------------------------------------------------------------------------------- ; *** other Intel XScale V5TE *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe000)==0x69052000 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--23. " Arch ,Architecture Version" ",V4,V4T,V5,V5T,V5TE,?..." textline " " bitfld.long 0x0 13.--13. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 10.--12. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8" textline " " hexmask.long 0x0 4.--9. 1. "ProdNum ,Product Number" hexmask.long 0x0 0.--3. 1. " ProdRev ,Product Revision" ; -------------------------------------------------------------------------------- ; *** other Intel XScale V5TE *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe000)==0x69054000 group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" bitfld.long 0x0 24.--24. "Trademark ,Implementation Trademark" "Intel,Intel" bitfld.long 0x0 16.--23. " Arch ,Architecture Version" ",V4,V4T,V5,V5T,V5TE,?..." textline " " bitfld.long 0x0 12.--12. "CoreGen ,Core Generation" "XScale,XScale" bitfld.long 0x0 8.--11. " CoreRev ,Core Revision" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long 0x0 4.--7. 1. "ProdNum ,Product Number" hexmask.long 0x0 0.--3. 1. " ProdRev ,Product Revision" ; -------------------------------------------------------------------------------- ; *** any else *** ; -------------------------------------------------------------------------------- else group c15:0x0--0x0 line.long 0x0 "ID,ID Register (read only)" ; 0x41 = ARM, 0x44 = Digital, 0x69 = Intel hexmask.long 0x0 24.--31. 1. "Implementor ,Implementation Trademark" hexmask.long 0x0 20.--23. 1. " Variant ,Implementation defined variant number" textline " " hexmask.long 0x0 16.--19. 1. "Architecture ,Architecture Version Code" hexmask.long 0x0 13.--15. 1. " Primary part number ,Core Generation" textline " " hexmask.long 0x0 0.--3. 1. "Revision ,Product Revision" endif ; -------------------------------------------------------------------------------- group c15:0x100--0x100 line.long 0x0 "CTYPE,Cache Type Register (read only)" bitfld.long 0x0 25.--28. "CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f" bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes" textline " " bitfld.long 0x0 18.--20. "DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k" bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128" bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16" textline " " bitfld.long 0x0 6.--8. "ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k" bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128" bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16" group c15:0x1--0x1 line.long 0x0 "CR,Control Register" bitfld.long 0x0 13. "V ,Exception Vector Relocation" "0x00000000,0xffff0000" bitfld.long 0x0 12. " I ,Instruction Cache" "disable,enable" bitfld.long 0x0 11. " Z ,Branch Target Buffer" "disable,enable" bitfld.long 0x0 9. " R ,ROM Protection" "off,on" bitfld.long 0x0 8. " S ,System Protection" "off,on" textline " " bitfld.long 0x0 7. "B ,Endianism" "little,big" bitfld.long 0x0 2. " C ,Data Cache" "disable,enable" bitfld.long 0x0 1. " A ,Alignment Fault" "disable,enable" bitfld.long 0x0 0. " M ,Memory Management Unit" "disable,enable" group c15:0x101--0x101 line.long 0x0 "AuxCR,Auxiliary Control Register" bitfld.long 0x0 4.--5. "MD ,Mini Data Cache Attributes" "write back - read allocate,write back - read/write allocate,write through - read allocate,unpredictable" bitfld.long 0x0 1. " P ,Page Table Memory Attribute" "0,1" bitfld.long 0x0 0. " K ,Write Buffer Coalescing Disable" "enable,disable" group c15:0x2--0x2 line.long 0x0 "TTB,Translation Table Base Register" hexmask.long 0x0 14.--31. 0x4000 "TTBA ,Translation Table Base Address" group c15:0x3--0x3 line.long 0x0 "DAC,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15 ,Domain Access 15" "no access,client,reserved,manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "no access,client,reserved,manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "no access,client,reserved,manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "no access,client,reserved,manager" textline " " bitfld.long 0x0 22.--23. "D11 ,Domain Access 11" "no access,client,reserved,manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "no access,client,reserved,manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "no access,client,reserved,manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "no access,client,reserved,manager" textline " " bitfld.long 0x0 14.--15. "D7 ,Domain Access 7" "no access,client,reserved,manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "no access,client,reserved,manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "no access,client,reserved,manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "no access,client,reserved,manager" textline " " bitfld.long 0x0 6.--7. "D3 ,Domain Access 3" "no access,client,reserved,manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "no access,client,reserved,manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "no access,client,reserved,manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "no access,client,reserved,manager" group c15:0x5--0x5 line.long 0x0 "FSR,Fault Status Register" bitfld.long 0x0 10. "X ,Status Field Extension" "0,1" bitfld.long 0x0 9. " D ,Debug event" "no,yes" bitfld.long 0x0 4.--7. " Domain ,Domain for Data Abort" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " Status ,Status X=0/X=1" "reserved/IMMU Exception,alignment/reserved,reserved,alignment/reserved,reserved/lock abort,transl_sect/reserved,reserved/external,transl_page,reserved/cache parity,domain_sect/reserved,reserved,domain_page,trans_lev_1/reserved,permission_sect/reserved,trans_lev_2/reserved,permission_page" group c15:0x6--0x6 line.long 0x0 "FAR,Fault Address Registerr" group c15:0x29--0x29 line.long 0x0 "DCLR, Data Cache Lock Register" bitfld.long 0x0 0. "L ,Data Cache Lock Register" "no locking,fill with lock" group c15:0xd--0xd line.long 0x0 "PID,Process Identifier" hexmask.long 0x0 25.--31. 0x2000000 "PID ,Process Identifier" group c15:0x8e--0x8e line.long 0x0 "IBCR0,Inctruction Breakpoint Register 0" hexmask.long 0x0 1.--31. 2. "MVA ,Instruction Breakpoint MVA" bitfld.long 0x0 0. " E ,Breakpoint Enable" "disable,enable" group c15:0x9e--0x9e line.long 0x0 "IBCR1,Inctruction Breakpoint Register 1" hexmask.long 0x0 1.--31. 2. "MVA ,Instruction Breakpoint MVA" bitfld.long 0x0 0. " E ,Breakpoint Enable" "disable,enable" group c15:0x0e--0x0e line.long 0x0 "DBR0,Data Breakpoint Register 0" group c15:0x3e--0x3e line.long 0x0 "DBR1,Data Breakpoint Register 1" group c15:0x4e--0x4e line.long 0x0 "DBCON,Data Breakpoint Configuration Register" bitfld.long 0x0 8. "M ,DBR1 Mode" "Data Breakpoint Address,Data Address Mask" bitfld.long 0x0 2.--3. " E1 ,DBR1 Breakpoint Enable" "disable,enable store,enable load/store,enable load" bitfld.long 0x0 0.--1. " E0 ,DBR0 Enable" "disable,enable store,enable load/store,enable load" ; -------------------------------------------------------------------------------- ; *** Intel 80200 *** ; -------------------------------------------------------------------------------- if (d.l(c15:0x0)&0xffffe3f0)==0x69052000 group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 13. "CP13 ,Coprocessor Access Rights" "denied,allowed" bitfld.long 0x0 0. " CP0 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- ; *** Intel 80321 (IOP321) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69052020||(d.l(c15:0x0)&0xffffe3f0)==0x69052030 group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 13. "CP13 ,Coprocessor Access Rights" "denied,allowed" bitfld.long 0x0 7. " CP7 ,Coprocessor Access Rights" "denied,allowed" bitfld.long 0x0 6. " CP6 ,Coprocessor Access Rights" "denied,allowed" bitfld.long 0x0 0. " CP0 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- ; *** Intel PXA210, PXA250 (Sabinal, Cotulla) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100||(d.l(c15:0x0)&0xffffe3f0)==0x69052120 group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 7. "CP7 ,Coprocessor Access Rights" "denied,allowed" bitfld.long 0x0 0. " CP0 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- ; *** Intel PXA27x (Bulverde) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69054110 group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed" bitfld.long 0x0 1. "CP1 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- ; *** Intel (Manitoba) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x690540a0 group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- ; *** Intel IXP2400, IXP2800 (Sausolito, Castine) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69054190||(d.l(c15:0x0)&0xffff41a0)==0x69052120 group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 7. "CP7 ,Coprocessor Access Rights" "denied,allowed" bitfld.long 0x0 0. " CP0 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- ; *** other Intel XScale V5TE *** ; *** includes XScale IXP425, because no product ID is available now *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe000)==0x69054000 group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- ; *** other Intel XScale V5TE *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe000)==0x69052000 group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- ; *** any else *** ; -------------------------------------------------------------------------------- else group c15:0x1f--0x1f line.long 0x0 "CPAR,Coprocessor Access Register" bitfld.long 0x0 0. "CP0 ,Coprocessor Access Rights" "denied,allowed" ; -------------------------------------------------------------------------------- endif tree.end ;end include file xscale/cp15.ph ;begin include file xscale/cp14.ph ;parameters: ; -------------------------------------------------------------------------------- ; 80200, PXA210, PXA250 ; not impl.: 80321, IXP425, IXP2400, IXP2800, Bulverde, Manitoba tree "CP14" ; State: preliminary ; -------------------------------------------------------------------------------- group c14:0x00--0x03 "Performance Monitoring" line.long 4*0x00 "PMNC, Performance Monitor control Register" bitfld.long 4*0x00 20.--27. "EvtCnt1 ,Source of Events that PMN1 counts" "IC miss ext,IC no inst,Data stall,ITLB miss,DTLB miss,Branch,Branch mispr,Inst exec,DC full every,DC full once,DC acc,DC miss,DC wback,SW changed PC,res,res,BCU requ,BCU que full,BCU que drain,res,unlogged ECC,BCU 1-bit err,RMW,?..." bitfld.long 4*0x00 12.--19. " EvtCnt0 ,Source of Events that PMN0 counts" "IC miss ext,IC no inst,Data stall,ITLB miss,DTLB miss,Branch,Branch mispr,Inst exec,DC full every,DC full once,DC acc,DC miss,DC wback,SW changed PC,res,res,BCU requ,BCU que full,BCU que drain,res,unlogged ECC,BCU 1-bit err,RMW,?..." textline " " bitfld.long 4*0x00 10. "CCNT-OV ,Clock Counter Overflow Flag" "no,yes" bitfld.long 4*0x00 9. " PMN1-OV ,Performace Counter 1 Overflow Flag" "no,yes" bitfld.long 4*0x00 8. " PMN0-OV ,Performace Counter 0 Overflow Flag" "no,yes" textline " " bitfld.long 4*0x00 6. "CCNT-IE ,Clock Counter Interrupt" "disable,enable" bitfld.long 4*0x00 5. " PMN1-IE ,Performace Counter 1 Interrupt" "disable,enable" bitfld.long 4*0x00 4. " PMN0-IE ,Performace Counter 0 Interrupt" "disable,enable" textline " " bitfld.long 4*0x00 3. "D ,Clock Count Divider" "1,64" bitfld.long 4*0x00 2. " C ,Clock Counter Reset" "no action,reset to 0" bitfld.long 4*0x00 1. " P ,Performace Counter Reset (both)" "no action,reset to 0" bitfld.long 4*0x00 0. " E ,Enable all 3 Counters" "disable,enable" line.long 4*0x01 "CCNT, 32-bit clock counter" line.long 4*0x02 "PMN0, 32-bit event counter" line.long 4*0x03 "PMN1, 32-bit event counter" ; -------------------------------------------------------------------------------- ; *** Intel 80200 *** ; -------------------------------------------------------------------------------- if (d.l(c15:0x0)&0xffffe3f0)==0x69052000 group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" bitfld.long 4*0x00 0.--3. "CCLKCFG ,Core Clock Configuration" "res,3,4,5,6,7,8,9,res,res,res,res,res,res,res,res" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,IDLE,res,SLEEP" ; -------------------------------------------------------------------------------- ; *** Intel 80321 or IOP321 (Verde) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69052020||(d.l(c15:0x0)&0xffffe3f0)==0x69052030 group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP" ; -------------------------------------------------------------------------------- ; *** Intel PXA210, PXA250 (Sabinal, Cotulla) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100||(d.l(c15:0x0)&0xffffe3f0)==0x69052120 group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" bitfld.long 4*0x00 1.--1. "FCS ,Frequency Change Sequence" "do not enter,enter" bitfld.long 4*0x00 0.--0. " TURBO ,Turbo Mode" "exit,enter" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "Run/Turbo,Idle,res,Sleep/Deep Sleep" ; -------------------------------------------------------------------------------- ; *** Intel (Bulverde) *** ; -------------------------------------------------------------------------------- ; wrong Product ID in developer's manual revision 0.1 (ID of PXA250!!!) elif (d.l(c15:0x0)&0xffffe3f0)==0x69052100 group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP" ; -------------------------------------------------------------------------------- ; *** Intel IXP2400, IXP2800 (Sausolito, Castine) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x69054190||(d.l(c15:0x0)&0xffffe3f0)==0x690541a0 group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP" ; -------------------------------------------------------------------------------- ; *** Intel (Manitoba) *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe3f0)==0x690540a0 group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP" ; -------------------------------------------------------------------------------- ; *** other Intel XScale V5TE *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe000)==0x69052000 group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP" ; -------------------------------------------------------------------------------- ; *** other Intel XScale V5TE *** ; *** includes XScale IXP425 *** ; -------------------------------------------------------------------------------- elif (d.l(c15:0x0)&0xffffe000)==0x69054000 group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP" ; -------------------------------------------------------------------------------- ; *** any other XScale *** ; -------------------------------------------------------------------------------- else group c14:0x06--0x07 "Clock and Power Management" line.long 4*0x00 "CCLKCFG,Core Clock Configuration Register" line.long 4*0x01 "PWRMODE,Power Management Register" bitfld.long 4*0x01 0.--1. "M ,Mode" "ACTIVE,defined by ASSP,defined by ASSP,defined by ASSP" endif group c14:0x08--0x0d "Software Debug" line.long 4*0x02 "DCSR,Debug Control and Status Register" bitfld.long 4*0x02 31. "GE ,Global Enable" "disable,enable" bitfld.long 4*0x02 30. " H ,Halt Mode" "Monitor Mode,Halt Mode" textline " " bitfld.long 4*0x02 23. "TF ,Trap FIQ" "disable,enable" bitfld.long 4*0x02 22. " TI ,Trap IRQ" "disable,enable" bitfld.long 4*0x02 20. " TD ,Trap Data Abort" "disable,enable" textline " " bitfld.long 4*0x02 19. "TA ,Trap Prefetch Abort" "disable,enable" bitfld.long 4*0x02 18. " TS ,Trap Software Interrupt" "disable,enable" bitfld.long 4*0x02 17. " TU ,Trap Undefined Instruction" "disable,enable" bitfld.long 4*0x02 16. " TR ,Trap Reset" "disable,enable" textline " " bitfld.long 4*0x02 5. "SA ,Sticky Abort" "no,yes" bitfld.long 4*0x02 2.--4. " MOE ,Method of Entry" "Reset,Inst Bkpt, Data Bkpt, BKPT Inst, Ext Debug Event, Vector Trap, Trace Buffer full, reserved" bitfld.long 4*0x02 1. " M ,Trace Buffer Mode" "wrap around,fill-once" bitfld.long 4*0x02 0. " E ,Trace Buffer Enable" "no,yes" line.long 4*0x04 "CHKPT0,Checkpoint 0 Register" line.long 4*0x05 "CHKPT1,Checkpoint 1 Register" tree.end ;end include file xscale/cp14.ph ;begin include file xscale/manitoba-memory.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; Copy of Cotulla plus extensions ; Missing: MDCNFG, MDREFR, SXLCR, SXCNFG, SXMRS, MDMRS ; Check: BOOT_DEF ; State: preliminary ; -------------------------------------------------------------------------------- tree "Memory Controller" ; -------------------------------------------------------------------------------- ; group asd:0x48000000++0x03 ; line.long 0x00 "MDCNFG,SDRAM Configuration Register 0" ; bitfld.long 0x00 28.--28. "DSA1111_2 ,Use SA1111 Addressing Muxing Mode for pair 2/3" "no,yes" ; bitfld.long 0x00 27.--27. " LATCH2 ,Return Data from SDRAM latching scheme for pair 2/3" "MEMCLK,return clock" ; bitfld.long 0x00 26.--26. " DADDR2 ,Use alternate addressing for pair 2/3" "no,yes" ; textline " " ; bitfld.long 0x00 24.--25. "DTC2 ,Timing Category for SDRAM pair 2/3" "Not Valid,tRP=2 CL=2 tRCD=2 tRAS=5 tRC=8,tRP=3 CL=3 tRCD=3 tRAS=7 tRC=10,tRP=3 CL=3 tRCD=3 tRAS=7 tRC=11" ; bitfld.long 0x00 23.--23. " DNB2 ,Number of banks in upper partition pair" "2,4" ; textline " " ; bitfld.long 0x00 21.--22. "DRAC2 ,SDRAM row address bit count for partition pair 2/3" "11,12,13,res" ; bitfld.long 0x00 19.--20. " DCAC2 ,Number of Column address bit for partition pair 2/3" "8,9,10,11" ; bitfld.long 0x00 18.--18. " DWID2 ,SDRAM data bus width for partition pair 2/3" "32,16" ; bitfld.long 0x00 17.--17. " DE3 ,SDRAM Enable for partition 3" "dis,ena" ; bitfld.long 0x00 16.--16. " DE2 ,SDRAM Enable for partition 2" "dis,ena" ; textline " " ; bitfld.long 0x00 12.--12. "DSA1111_0 ,Use SA1111 Addressing Muxing Mode for pair 0/1" "no,yes" ; bitfld.long 0x00 11.--11. " LATCH0 ,Return Data from SDRAM latching scheme for pair 0/1" "MEMCLK,return clock" ; bitfld.long 0x00 10.--10. " DADDR0 ,Use alternate addressing for pair 0/1" "no,yes" ; textline " " ; bitfld.long 0x00 8.--9. "DTC0 ,Timing Category for SDRAM pair 0/1" "Not Valid,tRP=2 CL=2 tRCD=2 tRAS=5 tRC=8,tRP=3 CL=3 tRCD=3 tRAS=7 tRC=10,tRP=3 CL=3 tRCD=3 tRAS=7 tRC=11" ; bitfld.long 0x00 7.--7. " DNB0 ,Number of banks in lower partition pair" "2,4" ; textline " " ; bitfld.long 0x00 5.--6. "DRAC0 ,SDRAM row address bit count for partition pair 0/1" "11,12,13,res" ; bitfld.long 0x00 3.--4. " DCAC0 ,Number of Column address bit for partition pair 0/1" "8,9,10,11" ; bitfld.long 0x00 2.--2. " DWID0 ,SDRAM data bus width for partition pair 0/1" "32,16" ; bitfld.long 0x00 1.--1. " DE1 ,SDRAM Enable for partition 1" "dis,ena" ; bitfld.long 0x00 0.--0. " DE0 ,SDRAM Enable for partition 0" "dis,ena" ;group asd:0x48000004++0x03 ; line.long 0x00 "MDREFR,SDRAM Refresh Control Register" ; bitfld.long 0x0 25.--25. "K2FREE ,SDRAM Free-Running Control SDCLK2" "no,yes" ; bitfld.long 0x0 24.--24. " K1FREE ,SDRAM Free-Running Control SDCLK1" "no,yes" ; bitfld.long 0x0 23.--23. " K0FREE ,SDRAM Free-Running Control SDCLK0" "no,yes" ; bitfld.long 0x0 22.--22. " SLFRSH ,SDRAM Self-Refresh Control/Status" "dis,ena" ; bitfld.long 0x0 20.--20. " APD ,SDRAM/Synchronous Static Memory Auto Power-Down Enable" "no,yes" ; textline " " ; bitfld.long 0x0 19.--19. "K2DB2 ,SDRAM Clock Pin 2 (SDCLK2) Divide by 2 Control/Status" "MEMCLK,MEMCLK/2" ; bitfld.long 0x0 18.--18. " K2RUN ,SDRAM Clock Pin 2 (SDCLK2) Run Control/Status" "dis,ena" ; bitfld.long 0x0 17.--17. " K1DB2 ,SDRAM Clock Pin 1 (SDCLK1) Divide by 2 Control/Status" "MEMCLK,MEMCLK/2" ; bitfld.long 0x0 16.--16. " K1RUN ,SDRAM Clock Pin 1 (SDCLK1) Run Control/Status" "dis,ena" ; textline " " ; bitfld.long 0x0 15.--15. "E1PIN ,Clock Enable Pin 1 (SDCKE1) Level Control/Status" "dis,ena" ; bitfld.long 0x0 14.--14. " K0DB2 ,SDRAM Clock Pin 0 (SDCLK0) Divide by 2 Control/Status" "MEMCLK,MEMCLK/2" ; bitfld.long 0x0 13.--13. " K0RUN ,SDRAM Clock Pin 0 (SDCLK0) Run Control/Status" "dis,ena" ; bitfld.long 0x0 12.--12. " E0PIN ,Clock Enable Pin 0 (SDCKE0) Level Control/Status" "dis,ena" ; hexmask.long 0x0 0.--11. 1. " DRI ,SDRAM refresh interval, all partitions" group asd:0x48000008++0x0b line.long 0x00 "MSC0,Static Memory Control Register 0" bitfld.long 0x0 31.--31. "RBUFF1 ,Return Buffer vs. Streaming behavior" "slower,faster" bitfld.long 0x0 28.--30. " RRR1 ,ROM/SRAM recovery time" "0,2,4,6,8,10,12,14" bitfld.long 0x0 24.--27. " RDN1 ,ROM delay next access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " RDF1 ,ROM delay first access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 19.--19. " RBW1 ,ROM bus width" "32 bit,16 bit" textline " " bitfld.long 0x0 16.--18. "RT1 ,ROM type" "Nonburst ROM or Flash,SRAM,Burst-of-four ROM or Flash,Burst-of-eight ROM or Flash,VLIO,res,res,res" textline " " bitfld.long 0x0 15.--15. "RBUFF0 ,Return Buffer vs. Streaming behavior" "slower,faster" bitfld.long 0x0 12.--14. " RRR0 ,ROM/SRAM recovery time" "0,2,4,6,8,10,12,14" bitfld.long 0x0 8.--11. " RDN0 ,ROM delay next access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 4.--7. " RDF0 ,ROM delay first access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 3.--3. " RBW0 ,ROM bus width" "32 bit,16 bit" textline " " bitfld.long 0x0 0.--2. "RT0 ,ROM type" "Nonburst ROM or Flash,SRAM,Burst-of-four ROM or Flash,Burst-of-eight ROM or Flash,VLIO,res,res,res" line.long 0x04 "MSC1,Static Memory Control Register 1" bitfld.long 0x4 31.--31. "RBUFF3 ,Return Buffer vs. Streaming behavior" "slower,faster" bitfld.long 0x4 28.--30. " RRR3 ,ROM/SRAM recovery time" "0,2,4,6,8,10,12,14" bitfld.long 0x4 24.--27. " RDN3 ,ROM delay next access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x4 20.--23. " RDF3 ,ROM delay first access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x4 19.--19. " RBW3 ,ROM bus width" "32 bit,16 bit" textline " " bitfld.long 0x4 16.--18. "RT3 ,ROM type" "Nonburst ROM or Flash,SRAM,Burst-of-four ROM or Flash,Burst-of-eight ROM or Flash,VLIO,res,res,res" textline " " bitfld.long 0x4 15.--15. "RBUFF2 ,Return Buffer vs. Streaming behavior" "slower,faster" bitfld.long 0x4 12.--14. " RRR2 ,ROM/SRAM recovery time" "0,2,4,6,8,10,12,14" bitfld.long 0x4 8.--11. " RDN2 ,ROM delay next access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x4 4.--7. " RDF2 ,ROM delay first access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x4 3.--3. " RBW2 ,ROM bus width" "32 bit,16 bit" textline " " bitfld.long 0x4 0.--2. "RT2 ,ROM type" "Nonburst ROM or Flash,SRAM,Burst-of-four ROM or Flash,Burst-of-eight ROM or Flash,VLIO,res,res,res" line.long 0x08 "MSC2,Static Memory Control Register 2" bitfld.long 0x8 31.--31. "RBUFF5 ,Return Buffer vs. Streaming behavior" "slower,faster" bitfld.long 0x8 28.--30. " RRR5 ,ROM/SRAM recovery time" "0,2,4,6,8,10,12,14" bitfld.long 0x8 24.--27. " RDN5 ,ROM delay next access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x8 20.--23. " RDF5 ,ROM delay first access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x8 19.--19. " RBW5 ,ROM bus width" "32 bit,16 bit" textline " " bitfld.long 0x8 16.--18. "RT5 ,ROM type" "Nonburst ROM or Flash,SRAM,Burst-of-four ROM or Flash,Burst-of-eight ROM or Flash,VLIO,res,res,res" textline " " bitfld.long 0x8 15.--15. "RBUFF4 ,Return Buffer vs. Streaming behavior" "slower,faster" bitfld.long 0x8 12.--14. " RRR4 ,ROM/SRAM recovery time" "0,2,4,6,8,10,12,14" bitfld.long 0x8 8.--11. " RDN4 ,ROM delay next access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x8 4.--7. " RDF4 ,ROM delay first access" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x8 3.--3. " RBW4 ,ROM bus width" "32 bit,16 bit" textline " " bitfld.long 0x8 0.--2. "RT4 ,ROM type" "Nonburst ROM or Flash,SRAM,Burst-of-four ROM or Flash,Burst-of-eight ROM or Flash,VLIO,res,res,res" group asd:0x48000014++0x03 line.long 0x00 "MECR,Expansion Memory (PCMCIA/Compact Flash) Bus Configuration Register" bitfld.long 0x00 1.--1. "CIT ,Card-Is-There" "no,yes" bitfld.long 0x00 0.--0. "NOS ,Number-of-Sockets" "1,2" group asd:0x48000018++0x03 line.long 0x00 "SXLCR,LCR value to be written to SDRAM-Timing Sychronous Flash" ; hexmask.long 0x0 26.--30. 1. "SXBNK2 ,LCR value to be written to SDRAM-like Flash Bank Pair 2" ; bitfld.long 0x0 25.--25. " SXMSK3 ,Mask LCR Write to Static Bank 3" "ena,dis" ; bitfld.long 0x0 24.--24. " SXMSK2 ,Mask LCR Write to Static Bank 2" "ena,dis" ; hexmask.long 0x0 16.--23. 1. " SXLCR2 ,LCR value to be written to SDRAM-like Flash Bank Pair 2" ; textline " " ; hexmask.long 0x0 10.--14. 1. "SXBNK0 ,LCR value to be written to SDRAM-like Flash Bank Pair 0" ; bitfld.long 0x0 9.--9. " SXMSK1 ,Mask LCR Write to Static Bank 1" "ena,dis" ; bitfld.long 0x0 8.--8. " SXMSK0 ,Mask LCR Write to Static Bank 0" "ena,dis" ; hexmask.long 0x0 0.--7. 1. " SXLCR0 ,LCR value to be written to SDRAM-like Flash Bank Pair 0" group asd:0x4800001c++0x03 line.long 0x00 "SXCNFG,Sychronous Static Memory Control Register" ; bitfld.long 0x0 30.--30. "SXLATCH2 ,SXMEM latching scheme for pair 2/3" "fixed delay,return clock" ; bitfld.long 0x0 28.--29. " SXTP2 ,SX Memory Type for partition pair 2/3" "SMROM,SDRAM-like Flash,non-SDRAM-like Flash,res" ; textline " " ; bitfld.long 0x0 26.--27. "SXCA2 ,SX Memory column address bit count for partition pair 2/3" "7,8,9,10" ; bitfld.long 0x0 24.--25. " SXRA2 ,SX Memory row address bit count for partition pair 2/3" "12,13,res,res" ; bitfld.long 0x0 21.--23. " SXRL2 ,RAS Latency for SX Memory partition pair 2/3" "1,2,3,4,5,6,7,8" ; bitfld.long 0x0 18.--20. " SXCL2 ,CAS Latency for SX Memory partition pair 2/3" "res,2,3,4,5,6,7,res" ; bitfld.long 0x0 16.--17. " SXEN2 ,Enable Bits for SX Memory partition 2 and 3" "dis,ena 2,ena 3,ena 2/3" ; textline " " ; bitfld.long 0x0 14.--14. "SXLATCH0 ,SXMEM latching scheme for pair 0/1" "fixed delay,return clock" ; bitfld.long 0x0 12.--13. " SXTP0 ,SX Memory Type for partition pair 0/1" "SMROM,SDRAM-like Flash,non-SDRAM-like Flash,res" ; textline " " ; bitfld.long 0x0 10.--11. "SXCA0 ,SX Memory column address bit count for partition pair 0/1" "7,8,9,10" ; bitfld.long 0x0 8.--9. " SXRA0 ,SX Memory row address bit count for partition pair 0/1" "12,13,res,res" ; bitfld.long 0x0 5.--7. " SXRL0 ,RAS Latency for SX Memory partition pair 0/1" "1,2,3,4,5,6,7,8" ; bitfld.long 0x0 2.--4. " SXCL0 ,CAS Latency for SX Memory partition pair 0/1" "res,2,3,4,5,6,7,res" ; bitfld.long 0x0 0.--1. " SXEN0 ,Enable Bits for SX Memory partition 0 and 1" "dis,ena 1,ena 1,ena 0/1" group asd:0x48000020++0x03 line.long 0x00 "FLYCNFG,Fly-by-DMA configuration Register" bitfld.long 0x0 21.--24. "FBDAST1 ,DVAL1 Deassert Time" "inv,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 17.--20. " FBAST1 ,DVAL1 Assert Time" "inv,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 16.--16. " FBPOL1 ,DVAL1 Polarity; active" "low,high" textline " " bitfld.long 0x0 5.--8. "FBDAST0 ,DVAL0 Deassert Time" "inv,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 1.--4. " FBAST0 ,DVAL0 Assert Time" "inv,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 0.--0. " FBPOL0 ,DVAL0 Polarity; active" "low,high" group asd:0x48000024++0x03 line.long 0x00 "SXMRS,MRS value to be written to Sychronous Flash or SMROM" ; hexmask.long 0x0 16.--30. 1. "SXMRS2 ,MRS value to be written to Synchronous-Static Memory requiring an MRS command for Bank Pair 2" ; hexmask.long 0x0 0.--14. 1. " SXMRS0 ,MRS value to be written to Synchronous-Static Memory requiring an MRS command for Bank Pair 0" group asd:0x48000028++0x07 line.long 0x00 "MCMEM0,Card Interface Common Memory Space Socket 0 Timing Configuration" hexmask.long 0x00 14.--19. 0x01 "MEM0_HOLD ,Number of memory clocks to hold address after command deassertion for MCMEM for socket 0" hexmask.long 0x00 7.--11. 0x01 " MEM0_ASST ,Code for the command assertion time" hexmask.long 0x00 0.--6. 0x01 " MEM0_SET ,Number of memory clocks to set up address before command assertion for MCMEM for socket 0" line.long 0x04 "MCMEM1,Card Interface Common Memory Space Socket 1 Timing Configuration" hexmask.long 0x04 14.--19. 0x01 "MEM1_HOLD ,Number of memory clocks to hold address after command deassertion for MCMEM for socket 1" hexmask.long 0x04 7.--11. 0x01 " MEM1_ASST ,Code for the command assertion time" hexmask.long 0x04 0.--6. 0x01 " MEM1_SET ,Number of memory clocks to set up address before command assertion for MCMEM for socket 1" group asd:0x48000030++0x07 line.long 0x00 "MCATT0,Card Interface Attribute Space Socket 0 Timing Configuration" hexmask.long 0x00 14.--19. 0x01 "ATT0_HOLD ,Number of memory clocks to hold address after command deassertion for MCATT for socket 0" hexmask.long 0x00 7.--11. 0x01 " ATT0_ASST ,Code for the command assertion time" hexmask.long 0x00 0.--6. 0x01 " ATT0_SET ,Number of memory clocks to set up address before command assertion for MCATT for socket 0" line.long 0x04 "MCATT1,Card Interface Attribute Space Socket 1 Timing Configuration" hexmask.long 0x04 14.--19. 0x01 "ATT1_HOLD ,Number of memory clocks to hold address after command deassertion for MCATT for socket 1" hexmask.long 0x04 7.--11. 0x01 " ATT1_ASST ,Code for the command assertion time" hexmask.long 0x04 0.--6. 0x01 " ATT1_SET ,Number of memory clocks to set up address before command assertion for MCATT for socket 1" group asd:0x48000038++0x07 line.long 0x00 "MCIO0,Card Interface I/O Space Socket 0 Timing Configuration" hexmask.long 0x00 14.--19. 0x01 "IO0_HOLD ,Number of memory clocks to hold address after command deassertion for MCIO for socket 0" hexmask.long 0x00 7.--11. 0x01 " IO0_ASST ,Code for the command assertion time" hexmask.long 0x00 0.--6. 0x01 " IO0_SET ,Number of memory clocks to set up address before command assertion for MCIO for socket 0" line.long 0x04 "MCIO1,Card Interface I/O Space Socket 1 Timing Configuration" hexmask.long 0x04 14.--19. 0x01 "IO1_HOLD ,Number of memory clocks to hold address after command deassertion for MCIO for socket 1" hexmask.long 0x04 7.--11. 0x01 " IO1_ASST ,Code for the command assertion time" hexmask.long 0x04 0.--6. 0x01 " IO1_SET ,Number of memory clocks to set up address before command assertion for MCIO for socket 1" group asd:0x48000040++0x03 line.long 0x00 "MDMRS,MRS value to be written to SDRAM" hexmask.long 0x00 23.--30. 0x01 "MDMRS2 ,MRS value to be written to SDRAM for partition pair 2" hexmask.long 0x00 20.--22. 0x01 " MDCL2 , SDRAM partition pair 2 CAS Latency" bitfld.long 0x00 19.--19. " MDADD2 ,SDRAM partition pair 2 Burst Type" "sequential,sequential" bitfld.long 0x00 16.--18. " MDBL2 ,SDRAM partition pair 2 Burst Length" "4,4,4,4,4,4,4,4" textline " " hexmask.long 0x00 7.--14. 0x01 "MDMRS0 ,MRS value to be written to SDRAM for partition pair 0" hexmask.long 0x00 4.--6. 0x01 " MDCL0 , SDRAM partition pair 0 CAS Latency" bitfld.long 0x00 3.--3. " MDADD0 ,SDRAM partition pair 0 Burst Type" "sequential,sequential" bitfld.long 0x00 0.--2. " MDBL0 ,SDRAM partition pair 0 Burst Length" "4,4,4,4,4,4,4,4" rgroup asd:0x48000044++0x03 line.long 0x00 "BOOT_DEF,Read-Only Boot-Time Register. " bitfld.long 0x00 3.--3. "PKG_TYPE ,Package Type" "16 Bit,undef" bitfld.long 0x00 0.--2. " BOOT_SEL ,Contains the three input pins BOOT_SEL[2:0]" "inv,Async 16 Bit Rom,inv,inv,inv,64 Mbit SMROM 16Bit,inv,32 Mbit SMROM 16Bit" tree.end ;end include file xscale/manitoba-memory.ph ;begin include file xscale/manitoba-dma.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; From "Manitoba Architecture Specification" rev 0.75 ; State: preliminary (some inconsistencies in specification) ; -------------------------------------------------------------------------------- tree "DMA Controller" ; -------------------------------------------------------------------------------- group asd:0x400000f0++0x03 line.long 0x0 "DINT,DMA Interrupt Register" bitfld.long 0x00 31.--31. "CHLINTR31 ,Channel 31 Interrupt" "no,yes" bitfld.long 0x00 30.--30. " CHLINTR30 ,Channel 30 Interrupt" "no,yes" bitfld.long 0x00 29.--29. " CHLINTR29 ,Channel 29 Interrupt" "no,yes" bitfld.long 0x00 28.--28. " CHLINTR28 ,Channel 28 Interrupt" "no,yes" textline " " bitfld.long 0x00 27.--27. "CHLINTR27 ,Channel 27 Interrupt" "no,yes" bitfld.long 0x00 26.--26. " CHLINTR26 ,Channel 26 Interrupt" "no,yes" bitfld.long 0x00 25.--25. " CHLINTR25 ,Channel 25 Interrupt" "no,yes" bitfld.long 0x00 24.--24. " CHLINTR24 ,Channel 24 Interrupt" "no,yes" textline " " bitfld.long 0x00 23.--23. "CHLINTR23 ,Channel 23 Interrupt" "no,yes" bitfld.long 0x00 22.--22. " CHLINTR22 ,Channel 22 Interrupt" "no,yes" bitfld.long 0x00 21.--21. " CHLINTR21 ,Channel 21 Interrupt" "no,yes" bitfld.long 0x00 20.--20. " CHLINTR20 ,Channel 20 Interrupt" "no,yes" textline " " bitfld.long 0x00 19.--19. "CHLINTR19 ,Channel 19 Interrupt" "no,yes" bitfld.long 0x00 18.--18. " CHLINTR15 ,Channel 15 Interrupt" "no,yes" bitfld.long 0x00 17.--17. " CHLINTR14 ,Channel 14 Interrupt" "no,yes" bitfld.long 0x00 16.--16. " CHLINTR13 ,Channel 13 Interrupt" "no,yes" textline " " bitfld.long 0x00 15.--15. "CHLINTR15 ,Channel 15 Interrupt" "no,yes" bitfld.long 0x00 14.--14. " CHLINTR14 ,Channel 14 Interrupt" "no,yes" bitfld.long 0x00 13.--13. " CHLINTR13 ,Channel 13 Interrupt" "no,yes" bitfld.long 0x00 12.--12. " CHLINTR12 ,Channel 12 Interrupt" "no,yes" textline " " bitfld.long 0x00 11.--11. "CHLINTR11 ,Channel 11 Interrupt" "no,yes" bitfld.long 0x00 10.--10. " CHLINTR10 ,Channel 10 Interrupt" "no,yes" bitfld.long 0x00 9.--9. " CHLINTR9 ,Channel 9 Interrupt" "no,yes" bitfld.long 0x00 8.--8. " CHLINTR8 ,Channel 8 Interrupt" "no,yes" textline " " bitfld.long 0x00 7.--7. "CHLINTR7 ,Channel 7 Interrupt" "no,yes" bitfld.long 0x00 6.--6. " CHLINTR6 ,Channel 6 Interrupt" "no,yes" bitfld.long 0x00 5.--5. " CHLINTR5 ,Channel 5 Interrupt" "no,yes" bitfld.long 0x00 4.--4. " CHLINTR4 ,Channel 4 Interrupt" "no,yes" textline " " bitfld.long 0x00 3.--3. "CHLINTR3 ,Channel 3 Interrupt" "no,yes" bitfld.long 0x00 2.--2. " CHLINTR2 ,Channel 2 Interrupt" "no,yes" bitfld.long 0x00 1.--1. " CHLINTR1 ,Channel 1 Interrupt" "no,yes" bitfld.long 0x00 0.--0. " CHLINTR0 ,Channel 0 Interrupt" "no,yes" tree "DMA Channel Controls and Descriptors" tree "Channel 0" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000000 0x40000200 0 group asd:0x40000000++0x3 line.long 0x00 "DCSR0, DMA Control/Status Register 0" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000200++0xF line.long 0x0 "DDADR0, DMA Descriptor Address Register 0" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD0, DMA Command Register 0" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR0, DMA Source Address Register 0" line.long 0x8 "DTADR0, DMA Target Address Register 0" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 1" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000004 0x40000210 1 group asd:0x40000004++0x3 line.long 0x00 "DCSR1, DMA Control/Status Register 1" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000210++0xF line.long 0x0 "DDADR1, DMA Descriptor Address Register 1" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD1, DMA Command Register 1" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR1, DMA Source Address Register 1" line.long 0x8 "DTADR1, DMA Target Address Register 1" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 2" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000008 0x40000220 2 group asd:0x40000008++0x3 line.long 0x00 "DCSR2, DMA Control/Status Register 2" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000220++0xF line.long 0x0 "DDADR2, DMA Descriptor Address Register 2" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD2, DMA Command Register 2" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR2, DMA Source Address Register 2" line.long 0x8 "DTADR2, DMA Target Address Register 2" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 3" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x4000000C 40000230 3 group asd:0x4000000C++0x3 line.long 0x00 "DCSR3, DMA Control/Status Register 3" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000230++0xF line.long 0x0 "DDADR3, DMA Descriptor Address Register 3" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD3, DMA Command Register 3" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR3, DMA Source Address Register 3" line.long 0x8 "DTADR3, DMA Target Address Register 3" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 4" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000010 40000240 4 group asd:0x40000010++0x3 line.long 0x00 "DCSR4, DMA Control/Status Register 4" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000240++0xF line.long 0x0 "DDADR4, DMA Descriptor Address Register 4" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD4, DMA Command Register 4" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR4, DMA Source Address Register 4" line.long 0x8 "DTADR4, DMA Target Address Register 4" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 5" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000014 40000250 5 group asd:0x40000014++0x3 line.long 0x00 "DCSR5, DMA Control/Status Register 5" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000250++0xF line.long 0x0 "DDADR5, DMA Descriptor Address Register 5" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD5, DMA Command Register 5" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR5, DMA Source Address Register 5" line.long 0x8 "DTADR5, DMA Target Address Register 5" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 6" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000018 0x40000260 6 group asd:0x40000018++0x3 line.long 0x00 "DCSR6, DMA Control/Status Register 6" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000260++0xF line.long 0x0 "DDADR6, DMA Descriptor Address Register 6" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD6, DMA Command Register 6" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR6, DMA Source Address Register 6" line.long 0x8 "DTADR6, DMA Target Address Register 6" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 7" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x4000001C 0x40000270 7 group asd:0x4000001C++0x3 line.long 0x00 "DCSR7, DMA Control/Status Register 7" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000270++0xF line.long 0x0 "DDADR7, DMA Descriptor Address Register 7" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD7, DMA Command Register 7" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR7, DMA Source Address Register 7" line.long 0x8 "DTADR7, DMA Target Address Register 7" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 8" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000020 0x40000280 8 group asd:0x40000020++0x3 line.long 0x00 "DCSR8, DMA Control/Status Register 8" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000280++0xF line.long 0x0 "DDADR8, DMA Descriptor Address Register 8" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD8, DMA Command Register 8" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR8, DMA Source Address Register 8" line.long 0x8 "DTADR8, DMA Target Address Register 8" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 9" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000024 0x40000290 9 group asd:0x40000024++0x3 line.long 0x00 "DCSR9, DMA Control/Status Register 9" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000290++0xF line.long 0x0 "DDADR9, DMA Descriptor Address Register 9" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD9, DMA Command Register 9" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR9, DMA Source Address Register 9" line.long 0x8 "DTADR9, DMA Target Address Register 9" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 10" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000028 0x400002A0 10 group asd:0x40000028++0x3 line.long 0x00 "DCSR10, DMA Control/Status Register 10" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400002A0++0xF line.long 0x0 "DDADR10, DMA Descriptor Address Register 10" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD10, DMA Command Register 10" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR10, DMA Source Address Register 10" line.long 0x8 "DTADR10, DMA Target Address Register 10" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 11" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x4000002c 0x400002B0 11 group asd:0x4000002c++0x3 line.long 0x00 "DCSR11, DMA Control/Status Register 11" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400002B0++0xF line.long 0x0 "DDADR11, DMA Descriptor Address Register 11" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD11, DMA Command Register 11" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR11, DMA Source Address Register 11" line.long 0x8 "DTADR11, DMA Target Address Register 11" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 12" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000030 0x400002C0 12 group asd:0x40000030++0x3 line.long 0x00 "DCSR12, DMA Control/Status Register 12" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400002C0++0xF line.long 0x0 "DDADR12, DMA Descriptor Address Register 12" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD12, DMA Command Register 12" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR12, DMA Source Address Register 12" line.long 0x8 "DTADR12, DMA Target Address Register 12" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 13" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000034 0x400002D0 13 group asd:0x40000034++0x3 line.long 0x00 "DCSR13, DMA Control/Status Register 13" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400002D0++0xF line.long 0x0 "DDADR13, DMA Descriptor Address Register 13" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD13, DMA Command Register 13" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR13, DMA Source Address Register 13" line.long 0x8 "DTADR13, DMA Target Address Register 13" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 14" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000038 0x400002E0 14 group asd:0x40000038++0x3 line.long 0x00 "DCSR14, DMA Control/Status Register 14" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400002E0++0xF line.long 0x0 "DDADR14, DMA Descriptor Address Register 14" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD14, DMA Command Register 14" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR14, DMA Source Address Register 14" line.long 0x8 "DTADR14, DMA Target Address Register 14" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 15" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x4000003c 0x400002F0 15 group asd:0x4000003c++0x3 line.long 0x00 "DCSR15, DMA Control/Status Register 15" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400002F0++0xF line.long 0x0 "DDADR15, DMA Descriptor Address Register 15" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD15, DMA Command Register 15" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR15, DMA Source Address Register 15" line.long 0x8 "DTADR15, DMA Target Address Register 15" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 16" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000040 0x40000300 16 group asd:0x40000040++0x3 line.long 0x00 "DCSR16, DMA Control/Status Register 16" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000300++0xF line.long 0x0 "DDADR16, DMA Descriptor Address Register 16" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD16, DMA Command Register 16" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR16, DMA Source Address Register 16" line.long 0x8 "DTADR16, DMA Target Address Register 16" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 17" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000044 0x40000310 17 group asd:0x40000044++0x3 line.long 0x00 "DCSR17, DMA Control/Status Register 17" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000310++0xF line.long 0x0 "DDADR17, DMA Descriptor Address Register 17" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD17, DMA Command Register 17" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR17, DMA Source Address Register 17" line.long 0x8 "DTADR17, DMA Target Address Register 17" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 18" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000048 0x40000320 18 group asd:0x40000048++0x3 line.long 0x00 "DCSR18, DMA Control/Status Register 18" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000320++0xF line.long 0x0 "DDADR18, DMA Descriptor Address Register 18" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD18, DMA Command Register 18" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR18, DMA Source Address Register 18" line.long 0x8 "DTADR18, DMA Target Address Register 18" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 19" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x4000004c 0x40000330 19 group asd:0x4000004c++0x3 line.long 0x00 "DCSR19, DMA Control/Status Register 19" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000330++0xF line.long 0x0 "DDADR19, DMA Descriptor Address Register 19" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD19, DMA Command Register 19" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR19, DMA Source Address Register 19" line.long 0x8 "DTADR19, DMA Target Address Register 19" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 20" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000050 0x40000340 20 group asd:0x40000050++0x3 line.long 0x00 "DCSR20, DMA Control/Status Register 20" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000340++0xF line.long 0x0 "DDADR20, DMA Descriptor Address Register 20" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD20, DMA Command Register 20" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR20, DMA Source Address Register 20" line.long 0x8 "DTADR20, DMA Target Address Register 20" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 21" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000054 0x40000350 21 group asd:0x40000054++0x3 line.long 0x00 "DCSR21, DMA Control/Status Register 21" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000350++0xF line.long 0x0 "DDADR21, DMA Descriptor Address Register 21" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD21, DMA Command Register 21" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR21, DMA Source Address Register 21" line.long 0x8 "DTADR21, DMA Target Address Register 21" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 22" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000058 0x40000360 22 group asd:0x40000058++0x3 line.long 0x00 "DCSR22, DMA Control/Status Register 22" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000360++0xF line.long 0x0 "DDADR22, DMA Descriptor Address Register 22" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD22, DMA Command Register 22" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR22, DMA Source Address Register 22" line.long 0x8 "DTADR22, DMA Target Address Register 22" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 23" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x4000005c 0x40000370 23 group asd:0x4000005c++0x3 line.long 0x00 "DCSR23, DMA Control/Status Register 23" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000370++0xF line.long 0x0 "DDADR23, DMA Descriptor Address Register 23" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD23, DMA Command Register 23" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR23, DMA Source Address Register 23" line.long 0x8 "DTADR23, DMA Target Address Register 23" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 24" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000060 0x40000380 24 group asd:0x40000060++0x3 line.long 0x00 "DCSR24, DMA Control/Status Register 24" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000380++0xF line.long 0x0 "DDADR24, DMA Descriptor Address Register 24" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD24, DMA Command Register 24" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR24, DMA Source Address Register 24" line.long 0x8 "DTADR24, DMA Target Address Register 24" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 25" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000064 0x40000390 25 group asd:0x40000064++0x3 line.long 0x00 "DCSR25, DMA Control/Status Register 25" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x40000390++0xF line.long 0x0 "DDADR25, DMA Descriptor Address Register 25" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD25, DMA Command Register 25" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR25, DMA Source Address Register 25" line.long 0x8 "DTADR25, DMA Target Address Register 25" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 26" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000068 0x400003A0 26 group asd:0x40000068++0x3 line.long 0x00 "DCSR26, DMA Control/Status Register 26" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400003A0++0xF line.long 0x0 "DDADR26, DMA Descriptor Address Register 26" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD26, DMA Command Register 26" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR26, DMA Source Address Register 26" line.long 0x8 "DTADR26, DMA Target Address Register 26" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 27" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x4000006c 0x400003B0 27 group asd:0x4000006c++0x3 line.long 0x00 "DCSR27, DMA Control/Status Register 27" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400003B0++0xF line.long 0x0 "DDADR27, DMA Descriptor Address Register 27" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD27, DMA Command Register 27" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR27, DMA Source Address Register 27" line.long 0x8 "DTADR27, DMA Target Address Register 27" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 28" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000070 0x400003C0 28 group asd:0x40000070++0x3 line.long 0x00 "DCSR28, DMA Control/Status Register 28" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400003C0++0xF line.long 0x0 "DDADR28, DMA Descriptor Address Register 28" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD28, DMA Command Register 28" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR28, DMA Source Address Register 28" line.long 0x8 "DTADR28, DMA Target Address Register 28" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 29" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000074 0x400003D0 29 group asd:0x40000074++0x3 line.long 0x00 "DCSR29, DMA Control/Status Register 29" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400003D0++0xF line.long 0x0 "DDADR29, DMA Descriptor Address Register 29" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD29, DMA Command Register 29" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR29, DMA Source Address Register 29" line.long 0x8 "DTADR29, DMA Target Address Register 29" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 30" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x40000078 0x400003E0 30 group asd:0x40000078++0x3 line.long 0x00 "DCSR30, DMA Control/Status Register 30" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400003E0++0xF line.long 0x0 "DDADR30, DMA Descriptor Address Register 30" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD30, DMA Command Register 30" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR30, DMA Source Address Register 30" line.long 0x8 "DTADR30, DMA Target Address Register 30" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree "Channel 31" ;begin include file xscale/manitoba-dma-dscr.ph ;parameters: 0x4000007c 0x400003F0 31 group asd:0x4000007c++0x3 line.long 0x00 "DCSR31, DMA Control/Status Register 31" bitfld.long 0x00 31.--31. "RUN ,Run Bit" "stop,start" bitfld.long 0x00 30.--30. " NoDescFetch ,Descriptor Fetch Mode" "yes,no" bitfld.long 0x00 29.--29. " StopIrqEn ,Stop Interrupt Enable" "dis,ena" bitfld.long 0x00 27.--27. " Prefetch ,Descriptor Prefetch is" "dis,ena" textline " " bitfld.long 0x00 26.--26. "EORIntEn ,End Of Receive Interrupt is" "dis,ena" bitfld.long 0x00 25.--25. " SetCmpFlg ,Set CmpFlg" "nop,set" bitfld.long 0x00 24.--24. " ClrCmpFlg ,Clear CmpFlg" "nop,clr" hexfld.byte 0x02 " LoopCnt ,Loop Operation Counter" textline " " bitfld.long 0x00 10.--10. "CmpFlg ,Compare of Source and Target was" "equ,inq" bitfld.long 0x00 9.--9. " EOR ,End Of Receive" "no,yes" bitfld.long 0x00 8.--8. " ReqPend ,Request Pending" "no,yes" bitfld.long 0x00 3.--3. " StopIntr ,Stop State" "run,stop" textline " " bitfld.long 0x00 2.--2. "EndIntr ,End Interrupt" "no,yes" bitfld.long 0x00 1.--1. " StartIntr ,Start Interrupt" "no,yes" bitfld.long 0x00 0.--0. " BusErrIntr ,Bus Error Interrupt" "no,yes" group asd:0x400003F0++0xF line.long 0x0 "DDADR31, DMA Descriptor Address Register 31" hexmask.long 0x0 4.--31. 0x1 "DescAdr ,Address of next Descriptor" bitfld.long 0x0 2.--2. " BrEn ,Descriptor branching is" "dis,ena" bitfld.long 0x0 1.--1. " LpEn ,Descriptor looping is" "dis,ena" bitfld.long 0x0 0.--0. " Stop ,Stop Command" "run,stop" line.long 0xC "DCMD31, DMA Command Register 31" bitfld.long 0xC 31.--31. "IncSrcAdr ,Source Address Increment is" "dis,ena" bitfld.long 0xC 30.--30. " IncTrgAdr ,Target Address Increment is" "dis,ena" bitfld.long 0xC 29.--29. " FlowSrc ,Flow Control for Source is" "dis,ena" bitfld.long 0xC 28.--28. " FlowTrg ,Flow Control for Target is" "dis,ena" textline " " bitfld.long 0xC 27.--27. "CompCond ,Compare Condition Bit; Compare is" "dis, ena" bitfld.long 0xC 25.--26. " AddrType ,Source/Target contain " "adr/adr,adr/dat,dat/adr,dat/dat" bitfld.long 0xC 22.--22. " StartIrqEn ,Start Interrupt is" "dis,ena" bitfld.long 0xC 21.--21. " EndIrqEn ,End Interrupt is" "dis,ena" textline " " bitfld.long 0xC 20.--20. "FlyByS ,FlyBy for Source is" "dis,ena" bitfld.long 0xC 19.--19. " FlyByT ,FlyBy for Target is" "dis,ena" bitfld.long 0xC 18.--18. " Endian ,Byte ordering is" "little,big" bitfld.long 0xC 16.--17. " Size ,Max Burst Size is" "res,8,16,32" textline " " bitfld.long 0xC 14.--15. "Width ,Width of on-chip peripheral in Bytes is" "res,1,2,4" hexmask.long 0xC 0.--12. 0x1 " Len ,Length of transfer in Bytes" line.long 0x4 "DSADR31, DMA Source Address Register 31" line.long 0x8 "DTADR31, DMA Target Address Register 31" ;end include file xscale/manitoba-dma-dscr.ph tree.end tree.end tree "DMA Request Maps" tree "DREQ (Companion Chip) Request Map" group asd:0x40000100++0x03 "DREQ0 Companion Chip Request 0 (DRCMR0)" line.long 0x00 "DRCMR,DMA Request to Channel Map Register" bitfld.long 0x00 7.--7. "MAPVLD ,Map Valid" "unmapped,mapped" bitfld.long 0x00 0.--4. " CHLNUM ,Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group asd:0x40000104++0x03 "DREQ1 Companion Chip Request 1 (DRCMR1)" copy tree.end tree "I2S DMA Request Map" group asd:0x40000108++0x03 "I2S Receive Request (DRCMR2)" copy group asd:0x4000010c++0x03 "I2S Transmit Request (DRCMR3)" copy tree.end tree "BTUART DMA Request Map" group asd:0x40000110++0x03 "BTUART Receive Request (DRCMR4)" copy group asd:0x40000114++0x03 "BTUART Transmit Request (DRCMR5)" copy tree.end tree "FFUART DMA Request Map" group asd:0x40000118++0x03 "FFUART Receive Request (DRCMR6)" copy group asd:0x4000011C++0x03 "FFUART Transmit Request (DRCMR7)" copy tree.end tree "AC97 DMA Request Map" group asd:0x40000120++0x03 "AC97 Microphone Request (DRCMR8)" copy group asd:0x40000124++0x03 "AC97 Modem Receive Request (DRCMR9)" copy group asd:0x40000128++0x03 "AC97 Modem Transmit Request (DRCMR10)" copy group asd:0x4000012C++0x03 "AC97 Audio Receive Request (DRCMR11)" copy group asd:0x40000130++0x03 "AC97 Audio Transmit Request (DRCMR12)" copy tree.end tree "SSP DMA Request Map" group asd:0x40000134++0x03 "SSP Receive Request (DRCMR13)" copy group asd:0x40000138++0x03 "SSP Transmit Request (DRCMR14)" copy tree.end tree "ICP DMA Request Map" group asd:0x40000144++0x03 "ICP Receive Request (DRCMR17)" copy group asd:0x40000148++0x03 "ICP Transmit Request (DRCMR18)" copy tree.end tree "STUART DMA Request Map" group asd:0x4000014c++0x03 "STUART Receive Request (DRCMR19)" copy group asd:0x40000150++0x03 "STUART Transmit Request (DRCMR20)" copy tree.end tree "MMC DMA Request Map" group asd:0x40000154++0x03 "MMC Receive Request (DRCMR21)" copy group asd:0x40000158++0x03 "MMC Transmit Request (DRCMR22)" copy tree.end tree "USB DMA Request Map" group asd:0x40000164++0x03 "USB Endpoint 1 Request (DRCMR25)" copy group asd:0x40000168++0x03 "USB Endpoint 2 Request (DRCMR26)" copy group asd:0x4000016c++0x03 "USB Endpoint 3 Request (DRCMR27)" copy group asd:0x40000170++0x03 "USB Endpoint 4 Request (DRCMR28)" copy group asd:0x40000178++0x03 "USB Endpoint 6 Request (DRCMR30)" copy group asd:0x4000017c++0x03 "USB Endpoint 7 Request (DRCMR31)" copy group asd:0x40000180++0x03 "USB Endpoint 8 Request (DRCMR32)" copy group asd:0x40000184++0x03 "USB Endpoint 9 Request (DRCMR33)" copy group asd:0x4000018c++0x03 "USB Endpoint 11 Request (DRCMR35)" copy group asd:0x40000190++0x03 "USB Endpoint 12 Request (DRCMR36)" copy group asd:0x40000194++0x03 "USB Endpoint 13 Request (DRCMR37)" copy group asd:0x40000198++0x03 "USB Endpoint 14 Request (DRCMR38)" copy tree.end tree "Baseband DMA Request Map" group asd:0x40000170++0x03 "Baseband Receive Request 1 (DRCMR40)" copy group asd:0x40000174++0x03 "Baseband Transmit Request 1 (DRCMR41)" copy group asd:0x40000178++0x03 "Baseband Receive Request 2 (DRCMR42)" copy group asd:0x4000017c++0x03 "Baseband Transmit Request 2 (DRCMR43)" copy group asd:0x40000180++0x03 "Baseband Receive Request 3 (DRCMR44)" copy group asd:0x40000184++0x03 "Baseband Transmit Request 3 (DRCMR45)" copy group asd:0x40000188++0x03 "Baseband Receive Request 4 (DRCMR46)" copy group asd:0x4000018c++0x03 "Baseband Transmit Request 4 (DRCMR47)" copy group asd:0x40000190++0x03 "Baseband Receive Request 5 (DRCMR48)" copy group asd:0x40000194++0x03 "Baseband Transmit Request 5 (DRCMR49)" copy group asd:0x40000198++0x03 "Baseband Receive Request 6 (DRCMR50)" copy group asd:0x4000019c++0x03 "Baseband Transmit Request 6 (DRCMR51)" copy group asd:0x400001a0++0x03 "Baseband Receive Request 7 (DRCMR52)" copy group asd:0x400001a4++0x03 "Baseband Transmit Request 7 (DRCMR53)" copy tree.end tree.end tree.end ;end include file xscale/manitoba-dma.ph ; %include xscale/manitoba-gasket.ph ; %include xscale/manitoba-mmc.ph ;begin include file xscale/manitoba-udc.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; Again inconsitencies in spec! ; Compare register map (pg 27) with UDC description (pg 274) ; Not clear if UDCICR1 and UDCISR1 have any meaning ; Not clear if UDCCR0 exists ; State: preliminary ; -------------------------------------------------------------------------------- tree "UDC" ; -------------------------------------------------------------------------------- group asd:0x40600000++0x0423 line.long 0x000 "UDCCR,UDC Control Register" bitfld.long 0x000 11.--12. "ACN ,Active UDC Configuration Number" "0,1,2,3" bitfld.long 0x000 8.--10. " AIN ,Active UDC Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x000 5.--7. " AAISN ,Acitve UDC Alternate Interface Settin Number" "0,1,2,3,4,5,6,7" bitfld.long 0x000 4.--4. " SMAC ,Switch Endpoint Memory to Activ Config" "no,yes" bitfld.long 0x000 3.--3. " EMCE ,Endpoint Memory Config Error" "no,yes" bitfld.long 0x000 2.--2. " UDR ,UDC Resume" "maintain,wakeup" bitfld.long 0x000 1.--1. " UDA ,UDC is active" "no,yes" bitfld.long 0x000 0.--0. " UDE ,UDC is" "dis,ena" width 8. 10. line.long 0x004 "UDCICR0,UDC Interrupt Control Register 0" bitfld.long 0x004 16.--17. "IEH ,Interrupt Enables for Endpoint H" "dis/dis,dis/ena,ena/dis,ena/ena" bitfld.long 0x004 14.--15. "IEG ,Interrupt Enables for Endpoint G" "dis/dis,dis/ena,ena/dis,ena/ena" bitfld.long 0x004 12.--13. "IEF ,Interrupt Enables for Endpoint F" "dis/dis,dis/ena,ena/dis,ena/ena" textline " " bitfld.long 0x004 10.--11. "IEE ,Interrupt Enables for Endpoint E" "dis/dis,dis/ena,ena/dis,ena/ena" bitfld.long 0x004 8.--9. "IED ,Interrupt Enables for Endpoint D" "dis/dis,dis/ena,ena/dis,ena/ena" bitfld.long 0x004 6.--7. "IEC ,Interrupt Enables for Endpoint C" "dis/dis,dis/ena,ena/dis,ena/ena" textline " " bitfld.long 0x004 4.--5. "IEB ,Interrupt Enables for Endpoint B" "dis/dis,dis/ena,ena/dis,ena/ena" bitfld.long 0x004 2.--3. "IEA ,Interrupt Enables for Endpoint A" "dis/dis,dis/ena,ena/dis,ena/ena" bitfld.long 0x004 0.--1. "IE0 ,Interrupt Enables for Endpoint 0" "dis/dis,dis/ena,ena/dis,ena/ena" ; line.long 0x008 "UDCICR1,UDC Interrupt Control Register 1" width 8. 8. line.long 0x00C "UDCISR0,UDC Interrupt Status Register 0" bitfld.long 0x00C 31.--31. "IRCC ,Configuration Interrupt Request" "no,yes" bitfld.long 0x00C 30.--30. " IRSOF ,Start Of Fram Interrupt Request" "no,yes" bitfld.long 0x00C 29.--29. " IRRU ,Resume Interrupt Request" "no,yes" bitfld.long 0x00C 28.--28. " IRSU ,Suspend Interrupt Request" "no,yes" bitfld.long 0x00C 27.--27. " IRRS ,Reset Interrupt Request" "no,yes" textline " " bitfld.long 0x00c 16.--17. "IRH ,Endpoint H Interrupt Requests" "0/0,0/1,1/0,1/1" bitfld.long 0x00c 14.--15. " IRG ,Endpoint G Interrupt Requests" "0/0,0/1,1/0,1/1" bitfld.long 0x00c 12.--13. " IRF ,Endpoint F Interrupt Requests" "0/0,0/1,1/0,1/1" bitfld.long 0x00c 10.--11. " IRE ,Endpoint E Interrupt Requests" "0/0,0/1,1/0,1/1" bitfld.long 0x00c 8.--9. " IRD ,Endpoint D Interrupt Requests" "0/0,0/1,1/0,1/1" textline " " bitfld.long 0x00c 6.--7. "IRC ,Endpoint C Interrupt Requests" "0/0,0/1,1/0,1/1" bitfld.long 0x00c 4.--5. " IRB ,Endpoint B Interrupt Requests" "0/0,0/1,1/0,1/1" bitfld.long 0x00c 2.--3. " IRA ,Endpoint A Interrupt Requests" "0/0,0/1,1/0,1/1" bitfld.long 0x00c 0.--1. " IR0 ,Endpoint 0 Interrupt Requests" "0/0,0/1,1/0,1/1" ; line.long 0x010 "UDCISR1,UDC Interrupt Status Register 1" line.long 0x014 "UDCFNR,UDC Frame Number Register" hexmask.long 0x014 0.--10. 0x1 "FN ,Frame Number" tree "Endpoint 0" group asd:0x40600000++0x403 line.long 0x100 "UDCCSR0,UDC Control/Status Register Endpoint 0" bitfld.long 0x100 7. "SA ,Setup command is active" "no,yes" bitfld.long 0x100 6. " RNE ,Receive Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " FTF ,Flush Transmit FIFO" "nop,flsh" bitfld.long 0x100 1. " IPR ,IN Packet Ready" "no,yes" bitfld.long 0x100 0. " OPC ,OUT Packet Complete" "no,yes" line.long 0x200 "UDCBCR0,UDC Byte Count Register Endpoint 0" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDR0,UDC Data Register Endpoint 0" in tree.end tree "Endpoint A" ;begin include file xscale/manitoba-udc-endpoint.ph ;parameters: A 0x40600004 group asd:0x40600004++0x403 line.long 0x400 "UDCCRA,UDC Enpoint A Configuration Register" bitfld.long 0x400 25.--26. "CN ,Configuration Number" "0,1,2,3" bitfld.long 0x400 22.--24. " IN ,Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 19.--21. " AISN ,Alternate Interface Setting Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 15.--18. " EN ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x400 13.--14. " ET ,Endpoint Type" "---,isochr,bulk,intr" textline " " bitfld.long 0x400 12. "ED ,Endpoint Direction" "OUT,IN" hexmask.long 0x400 2.--11. 0x1 " MPS ,Maximum Packet Size" bitfld.long 0x400 1. " DE ,Double Buffering Enable" "dis,ena" bitfld.long 0x400 0. " EE ,Endpoint Enable" "dis,ena" line.long 0x100 "UDCCSRA,UDC Control/Status Register Endpoint A" bitfld.long 0x100 9. "DPE ,Data Packet Error" "no,yes" bitfld.long 0x100 8. " FEF ,Flush Endpoint Fifo" "nop,flsh" bitfld.long 0x100 7. " SP ,Short Packet Control/Status" "nop,rdy" bitfld.long 0x100 6. " FNE ,Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " EFE ,Endpoint Fifo Error" "no,yes" bitfld.long 0x100 1. " PC ,Packet is complete" "no,yes" bitfld.long 0x100 0. " FS ,Fifo needs service" "no,yes" line.long 0x200 "UDCBCRA,UDC Byte Count Register Endpoint A" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDRA,UDC Data Register Endpoint A" in ;end include file xscale/manitoba-udc-endpoint.ph tree.end tree "Endpoint B" ;begin include file xscale/manitoba-udc-endpoint.ph ;parameters: B 0x40600008 group asd:0x40600008++0x403 line.long 0x400 "UDCCRB,UDC Enpoint B Configuration Register" bitfld.long 0x400 25.--26. "CN ,Configuration Number" "0,1,2,3" bitfld.long 0x400 22.--24. " IN ,Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 19.--21. " AISN ,Alternate Interface Setting Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 15.--18. " EN ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x400 13.--14. " ET ,Endpoint Type" "---,isochr,bulk,intr" textline " " bitfld.long 0x400 12. "ED ,Endpoint Direction" "OUT,IN" hexmask.long 0x400 2.--11. 0x1 " MPS ,Maximum Packet Size" bitfld.long 0x400 1. " DE ,Double Buffering Enable" "dis,ena" bitfld.long 0x400 0. " EE ,Endpoint Enable" "dis,ena" line.long 0x100 "UDCCSRB,UDC Control/Status Register Endpoint B" bitfld.long 0x100 9. "DPE ,Data Packet Error" "no,yes" bitfld.long 0x100 8. " FEF ,Flush Endpoint Fifo" "nop,flsh" bitfld.long 0x100 7. " SP ,Short Packet Control/Status" "nop,rdy" bitfld.long 0x100 6. " FNE ,Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " EFE ,Endpoint Fifo Error" "no,yes" bitfld.long 0x100 1. " PC ,Packet is complete" "no,yes" bitfld.long 0x100 0. " FS ,Fifo needs service" "no,yes" line.long 0x200 "UDCBCRB,UDC Byte Count Register Endpoint B" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDRB,UDC Data Register Endpoint B" in ;end include file xscale/manitoba-udc-endpoint.ph tree.end tree "Endpoint C" ;begin include file xscale/manitoba-udc-endpoint.ph ;parameters: C 0x4060000C group asd:0x4060000C++0x403 line.long 0x400 "UDCCRC,UDC Enpoint C Configuration Register" bitfld.long 0x400 25.--26. "CN ,Configuration Number" "0,1,2,3" bitfld.long 0x400 22.--24. " IN ,Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 19.--21. " AISN ,Alternate Interface Setting Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 15.--18. " EN ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x400 13.--14. " ET ,Endpoint Type" "---,isochr,bulk,intr" textline " " bitfld.long 0x400 12. "ED ,Endpoint Direction" "OUT,IN" hexmask.long 0x400 2.--11. 0x1 " MPS ,Maximum Packet Size" bitfld.long 0x400 1. " DE ,Double Buffering Enable" "dis,ena" bitfld.long 0x400 0. " EE ,Endpoint Enable" "dis,ena" line.long 0x100 "UDCCSRC,UDC Control/Status Register Endpoint C" bitfld.long 0x100 9. "DPE ,Data Packet Error" "no,yes" bitfld.long 0x100 8. " FEF ,Flush Endpoint Fifo" "nop,flsh" bitfld.long 0x100 7. " SP ,Short Packet Control/Status" "nop,rdy" bitfld.long 0x100 6. " FNE ,Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " EFE ,Endpoint Fifo Error" "no,yes" bitfld.long 0x100 1. " PC ,Packet is complete" "no,yes" bitfld.long 0x100 0. " FS ,Fifo needs service" "no,yes" line.long 0x200 "UDCBCRC,UDC Byte Count Register Endpoint C" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDRC,UDC Data Register Endpoint C" in ;end include file xscale/manitoba-udc-endpoint.ph tree.end tree "Endpoint D" ;begin include file xscale/manitoba-udc-endpoint.ph ;parameters: D 0x40600010 group asd:0x40600010++0x403 line.long 0x400 "UDCCRD,UDC Enpoint D Configuration Register" bitfld.long 0x400 25.--26. "CN ,Configuration Number" "0,1,2,3" bitfld.long 0x400 22.--24. " IN ,Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 19.--21. " AISN ,Alternate Interface Setting Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 15.--18. " EN ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x400 13.--14. " ET ,Endpoint Type" "---,isochr,bulk,intr" textline " " bitfld.long 0x400 12. "ED ,Endpoint Direction" "OUT,IN" hexmask.long 0x400 2.--11. 0x1 " MPS ,Maximum Packet Size" bitfld.long 0x400 1. " DE ,Double Buffering Enable" "dis,ena" bitfld.long 0x400 0. " EE ,Endpoint Enable" "dis,ena" line.long 0x100 "UDCCSRD,UDC Control/Status Register Endpoint D" bitfld.long 0x100 9. "DPE ,Data Packet Error" "no,yes" bitfld.long 0x100 8. " FEF ,Flush Endpoint Fifo" "nop,flsh" bitfld.long 0x100 7. " SP ,Short Packet Control/Status" "nop,rdy" bitfld.long 0x100 6. " FNE ,Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " EFE ,Endpoint Fifo Error" "no,yes" bitfld.long 0x100 1. " PC ,Packet is complete" "no,yes" bitfld.long 0x100 0. " FS ,Fifo needs service" "no,yes" line.long 0x200 "UDCBCRD,UDC Byte Count Register Endpoint D" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDRD,UDC Data Register Endpoint D" in ;end include file xscale/manitoba-udc-endpoint.ph tree.end tree "Endpoint E" ;begin include file xscale/manitoba-udc-endpoint.ph ;parameters: E 0x40600014 group asd:0x40600014++0x403 line.long 0x400 "UDCCRE,UDC Enpoint E Configuration Register" bitfld.long 0x400 25.--26. "CN ,Configuration Number" "0,1,2,3" bitfld.long 0x400 22.--24. " IN ,Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 19.--21. " AISN ,Alternate Interface Setting Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 15.--18. " EN ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x400 13.--14. " ET ,Endpoint Type" "---,isochr,bulk,intr" textline " " bitfld.long 0x400 12. "ED ,Endpoint Direction" "OUT,IN" hexmask.long 0x400 2.--11. 0x1 " MPS ,Maximum Packet Size" bitfld.long 0x400 1. " DE ,Double Buffering Enable" "dis,ena" bitfld.long 0x400 0. " EE ,Endpoint Enable" "dis,ena" line.long 0x100 "UDCCSRE,UDC Control/Status Register Endpoint E" bitfld.long 0x100 9. "DPE ,Data Packet Error" "no,yes" bitfld.long 0x100 8. " FEF ,Flush Endpoint Fifo" "nop,flsh" bitfld.long 0x100 7. " SP ,Short Packet Control/Status" "nop,rdy" bitfld.long 0x100 6. " FNE ,Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " EFE ,Endpoint Fifo Error" "no,yes" bitfld.long 0x100 1. " PC ,Packet is complete" "no,yes" bitfld.long 0x100 0. " FS ,Fifo needs service" "no,yes" line.long 0x200 "UDCBCRE,UDC Byte Count Register Endpoint E" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDRE,UDC Data Register Endpoint E" in ;end include file xscale/manitoba-udc-endpoint.ph tree.end tree "Endpoint F" ;begin include file xscale/manitoba-udc-endpoint.ph ;parameters: F 0x40600018 group asd:0x40600018++0x403 line.long 0x400 "UDCCRF,UDC Enpoint F Configuration Register" bitfld.long 0x400 25.--26. "CN ,Configuration Number" "0,1,2,3" bitfld.long 0x400 22.--24. " IN ,Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 19.--21. " AISN ,Alternate Interface Setting Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 15.--18. " EN ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x400 13.--14. " ET ,Endpoint Type" "---,isochr,bulk,intr" textline " " bitfld.long 0x400 12. "ED ,Endpoint Direction" "OUT,IN" hexmask.long 0x400 2.--11. 0x1 " MPS ,Maximum Packet Size" bitfld.long 0x400 1. " DE ,Double Buffering Enable" "dis,ena" bitfld.long 0x400 0. " EE ,Endpoint Enable" "dis,ena" line.long 0x100 "UDCCSRF,UDC Control/Status Register Endpoint F" bitfld.long 0x100 9. "DPE ,Data Packet Error" "no,yes" bitfld.long 0x100 8. " FEF ,Flush Endpoint Fifo" "nop,flsh" bitfld.long 0x100 7. " SP ,Short Packet Control/Status" "nop,rdy" bitfld.long 0x100 6. " FNE ,Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " EFE ,Endpoint Fifo Error" "no,yes" bitfld.long 0x100 1. " PC ,Packet is complete" "no,yes" bitfld.long 0x100 0. " FS ,Fifo needs service" "no,yes" line.long 0x200 "UDCBCRF,UDC Byte Count Register Endpoint F" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDRF,UDC Data Register Endpoint F" in ;end include file xscale/manitoba-udc-endpoint.ph tree.end tree "Endpoint G" ;begin include file xscale/manitoba-udc-endpoint.ph ;parameters: G 0x4060001C group asd:0x4060001C++0x403 line.long 0x400 "UDCCRG,UDC Enpoint G Configuration Register" bitfld.long 0x400 25.--26. "CN ,Configuration Number" "0,1,2,3" bitfld.long 0x400 22.--24. " IN ,Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 19.--21. " AISN ,Alternate Interface Setting Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 15.--18. " EN ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x400 13.--14. " ET ,Endpoint Type" "---,isochr,bulk,intr" textline " " bitfld.long 0x400 12. "ED ,Endpoint Direction" "OUT,IN" hexmask.long 0x400 2.--11. 0x1 " MPS ,Maximum Packet Size" bitfld.long 0x400 1. " DE ,Double Buffering Enable" "dis,ena" bitfld.long 0x400 0. " EE ,Endpoint Enable" "dis,ena" line.long 0x100 "UDCCSRG,UDC Control/Status Register Endpoint G" bitfld.long 0x100 9. "DPE ,Data Packet Error" "no,yes" bitfld.long 0x100 8. " FEF ,Flush Endpoint Fifo" "nop,flsh" bitfld.long 0x100 7. " SP ,Short Packet Control/Status" "nop,rdy" bitfld.long 0x100 6. " FNE ,Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " EFE ,Endpoint Fifo Error" "no,yes" bitfld.long 0x100 1. " PC ,Packet is complete" "no,yes" bitfld.long 0x100 0. " FS ,Fifo needs service" "no,yes" line.long 0x200 "UDCBCRG,UDC Byte Count Register Endpoint G" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDRG,UDC Data Register Endpoint G" in ;end include file xscale/manitoba-udc-endpoint.ph tree.end tree "Endpoint H" ;begin include file xscale/manitoba-udc-endpoint.ph ;parameters: H 0x40600020 group asd:0x40600020++0x403 line.long 0x400 "UDCCRH,UDC Enpoint H Configuration Register" bitfld.long 0x400 25.--26. "CN ,Configuration Number" "0,1,2,3" bitfld.long 0x400 22.--24. " IN ,Interface Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 19.--21. " AISN ,Alternate Interface Setting Number" "0,1,2,3,4,5,6,7" bitfld.long 0x400 15.--18. " EN ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x400 13.--14. " ET ,Endpoint Type" "---,isochr,bulk,intr" textline " " bitfld.long 0x400 12. "ED ,Endpoint Direction" "OUT,IN" hexmask.long 0x400 2.--11. 0x1 " MPS ,Maximum Packet Size" bitfld.long 0x400 1. " DE ,Double Buffering Enable" "dis,ena" bitfld.long 0x400 0. " EE ,Endpoint Enable" "dis,ena" line.long 0x100 "UDCCSRH,UDC Control/Status Register Endpoint H" bitfld.long 0x100 9. "DPE ,Data Packet Error" "no,yes" bitfld.long 0x100 8. " FEF ,Flush Endpoint Fifo" "nop,flsh" bitfld.long 0x100 7. " SP ,Short Packet Control/Status" "nop,rdy" bitfld.long 0x100 6. " FNE ,Fifo is empty" "yes,no" bitfld.long 0x100 5. " FST ,Force Stall" "nop,stall" textline " " bitfld.long 0x100 4. "SST ,Sent Stall" "nop,sent" bitfld.long 0x100 3. " DME ,DMA Enable" "dis,ena" bitfld.long 0x100 2. " EFE ,Endpoint Fifo Error" "no,yes" bitfld.long 0x100 1. " PC ,Packet is complete" "no,yes" bitfld.long 0x100 0. " FS ,Fifo needs service" "no,yes" line.long 0x200 "UDCBCRH,UDC Byte Count Register Endpoint H" hexmask.long 0x200 0.--9. 0x1 "BC ,Byte Count" hide.long 0x300 "UDCDRH,UDC Data Register Endpoint H" in ;end include file xscale/manitoba-udc-endpoint.ph tree.end tree.end ;end include file xscale/manitoba-udc.ph ;begin include file xscale/manitoba-bbi.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; From "Manitoba Architecture Specification" rev 0.75 ; Inconsistencies : Where are Channel 0 and Channel 5-15 Registers ?? ; What are Register BBLxxx ? ; State: preliminary ; -------------------------------------------------------------------------------- tree "Baseband Interface" ; -------------------------------------------------------------------------------- group asd:0x50100000++0x17F line.long 0x100 "BBCSTP ,Channel stop threshold register" bitfld.long 0x100 0.--2. "Threshold ,Threshold in bytes" "0,1,2,3,4,5,6,7" line.long 0x104 "BBCSTR ,Channel start threshold register" bitfld.long 0x104 0.--2. "Threshold ,Threshold in bytes" "0,1,2,3,4,5,6,7" line.long 0x108 "BBI1ID ,INT1 Interrupt ID register" hexmask.long 0x108 17.--23. 0x1 "TX_INT ,Transmit FIFO interrupt for channel" hexmask.long 0x108 1.--7. 0x1 " RX_INT ,Receive FIO interrupt for channel" bitfld.long 0x108 0. " GPIO_INT ,GPIO interrupt" "no,yes" line.long 0x10C "BBI2ID ,INT2 Interrupt ID register" hexmask.long 0x10C 17.--23. 0x1 "TX_INT ,Transmit FIFO interrupt for channel" hexmask.long 0x10C 1.--7. 0x1 " RX_INT ,Receive FIO interrupt for channel" bitfld.long 0x10C 0. " GPIO_INT ,GPIO interrupt" "no,yes" line.long 0x110 "BBFREQ ,Transmit frequency select register" hexfld.byte 0x110 "DIV ,BB_INT_CLK clock divider" line.long 0x114 "BBWAIT ,Wait count register" hexfld.word 0x114 "Count ,Number of clock cycles before retrying" line.long 0x118 "BBCST ,Clock stop time register" bitfld.long 0x118 0.--3. "Count ,Number of clock cycles before turning off clock" "1,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree "Virtual GPIOs" group asd:0x50100000++0x17F line.long 0x11C "BBVGIL ,Virtual GPIO input pin level register" Bitfld.long 0x11C 31. "p31 ,Pin 31" "L,H" Bitfld.long 0x11C 30. " p30 ,Pin 30" "L,H" Bitfld.long 0x11C 29. " p29 ,Pin 29" "L,H" Bitfld.long 0x11C 28. " p28 ,Pin 28" "L,H" Bitfld.long 0x11C 27. " p27 ,Pin 27" "L,H" Bitfld.long 0x11C 26. " p26 ,Pin 26" "L,H" Bitfld.long 0x11C 25. " p25 ,Pin 25" "L,H" Bitfld.long 0x11C 24. " p24 ,Pin 24" "L,H" textline " " Bitfld.long 0x11C 23. "p23 ,Pin 23" "L,H" Bitfld.long 0x11C 22. " p22 ,Pin 22" "L,H" Bitfld.long 0x11C 21. " p21 ,Pin 21" "L,H" Bitfld.long 0x11C 20. " p20 ,Pin 20" "L,H" Bitfld.long 0x11C 19. " p19 ,Pin 19" "L,H" Bitfld.long 0x11C 18. " p18 ,Pin 18" "L,H" Bitfld.long 0x11C 17. " p17 ,Pin 17" "L,H" Bitfld.long 0x11C 16. " p16 ,Pin 16" "L,H" textline " " Bitfld.long 0x11C 15. "p15 ,Pin 15" "L,H" Bitfld.long 0x11C 14. " p14 ,Pin 14" "L,H" Bitfld.long 0x11C 13. " p13 ,Pin 13" "L,H" Bitfld.long 0x11C 12. " p12 ,Pin 12" "L,H" Bitfld.long 0x11C 11. " p11 ,Pin 11" "L,H" Bitfld.long 0x11C 10. " p10 ,Pin 10" "L,H" Bitfld.long 0x11C 9. " p9 ,Pin 9" "L,H" Bitfld.long 0x11C 8. " p8 ,Pin 8" "L,H" textline " " Bitfld.long 0x11C 7. " p7 ,Pin 7" "L,H" Bitfld.long 0x11C 6. " p6 ,Pin 6" "L,H" Bitfld.long 0x11C 5. " p5 ,Pin 5" "L,H" Bitfld.long 0x11C 4. " p4 ,Pin 4" "L,H" Bitfld.long 0x11C 3. " p3 ,Pin 3" "L,H" Bitfld.long 0x11C 2. " p2 ,Pin 2" "L,H" Bitfld.long 0x11C 1. " p1 ,Pin 1" "L,H" Bitfld.long 0x11C 0. " p0 ,Pin 0" "L,H" line.long 0x120 "BBVGOL ,Virtual GPIO output pin level register" Bitfld.long 0x120 31. "p31 ,Pin 31" "L,H" Bitfld.long 0x120 30. " p30 ,Pin 30" "L,H" Bitfld.long 0x120 29. " p29 ,Pin 29" "L,H" Bitfld.long 0x120 28. " p28 ,Pin 28" "L,H" Bitfld.long 0x120 27. " p27 ,Pin 27" "L,H" Bitfld.long 0x120 26. " p26 ,Pin 26" "L,H" Bitfld.long 0x120 25. " p25 ,Pin 25" "L,H" Bitfld.long 0x120 24. " p24 ,Pin 24" "L,H" textline " " Bitfld.long 0x120 23. "p23 ,Pin 23" "L,H" Bitfld.long 0x120 22. " p22 ,Pin 22" "L,H" Bitfld.long 0x120 21. " p21 ,Pin 21" "L,H" Bitfld.long 0x120 20. " p20 ,Pin 20" "L,H" Bitfld.long 0x120 19. " p19 ,Pin 19" "L,H" Bitfld.long 0x120 18. " p18 ,Pin 18" "L,H" Bitfld.long 0x120 17. " p17 ,Pin 17" "L,H" Bitfld.long 0x120 16. " p16 ,Pin 16" "L,H" textline " " Bitfld.long 0x120 15. "p15 ,Pin 15" "L,H" Bitfld.long 0x120 14. " p14 ,Pin 14" "L,H" Bitfld.long 0x120 13. " p13 ,Pin 13" "L,H" Bitfld.long 0x120 12. " p12 ,Pin 12" "L,H" Bitfld.long 0x120 11. " p11 ,Pin 11" "L,H" Bitfld.long 0x120 10. " p10 ,Pin 10" "L,H" Bitfld.long 0x120 9. " p9 ,Pin 9" "L,H" Bitfld.long 0x120 8. " p8 ,Pin 8" "L,H" textline " " Bitfld.long 0x120 7. " p7 ,Pin 7" "L,H" Bitfld.long 0x120 6. " p6 ,Pin 6" "L,H" Bitfld.long 0x120 5. " p5 ,Pin 5" "L,H" Bitfld.long 0x120 4. " p4 ,Pin 4" "L,H" Bitfld.long 0x120 3. " p3 ,Pin 3" "L,H" Bitfld.long 0x120 2. " p2 ,Pin 2" "L,H" Bitfld.long 0x120 1. " p1 ,Pin 1" "L,H" Bitfld.long 0x120 0. " p0 ,Pin 0" "L,H" line.long 0x124 "BBVGSR ,Virtual GPIO output pin set register" Bitfld.long 0x124 31. "p31 ,Pin 31" "-,H" Bitfld.long 0x124 30. " p30 ,Pin 30" "-,H" Bitfld.long 0x124 29. " p29 ,Pin 29" "-,H" Bitfld.long 0x124 28. " p28 ,Pin 28" "-,H" Bitfld.long 0x124 27. " p27 ,Pin 27" "-,H" Bitfld.long 0x124 26. " p26 ,Pin 26" "-,H" Bitfld.long 0x124 25. " p25 ,Pin 25" "-,H" Bitfld.long 0x124 24. " p24 ,Pin 24" "-,H" textline " " Bitfld.long 0x124 23. "p23 ,Pin 23" "-,H" Bitfld.long 0x124 22. " p22 ,Pin 22" "-,H" Bitfld.long 0x124 21. " p21 ,Pin 21" "-,H" Bitfld.long 0x124 20. " p20 ,Pin 20" "-,H" Bitfld.long 0x124 19. " p19 ,Pin 19" "-,H" Bitfld.long 0x124 18. " p18 ,Pin 18" "-,H" Bitfld.long 0x124 17. " p17 ,Pin 17" "-,H" Bitfld.long 0x124 16. " p16 ,Pin 16" "-,H" textline " " Bitfld.long 0x124 15. "p15 ,Pin 15" "-,H" Bitfld.long 0x124 14. " p14 ,Pin 14" "-,H" Bitfld.long 0x124 13. " p13 ,Pin 13" "-,H" Bitfld.long 0x124 12. " p12 ,Pin 12" "-,H" Bitfld.long 0x124 11. " p11 ,Pin 11" "-,H" Bitfld.long 0x124 10. " p10 ,Pin 10" "-,H" Bitfld.long 0x124 9. " p9 ,Pin 9" "-,H" Bitfld.long 0x124 8. " p8 ,Pin 8" "-,H" textline " " Bitfld.long 0x124 7. " p7 ,Pin 7" "-,H" Bitfld.long 0x124 6. " p6 ,Pin 6" "-,H" Bitfld.long 0x124 5. " p5 ,Pin 5" "-,H" Bitfld.long 0x124 4. " p4 ,Pin 4" "-,H" Bitfld.long 0x124 3. " p3 ,Pin 3" "-,H" Bitfld.long 0x124 2. " p2 ,Pin 2" "-,H" Bitfld.long 0x124 1. " p1 ,Pin 1" "-,H" Bitfld.long 0x124 0. " p0 ,Pin 0" "-,H" line.long 0x128 "BBVGCR ,Virtual GPIO output pin clear register" Bitfld.long 0x128 31. "p31 ,Pin 31" "-,L" Bitfld.long 0x128 30. " p30 ,Pin 30" "-,L" Bitfld.long 0x128 29. " p29 ,Pin 29" "-,L" Bitfld.long 0x128 28. " p28 ,Pin 28" "-,L" Bitfld.long 0x128 27. " p27 ,Pin 27" "-,L" Bitfld.long 0x128 26. " p26 ,Pin 26" "-,L" Bitfld.long 0x128 25. " p25 ,Pin 25" "-,L" Bitfld.long 0x128 24. " p24 ,Pin 24" "-,L" textline " " Bitfld.long 0x128 23. "p23 ,Pin 23" "-,L" Bitfld.long 0x128 22. " p22 ,Pin 22" "-,L" Bitfld.long 0x128 21. " p21 ,Pin 21" "-,L" Bitfld.long 0x128 20. " p20 ,Pin 20" "-,L" Bitfld.long 0x128 19. " p19 ,Pin 19" "-,L" Bitfld.long 0x128 18. " p18 ,Pin 18" "-,L" Bitfld.long 0x128 17. " p17 ,Pin 17" "-,L" Bitfld.long 0x128 16. " p16 ,Pin 16" "-,L" textline " " Bitfld.long 0x128 15. "p15 ,Pin 15" "-,L" Bitfld.long 0x128 14. " p14 ,Pin 14" "-,L" Bitfld.long 0x128 13. " p13 ,Pin 13" "-,L" Bitfld.long 0x128 12. " p12 ,Pin 12" "-,L" Bitfld.long 0x128 11. " p11 ,Pin 11" "-,L" Bitfld.long 0x128 10. " p10 ,Pin 10" "-,L" Bitfld.long 0x128 9. " p9 ,Pin 9" "-,L" Bitfld.long 0x128 8. " p8 ,Pin 8" "-,L" textline " " Bitfld.long 0x128 7. " p7 ,Pin 7" "-,L" Bitfld.long 0x128 6. " p6 ,Pin 6" "-,L" Bitfld.long 0x128 5. " p5 ,Pin 5" "-,L" Bitfld.long 0x128 4. " p4 ,Pin 4" "-,L" Bitfld.long 0x128 3. " p3 ,Pin 3" "-,L" Bitfld.long 0x128 2. " p2 ,Pin 2" "-,L" Bitfld.long 0x128 1. " p1 ,Pin 1" "-,L" Bitfld.long 0x128 0. " p0 ,Pin 0" "-,L" line.long 0x12C "BBVGRE ,Virtual GPIO rising edge detect register" Bitfld.long 0x12C 31. "p31 ,Pin 31 rising edge detect" "dis,ena" Bitfld.long 0x12C 30. " p30 ,Pin 30 rising edge detect" "dis,ena" Bitfld.long 0x12C 29. " p29 ,Pin 29 rising edge detect" "dis,ena" Bitfld.long 0x12C 28. " p28 ,Pin 28 rising edge detect" "dis,ena" Bitfld.long 0x12C 27. " p27 ,Pin 27 rising edge detect" "dis,ena" Bitfld.long 0x12C 26. " p26 ,Pin 26 rising edge detect" "dis,ena" Bitfld.long 0x12C 25. " p25 ,Pin 25 rising edge detect" "dis,ena" Bitfld.long 0x12C 24. " p24 ,Pin 24 rising edge detect" "dis,ena" textline " " Bitfld.long 0x12C 23. "p23 ,Pin 23 rising edge detect" "dis,ena" Bitfld.long 0x12C 22. " p22 ,Pin 22 rising edge detect" "dis,ena" Bitfld.long 0x12C 21. " p21 ,Pin 21 rising edge detect" "dis,ena" Bitfld.long 0x12C 20. " p20 ,Pin 20 rising edge detect" "dis,ena" Bitfld.long 0x12C 19. " p19 ,Pin 19 rising edge detect" "dis,ena" Bitfld.long 0x12C 18. " p18 ,Pin 18 rising edge detect" "dis,ena" Bitfld.long 0x12C 17. " p17 ,Pin 17 rising edge detect" "dis,ena" Bitfld.long 0x12C 16. " p16 ,Pin 16 rising edge detect" "dis,ena" textline " " Bitfld.long 0x12C 15. "p15 ,Pin 15 rising edge detect" "dis,ena" Bitfld.long 0x12C 14. " p14 ,Pin 14 rising edge detect" "dis,ena" Bitfld.long 0x12C 13. " p13 ,Pin 13 rising edge detect" "dis,ena" Bitfld.long 0x12C 12. " p12 ,Pin 12 rising edge detect" "dis,ena" Bitfld.long 0x12C 11. " p11 ,Pin 11 rising edge detect" "dis,ena" Bitfld.long 0x12C 10. " p10 ,Pin 10 rising edge detect" "dis,ena" Bitfld.long 0x12C 9. " p9 ,Pin 9 rising edge detect" "dis,ena" Bitfld.long 0x12C 8. " p8 ,Pin 8 rising edge detect" "dis,ena" textline " " Bitfld.long 0x12C 7. " p7 ,Pin 7 rising edge detect" "dis,ena" Bitfld.long 0x12C 6. " p6 ,Pin 6 rising edge detect" "dis,ena" Bitfld.long 0x12C 5. " p5 ,Pin 5 rising edge detect" "dis,ena" Bitfld.long 0x12C 4. " p4 ,Pin 4 rising edge detect" "dis,ena" Bitfld.long 0x12C 3. " p3 ,Pin 3 rising edge detect" "dis,ena" Bitfld.long 0x12C 2. " p2 ,Pin 2 rising edge detect" "dis,ena" Bitfld.long 0x12C 1. " p1 ,Pin 1 rising edge detect" "dis,ena" Bitfld.long 0x12C 0. " p0 ,Pin 0 rising edge detect" "dis,ena" line.long 0x130 "BBVGFE ,Virtual GPIO falling edge detect register" Bitfld.long 0x130 31. "p31 ,Pin 31 falling edge detect" "dis,ena" Bitfld.long 0x130 30. " p30 ,Pin 30 falling edge detect" "dis,ena" Bitfld.long 0x130 29. " p29 ,Pin 29 falling edge detect" "dis,ena" Bitfld.long 0x130 28. " p28 ,Pin 28 falling edge detect" "dis,ena" Bitfld.long 0x130 27. " p27 ,Pin 27 falling edge detect" "dis,ena" Bitfld.long 0x130 26. " p26 ,Pin 26 falling edge detect" "dis,ena" Bitfld.long 0x130 25. " p25 ,Pin 25 falling edge detect" "dis,ena" Bitfld.long 0x130 24. " p24 ,Pin 24 falling edge detect" "dis,ena" textline " " Bitfld.long 0x130 23. "p23 ,Pin 23 falling edge detect" "dis,ena" Bitfld.long 0x130 22. " p22 ,Pin 22 falling edge detect" "dis,ena" Bitfld.long 0x130 21. " p21 ,Pin 21 falling edge detect" "dis,ena" Bitfld.long 0x130 20. " p20 ,Pin 20 falling edge detect" "dis,ena" Bitfld.long 0x130 19. " p19 ,Pin 19 falling edge detect" "dis,ena" Bitfld.long 0x130 18. " p18 ,Pin 18 falling edge detect" "dis,ena" Bitfld.long 0x130 17. " p17 ,Pin 17 falling edge detect" "dis,ena" Bitfld.long 0x130 16. " p16 ,Pin 16 falling edge detect" "dis,ena" textline " " Bitfld.long 0x130 15. "p15 ,Pin 15 falling edge detect" "dis,ena" Bitfld.long 0x130 14. " p14 ,Pin 14 falling edge detect" "dis,ena" Bitfld.long 0x130 13. " p13 ,Pin 13 falling edge detect" "dis,ena" Bitfld.long 0x130 12. " p12 ,Pin 12 falling edge detect" "dis,ena" Bitfld.long 0x130 11. " p11 ,Pin 11 falling edge detect" "dis,ena" Bitfld.long 0x130 10. " p10 ,Pin 10 falling edge detect" "dis,ena" Bitfld.long 0x130 9. " p9 ,Pin 9 falling edge detect" "dis,ena" Bitfld.long 0x130 8. " p8 ,Pin 8 falling edge detect" "dis,ena" textline " " Bitfld.long 0x130 7. " p7 ,Pin 7 falling edge detect" "dis,ena" Bitfld.long 0x130 6. " p6 ,Pin 6 falling edge detect" "dis,ena" Bitfld.long 0x130 5. " p5 ,Pin 5 falling edge detect" "dis,ena" Bitfld.long 0x130 4. " p4 ,Pin 4 falling edge detect" "dis,ena" Bitfld.long 0x130 3. " p3 ,Pin 3 falling edge detect" "dis,ena" Bitfld.long 0x130 2. " p2 ,Pin 2 falling edge detect" "dis,ena" Bitfld.long 0x130 1. " p1 ,Pin 1 falling edge detect" "dis,ena" Bitfld.long 0x130 0. " p0 ,Pin 0 falling edge detect" "dis,ena" line.long 0x134 "BBVGED ,Virtual GPIO edge detect status register" Bitfld.long 0x134 31. "p31 ,Pin 31 edge occured" "no,yes" Bitfld.long 0x134 30. " p30 ,Pin 30 edge occured" "no,yes" Bitfld.long 0x134 29. " p29 ,Pin 29 edge occured" "no,yes" Bitfld.long 0x134 28. " p28 ,Pin 28 edge occured" "no,yes" Bitfld.long 0x134 27. " p27 ,Pin 27 edge occured" "no,yes" Bitfld.long 0x134 26. " p26 ,Pin 26 edge occured" "no,yes" Bitfld.long 0x134 25. " p25 ,Pin 25 edge occured" "no,yes" Bitfld.long 0x134 24. " p24 ,Pin 24 edge occured" "no,yes" textline " " Bitfld.long 0x134 23. "p23 ,Pin 23 edge occured" "no,yes" Bitfld.long 0x134 22. " p22 ,Pin 22 edge occured" "no,yes" Bitfld.long 0x134 21. " p21 ,Pin 21 edge occured" "no,yes" Bitfld.long 0x134 20. " p20 ,Pin 20 edge occured" "no,yes" Bitfld.long 0x134 19. " p19 ,Pin 19 edge occured" "no,yes" Bitfld.long 0x134 18. " p18 ,Pin 18 edge occured" "no,yes" Bitfld.long 0x134 17. " p17 ,Pin 17 edge occured" "no,yes" Bitfld.long 0x134 16. " p16 ,Pin 16 edge occured" "no,yes" textline " " Bitfld.long 0x134 15. "p15 ,Pin 15 edge occured" "no,yes" Bitfld.long 0x134 14. " p14 ,Pin 14 edge occured" "no,yes" Bitfld.long 0x134 13. " p13 ,Pin 13 edge occured" "no,yes" Bitfld.long 0x134 12. " p12 ,Pin 12 edge occured" "no,yes" Bitfld.long 0x134 11. " p11 ,Pin 11 edge occured" "no,yes" Bitfld.long 0x134 10. " p10 ,Pin 10 edge occured" "no,yes" Bitfld.long 0x134 9. " p9 ,Pin 9 edge occured" "no,yes" Bitfld.long 0x134 8. " p8 ,Pin 8 edge occured" "no,yes" textline " " Bitfld.long 0x134 7. " p7 ,Pin 7 edge occured" "no,yes" Bitfld.long 0x134 6. " p6 ,Pin 6 edge occured" "no,yes" Bitfld.long 0x134 5. " p5 ,Pin 5 edge occured" "no,yes" Bitfld.long 0x134 4. " p4 ,Pin 4 edge occured" "no,yes" Bitfld.long 0x134 3. " p3 ,Pin 3 edge occured" "no,yes" Bitfld.long 0x134 2. " p2 ,Pin 2 edge occured" "no,yes" Bitfld.long 0x134 1. " p1 ,Pin 1 edge occured" "no,yes" Bitfld.long 0x134 0. " p0 ,Pin 0 edge occured" "no,yes" line.long 0x138 "BBVGIT ,Virtual GPIO interrupt type register" Bitfld.long 0x138 31. "p31 ,Pin 31 interrupt tyte" "I1,I2" Bitfld.long 0x138 30. " p30 ,Pin 30 interrupt tyte" "I1,I2" Bitfld.long 0x138 29. " p29 ,Pin 29 interrupt tyte" "I1,I2" Bitfld.long 0x138 28. " p28 ,Pin 28 interrupt tyte" "I1,I2" Bitfld.long 0x138 27. " p27 ,Pin 27 interrupt tyte" "I1,I2" Bitfld.long 0x138 26. " p26 ,Pin 26 interrupt tyte" "I1,I2" Bitfld.long 0x138 25. " p25 ,Pin 25 interrupt tyte" "I1,I2" Bitfld.long 0x138 24. " p24 ,Pin 24 interrupt tyte" "I1,I2" textline " " Bitfld.long 0x138 23. "p23 ,Pin 23 interrupt tyte" "I1,I2" Bitfld.long 0x138 22. " p22 ,Pin 22 interrupt tyte" "I1,I2" Bitfld.long 0x138 21. " p21 ,Pin 21 interrupt tyte" "I1,I2" Bitfld.long 0x138 20. " p20 ,Pin 20 interrupt tyte" "I1,I2" Bitfld.long 0x138 19. " p19 ,Pin 19 interrupt tyte" "I1,I2" Bitfld.long 0x138 18. " p18 ,Pin 18 interrupt tyte" "I1,I2" Bitfld.long 0x138 17. " p17 ,Pin 17 interrupt tyte" "I1,I2" Bitfld.long 0x138 16. " p16 ,Pin 16 interrupt tyte" "I1,I2" textline " " Bitfld.long 0x138 15. "p15 ,Pin 15 interrupt tyte" "I1,I2" Bitfld.long 0x138 14. " p14 ,Pin 14 interrupt tyte" "I1,I2" Bitfld.long 0x138 13. " p13 ,Pin 13 interrupt tyte" "I1,I2" Bitfld.long 0x138 12. " p12 ,Pin 12 interrupt tyte" "I1,I2" Bitfld.long 0x138 11. " p11 ,Pin 11 interrupt tyte" "I1,I2" Bitfld.long 0x138 10. " p10 ,Pin 10 interrupt tyte" "I1,I2" Bitfld.long 0x138 9. " p9 ,Pin 9 interrupt tyte" "I1,I2" Bitfld.long 0x138 8. " p8 ,Pin 8 interrupt tyte" "I1,I2" textline " " Bitfld.long 0x138 7. " p7 ,Pin 7 interrupt tyte" "I1,I2" Bitfld.long 0x138 6. " p6 ,Pin 6 interrupt tyte" "I1,I2" Bitfld.long 0x138 5. " p5 ,Pin 5 interrupt tyte" "I1,I2" Bitfld.long 0x138 4. " p4 ,Pin 4 interrupt tyte" "I1,I2" Bitfld.long 0x138 3. " p3 ,Pin 3 interrupt tyte" "I1,I2" Bitfld.long 0x138 2. " p2 ,Pin 2 interrupt tyte" "I1,I2" Bitfld.long 0x138 1. " p1 ,Pin 1 interrupt tyte" "I1,I2" Bitfld.long 0x138 0. " p0 ,Pin 0 interrupt tyte" "I1,I2" tree.end tree "Channel 1" ;begin include file xscale/manitoba-bbi-channel.ph ;parameters: 1 0x0 group asd:(0x50100000+0x0)++0xC7 line.long 0x44 "BBCFG1 ,Channel 1 congiguration register" bitfld.long 0x44 21.--23. "RxService ,Receive FIFO service select" "none,DMA,INT1,INT2,res,res,res,res" bitfld.long 0x44 19.--20. " RxThreshLevel ,Receive FIFO service threshold" "4,8,16,32" bitfld.long 0x44 18. " RxDFCenable ,Direct Flow Control enable" "dis,ena" bitfld.long 0x44 17. " RxMFCenable ,Message Flow Control enable" "dis,ena" textline " " bitfld.long 0x44 8.--10. "TxBlock ,Transmit block size" "4,8,16,32,res,res,res,res" bitfld.long 0x44 5.--7. " TxService ,Transmit FIFO service select" "none,DMA,INT1,INT2,res,res,res,res" bitfld.long 0x44 3.--4. " TxThreshLevel ,Transmit FIFO service threshold" "4,8,16,32" bitfld.long 0x44 2. " TxDFCenable ,Direct Flow Control enable" "dis,ena" textline " " bitfld.long 0x44 1. "TxMFCenable ,Message Flow Control enable" "dis,ena" bitfld.long 0x44 0. " TxEnable ,Transmit FIFO channel enable" "dis,ena" line.long 0x84 "BBSTAT1 ,Channel 1 status register" bitfld.long 0x84 24. "RxWait ,Receive channel is in wait state" "no,yes" bitfld.long 0x84 23. " RxEmpty ,Receive FIFO is empty" "no,yes" bitfld.long 0x84 22. " RxFull ,Receive FIFO is full" "no,yes" hexmask.long 0x84 16.--21. 0x1 " RxFullness ,Fullness of receive Fifo" textline " " bitfld.long 0x84 8. "TxWait ,Transmit channel is in wait state" "no,yes" bitfld.long 0x84 7. " TxEmpty ,Transmit FIFO is empty" "no,yes" bitfld.long 0x84 6. " TxFull ,Transmit FIFO is full" "no,yes" hexmask.long 0x84 0.--5. 0x1 " TxFullness ,Fullness of transmit Fifo" hide.long 0x04 "BBFIFO1 ,Channel 1 transmit FIFO register" in hide.long 0xC4 "BBEOM1 ,Channel 1 EndOfMessage register" ;end include file xscale/manitoba-bbi-channel.ph tree.end tree "Channel 2" ;begin include file xscale/manitoba-bbi-channel.ph ;parameters: 2 0x4 group asd:(0x50100000+0x4)++0xC7 line.long 0x44 "BBCFG2 ,Channel 2 congiguration register" bitfld.long 0x44 21.--23. "RxService ,Receive FIFO service select" "none,DMA,INT1,INT2,res,res,res,res" bitfld.long 0x44 19.--20. " RxThreshLevel ,Receive FIFO service threshold" "4,8,16,32" bitfld.long 0x44 18. " RxDFCenable ,Direct Flow Control enable" "dis,ena" bitfld.long 0x44 17. " RxMFCenable ,Message Flow Control enable" "dis,ena" textline " " bitfld.long 0x44 8.--10. "TxBlock ,Transmit block size" "4,8,16,32,res,res,res,res" bitfld.long 0x44 5.--7. " TxService ,Transmit FIFO service select" "none,DMA,INT1,INT2,res,res,res,res" bitfld.long 0x44 3.--4. " TxThreshLevel ,Transmit FIFO service threshold" "4,8,16,32" bitfld.long 0x44 2. " TxDFCenable ,Direct Flow Control enable" "dis,ena" textline " " bitfld.long 0x44 1. "TxMFCenable ,Message Flow Control enable" "dis,ena" bitfld.long 0x44 0. " TxEnable ,Transmit FIFO channel enable" "dis,ena" line.long 0x84 "BBSTAT2 ,Channel 2 status register" bitfld.long 0x84 24. "RxWait ,Receive channel is in wait state" "no,yes" bitfld.long 0x84 23. " RxEmpty ,Receive FIFO is empty" "no,yes" bitfld.long 0x84 22. " RxFull ,Receive FIFO is full" "no,yes" hexmask.long 0x84 16.--21. 0x1 " RxFullness ,Fullness of receive Fifo" textline " " bitfld.long 0x84 8. "TxWait ,Transmit channel is in wait state" "no,yes" bitfld.long 0x84 7. " TxEmpty ,Transmit FIFO is empty" "no,yes" bitfld.long 0x84 6. " TxFull ,Transmit FIFO is full" "no,yes" hexmask.long 0x84 0.--5. 0x1 " TxFullness ,Fullness of transmit Fifo" hide.long 0x04 "BBFIFO2 ,Channel 2 transmit FIFO register" in hide.long 0xC4 "BBEOM2 ,Channel 2 EndOfMessage register" ;end include file xscale/manitoba-bbi-channel.ph tree.end tree "Channel 3" ;begin include file xscale/manitoba-bbi-channel.ph ;parameters: 3 0x8 group asd:(0x50100000+0x8)++0xC7 line.long 0x44 "BBCFG3 ,Channel 3 congiguration register" bitfld.long 0x44 21.--23. "RxService ,Receive FIFO service select" "none,DMA,INT1,INT2,res,res,res,res" bitfld.long 0x44 19.--20. " RxThreshLevel ,Receive FIFO service threshold" "4,8,16,32" bitfld.long 0x44 18. " RxDFCenable ,Direct Flow Control enable" "dis,ena" bitfld.long 0x44 17. " RxMFCenable ,Message Flow Control enable" "dis,ena" textline " " bitfld.long 0x44 8.--10. "TxBlock ,Transmit block size" "4,8,16,32,res,res,res,res" bitfld.long 0x44 5.--7. " TxService ,Transmit FIFO service select" "none,DMA,INT1,INT2,res,res,res,res" bitfld.long 0x44 3.--4. " TxThreshLevel ,Transmit FIFO service threshold" "4,8,16,32" bitfld.long 0x44 2. " TxDFCenable ,Direct Flow Control enable" "dis,ena" textline " " bitfld.long 0x44 1. "TxMFCenable ,Message Flow Control enable" "dis,ena" bitfld.long 0x44 0. " TxEnable ,Transmit FIFO channel enable" "dis,ena" line.long 0x84 "BBSTAT3 ,Channel 3 status register" bitfld.long 0x84 24. "RxWait ,Receive channel is in wait state" "no,yes" bitfld.long 0x84 23. " RxEmpty ,Receive FIFO is empty" "no,yes" bitfld.long 0x84 22. " RxFull ,Receive FIFO is full" "no,yes" hexmask.long 0x84 16.--21. 0x1 " RxFullness ,Fullness of receive Fifo" textline " " bitfld.long 0x84 8. "TxWait ,Transmit channel is in wait state" "no,yes" bitfld.long 0x84 7. " TxEmpty ,Transmit FIFO is empty" "no,yes" bitfld.long 0x84 6. " TxFull ,Transmit FIFO is full" "no,yes" hexmask.long 0x84 0.--5. 0x1 " TxFullness ,Fullness of transmit Fifo" hide.long 0x04 "BBFIFO3 ,Channel 3 transmit FIFO register" in hide.long 0xC4 "BBEOM3 ,Channel 3 EndOfMessage register" ;end include file xscale/manitoba-bbi-channel.ph tree.end tree "Channel 4" ;begin include file xscale/manitoba-bbi-channel.ph ;parameters: 4 0xC group asd:(0x50100000+0xC)++0xC7 line.long 0x44 "BBCFG4 ,Channel 4 congiguration register" bitfld.long 0x44 21.--23. "RxService ,Receive FIFO service select" "none,DMA,INT1,INT2,res,res,res,res" bitfld.long 0x44 19.--20. " RxThreshLevel ,Receive FIFO service threshold" "4,8,16,32" bitfld.long 0x44 18. " RxDFCenable ,Direct Flow Control enable" "dis,ena" bitfld.long 0x44 17. " RxMFCenable ,Message Flow Control enable" "dis,ena" textline " " bitfld.long 0x44 8.--10. "TxBlock ,Transmit block size" "4,8,16,32,res,res,res,res" bitfld.long 0x44 5.--7. " TxService ,Transmit FIFO service select" "none,DMA,INT1,INT2,res,res,res,res" bitfld.long 0x44 3.--4. " TxThreshLevel ,Transmit FIFO service threshold" "4,8,16,32" bitfld.long 0x44 2. " TxDFCenable ,Direct Flow Control enable" "dis,ena" textline " " bitfld.long 0x44 1. "TxMFCenable ,Message Flow Control enable" "dis,ena" bitfld.long 0x44 0. " TxEnable ,Transmit FIFO channel enable" "dis,ena" line.long 0x84 "BBSTAT4 ,Channel 4 status register" bitfld.long 0x84 24. "RxWait ,Receive channel is in wait state" "no,yes" bitfld.long 0x84 23. " RxEmpty ,Receive FIFO is empty" "no,yes" bitfld.long 0x84 22. " RxFull ,Receive FIFO is full" "no,yes" hexmask.long 0x84 16.--21. 0x1 " RxFullness ,Fullness of receive Fifo" textline " " bitfld.long 0x84 8. "TxWait ,Transmit channel is in wait state" "no,yes" bitfld.long 0x84 7. " TxEmpty ,Transmit FIFO is empty" "no,yes" bitfld.long 0x84 6. " TxFull ,Transmit FIFO is full" "no,yes" hexmask.long 0x84 0.--5. 0x1 " TxFullness ,Fullness of transmit Fifo" hide.long 0x04 "BBFIFO4 ,Channel 4 transmit FIFO register" in hide.long 0xC4 "BBEOM4 ,Channel 4 EndOfMessage register" ;end include file xscale/manitoba-bbi-channel.ph tree.end tree.end ;end include file xscale/manitoba-bbi.ph ; %include xscale/manitoba-uart.ph 0x40700000 ST "Standard UART 1 " ;begin include file xscale/manitoba-rtc.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; Should be ok ; State: Preliminary ; -------------------------------------------------------------------------------- tree "RTC" ; -------------------------------------------------------------------------------- group asd:0x40900000++0xf line.long 0x00 "RCNR,RTC Count Register" line.long 0x04 "RTAR,RTC Alarm Register" line.long 0x08 "RTSR,RTC Status Register" bitfld.long 0x08 3.--3. "HZE ,HZ Interrupt Enable" "dis,ena" bitfld.long 0x08 2.--2. " ALE ,RTC Alarm Interrupt Enable" "dis,ena" bitfld.long 0x08 1.--1. " HZ ,HZ rising-edge detected" "no,yes" bitfld.long 0x08 0.--0. " AL ,RTC Alarm detected" "no,yes" line.long 0x0c "RTTR,RTC Timer Trim Register" bitfld.long 0x0c 31.--31. "LCK ,Locking bit for the trim value" "unlocked,locked" hexmask.long 0x0c 16.--25. 0x01 " DEL ,Trim delete count" hexmask.long 0x0c 0.--15. 0x01 " CK_DIV ,Clock divider count" tree.end ;end include file xscale/manitoba-rtc.ph ; %include xscale/manitoba-timer.ph ; tree "PWMs" ;begin include file xscale/manitoba-pwm.ph ;parameters: 0x40b00000 0 ; -------------------------------------------------------------------------------- ; Manitoba ; Should be Ok ; State: preliminary ; -------------------------------------------------------------------------------- tree "PWM0" ; -------------------------------------------------------------------------------- width 13. group asd:(0x40b00000+0x00)++0x03 line.long 0x00 "PWM_CTRL0,PWM 0 Control Register" bitfld.long 0x00 6.--6. "PWM_SD ,PWM0 Shutdown Method" "graceful,abrupt" bitfld.long 0x00 0.--5. " PRESCALE ,PWM0 Prescale Divisor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group asd:(0x40b00000+0x04)++0x03 line.long 0x00 "PWM_PWDUTY0,PWM 0 Duty Cycle Register" bitfld.long 0x00 10.--10. "FDCYCLE ,PWM0 Full Duty Cycle" "DCYCLE,full" hexmask.long 0x00 0.--9. 0x01 " DCYCLE ,PWM0 Duty Cycle" group asd:(0x40b00000+0x08)++0x03 line.long 0x00 "PWM_PERVAL0,PWM 0 Period Control Register" hexmask.long 0x00 0.--9. 0x01 "PV ,PWM0 Period Control" width 8. tree.end ;end include file xscale/manitoba-pwm.ph ;begin include file xscale/manitoba-pwm.ph ;parameters: 0x40c00000 1 ; -------------------------------------------------------------------------------- ; Manitoba ; Should be Ok ; State: preliminary ; -------------------------------------------------------------------------------- tree "PWM1" ; -------------------------------------------------------------------------------- width 13. group asd:(0x40c00000+0x00)++0x03 line.long 0x00 "PWM_CTRL1,PWM 1 Control Register" bitfld.long 0x00 6.--6. "PWM_SD ,PWM1 Shutdown Method" "graceful,abrupt" bitfld.long 0x00 0.--5. " PRESCALE ,PWM1 Prescale Divisor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group asd:(0x40c00000+0x04)++0x03 line.long 0x00 "PWM_PWDUTY1,PWM 1 Duty Cycle Register" bitfld.long 0x00 10.--10. "FDCYCLE ,PWM1 Full Duty Cycle" "DCYCLE,full" hexmask.long 0x00 0.--9. 0x01 " DCYCLE ,PWM1 Duty Cycle" group asd:(0x40c00000+0x08)++0x03 line.long 0x00 "PWM_PERVAL1,PWM 1 Period Control Register" hexmask.long 0x00 0.--9. 0x01 "PV ,PWM1 Period Control" width 8. tree.end ;end include file xscale/manitoba-pwm.ph ;begin include file xscale/manitoba-pwm.ph ;parameters: 0x40b00010 2 ; -------------------------------------------------------------------------------- ; Manitoba ; Should be Ok ; State: preliminary ; -------------------------------------------------------------------------------- tree "PWM2" ; -------------------------------------------------------------------------------- width 13. group asd:(0x40b00010+0x00)++0x03 line.long 0x00 "PWM_CTRL2,PWM 2 Control Register" bitfld.long 0x00 6.--6. "PWM_SD ,PWM2 Shutdown Method" "graceful,abrupt" bitfld.long 0x00 0.--5. " PRESCALE ,PWM2 Prescale Divisor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..." group asd:(0x40b00010+0x04)++0x03 line.long 0x00 "PWM_PWDUTY2,PWM 2 Duty Cycle Register" bitfld.long 0x00 10.--10. "FDCYCLE ,PWM2 Full Duty Cycle" "DCYCLE,full" hexmask.long 0x00 0.--9. 0x01 " DCYCLE ,PWM2 Duty Cycle" group asd:(0x40b00010+0x08)++0x03 line.long 0x00 "PWM_PERVAL2,PWM 2 Period Control Register" hexmask.long 0x00 0.--9. 0x01 "PV ,PWM2 Period Control" width 8. tree.end ;end include file xscale/manitoba-pwm.ph ; tree.end ;begin include file xscale/manitoba-int.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; Interrupt 0-7 and 14 ToBeDone in Spec. ; GSM Interrupt Controller not specified. ; State: Preliminary ; -------------------------------------------------------------------------------- tree "Interrupt Control" ; -------------------------------------------------------------------------------- group asd:0x40d00014++0x03 line.long 0x00 "ICCR,Interrupt Controller Control Register" bitfld.long 0x00 0.--0. "DIM ,Disable IDLE Mask" "dis,ena" group asd:0x40d00004++0x03 line.long 0x00 "ICMR,Interrupt Controller Mask Register" bitfld.long 0x00 31.--31. "IM31 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 30.--30. " IM30 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 29.--29. " IM29 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 28.--28. " IM28 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 27.--27. " IM27 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 26.--26. " IM26 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 25.--25. " IM25 ,Mask for Pending Interrupt" "dis,ena" textline " " bitfld.long 0x00 24.--24. "IM24 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 23.--23. " IM23 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 22.--22. " IM22 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 21.--21. " IM21 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 20.--20. " IM20 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 19.--19. " IM19 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 18.--18. " IM18 ,Mask for Pending Interrupt" "dis,ena" textline " " bitfld.long 0x00 17.--17. "IM17 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 16.--16. " IM16 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 15.--15. " IM15 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 14.--14. " IM14 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 13.--13. " IM13 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 12.--12. " IM12 ,Mask for Pending Interrupt" "dis,ena" textline " " bitfld.long 0x00 11.--11. "IM11 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 10.--10. " IM10 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 9.--9. " IM9 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 8.--8. " IM8 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 7.--7. " IM7 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 6.--6. " IM6 ,Mask for Pending Interrupt" "dis,ena" textline " " bitfld.long 0x00 5.--5. "IM5 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 4.--4. " IM4 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 3.--3. " IM3 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 2.--2. " IM2 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 1.--1. " IM1 ,Mask for Pending Interrupt" "dis,ena" bitfld.long 0x00 0.--0. " IM0 ,Mask for Pending Interrupt" "dis,ena" group asd:0x40d00008++0x03 line.long 0x00 "ICLR,Interrupt Controller Level Register" bitfld.long 0x00 31.--31. "IL31 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 30.--30. " IL30 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 29.--29. " IL29 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 28.--28. " IL28 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 27.--27. " IL27 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 26.--26. " IL26 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 25.--25. " IL25 ,Interrupt Level" "IRQ,FIQ" textline " " bitfld.long 0x00 24.--24. "IL24 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 23.--23. " IL23 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 22.--22. " IL22 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 21.--21. " IL21 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 20.--20. " IL20 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 19.--19. " IL19 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 18.--18. " IL18 ,Interrupt Level" "IRQ,FIQ" textline " " bitfld.long 0x00 17.--17. "IL17 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 16.--16. " IL16 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 15.--15. " IL15 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 14.--14. " IL14 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 13.--13. " IL13 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 12.--12. " IL12 ,Interrupt Level" "IRQ,FIQ" textline " " bitfld.long 0x00 11.--11. "IL11 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 10.--10. " IL10 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 9.--9. " IL9 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 8.--8. " IL8 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 7.--7. " IL7 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 6.--6. " IL6 ,Interrupt Level" "IRQ,FIQ" textline " " bitfld.long 0x00 5.--5. "IL5 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 4.--4. " IL4 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 3.--3. " IL3 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 2.--2. " IL2 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 1.--1. " IL1 ,Interrupt Level" "IRQ,FIQ" bitfld.long 0x00 0.--0. " IL0 ,Interrupt Level" "IRQ,FIQ" group asd:0x40d00000++0x03 line.long 0x00 "ICIP,Interrupt Controller IRQ Pending Register" bitfld.long 0x00 31.--31. "IP31 ,IRQ Pending" "no,yes" bitfld.long 0x00 30.--30. " IP30 ,IRQ Pending" "no,yes" bitfld.long 0x00 29.--29. " IP29 ,IRQ Pending" "no,yes" bitfld.long 0x00 28.--28. " IP28 ,IRQ Pending" "no,yes" bitfld.long 0x00 27.--27. " IP27 ,IRQ Pending" "no,yes" bitfld.long 0x00 26.--26. " IP26 ,IRQ Pending" "no,yes" bitfld.long 0x00 25.--25. " IP25 ,IRQ Pending" "no,yes" textline " " bitfld.long 0x00 24.--24. "IP24 ,IRQ Pending" "no,yes" bitfld.long 0x00 23.--23. " IP23 ,IRQ Pending" "no,yes" bitfld.long 0x00 22.--22. " IP22 ,IRQ Pending" "no,yes" bitfld.long 0x00 21.--21. " IP21 ,IRQ Pending" "no,yes" bitfld.long 0x00 20.--20. " IP20 ,IRQ Pending" "no,yes" bitfld.long 0x00 19.--19. " IP19 ,IRQ Pending" "no,yes" bitfld.long 0x00 18.--18. " IP18 ,IRQ Pending" "no,yes" textline " " bitfld.long 0x00 17.--17. "IP17 ,IRQ Pending" "no,yes" bitfld.long 0x00 16.--16. " IP16 ,IRQ Pending" "no,yes" bitfld.long 0x00 15.--15. " IP15 ,IRQ Pending" "no,yes" bitfld.long 0x00 14.--14. " IP14 ,IRQ Pending" "no,yes" bitfld.long 0x00 13.--13. " IP13 ,IRQ Pending" "no,yes" bitfld.long 0x00 12.--12. " IP12 ,IRQ Pending" "no,yes" textline " " bitfld.long 0x00 11.--11. "IP11 ,IRQ Pending" "no,yes" bitfld.long 0x00 10.--10. " IP10 ,IRQ Pending" "no,yes" bitfld.long 0x00 9.--9. " IP9 ,IRQ Pending" "no,yes" bitfld.long 0x00 8.--8. " IP8 ,IRQ Pending" "no,yes" bitfld.long 0x00 7.--7. " IP7 ,IRQ Pending" "no,yes" bitfld.long 0x00 6.--6. " IP6 ,IRQ Pending" "no,yes" textline " " bitfld.long 0x00 5.--5. "IP5 ,IRQ Pending" "no,yes" bitfld.long 0x00 4.--4. " IP4 ,IRQ Pending" "no,yes" bitfld.long 0x00 3.--3. " IP3 ,IRQ Pending" "no,yes" bitfld.long 0x00 2.--2. " IP2 ,IRQ Pending" "no,yes" bitfld.long 0x00 1.--1. " IP1 ,IRQ Pending" "no,yes" bitfld.long 0x00 0.--0. " IP0 ,IRQ Pending" "no,yes" group asd:0x40d0000c++0x03 line.long 0x00 "ICFP,Interrupt Controller FIQ Pending Register" bitfld.long 0x00 31.--31. "FP31 ,FIQ Pending" "no,yes" bitfld.long 0x00 30.--30. " FP30 ,FIQ Pending" "no,yes" bitfld.long 0x00 29.--29. " FP29 ,FIQ Pending" "no,yes" bitfld.long 0x00 28.--28. " FP28 ,FIQ Pending" "no,yes" bitfld.long 0x00 27.--27. " FP27 ,FIQ Pending" "no,yes" bitfld.long 0x00 26.--26. " FP26 ,FIQ Pending" "no,yes" bitfld.long 0x00 25.--25. " FP25 ,FIQ Pending" "no,yes" textline " " bitfld.long 0x00 24.--24. "FP24 ,FIQ Pending" "no,yes" bitfld.long 0x00 23.--23. " FP23 ,FIQ Pending" "no,yes" bitfld.long 0x00 22.--22. " FP22 ,FIQ Pending" "no,yes" bitfld.long 0x00 21.--21. " FP21 ,FIQ Pending" "no,yes" bitfld.long 0x00 20.--20. " FP20 ,FIQ Pending" "no,yes" bitfld.long 0x00 19.--19. " FP19 ,FIQ Pending" "no,yes" bitfld.long 0x00 18.--18. " FP18 ,FIQ Pending" "no,yes" textline " " bitfld.long 0x00 17.--17. "FP17 ,FIQ Pending" "no,yes" bitfld.long 0x00 16.--16. " FP16 ,FIQ Pending" "no,yes" bitfld.long 0x00 15.--15. " FP15 ,FIQ Pending" "no,yes" bitfld.long 0x00 14.--14. " FP14 ,FIQ Pending" "no,yes" bitfld.long 0x00 13.--13. " FP13 ,FIQ Pending" "no,yes" bitfld.long 0x00 12.--12. " FP12 ,FIQ Pending" "no,yes" textline " " bitfld.long 0x00 11.--11. "FP11 ,FIQ Pending" "no,yes" bitfld.long 0x00 10.--10. " FP10 ,FIQ Pending" "no,yes" bitfld.long 0x00 9.--9. " FP9 ,FIQ Pending" "no,yes" bitfld.long 0x00 8.--8. " FP8 ,FIQ Pending" "no,yes" bitfld.long 0x00 7.--7. " FP7 ,FIQ Pending" "no,yes" bitfld.long 0x00 6.--6. " FP6 ,FIQ Pending" "no,yes" textline " " bitfld.long 0x00 5.--5. "FP5 ,FIQ Pending" "no,yes" bitfld.long 0x00 4.--4. " FP4 ,FIQ Pending" "no,yes" bitfld.long 0x00 3.--3. " FP3 ,FIQ Pending" "no,yes" bitfld.long 0x00 2.--2. " FP2 ,FIQ Pending" "no,yes" bitfld.long 0x00 1.--1. " FP1 ,FIQ Pending" "no,yes" bitfld.long 0x00 0.--0. " FP0 ,FIQ Pending" "no,yes" group asd:0x40d00010++0x03 line.long 0x00 "ICPR,Interrupt Controller Pending Register" bitfld.long 0x00 31.--31. "IS31 ,RTC Alarm Match Register Interrupt Pending" "no,yes" bitfld.long 0x00 30.--30. " IS30 ,RTC HZ Clock Tick Interrupt Pending" "no,yes" bitfld.long 0x00 29.--29. " IS29 ,OS Timer Match Register 3 Interrupt Pending" "no,yes" bitfld.long 0x00 28.--28. " IS28 ,OS Timer Match Register 2 Interrupt Pending" "no,yes" bitfld.long 0x00 27.--27. " IS27 ,OS Timer Match Register 1 Interrupt Pending" "no,yes" bitfld.long 0x00 26.--26. " IS26 ,OS Timer Match Register 0 Interrupt Pending" "no,yes" bitfld.long 0x00 25.--25. " IS25 ,DMA Channel Service Request Interrupt Pending" "no,yes" textline " " bitfld.long 0x00 24.--24. "IS24 ,SSP Service Request Interrupt Pending" "no,yes" bitfld.long 0x00 23.--23. " IS23 ,GSM or TCU Specific Interrupt Pending" "no,yes" bitfld.long 0x00 22.--22. " IS22 ,FFUART Transmit/Receive/Error Interrupt Pending" "no,yes" bitfld.long 0x00 21.--21. " IS21 ,BTUART Transmit/Receive/Error Interrupt Pending" "no,yes" bitfld.long 0x00 20.--20. " IS20 ,STUART Transmit/Receive/Error Interrupt Pending" "no,yes" bitfld.long 0x00 19.--19. " IS19 ,GSM SIM Card Interrupt Pending" "no,yes" bitfld.long 0x00 18.--18. " IS18 ,I2C Service Request Interrupt Pending" "no,yes" textline " " bitfld.long 0x00 17.--17. "IS17 ,LCD Controller Service Request Interrupt Pending" "no,yes" bitfld.long 0x00 16.--16. " IS16 ,External Memory Stick Interrupt Pending" "no,yes" bitfld.long 0x00 15.--15. " IS15 ,MMC Interface Interrupt Pending" "no,yes" bitfld.long 0x00 14.--14. " IS14 ,Battery Management Interrupt Pending" "no,yes" bitfld.long 0x00 13.--13. " IS13 ,I2S Interrupt Pending" "no,yes" bitfld.long 0x00 12.--12. " IS12 ,Performance Monitoring Unit (PMU) Interrupt Pending" "no,yes" textline " " bitfld.long 0x00 11.--11. "IS11 ,USB Service Interrupt Pending" "no,yes" bitfld.long 0x00 10.--10. " IS10 ,GPIO[72:2] Edge Detect Interrupt Pending" "no,yes" bitfld.long 0x00 9.--9. " IS9 ,GPIO[1] Edge Detect Interrupt Pending" "no,yes" bitfld.long 0x00 8.--8. " IS8 ,GPIO[0] Edge Detect Interrupt Pending" "no,yes" bitfld.long 0x00 7.--7. " IS7 ,OS timer match 4-11 Interrupt Pending" "no,yes" bitfld.long 0x00 6.--6. " IS6 ,Keypad Controller Interrupt Pending" "no,yes" textline " " bitfld.long 0x00 5.--5. "IS5 ,USB Host Interrupt 1 Pending" "no,yes" bitfld.long 0x00 4.--4. " IS4 ,USB Host Interrupt 2 Pending" "no,yes" bitfld.long 0x00 3.--3. " IS3 ,Bluetooth Interrupt 1 Pending" "no,yes" bitfld.long 0x00 2.--2. " IS2 ,Bluetooth Interrupt 2Pending" "no,yes" bitfld.long 0x00 1.--1. " IS1 ,Baseband Interface Interrupt 1 Pending" "no,yes" bitfld.long 0x00 0.--0. " IS0 ,Baseband Interface Interrupt 2 Pending" "no,yes" group asd:0x40D00020++0x0F line.long 0x00 "IIBR, IRQ Base Register" hexmask.long 0x00 12.--31. 0x1 "BaseAdr ,Base Address for IRQ Vector Generation" line.long 0x04 "IIVR, IRQ Vector Register" hexmask.long 0x00 12.--31. 0x1 "BaseAdr ,Base Address for IRQ Vector Generation" hexmask.long 0x00 4.--11. 0x1 " Offset ,Bit number of highest priority IRQ" line.long 0x00 "IFBR, FIQ Base Register" hexmask.long 0x00 12.--31. 0x1 "BaseAdr ,Base Address for FIQ Vector Generation" line.long 0x04 "IFVR, FIQ Vector Register" hexmask.long 0x00 12.--31. 0x1 "BaseAdr ,Base Address for FIQ Vector Generation" hexmask.long 0x00 4.--11. 0x1 " Offset ,Bit number of highest priority FIQ" group asd:0x40D00100++0x7F line.long 0x00 "IPR0 , Interrupt Priority Register 0" bitfld.long 0x00 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x04 "IPR1 , Interrupt Priority Register 1" bitfld.long 0x04 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x08 "IPR2 , Interrupt Priority Register 2" bitfld.long 0x08 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x0C "IPR3 , Interrupt Priority Register 3" bitfld.long 0x0c 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x10 "IPR4 , Interrupt Priority Register 4" bitfld.long 0x10 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x14 "IPR5 , Interrupt Priority Register 5" bitfld.long 0x14 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x18 "IPR6 , Interrupt Priority Register 6" bitfld.long 0x18 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x1C "IPR7 , Interrupt Priority Register 7" bitfld.long 0x1c 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x20 "IPR8 , Interrupt Priority Register 8" bitfld.long 0x20 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x24 "IPR9 , Interrupt Priority Register 9" bitfld.long 0x24 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x28 "IPR10, Interrupt Priority Register 10" bitfld.long 0x28 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x2C "IPR11, Interrupt Priority Register 11" bitfld.long 0x2c 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x30 "IPR12, Interrupt Priority Register 12" bitfld.long 0x30 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x34 "IPR13, Interrupt Priority Register 13" bitfld.long 0x34 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x38 "IPR14, Interrupt Priority Register 14" bitfld.long 0x38 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x3C "IPR15, Interrupt Priority Register 15" bitfld.long 0x3c 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x40 "IPR16, Interrupt Priority Register 16" bitfld.long 0x40 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x44 "IPR17, Interrupt Priority Register 17" bitfld.long 0x44 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x48 "IPR18, Interrupt Priority Register 18" bitfld.long 0x48 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x4C "IPR19, Interrupt Priority Register 19" bitfld.long 0x4c 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x50 "IPR20, Interrupt Priority Register 20" bitfld.long 0x50 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x54 "IPR21, Interrupt Priority Register 21" bitfld.long 0x54 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x58 "IPR22, Interrupt Priority Register 22" bitfld.long 0x58 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x5C "IPR23, Interrupt Priority Register 23" bitfld.long 0x5c 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x60 "IPR24, Interrupt Priority Register 24" bitfld.long 0x60 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x64 "IPR25, Interrupt Priority Register 25" bitfld.long 0x64 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x68 "IPR26, Interrupt Priority Register 26" bitfld.long 0x68 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x6C "IPR27, Interrupt Priority Register 27" bitfld.long 0x6c 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x70 "IPR28, Interrupt Priority Register 28" bitfld.long 0x70 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x74 "IPR29, Interrupt Priority Register 29" bitfld.long 0x74 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x78 "IPR30, Interrupt Priority Register 30" bitfld.long 0x78 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" line.long 0x7C "IPR31, Interrupt Priority Register 31" bitfld.long 0x7c 0.--2. "Priority ,Interrupt priority" "0,1,2,3,4,5,6,7" tree.end ;end include file xscale/manitoba-int.ph ;begin include file xscale/manitoba-timer.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; BEWARE: The spec. is inconsistent on the register addresses. ; Compare Page 29 to Page 165 ; TWSR comes from page 176. ; State: preliminary ; -------------------------------------------------------------------------------- tree "Timers" ; -------------------------------------------------------------------------------- group asd:0x40a00000++0x3 line.long 0x00 "TCCR ,Timer Clock Control Register" bitfld.long 0x00 2.--3. " CS_2 ,Clock Source for Timer 2" "1Hz,32Khz,fast,res" bitfld.long 0x00 0.--0. " CS_1 ,Clock Source for Timer 1" "32Khz,fast" ;tree "Timer 1" ;begin include file xscale/manitoba-timer-regs.ph ;parameters: 0x40a00004 0x40a00028 1 group asd:0x40a00004++0xB "Timer 1" line.long 0x00 "TMR1[0] ,Timer 1 match register 0" line.long 0x04 "TMR1[1] ,Timer 1 match register 1" line.long 0x08 "TMR1[2] ,Timer 1 match register 2" group asd:0x40a00028++0x33 line.long 0x0C "TSR1 ,Timer 1 status register" bitfld.long 0x0C 2.--2. "M2 ,Match Status channel 2" "no,yes" bitfld.long 0x0C 1.--1. "M1 ,Match Status channel 1" "no,yes" bitfld.long 0x0C 0.--0. "M0 ,Match Status channel 0" "no,yes" line.long 0x18 "TIER1 ,Timer 1 interrupt enable register" bitfld.long 0x18 2.--2. "E2 ,Interrupt enable for comparator 2" "no,yes" bitfld.long 0x18 1.--1. "E1 ,Interrupt enable for comparator 1" "no,yes" bitfld.long 0x18 0.--0. "E0 ,Interrupt enable for comparator 0" "no,yes" line.long 0x30 "TPLCR1 ,Timer 1 preload control register" bitfld.long 0x30 0.--1. "MCS ,Match comparator select; match with comparator" "dis,0,1,2" line.long 0x24 "TPLVR1 ,Timer 1 preload value register" line.long 0x00 "TCR1 ,Timer 1 count register" ;end include file xscale/manitoba-timer-regs.ph ;tree.end ;tree "Timer 2" ;begin include file xscale/manitoba-timer-regs.ph ;parameters: 0x40a00010 0x40a0002C 2 group asd:0x40a00010++0xB "Timer 2" line.long 0x00 "TMR2[0] ,Timer 2 match register 0" line.long 0x04 "TMR2[1] ,Timer 2 match register 1" line.long 0x08 "TMR2[2] ,Timer 2 match register 2" group asd:0x40a0002C++0x33 line.long 0x0C "TSR2 ,Timer 2 status register" bitfld.long 0x0C 2.--2. "M2 ,Match Status channel 2" "no,yes" bitfld.long 0x0C 1.--1. "M1 ,Match Status channel 1" "no,yes" bitfld.long 0x0C 0.--0. "M0 ,Match Status channel 0" "no,yes" line.long 0x18 "TIER2 ,Timer 2 interrupt enable register" bitfld.long 0x18 2.--2. "E2 ,Interrupt enable for comparator 2" "no,yes" bitfld.long 0x18 1.--1. "E1 ,Interrupt enable for comparator 1" "no,yes" bitfld.long 0x18 0.--0. "E0 ,Interrupt enable for comparator 0" "no,yes" line.long 0x30 "TPLCR2 ,Timer 2 preload control register" bitfld.long 0x30 0.--1. "MCS ,Match comparator select; match with comparator" "dis,0,1,2" line.long 0x24 "TPLVR2 ,Timer 2 preload value register" line.long 0x00 "TCR2 ,Timer 2 count register" ;end include file xscale/manitoba-timer-regs.ph ;tree.end ;tree "Timer 3" ;begin include file xscale/manitoba-timer-regs.ph ;parameters: 0x40a0001C 0x40a00030 3 group asd:0x40a0001C++0xB "Timer 3" line.long 0x00 "TMR3[0] ,Timer 3 match register 0" line.long 0x04 "TMR3[1] ,Timer 3 match register 1" line.long 0x08 "TMR3[2] ,Timer 3 match register 2" group asd:0x40a00030++0x33 line.long 0x0C "TSR3 ,Timer 3 status register" bitfld.long 0x0C 2.--2. "M2 ,Match Status channel 2" "no,yes" bitfld.long 0x0C 1.--1. "M1 ,Match Status channel 1" "no,yes" bitfld.long 0x0C 0.--0. "M0 ,Match Status channel 0" "no,yes" line.long 0x18 "TIER3 ,Timer 3 interrupt enable register" bitfld.long 0x18 2.--2. "E2 ,Interrupt enable for comparator 2" "no,yes" bitfld.long 0x18 1.--1. "E1 ,Interrupt enable for comparator 1" "no,yes" bitfld.long 0x18 0.--0. "E0 ,Interrupt enable for comparator 0" "no,yes" line.long 0x30 "TPLCR3 ,Timer 3 preload control register" bitfld.long 0x30 0.--1. "MCS ,Match comparator select; match with comparator" "dis,0,1,2" line.long 0x24 "TPLVR3 ,Timer 3 preload value register" line.long 0x00 "TCR3 ,Timer 3 count register" ;end include file xscale/manitoba-timer-regs.ph ;tree.end ;tree "Watchdog" group asd:0x40a00064++0xF line.long 0x00 "TWMER ,Timer Watchdog match enable register" bitfld.long 0x00 2.--2. "WIE ,Timer Watchdog interrupt enable" "dis,ena" bitfld.long 0x00 1.--1. " WME ,Timer Watchdog match reset" "dis,ena" bitfld.long 0x00 0.--0. " WE ,Timer Watchdog count enable" "dis,ena" line.long 0x04 "TWMR ,Timer Watchdog match register" hexmask.long 0x04 0.--5. 0x1 "WTM ,Timer Watchdog match value" line.long 0x08 "TWVR ,Timer Watchdog value register" hexmask.long 0x08 0.--5. 0x1 "WTV ,Timer Watchdog value" line.long 0x0C "TWSR ,Timer Watchdog status register" bitfld.long 0x00 0.--0. "WTS ,Timer Watchdog status; last reset was" "HW,WDT" ;tree.end tree.end ;end include file xscale/manitoba-timer.ph ; %include xscale/manitoba-gsmic.ph ; %include xscale/manitoba-tcu.ph ; %include xscale/manitoba-gsmsc.ph ;begin include file xscale/manitoba-gpio.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; Copied most of it from Cotulla. ; Inconsistencies in the Spec (72 or 80 Pins ?) ; Check: Alternate Functions (comment about 16 Bit Package) ; State: Preliminary ; -------------------------------------------------------------------------------- tree "GPIO" ; -------------------------------------------------------------------------------- group asd:0x40e00000++0x0b line.long 0x00 "GPLR0,GPIO Pin-Level Register GPIO<31:0>" bitfld.long 0x00 31.--31. "PL31 ,GP31 Pin State" "L,H" bitfld.long 0x00 30.--30. " PL30 ,GP30 Pin State" "L,H" bitfld.long 0x00 29.--29. " PL29 ,GP29 Pin State" "L,H" bitfld.long 0x00 28.--28. " PL28 ,GP28 Pin State" "L,H" bitfld.long 0x00 27.--27. " PL27 ,GP27 Pin State" "L,H" bitfld.long 0x00 26.--26. " PL26 ,GP26 Pin State" "L,H" bitfld.long 0x00 25.--25. " PL25 ,GP25 Pin State" "L,H" bitfld.long 0x00 24.--24. " PL24 ,GP24 Pin State" "L,H" textline " " bitfld.long 0x00 23.--23. "PL23 ,GP23 Pin State" "L,H" bitfld.long 0x00 22.--22. " PL22 ,GP22 Pin State" "L,H" bitfld.long 0x00 21.--21. " PL21 ,GP21 Pin State" "L,H" bitfld.long 0x00 20.--20. " PL20 ,GP20 Pin State" "L,H" bitfld.long 0x00 19.--19. " PL19 ,GP19 Pin State" "L,H" bitfld.long 0x00 18.--18. " PL18 ,GP18 Pin State" "L,H" bitfld.long 0x00 17.--17. " PL17 ,GP17 Pin State" "L,H" bitfld.long 0x00 16.--16. " PL16 ,GP16 Pin State" "L,H" textline " " bitfld.long 0x00 15.--15. "PL15 ,GP15 Pin State" "L,H" bitfld.long 0x00 14.--14. " PL14 ,GP14 Pin State" "L,H" bitfld.long 0x00 13.--13. " PL13 ,GP13 Pin State" "L,H" bitfld.long 0x00 12.--12. " PL12 ,GP12 Pin State" "L,H" bitfld.long 0x00 11.--11. " PL11 ,GP11 Pin State" "L,H" bitfld.long 0x00 10.--10. " PL10 ,GP10 Pin State" "L,H" bitfld.long 0x00 9.--9. " PL9 ,GP9 Pin State" "L,H" bitfld.long 0x00 8.--8. " PL8 ,GP8 Pin State" "L,H" textline " " bitfld.long 0x00 7.--7. "PL7 ,GP7 Pin State" "L,H" bitfld.long 0x00 6.--6. " PL6 ,GP6 Pin State" "L,H" bitfld.long 0x00 5.--5. " PL5 ,GP5 Pin State" "L,H" bitfld.long 0x00 4.--4. " PL4 ,GP4 Pin State" "L,H" bitfld.long 0x00 3.--3. " PL3 ,GP3 Pin State" "L,H" bitfld.long 0x00 2.--2. " PL2 ,GP2 Pin State" "L,H" bitfld.long 0x00 1.--1. " PL1 ,GP1 Pin State" "L,H" bitfld.long 0x00 0.--0. " PL0 ,GP0 Pin State" "L,H" line.long 0x04 "GPLR1,GPIO Pin-Level Register GPIO<63:32>" bitfld.long 0x04 31.--31. "PL63 ,GP63 Pin State" "L,H" bitfld.long 0x04 30.--30. " PL62 ,GP62 Pin State" "L,H" bitfld.long 0x04 29.--29. " PL61 ,GP61 Pin State" "L,H" bitfld.long 0x04 28.--28. " PL60 ,GP60 Pin State" "L,H" bitfld.long 0x04 27.--27. " PL59 ,GP59 Pin State" "L,H" bitfld.long 0x04 26.--26. " PL58 ,GP58 Pin State" "L,H" bitfld.long 0x04 25.--25. " PL57 ,GP57 Pin State" "L,H" bitfld.long 0x04 24.--24. " PL56 ,GP56 Pin State" "L,H" textline " " bitfld.long 0x04 23.--23. "PL55 ,GP55 Pin State" "L,H" bitfld.long 0x04 22.--22. " PL54 ,GP54 Pin State" "L,H" bitfld.long 0x04 21.--21. " PL53 ,GP53 Pin State" "L,H" bitfld.long 0x04 20.--20. " PL52 ,GP52 Pin State" "L,H" bitfld.long 0x04 19.--19. " PL51 ,GP51 Pin State" "L,H" bitfld.long 0x04 18.--18. " PL50 ,GP50 Pin State" "L,H" bitfld.long 0x04 17.--17. " PL49 ,GP49 Pin State" "L,H" bitfld.long 0x04 16.--16. " PL48 ,GP48 Pin State" "L,H" textline " " bitfld.long 0x04 15.--15. "PL47 ,GP47 Pin State" "L,H" bitfld.long 0x04 14.--14. " PL46 ,GP46 Pin State" "L,H" bitfld.long 0x04 13.--13. " PL45 ,GP45 Pin State" "L,H" bitfld.long 0x04 12.--12. " PL44 ,GP44 Pin State" "L,H" bitfld.long 0x04 11.--11. " PL43 ,GP43 Pin State" "L,H" bitfld.long 0x04 10.--10. " PL42 ,GP42 Pin State" "L,H" bitfld.long 0x04 9.--9. " PL41 ,GP41 Pin State" "L,H" bitfld.long 0x04 8.--8. " PL40 ,GP40 Pin State" "L,H" textline " " bitfld.long 0x04 7.--7. "PL39 ,GP39 Pin State" "L,H" bitfld.long 0x04 6.--6. " PL38 ,GP38 Pin State" "L,H" bitfld.long 0x04 5.--5. " PL37 ,GP37 Pin State" "L,H" bitfld.long 0x04 4.--4. " PL36 ,GP36 Pin State" "L,H" bitfld.long 0x04 3.--3. " PL35 ,GP35 Pin State" "L,H" bitfld.long 0x04 2.--2. " PL34 ,GP34 Pin State" "L,H" bitfld.long 0x04 1.--1. " PL33 ,GP33 Pin State" "L,H" bitfld.long 0x04 0.--0. " PL32 ,GP32 Pin State" "L,H" line.long 0x08 "GPLR2,GPIO Pin-Level Register GPIO<71:64>" bitfld.long 0x08 7.--7. "PL71 ,GP71 Pin State" "L,H" bitfld.long 0x08 6.--6. " PL70 ,GP70 Pin State" "L,H" bitfld.long 0x08 5.--5. " PL69 ,GP69 Pin State" "L,H" bitfld.long 0x08 4.--4. " PL68 ,GP68 Pin State" "L,H" bitfld.long 0x08 3.--3. " PL67 ,GP67 Pin State" "L,H" bitfld.long 0x08 2.--2. " PL66 ,GP66 Pin State" "L,H" bitfld.long 0x08 1.--1. " PL65 ,GP65 Pin State" "L,H" bitfld.long 0x08 0.--0. " PL64 ,GP64 Pin State" "L,H" textline " " group asd:0x40e0000c++0x0b line.long 0x00 "GPDR0,GPIO Pin Direction Register GPIO<31:0>" bitfld.long 0x00 31.--31. "PD31 ,GP31 Pin Direction" "I,O" bitfld.long 0x00 30.--30. " PD30 ,GP30 Pin Direction" "I,O" bitfld.long 0x00 29.--29. " PD29 ,GP29 Pin Direction" "I,O" bitfld.long 0x00 28.--28. " PD28 ,GP28 Pin Direction" "I,O" bitfld.long 0x00 27.--27. " PD27 ,GP27 Pin Direction" "I,O" bitfld.long 0x00 26.--26. " PD26 ,GP26 Pin Direction" "I,O" bitfld.long 0x00 25.--25. " PD25 ,GP25 Pin Direction" "I,O" bitfld.long 0x00 24.--24. " PD24 ,GP24 Pin Direction" "I,O" textline " " bitfld.long 0x00 23.--23. "PD23 ,GP23 Pin Direction" "I,O" bitfld.long 0x00 22.--22. " PD22 ,GP22 Pin Direction" "I,O" bitfld.long 0x00 21.--21. " PD21 ,GP21 Pin Direction" "I,O" bitfld.long 0x00 20.--20. " PD20 ,GP20 Pin Direction" "I,O" bitfld.long 0x00 19.--19. " PD19 ,GP19 Pin Direction" "I,O" bitfld.long 0x00 18.--18. " PD18 ,GP18 Pin Direction" "I,O" bitfld.long 0x00 17.--17. " PD17 ,GP17 Pin Direction" "I,O" bitfld.long 0x00 16.--16. " PD16 ,GP16 Pin Direction" "I,O" textline " " bitfld.long 0x00 15.--15. "PD15 ,GP15 Pin Direction" "I,O" bitfld.long 0x00 14.--14. " PD14 ,GP14 Pin Direction" "I,O" bitfld.long 0x00 13.--13. " PD13 ,GP13 Pin Direction" "I,O" bitfld.long 0x00 12.--12. " PD12 ,GP12 Pin Direction" "I,O" bitfld.long 0x00 11.--11. " PD11 ,GP11 Pin Direction" "I,O" bitfld.long 0x00 10.--10. " PD10 ,GP10 Pin Direction" "I,O" bitfld.long 0x00 9.--9. " PD9 ,GP9 Pin Direction" "I,O" bitfld.long 0x00 8.--8. " PD8 ,GP8 Pin Direction" "I,O" textline " " bitfld.long 0x00 7.--7. "PD7 ,GP7 Pin Direction" "I,O" bitfld.long 0x00 6.--6. " PD6 ,GP6 Pin Direction" "I,O" bitfld.long 0x00 5.--5. " PD5 ,GP5 Pin Direction" "I,O" bitfld.long 0x00 4.--4. " PD4 ,GP4 Pin Direction" "I,O" bitfld.long 0x00 3.--3. " PD3 ,GP3 Pin Direction" "I,O" bitfld.long 0x00 2.--2. " PD2 ,GP2 Pin Direction" "I,O" bitfld.long 0x00 1.--1. " PD1 ,GP1 Pin Direction" "I,O" bitfld.long 0x00 0.--0. " PD0 ,GP0 Pin Direction" "I,O" line.long 0x04 "GPDR1,GPIO Pin Direction Register GPIO<63:32>" bitfld.long 0x04 31.--31. "PD63 ,GP63 Pin Direction" "I,O" bitfld.long 0x04 30.--30. " PD62 ,GP62 Pin Direction" "I,O" bitfld.long 0x04 29.--29. " PD61 ,GP61 Pin Direction" "I,O" bitfld.long 0x04 28.--28. " PD60 ,GP60 Pin Direction" "I,O" bitfld.long 0x04 27.--27. " PD59 ,GP59 Pin Direction" "I,O" bitfld.long 0x04 26.--26. " PD58 ,GP58 Pin Direction" "I,O" bitfld.long 0x04 25.--25. " PD57 ,GP57 Pin Direction" "I,O" bitfld.long 0x04 24.--24. " PD56 ,GP56 Pin Direction" "I,O" textline " " bitfld.long 0x04 23.--23. "PD55 ,GP55 Pin Direction" "I,O" bitfld.long 0x04 22.--22. " PD54 ,GP54 Pin Direction" "I,O" bitfld.long 0x04 21.--21. " PD53 ,GP53 Pin Direction" "I,O" bitfld.long 0x04 20.--20. " PD52 ,GP52 Pin Direction" "I,O" bitfld.long 0x04 19.--19. " PD51 ,GP51 Pin Direction" "I,O" bitfld.long 0x04 18.--18. " PD50 ,GP50 Pin Direction" "I,O" bitfld.long 0x04 17.--17. " PD49 ,GP49 Pin Direction" "I,O" bitfld.long 0x04 16.--16. " PD48 ,GP48 Pin Direction" "I,O" textline " " bitfld.long 0x04 15.--15. "PD47 ,GP47 Pin Direction" "I,O" bitfld.long 0x04 14.--14. " PD46 ,GP46 Pin Direction" "I,O" bitfld.long 0x04 13.--13. " PD45 ,GP45 Pin Direction" "I,O" bitfld.long 0x04 12.--12. " PD44 ,GP44 Pin Direction" "I,O" bitfld.long 0x04 11.--11. " PD43 ,GP43 Pin Direction" "I,O" bitfld.long 0x04 10.--10. " PD42 ,GP42 Pin Direction" "I,O" bitfld.long 0x04 9.--9. " PD41 ,GP41 Pin Direction" "I,O" bitfld.long 0x04 8.--8. " PD40 ,GP40 Pin Direction" "I,O" textline " " bitfld.long 0x04 7.--7. "PD39 ,GP39 Pin Direction" "I,O" bitfld.long 0x04 6.--6. " PD38 ,GP38 Pin Direction" "I,O" bitfld.long 0x04 5.--5. " PD37 ,GP37 Pin Direction" "I,O" bitfld.long 0x04 4.--4. " PD36 ,GP36 Pin Direction" "I,O" bitfld.long 0x04 3.--3. " PD35 ,GP35 Pin Direction" "I,O" bitfld.long 0x04 2.--2. " PD34 ,GP34 Pin Direction" "I,O" bitfld.long 0x04 1.--1. " PD33 ,GP33 Pin Direction" "I,O" bitfld.long 0x04 0.--0. " PD32 ,GP32 Pin Direction" "I,O" line.long 0x08 "GPDR2,GPIO Pin Direction Register GPIO<71:64>" bitfld.long 0x08 7.--7. "PD71 ,GP71 Pin Direction" "I,O" bitfld.long 0x08 6.--6. " PD70 ,GP70 Pin Direction" "I,O" bitfld.long 0x08 5.--5. " PD69 ,GP69 Pin Direction" "I,O" bitfld.long 0x08 4.--4. " PD68 ,GP68 Pin Direction" "I,O" bitfld.long 0x08 3.--3. " PD67 ,GP67 Pin Direction" "I,O" bitfld.long 0x08 2.--2. " PD66 ,GP66 Pin Direction" "I,O" bitfld.long 0x08 1.--1. " PD65 ,GP65 Pin Direction" "I,O" bitfld.long 0x08 0.--0. " PD64 ,GP64 Pin Direction" "I,O" textline " " group asd:0x40e00018++0x0b line.long 0x00 "GPSR0,GPIO Pin Output Set Register GPIO<31:0>" bitfld.long 0x00 31.--31. "PS31 ,GP31 Output Pin Set" "-,H" bitfld.long 0x00 30.--30. " PS30 ,GP30 Output Pin Set" "-,H" bitfld.long 0x00 29.--29. " PS29 ,GP29 Output Pin Set" "-,H" bitfld.long 0x00 28.--28. " PS28 ,GP28 Output Pin Set" "-,H" bitfld.long 0x00 27.--27. " PS27 ,GP27 Output Pin Set" "-,H" bitfld.long 0x00 26.--26. " PS26 ,GP26 Output Pin Set" "-,H" bitfld.long 0x00 25.--25. " PS25 ,GP25 Output Pin Set" "-,H" bitfld.long 0x00 24.--24. " PS24 ,GP24 Output Pin Set" "-,H" textline " " bitfld.long 0x00 23.--23. "PS23 ,GP23 Output Pin Set" "-,H" bitfld.long 0x00 22.--22. " PS22 ,GP22 Output Pin Set" "-,H" bitfld.long 0x00 21.--21. " PS21 ,GP21 Output Pin Set" "-,H" bitfld.long 0x00 20.--20. " PS20 ,GP20 Output Pin Set" "-,H" bitfld.long 0x00 19.--19. " PS19 ,GP19 Output Pin Set" "-,H" bitfld.long 0x00 18.--18. " PS18 ,GP18 Output Pin Set" "-,H" bitfld.long 0x00 17.--17. " PS17 ,GP17 Output Pin Set" "-,H" bitfld.long 0x00 16.--16. " PS16 ,GP16 Output Pin Set" "-,H" textline " " bitfld.long 0x00 15.--15. "PS15 ,GP15 Output Pin Set" "-,H" bitfld.long 0x00 14.--14. " PS14 ,GP14 Output Pin Set" "-,H" bitfld.long 0x00 13.--13. " PS13 ,GP13 Output Pin Set" "-,H" bitfld.long 0x00 12.--12. " PS12 ,GP12 Output Pin Set" "-,H" bitfld.long 0x00 11.--11. " PS11 ,GP11 Output Pin Set" "-,H" bitfld.long 0x00 10.--10. " PS10 ,GP10 Output Pin Set" "-,H" bitfld.long 0x00 9.--9. " PS9 ,GP9 Output Pin Set" "-,H" bitfld.long 0x00 8.--8. " PS8 ,GP8 Output Pin Set" "-,H" textline " " bitfld.long 0x00 7.--7. "PS7 ,GP7 Output Pin Set" "-,H" bitfld.long 0x00 6.--6. " PS6 ,GP6 Output Pin Set" "-,H" bitfld.long 0x00 5.--5. " PS5 ,GP5 Output Pin Set" "-,H" bitfld.long 0x00 4.--4. " PS4 ,GP4 Output Pin Set" "-,H" bitfld.long 0x00 3.--3. " PS3 ,GP3 Output Pin Set" "-,H" bitfld.long 0x00 2.--2. " PS2 ,GP2 Output Pin Set" "-,H" bitfld.long 0x00 1.--1. " PS1 ,GP1 Output Pin Set" "-,H" bitfld.long 0x00 0.--0. " PS0 ,GP0 Output Pin Set" "-,H" line.long 0x04 "GPSR1,GPIO Pin Output Set Register GPIO<63:32>" bitfld.long 0x04 31.--31. "PS63 ,GP63 Output Pin Set" "-,H" bitfld.long 0x04 30.--30. " PS62 ,GP62 Output Pin Set" "-,H" bitfld.long 0x04 29.--29. " PS61 ,GP61 Output Pin Set" "-,H" bitfld.long 0x04 28.--28. " PS60 ,GP60 Output Pin Set" "-,H" bitfld.long 0x04 27.--27. " PS59 ,GP59 Output Pin Set" "-,H" bitfld.long 0x04 26.--26. " PS58 ,GP58 Output Pin Set" "-,H" bitfld.long 0x04 25.--25. " PS57 ,GP57 Output Pin Set" "-,H" bitfld.long 0x04 24.--24. " PS56 ,GP56 Output Pin Set" "-,H" textline " " bitfld.long 0x04 23.--23. "PS55 ,GP55 Output Pin Set" "-,H" bitfld.long 0x04 22.--22. " PS54 ,GP54 Output Pin Set" "-,H" bitfld.long 0x04 21.--21. " PS53 ,GP53 Output Pin Set" "-,H" bitfld.long 0x04 20.--20. " PS52 ,GP52 Output Pin Set" "-,H" bitfld.long 0x04 19.--19. " PS51 ,GP51 Output Pin Set" "-,H" bitfld.long 0x04 18.--18. " PS50 ,GP50 Output Pin Set" "-,H" bitfld.long 0x04 17.--17. " PS49 ,GP49 Output Pin Set" "-,H" bitfld.long 0x04 16.--16. " PS48 ,GP48 Output Pin Set" "-,H" textline " " bitfld.long 0x04 15.--15. "PS47 ,GP47 Output Pin Set" "-,H" bitfld.long 0x04 14.--14. " PS46 ,GP46 Output Pin Set" "-,H" bitfld.long 0x04 13.--13. " PS45 ,GP45 Output Pin Set" "-,H" bitfld.long 0x04 12.--12. " PS44 ,GP44 Output Pin Set" "-,H" bitfld.long 0x04 11.--11. " PS43 ,GP43 Output Pin Set" "-,H" bitfld.long 0x04 10.--10. " PS42 ,GP42 Output Pin Set" "-,H" bitfld.long 0x04 9.--9. " PS41 ,GP41 Output Pin Set" "-,H" bitfld.long 0x04 8.--8. " PS40 ,GP40 Output Pin Set" "-,H" textline " " bitfld.long 0x04 7.--7. "PS39 ,GP39 Output Pin Set" "-,H" bitfld.long 0x04 6.--6. " PS38 ,GP38 Output Pin Set" "-,H" bitfld.long 0x04 5.--5. " PS37 ,GP37 Output Pin Set" "-,H" bitfld.long 0x04 4.--4. " PS36 ,GP36 Output Pin Set" "-,H" bitfld.long 0x04 3.--3. " PS35 ,GP35 Output Pin Set" "-,H" bitfld.long 0x04 2.--2. " PS34 ,GP34 Output Pin Set" "-,H" bitfld.long 0x04 1.--1. " PS33 ,GP33 Output Pin Set" "-,H" bitfld.long 0x04 0.--0. " PS32 ,GP32 Output Pin Set" "-,H" line.long 0x08 "GPSR2,GPIO Pin Output Set Register GPIO<71:64>" bitfld.long 0x08 7.--7. "PS71 ,GP71 Output Pin Set" "-,H" bitfld.long 0x08 6.--6. " PS70 ,GP70 Output Pin Set" "-,H" bitfld.long 0x08 5.--5. " PS69 ,GP69 Output Pin Set" "-,H" bitfld.long 0x08 4.--4. " PS68 ,GP68 Output Pin Set" "-,H" bitfld.long 0x08 3.--3. " PS67 ,GP67 Output Pin Set" "-,H" bitfld.long 0x08 2.--2. " PS66 ,GP66 Output Pin Set" "-,H" bitfld.long 0x08 1.--1. " PS65 ,GP65 Output Pin Set" "-,H" bitfld.long 0x08 0.--0. " PS64 ,GP64 Output Pin Set" "-,H" textline " " group asd:0x40e00024++0x0b line.long 0x00 "GPCR0,GPIO Pin Output Clear Register GPIO<31:0>" bitfld.long 0x00 31.--31. "PC31 ,GP31 Output Pin Clear" "-,L" bitfld.long 0x00 30.--30. " PC30 ,GP30 Output Pin Clear" "-,L" bitfld.long 0x00 29.--29. " PC29 ,GP29 Output Pin Clear" "-,L" bitfld.long 0x00 28.--28. " PC28 ,GP28 Output Pin Clear" "-,L" bitfld.long 0x00 27.--27. " PC27 ,GP27 Output Pin Clear" "-,L" bitfld.long 0x00 26.--26. " PC26 ,GP26 Output Pin Clear" "-,L" bitfld.long 0x00 25.--25. " PC25 ,GP25 Output Pin Clear" "-,L" bitfld.long 0x00 24.--24. " PC24 ,GP24 Output Pin Clear" "-,L" textline " " bitfld.long 0x00 23.--23. "PC23 ,GP23 Output Pin Clear" "-,L" bitfld.long 0x00 22.--22. " PC22 ,GP22 Output Pin Clear" "-,L" bitfld.long 0x00 21.--21. " PC21 ,GP21 Output Pin Clear" "-,L" bitfld.long 0x00 20.--20. " PC20 ,GP20 Output Pin Clear" "-,L" bitfld.long 0x00 19.--19. " PC19 ,GP19 Output Pin Clear" "-,L" bitfld.long 0x00 18.--18. " PC18 ,GP18 Output Pin Clear" "-,L" bitfld.long 0x00 17.--17. " PC17 ,GP17 Output Pin Clear" "-,L" bitfld.long 0x00 16.--16. " PC16 ,GP16 Output Pin Clear" "-,L" textline " " bitfld.long 0x00 15.--15. "PC15 ,GP15 Output Pin Clear" "-,L" bitfld.long 0x00 14.--14. " PC14 ,GP14 Output Pin Clear" "-,L" bitfld.long 0x00 13.--13. " PC13 ,GP13 Output Pin Clear" "-,L" bitfld.long 0x00 12.--12. " PC12 ,GP12 Output Pin Clear" "-,L" bitfld.long 0x00 11.--11. " PC11 ,GP11 Output Pin Clear" "-,L" bitfld.long 0x00 10.--10. " PC10 ,GP10 Output Pin Clear" "-,L" bitfld.long 0x00 9.--9. " PC9 ,GP9 Output Pin Clear" "-,L" bitfld.long 0x00 8.--8. " PC8 ,GP8 Output Pin Clear" "-,L" textline " " bitfld.long 0x00 7.--7. "PC7 ,GP7 Output Pin Clear" "-,L" bitfld.long 0x00 6.--6. " PC6 ,GP6 Output Pin Clear" "-,L" bitfld.long 0x00 5.--5. " PC5 ,GP5 Output Pin Clear" "-,L" bitfld.long 0x00 4.--4. " PC4 ,GP4 Output Pin Clear" "-,L" bitfld.long 0x00 3.--3. " PC3 ,GP3 Output Pin Clear" "-,L" bitfld.long 0x00 2.--2. " PC2 ,GP2 Output Pin Clear" "-,L" bitfld.long 0x00 1.--1. " PC1 ,GP1 Output Pin Clear" "-,L" bitfld.long 0x00 0.--0. " PC0 ,GP0 Output Pin Clear" "-,L" line.long 0x04 "GPCR1,GPIO Pin Output Clear Register GPIO<63:32>" bitfld.long 0x04 31.--31. "PC63 ,GP63 Output Pin Clear" "-,L" bitfld.long 0x04 30.--30. " PC62 ,GP62 Output Pin Clear" "-,L" bitfld.long 0x04 29.--29. " PC61 ,GP61 Output Pin Clear" "-,L" bitfld.long 0x04 28.--28. " PC60 ,GP60 Output Pin Clear" "-,L" bitfld.long 0x04 27.--27. " PC59 ,GP59 Output Pin Clear" "-,L" bitfld.long 0x04 26.--26. " PC58 ,GP58 Output Pin Clear" "-,L" bitfld.long 0x04 25.--25. " PC57 ,GP57 Output Pin Clear" "-,L" bitfld.long 0x04 24.--24. " PC56 ,GP56 Output Pin Clear" "-,L" textline " " bitfld.long 0x04 23.--23. "PC55 ,GP55 Output Pin Clear" "-,L" bitfld.long 0x04 22.--22. " PC54 ,GP54 Output Pin Clear" "-,L" bitfld.long 0x04 21.--21. " PC53 ,GP53 Output Pin Clear" "-,L" bitfld.long 0x04 20.--20. " PC52 ,GP52 Output Pin Clear" "-,L" bitfld.long 0x04 19.--19. " PC51 ,GP51 Output Pin Clear" "-,L" bitfld.long 0x04 18.--18. " PC50 ,GP50 Output Pin Clear" "-,L" bitfld.long 0x04 17.--17. " PC49 ,GP49 Output Pin Clear" "-,L" bitfld.long 0x04 16.--16. " PC48 ,GP48 Output Pin Clear" "-,L" textline " " bitfld.long 0x04 15.--15. "PC47 ,GP47 Output Pin Clear" "-,L" bitfld.long 0x04 14.--14. " PC46 ,GP46 Output Pin Clear" "-,L" bitfld.long 0x04 13.--13. " PC45 ,GP45 Output Pin Clear" "-,L" bitfld.long 0x04 12.--12. " PC44 ,GP44 Output Pin Clear" "-,L" bitfld.long 0x04 11.--11. " PC43 ,GP43 Output Pin Clear" "-,L" bitfld.long 0x04 10.--10. " PC42 ,GP42 Output Pin Clear" "-,L" bitfld.long 0x04 9.--9. " PC41 ,GP41 Output Pin Clear" "-,L" bitfld.long 0x04 8.--8. " PC40 ,GP40 Output Pin Clear" "-,L" textline " " bitfld.long 0x04 7.--7. "PC39 ,GP39 Output Pin Clear" "-,L" bitfld.long 0x04 6.--6. " PC38 ,GP38 Output Pin Clear" "-,L" bitfld.long 0x04 5.--5. " PC37 ,GP37 Output Pin Clear" "-,L" bitfld.long 0x04 4.--4. " PC36 ,GP36 Output Pin Clear" "-,L" bitfld.long 0x04 3.--3. " PC35 ,GP35 Output Pin Clear" "-,L" bitfld.long 0x04 2.--2. " PC34 ,GP34 Output Pin Clear" "-,L" bitfld.long 0x04 1.--1. " PC33 ,GP33 Output Pin Clear" "-,L" bitfld.long 0x04 0.--0. " PC32 ,GP32 Output Pin Clear" "-,L" line.long 0x08 "GPCR2,GPIO Pin Output Clear Register GPIO<71:64>" bitfld.long 0x08 7.--7. "PC71 ,GP71 Output Pin Clear" "-,L" bitfld.long 0x08 6.--6. " PC70 ,GP70 Output Pin Clear" "-,L" bitfld.long 0x08 5.--5. " PC69 ,GP69 Output Pin Clear" "-,L" bitfld.long 0x08 4.--4. " PC68 ,GP68 Output Pin Clear" "-,L" bitfld.long 0x08 3.--3. " PC67 ,GP67 Output Pin Clear" "-,L" bitfld.long 0x08 2.--2. " PC66 ,GP66 Output Pin Clear" "-,L" bitfld.long 0x08 1.--1. " PC65 ,GP65 Output Pin Clear" "-,L" bitfld.long 0x08 0.--0. " PC64 ,GP64 Output Pin Clear" "-,L" textline " " group asd:0x40e00030++0x0b line.long 0x00 "GRER0,GPIO Rising-Edge Detect Register GPIO<31:0>" bitfld.long 0x00 31.--31. "RE31 ,GP31 Rising Edge Detect" "dis,ena" bitfld.long 0x00 30.--30. " RE30 ,GP30 Rising Edge Detect" "dis,ena" bitfld.long 0x00 29.--29. " RE29 ,GP29 Rising Edge Detect" "dis,ena" bitfld.long 0x00 28.--28. " RE28 ,GP28 Rising Edge Detect" "dis,ena" bitfld.long 0x00 27.--27. " RE27 ,GP27 Rising Edge Detect" "dis,ena" bitfld.long 0x00 26.--26. " RE26 ,GP26 Rising Edge Detect" "dis,ena" bitfld.long 0x00 25.--25. " RE25 ,GP25 Rising Edge Detect" "dis,ena" bitfld.long 0x00 24.--24. " RE24 ,GP24 Rising Edge Detect" "dis,ena" textline " " bitfld.long 0x00 23.--23. "RE23 ,GP23 Rising Edge Detect" "dis,ena" bitfld.long 0x00 22.--22. " RE22 ,GP22 Rising Edge Detect" "dis,ena" bitfld.long 0x00 21.--21. " RE21 ,GP21 Rising Edge Detect" "dis,ena" bitfld.long 0x00 20.--20. " RE20 ,GP20 Rising Edge Detect" "dis,ena" bitfld.long 0x00 19.--19. " RE19 ,GP19 Rising Edge Detect" "dis,ena" bitfld.long 0x00 18.--18. " RE18 ,GP18 Rising Edge Detect" "dis,ena" bitfld.long 0x00 17.--17. " RE17 ,GP17 Rising Edge Detect" "dis,ena" bitfld.long 0x00 16.--16. " RE16 ,GP16 Rising Edge Detect" "dis,ena" textline " " bitfld.long 0x00 15.--15. "RE15 ,GP15 Rising Edge Detect" "dis,ena" bitfld.long 0x00 14.--14. " RE14 ,GP14 Rising Edge Detect" "dis,ena" bitfld.long 0x00 13.--13. " RE13 ,GP13 Rising Edge Detect" "dis,ena" bitfld.long 0x00 12.--12. " RE12 ,GP12 Rising Edge Detect" "dis,ena" bitfld.long 0x00 11.--11. " RE11 ,GP11 Rising Edge Detect" "dis,ena" bitfld.long 0x00 10.--10. " RE10 ,GP10 Rising Edge Detect" "dis,ena" bitfld.long 0x00 9.--9. " RE9 ,GP9 Rising Edge Detect" "dis,ena" bitfld.long 0x00 8.--8. " RE8 ,GP8 Rising Edge Detect" "dis,ena" textline " " bitfld.long 0x00 7.--7. "RE7 ,GP7 Rising Edge Detect" "dis,ena" bitfld.long 0x00 6.--6. " RE6 ,GP6 Rising Edge Detect" "dis,ena" bitfld.long 0x00 5.--5. " RE5 ,GP5 Rising Edge Detect" "dis,ena" bitfld.long 0x00 4.--4. " RE4 ,GP4 Rising Edge Detect" "dis,ena" bitfld.long 0x00 3.--3. " RE3 ,GP3 Rising Edge Detect" "dis,ena" bitfld.long 0x00 2.--2. " RE2 ,GP2 Rising Edge Detect" "dis,ena" bitfld.long 0x00 1.--1. " RE1 ,GP1 Rising Edge Detect" "dis,ena" bitfld.long 0x00 0.--0. " RE0 ,GP0 Rising Edge Detect" "dis,ena" line.long 0x04 "GRER1,GPIO Rising-Edge Detect Register GPIO<63:32>" bitfld.long 0x04 31.--31. "RE63 ,GP63 Rising Edge Detect" "dis,ena" bitfld.long 0x04 30.--30. " RE62 ,GP62 Rising Edge Detect" "dis,ena" bitfld.long 0x04 29.--29. " RE61 ,GP61 Rising Edge Detect" "dis,ena" bitfld.long 0x04 28.--28. " RE60 ,GP60 Rising Edge Detect" "dis,ena" bitfld.long 0x04 27.--27. " RE59 ,GP59 Rising Edge Detect" "dis,ena" bitfld.long 0x04 26.--26. " RE58 ,GP58 Rising Edge Detect" "dis,ena" bitfld.long 0x04 25.--25. " RE57 ,GP57 Rising Edge Detect" "dis,ena" bitfld.long 0x04 24.--24. " RE56 ,GP56 Rising Edge Detect" "dis,ena" textline " " bitfld.long 0x04 23.--23. "RE55 ,GP55 Rising Edge Detect" "dis,ena" bitfld.long 0x04 22.--22. " RE54 ,GP54 Rising Edge Detect" "dis,ena" bitfld.long 0x04 21.--21. " RE53 ,GP53 Rising Edge Detect" "dis,ena" bitfld.long 0x04 20.--20. " RE52 ,GP52 Rising Edge Detect" "dis,ena" bitfld.long 0x04 19.--19. " RE51 ,GP51 Rising Edge Detect" "dis,ena" bitfld.long 0x04 18.--18. " RE50 ,GP50 Rising Edge Detect" "dis,ena" bitfld.long 0x04 17.--17. " RE49 ,GP49 Rising Edge Detect" "dis,ena" bitfld.long 0x04 16.--16. " RE48 ,GP48 Rising Edge Detect" "dis,ena" textline " " bitfld.long 0x04 15.--15. "RE47 ,GP47 Rising Edge Detect" "dis,ena" bitfld.long 0x04 14.--14. " RE46 ,GP46 Rising Edge Detect" "dis,ena" bitfld.long 0x04 13.--13. " RE45 ,GP45 Rising Edge Detect" "dis,ena" bitfld.long 0x04 12.--12. " RE44 ,GP44 Rising Edge Detect" "dis,ena" bitfld.long 0x04 11.--11. " RE43 ,GP43 Rising Edge Detect" "dis,ena" bitfld.long 0x04 10.--10. " RE42 ,GP42 Rising Edge Detect" "dis,ena" bitfld.long 0x04 9.--9. " RE41 ,GP41 Rising Edge Detect" "dis,ena" bitfld.long 0x04 8.--8. " RE40 ,GP40 Rising Edge Detect" "dis,ena" textline " " bitfld.long 0x04 7.--7. "RE39 ,GP39 Rising Edge Detect" "dis,ena" bitfld.long 0x04 6.--6. " RE38 ,GP38 Rising Edge Detect" "dis,ena" bitfld.long 0x04 5.--5. " RE37 ,GP37 Rising Edge Detect" "dis,ena" bitfld.long 0x04 4.--4. " RE36 ,GP36 Rising Edge Detect" "dis,ena" bitfld.long 0x04 3.--3. " RE35 ,GP35 Rising Edge Detect" "dis,ena" bitfld.long 0x04 2.--2. " RE34 ,GP34 Rising Edge Detect" "dis,ena" bitfld.long 0x04 1.--1. " RE33 ,GP33 Rising Edge Detect" "dis,ena" bitfld.long 0x04 0.--0. " RE32 ,GP32 Rising Edge Detect" "dis,ena" line.long 0x08 "GRER2,GPIO Rising-Edge Detect Register GPIO<71:64>" bitfld.long 0x08 7.--7. "RE71 ,GP71 Rising Edge Detect" "dis,ena" bitfld.long 0x08 6.--6. " RE70 ,GP70 Rising Edge Detect" "dis,ena" bitfld.long 0x08 5.--5. " RE69 ,GP69 Rising Edge Detect" "dis,ena" bitfld.long 0x08 4.--4. " RE68 ,GP68 Rising Edge Detect" "dis,ena" bitfld.long 0x08 3.--3. " RE67 ,GP67 Rising Edge Detect" "dis,ena" bitfld.long 0x08 2.--2. " RE66 ,GP66 Rising Edge Detect" "dis,ena" bitfld.long 0x08 1.--1. " RE65 ,GP65 Rising Edge Detect" "dis,ena" bitfld.long 0x08 0.--0. " RE64 ,GP64 Rising Edge Detect" "dis,ena" textline " " group asd:0x40e0003c++0x0b line.long 0x00 "GFER0,GPIO Falling-Edge Detect Register GPIO<31:0>" bitfld.long 0x00 31.--31. "FE31 ,GP31 Falling Edge Detect" "dis,ena" bitfld.long 0x00 30.--30. " FE30 ,GP30 Falling Edge Detect" "dis,ena" bitfld.long 0x00 29.--29. " FE29 ,GP29 Falling Edge Detect" "dis,ena" bitfld.long 0x00 28.--28. " FE28 ,GP28 Falling Edge Detect" "dis,ena" bitfld.long 0x00 27.--27. " FE27 ,GP27 Falling Edge Detect" "dis,ena" bitfld.long 0x00 26.--26. " FE26 ,GP26 Falling Edge Detect" "dis,ena" bitfld.long 0x00 25.--25. " FE25 ,GP25 Falling Edge Detect" "dis,ena" bitfld.long 0x00 24.--24. " FE24 ,GP24 Falling Edge Detect" "dis,ena" textline " " bitfld.long 0x00 23.--23. "FE23 ,GP23 Falling Edge Detect" "dis,ena" bitfld.long 0x00 22.--22. " FE22 ,GP22 Falling Edge Detect" "dis,ena" bitfld.long 0x00 21.--21. " FE21 ,GP21 Falling Edge Detect" "dis,ena" bitfld.long 0x00 20.--20. " FE20 ,GP20 Falling Edge Detect" "dis,ena" bitfld.long 0x00 19.--19. " FE19 ,GP19 Falling Edge Detect" "dis,ena" bitfld.long 0x00 18.--18. " FE18 ,GP18 Falling Edge Detect" "dis,ena" bitfld.long 0x00 17.--17. " FE17 ,GP17 Falling Edge Detect" "dis,ena" bitfld.long 0x00 16.--16. " FE16 ,GP16 Falling Edge Detect" "dis,ena" textline " " bitfld.long 0x00 15.--15. "FE15 ,GP15 Falling Edge Detect" "dis,ena" bitfld.long 0x00 14.--14. " FE14 ,GP14 Falling Edge Detect" "dis,ena" bitfld.long 0x00 13.--13. " FE13 ,GP13 Falling Edge Detect" "dis,ena" bitfld.long 0x00 12.--12. " FE12 ,GP12 Falling Edge Detect" "dis,ena" bitfld.long 0x00 11.--11. " FE11 ,GP11 Falling Edge Detect" "dis,ena" bitfld.long 0x00 10.--10. " FE10 ,GP10 Falling Edge Detect" "dis,ena" bitfld.long 0x00 9.--9. " FE9 ,GP9 Falling Edge Detect" "dis,ena" bitfld.long 0x00 8.--8. " FE8 ,GP8 Falling Edge Detect" "dis,ena" textline " " bitfld.long 0x00 7.--7. "FE7 ,GP7 Falling Edge Detect" "dis,ena" bitfld.long 0x00 6.--6. " FE6 ,GP6 Falling Edge Detect" "dis,ena" bitfld.long 0x00 5.--5. " FE5 ,GP5 Falling Edge Detect" "dis,ena" bitfld.long 0x00 4.--4. " FE4 ,GP4 Falling Edge Detect" "dis,ena" bitfld.long 0x00 3.--3. " FE3 ,GP3 Falling Edge Detect" "dis,ena" bitfld.long 0x00 2.--2. " FE2 ,GP2 Falling Edge Detect" "dis,ena" bitfld.long 0x00 1.--1. " FE1 ,GP1 Falling Edge Detect" "dis,ena" bitfld.long 0x00 0.--0. " FE0 ,GP0 Falling Edge Detect" "dis,ena" line.long 0x04 "GFER1,GPIO Falling-Edge Detect Register GPIO<63:32>" bitfld.long 0x04 31.--31. "FE63 ,GP63 Falling Edge Detect" "dis,ena" bitfld.long 0x04 30.--30. " FE62 ,GP62 Falling Edge Detect" "dis,ena" bitfld.long 0x04 29.--29. " FE61 ,GP61 Falling Edge Detect" "dis,ena" bitfld.long 0x04 28.--28. " FE60 ,GP60 Falling Edge Detect" "dis,ena" bitfld.long 0x04 27.--27. " FE59 ,GP59 Falling Edge Detect" "dis,ena" bitfld.long 0x04 26.--26. " FE58 ,GP58 Falling Edge Detect" "dis,ena" bitfld.long 0x04 25.--25. " FE57 ,GP57 Falling Edge Detect" "dis,ena" bitfld.long 0x04 24.--24. " FE56 ,GP56 Falling Edge Detect" "dis,ena" textline " " bitfld.long 0x04 23.--23. "FE55 ,GP55 Falling Edge Detect" "dis,ena" bitfld.long 0x04 22.--22. " FE54 ,GP54 Falling Edge Detect" "dis,ena" bitfld.long 0x04 21.--21. " FE53 ,GP53 Falling Edge Detect" "dis,ena" bitfld.long 0x04 20.--20. " FE52 ,GP52 Falling Edge Detect" "dis,ena" bitfld.long 0x04 19.--19. " FE51 ,GP51 Falling Edge Detect" "dis,ena" bitfld.long 0x04 18.--18. " FE50 ,GP50 Falling Edge Detect" "dis,ena" bitfld.long 0x04 17.--17. " FE49 ,GP49 Falling Edge Detect" "dis,ena" bitfld.long 0x04 16.--16. " FE48 ,GP48 Falling Edge Detect" "dis,ena" textline " " bitfld.long 0x04 15.--15. "FE47 ,GP47 Falling Edge Detect" "dis,ena" bitfld.long 0x04 14.--14. " FE46 ,GP46 Falling Edge Detect" "dis,ena" bitfld.long 0x04 13.--13. " FE45 ,GP45 Falling Edge Detect" "dis,ena" bitfld.long 0x04 12.--12. " FE44 ,GP44 Falling Edge Detect" "dis,ena" bitfld.long 0x04 11.--11. " FE43 ,GP43 Falling Edge Detect" "dis,ena" bitfld.long 0x04 10.--10. " FE42 ,GP42 Falling Edge Detect" "dis,ena" bitfld.long 0x04 9.--9. " FE41 ,GP41 Falling Edge Detect" "dis,ena" bitfld.long 0x04 8.--8. " FE40 ,GP40 Falling Edge Detect" "dis,ena" textline " " bitfld.long 0x04 7.--7. "FE39 ,GP39 Falling Edge Detect" "dis,ena" bitfld.long 0x04 6.--6. " FE38 ,GP38 Falling Edge Detect" "dis,ena" bitfld.long 0x04 5.--5. " FE37 ,GP37 Falling Edge Detect" "dis,ena" bitfld.long 0x04 4.--4. " FE36 ,GP36 Falling Edge Detect" "dis,ena" bitfld.long 0x04 3.--3. " FE35 ,GP35 Falling Edge Detect" "dis,ena" bitfld.long 0x04 2.--2. " FE34 ,GP34 Falling Edge Detect" "dis,ena" bitfld.long 0x04 1.--1. " FE33 ,GP33 Falling Edge Detect" "dis,ena" bitfld.long 0x04 0.--0. " FE32 ,GP32 Falling Edge Detect" "dis,ena" line.long 0x08 "GFER2,GPIO Falling-Edge Detect Register GPIO<71:64>" bitfld.long 0x08 7.--7. "FE71 ,GP71 Falling Edge Detect" "dis,ena" bitfld.long 0x08 6.--6. " FE70 ,GP70 Falling Edge Detect" "dis,ena" bitfld.long 0x08 5.--5. " FE69 ,GP69 Falling Edge Detect" "dis,ena" bitfld.long 0x08 4.--4. " FE68 ,GP68 Falling Edge Detect" "dis,ena" bitfld.long 0x08 3.--3. " FE67 ,GP67 Falling Edge Detect" "dis,ena" bitfld.long 0x08 2.--2. " FE66 ,GP66 Falling Edge Detect" "dis,ena" bitfld.long 0x08 1.--1. " FE65 ,GP65 Falling Edge Detect" "dis,ena" bitfld.long 0x08 0.--0. " FE64 ,GP64 Falling Edge Detect" "dis,ena" textline " " group asd:0x40e00048++0x0b line.long 0x00 "GEDR0,GPIO Edge Detect Status Register GPIO<31:0>" bitfld.long 0x00 31.--31. "ED31 ,GP31 Edge Detect occured" "no,yes" bitfld.long 0x00 30.--30. " ED30 ,GP30 Edge Detect occured" "no,yes" bitfld.long 0x00 29.--29. " ED29 ,GP29 Edge Detect occured" "no,yes" bitfld.long 0x00 28.--28. " ED28 ,GP28 Edge Detect occured" "no,yes" bitfld.long 0x00 27.--27. " ED27 ,GP27 Edge Detect occured" "no,yes" bitfld.long 0x00 26.--26. " ED26 ,GP26 Edge Detect occured" "no,yes" bitfld.long 0x00 25.--25. " ED25 ,GP25 Edge Detect occured" "no,yes" bitfld.long 0x00 24.--24. " ED24 ,GP24 Edge Detect occured" "no,yes" textline " " bitfld.long 0x00 23.--23. "ED23 ,GP23 Edge Detect occured" "no,yes" bitfld.long 0x00 22.--22. " ED22 ,GP22 Edge Detect occured" "no,yes" bitfld.long 0x00 21.--21. " ED21 ,GP21 Edge Detect occured" "no,yes" bitfld.long 0x00 20.--20. " ED20 ,GP20 Edge Detect occured" "no,yes" bitfld.long 0x00 19.--19. " ED19 ,GP19 Edge Detect occured" "no,yes" bitfld.long 0x00 18.--18. " ED18 ,GP18 Edge Detect occured" "no,yes" bitfld.long 0x00 17.--17. " ED17 ,GP17 Edge Detect occured" "no,yes" bitfld.long 0x00 16.--16. " ED16 ,GP16 Edge Detect occured" "no,yes" textline " " bitfld.long 0x00 15.--15. "ED15 ,GP15 Edge Detect occured" "no,yes" bitfld.long 0x00 14.--14. " ED14 ,GP14 Edge Detect occured" "no,yes" bitfld.long 0x00 13.--13. " ED13 ,GP13 Edge Detect occured" "no,yes" bitfld.long 0x00 12.--12. " ED12 ,GP12 Edge Detect occured" "no,yes" bitfld.long 0x00 11.--11. " ED11 ,GP11 Edge Detect occured" "no,yes" bitfld.long 0x00 10.--10. " ED10 ,GP10 Edge Detect occured" "no,yes" bitfld.long 0x00 9.--9. " ED9 ,GP9 Edge Detect occured" "no,yes" bitfld.long 0x00 8.--8. " ED8 ,GP8 Edge Detect occured" "no,yes" textline " " bitfld.long 0x00 7.--7. "ED7 ,GP7 Edge Detect occured" "no,yes" bitfld.long 0x00 6.--6. " ED6 ,GP6 Edge Detect occured" "no,yes" bitfld.long 0x00 5.--5. " ED5 ,GP5 Edge Detect occured" "no,yes" bitfld.long 0x00 4.--4. " ED4 ,GP4 Edge Detect occured" "no,yes" bitfld.long 0x00 3.--3. " ED3 ,GP3 Edge Detect occured" "no,yes" bitfld.long 0x00 2.--2. " ED2 ,GP2 Edge Detect occured" "no,yes" bitfld.long 0x00 1.--1. " ED1 ,GP1 Edge Detect occured" "no,yes" bitfld.long 0x00 0.--0. " ED0 ,GP0 Edge Detect occured" "no,yes" line.long 0x04 "GEDR1,GPIO Edge Detect Status Register GPIO<63:32>" bitfld.long 0x04 31.--31. "ED63 ,GP63 Edge Detect occured" "no,yes" bitfld.long 0x04 30.--30. " ED62 ,GP62 Edge Detect occured" "no,yes" bitfld.long 0x04 29.--29. " ED61 ,GP61 Edge Detect occured" "no,yes" bitfld.long 0x04 28.--28. " ED60 ,GP60 Edge Detect occured" "no,yes" bitfld.long 0x04 27.--27. " ED59 ,GP59 Edge Detect occured" "no,yes" bitfld.long 0x04 26.--26. " ED58 ,GP58 Edge Detect occured" "no,yes" bitfld.long 0x04 25.--25. " ED57 ,GP57 Edge Detect occured" "no,yes" bitfld.long 0x04 24.--24. " ED56 ,GP56 Edge Detect occured" "no,yes" textline " " bitfld.long 0x04 23.--23. "ED55 ,GP55 Edge Detect occured" "no,yes" bitfld.long 0x04 22.--22. " ED54 ,GP54 Edge Detect occured" "no,yes" bitfld.long 0x04 21.--21. " ED53 ,GP53 Edge Detect occured" "no,yes" bitfld.long 0x04 20.--20. " ED52 ,GP52 Edge Detect occured" "no,yes" bitfld.long 0x04 19.--19. " ED51 ,GP51 Edge Detect occured" "no,yes" bitfld.long 0x04 18.--18. " ED50 ,GP50 Edge Detect occured" "no,yes" bitfld.long 0x04 17.--17. " ED49 ,GP49 Edge Detect occured" "no,yes" bitfld.long 0x04 16.--16. " ED48 ,GP48 Edge Detect occured" "no,yes" textline " " bitfld.long 0x04 15.--15. "ED47 ,GP47 Edge Detect occured" "no,yes" bitfld.long 0x04 14.--14. " ED46 ,GP46 Edge Detect occured" "no,yes" bitfld.long 0x04 13.--13. " ED45 ,GP45 Edge Detect occured" "no,yes" bitfld.long 0x04 12.--12. " ED44 ,GP44 Edge Detect occured" "no,yes" bitfld.long 0x04 11.--11. " ED43 ,GP43 Edge Detect occured" "no,yes" bitfld.long 0x04 10.--10. " ED42 ,GP42 Edge Detect occured" "no,yes" bitfld.long 0x04 9.--9. " ED41 ,GP41 Edge Detect occured" "no,yes" bitfld.long 0x04 8.--8. " ED40 ,GP40 Edge Detect occured" "no,yes" textline " " bitfld.long 0x04 7.--7. "ED39 ,GP39 Edge Detect occured" "no,yes" bitfld.long 0x04 6.--6. " ED38 ,GP38 Edge Detect occured" "no,yes" bitfld.long 0x04 5.--5. " ED37 ,GP37 Edge Detect occured" "no,yes" bitfld.long 0x04 4.--4. " ED36 ,GP36 Edge Detect occured" "no,yes" bitfld.long 0x04 3.--3. " ED35 ,GP35 Edge Detect occured" "no,yes" bitfld.long 0x04 2.--2. " ED34 ,GP34 Edge Detect occured" "no,yes" bitfld.long 0x04 1.--1. " ED33 ,GP33 Edge Detect occured" "no,yes" bitfld.long 0x04 0.--0. " ED32 ,GP32 Edge Detect occured" "no,yes" line.long 0x08 "GEDR2,GPIO Edge Detect Status Register GPIO<71:64>" bitfld.long 0x08 7.--7. "ED71 ,GP71 Edge Detect occured" "no,yes" bitfld.long 0x08 6.--6. " ED70 ,GP70 Edge Detect occured" "no,yes" bitfld.long 0x08 5.--5. " ED69 ,GP69 Edge Detect occured" "no,yes" bitfld.long 0x08 4.--4. " ED68 ,GP68 Edge Detect occured" "no,yes" bitfld.long 0x08 3.--3. " ED67 ,GP67 Edge Detect occured" "no,yes" bitfld.long 0x08 2.--2. " ED66 ,GP66 Edge Detect occured" "no,yes" bitfld.long 0x08 1.--1. " ED65 ,GP65 Edge Detect occured" "no,yes" bitfld.long 0x08 0.--0. " ED64 ,GP64 Edge Detect occured" "no,yes" textline " " group asd:0x40e00054++0x17 line.long 0x00 "GAFR0_L,GPIO Alternate Funtion Select Register GPIO<15:0>" bitfld.long 0x00 30.--31. "AF15 ,GP15 F2_OUT Active low chip select 1" "I/O,f1,nCS_1,f3" bitfld.long 0x00 28.--29. " AF14 ,GP14 F1_IN memory controller alternate bus master request" "I/O,MBREQ,f2,f3" bitfld.long 0x00 26.--27. " AF13 ,GP13 F2_OUT memory controller grant" "I/O,f1,MBGNT,f3" bitfld.long 0x00 24.--25. " AF12 ,GP12 F1_OUT 32 kHz out" "I/O,32kHz,f2,f3" textline " " bitfld.long 0x00 22.--23. "AF11 ,GP11 F1_OUT 3.6 MHz oscillator output" "I/O,3.6MHz,f2,f3" bitfld.long 0x00 20.--21. " AF10 ,GP10 F1_OUT real time clock (1Hz)" "I/O,RTCCLK,f2,f3" bitfld.long 0x00 18.--19. " AF9 ,GP9 F1_OUT MMC Chip Select 1" "I/O,MMCCS1,f2,f3" bitfld.long 0x00 16.--17. " AF8 ,GP8 F1_OUT MMC Chip Select 0" "I/O,MMCCS0,f2,f3" textline " " bitfld.long 0x00 14.--15. "AF7 ,GP7 F1_OUT 48 MHz clock output" "I/O,48MHz clk,f2,f3" bitfld.long 0x00 12.--13. " AF6 ,GP6 F1_OUT MMC Clock" "I/O,MMCCLK,f2,f3" bitfld.long 0x00 10.--11. " AF5 ,GP5" "N/A,f1,f2,f3" bitfld.long 0x00 8.--9. " AF4 ,GP4" "N/A,f1,f2,f3" textline " " bitfld.long 0x00 6.--7. "AF3 ,GP3" "N/A,f1,f2,f3" bitfld.long 0x00 4.--5. " AF2 ,GP2" "N/A,f1,f2,f3" bitfld.long 0x00 2.--3. " AF1 ,GP1 F1_IN Active low GP_reset" "I/O,GP_RST,f2,f3" bitfld.long 0x00 0.--1. " AF0 ,GP0" "N/A,f1,f2,f3" line.long 0x04 "GAFR0_U,GPIO Alternate Funtion Select Register GPIO<31:16>" bitfld.long 0x04 30.--31. "AF31 ,GP31 F1_OUT AC97 Sync, F2_OUT I2S Sync" "I/O,SYNC,SYNC,f3" bitfld.long 0x04 28.--29. " AF30 ,GP30 F1_OUT AC97 Sdata_out, F2_OUT I2S Sdata_out" "I/O,SDATA_OUT,SDATA_OUT,f3" bitfld.long 0x04 26.--27. " AF29 ,GP29 F1_IN AC97 Sdata_in0, F2_IN I2S Sdata_in" "I/O,SDATA_IN0,SDATA_IN,f3" bitfld.long 0x04 24.--25. " AF28 ,GP28 F1_IN AC97 bit_clk, F1_OUT I2S bit_clk, F2_IN I2S bit_clk" "I/O,BITCLK,BITCLK,f3" textline " " bitfld.long 0x04 22.--23. "AF27 ,GP27 F1_IN SSP ext_clock" "I/O,EXTCLK,f2,f3" bitfld.long 0x04 20.--21. " AF26 ,GP26 F1_IN SSP receive" "I/O,RXD,f2,f3" bitfld.long 0x04 18.--19. " AF25 ,GP25 F2_OUT SSP transmit" "I/O,f1,TXD,f3" bitfld.long 0x04 16.--17. " AF24 ,GP24 F2_OUT SSP Frame" "I/O,f1,SFRM,f3" textline " " bitfld.long 0x04 14.--15. "AF23 ,GP23 F2_OUT SSP clock" "I/O,f1,SCLK,f3" bitfld.long 0x04 12.--13. " AF22 ,GP22" "I/O,f1,f2,f3" bitfld.long 0x04 10.--11. " AF21 ,GP21" "I/O,f1,f2,f3" bitfld.long 0x04 8.--9. " AF20 ,GP20 F1_IN External DMA Request" "I/O,DREQ[0],f2,f3" textline " " bitfld.long 0x04 6.--7. "AF19 ,GP19 F1_IN External DMA Request" "I/O,DREQ[1],f2,f3" bitfld.long 0x04 4.--5. " AF18 ,GP18 F1_IN Ext. Bus Ready" "I/O,RDY,f2,f3" bitfld.long 0x04 2.--3. " AF17 ,GP17 F2_OUT PWM1 output" "I/O,f1,PWM1,f3" bitfld.long 0x04 0.--1. " AF16 ,GP16 F2_OUT PWM0 output" "I/O,f1,PWM0,f3" line.long 0x08 "GAFR1_L,GPIO Alternate Funtion Select Register GPIO<47:32>" bitfld.long 0x08 30.--31. "AF47 ,GP47 F1_OUT transmit data, F2_OUT STD_UART ICP transmit data" "I/O,TXD,ICP_TXD,f3" bitfld.long 0x08 28.--29. " AF46 ,GP46 F1_IN ICP receive data, F2_IN STD_UART receive data" "I/O,ICP_RXD,RXD,f3" bitfld.long 0x08 26.--27. " AF45 ,GP45 F2_OUT BTUART request to send" "I/O,f1,RTS,f3" bitfld.long 0x08 24.--25. " AF44 ,GP44 F1_IN BTUART clear to send" "I/O,CTS,f2,f3" textline " " bitfld.long 0x08 22.--23. "AF43 ,GP43 F2_OUT BTUART Transmit Data" "N/A,f1,BTTXD,f3" bitfld.long 0x08 20.--21. " AF42 ,GP42 F1_IN BTUART Receive Data" "I/O,BTRXD,f2,f3" bitfld.long 0x08 18.--19. " AF41 ,GP41 F2_OUT FFUART Request to Send" "I/O,f1,RTS,f3" bitfld.long 0x08 16.--17. " AF40 ,GP40 F2_OUT FFUART Data Terminal Ready" "I/O,f1,DTR,f3" textline " " bitfld.long 0x08 14.--15. "AF39 ,GP39 F1_OUT MMC Chip Select 1, F2_OUT FFUART transmit data" "N/A,MMCCS1,FFTXD,f3" bitfld.long 0x08 12.--13. " AF38 ,GP38 F1_IN FFUART Ring Indicator" "I/O,RI,f2,f3" bitfld.long 0x08 10.--11. " AF37 ,GP37 F1_IN FFUART Data Set Ready" "I/O,DSR,f2,f3" bitfld.long 0x08 8.--9. " AF36 ,GP36 F1_IN FFUART Data Carrier Detect" "I/O,DCD,f2,f3" textline " " bitfld.long 0x08 6.--7. "AF35 ,GP35 F1_IN FFUART Clear to send" "I/O,CTS,f2,f3" bitfld.long 0x08 4.--5. " AF34 ,GP34 F1_IN FFUART receive, F2_OUT MMC Chip Select 0" "N/A,FFRXD,MMCCS0,f3" bitfld.long 0x08 2.--3. " AF33 ,GP33 F2_OUT Active low chip select 5" "I/O,f1,nCS[5],f3" bitfld.long 0x08 0.--1. " AF32 ,GP32 F1_IN AC97 Sdata_in1" "I/O,SDATA_IN1,f2,f3" line.long 0x0c "GAFR1_U,GPIO Alternate Funtion Select Register GPIO<63:48>" bitfld.long 0x0c 30.--31. "AF63 ,GP63 F2_OUT LCD data pin 5" "I/O,f1,LDD[5],f3" bitfld.long 0x0c 28.--29. " AF62 ,GP62 F2_OUT LCD data pin 4" "I/O,f1,LDD[4],f3" bitfld.long 0x0c 26.--27. " AF61 ,GP61 F2_OUT LCD data pin 3" "I/O,f1,LDD[3],f3" bitfld.long 0x0c 24.--25. " AF60 ,GP60 F2_OUT LCD data pin 2" "I/O,f1,LDD[2],f3" textline " " bitfld.long 0x0c 22.--23. "AF59 ,GP59 F2_OUT LCD data pin 1" "I/O,f1,LDD[1],f3" bitfld.long 0x0c 20.--21. " AF58 ,GP58 F2_OUT LCD data pin 0" "I/O,f1,LDD[0],f3" bitfld.long 0x0c 18.--19. " AF57 ,GP57 F1_IN Bus Width Select for I/O Card Space" "I/O,nIOIS16,f2,f3" bitfld.long 0x0c 16.--17. " AF56 ,GP56 F1_IN Wait signal for Card Space" "I/O,nPWAIT,f2,f3" textline " " bitfld.long 0x0c 14.--15. "AF55 ,GP55 F2_OUT Card Address bit 26" "I/O,f1,nPREG,f3" bitfld.long 0x0c 12.--13. " AF54 ,GP54 F1_OUT MMC clock, F2_OUT Socket Select for Card Space" "I/O,MMCCLK,nSKTSEL,f3" bitfld.long 0x0c 10.--11. " AF53 ,GP53 F1_OUT MMC clock, F2_OUT Card Enable for Card Space" "I/O,MMCCLK,nPCE[2],f3" bitfld.long 0x0c 8.--9. " AF52 ,GP52 F2_OUT Card Enable for Card Space" "I/O,f1,nPCE[1],f3" textline " " bitfld.long 0x0c 6.--7. "AF51 ,GP51 F2_OUT I/O Write for Card Space" "I/O,f1,nPIOW,f3" bitfld.long 0x0c 4.--5. " AF50 ,GP50 F2_OUT I/O Read for Card Space" "I/O,f1,nPIOR,f3" bitfld.long 0x0c 2.--3. " AF49 ,GP49 F2_OUT Write Enable for Card Space" "I/O,f1,nPWE,f3" bitfld.long 0x0c 0.--1. " AF48 ,GP48 F2_OUT Output Enable for Card Space" "I/O,f1,nPOE,f3" line.long 0x10 "GAFR2_L,GPIO Alternate Funtion Select Register GPIO<79:64>" bitfld.long 0x10 14.--15. "AF71 ,GP71 F1_OUT 3.6MHz Oscillator Clock, F2_OUT LCD data pin 13" "I/O,3.6MHz,LDD[13],f3" bitfld.long 0x10 12.--13. " AF70 ,GP70 F1_OUT Real Time Clock (1Hz), F2_OUT LCD data pin 12" "I/O,RTCCLK,LDD[12],f3" bitfld.long 0x10 10.--11. " AF69 ,GP69 F1_OUT MMC_CLK, F2_OUT LCD data pin 11" "I/O,MMCCLK,LDD[11],f3" bitfld.long 0x10 8.--9. " AF68 ,GP68 F1_OUT MMC Chip Select 1, F2_OUT LCD data pin 10" "I/O,MMCCS1,LDD[10],f3" textline " " bitfld.long 0x10 6.--7. "AF67 ,GP67 F1_OUT MMC Chip Select 0, F2_OUT LCD data pin 9" "I/O,MMCCS0,LDD[9],f3" bitfld.long 0x10 4.--5. " AF66 ,GP66 F1_IN memory controller alternate bus master request, F2_OUT LCD data pin 8" "I/O,MBREQ,LDD[8],f3" bitfld.long 0x10 2.--3. " AF65 ,GP65 F2_OUT LCD data pin 7" "I/O,f1,LDD[7],f3" bitfld.long 0x10 0.--1. " AF64 ,GP64 F2_OUT LCD data pin 6" "I/O,f1,LDD[6],f3" tree.end ;end include file xscale/manitoba-gpio.ph ; %include xscale/manitoba-config.ph ; %include xscale/manitoba-ipc.ph ; %include xscale/manitoba-clock.ph ; %include xscale/manitoba-power.ph ; %include xscale/manitoba-pll.ph ; %include xscale/manitoba-multimedia.ph ;begin include file xscale/manitoba-uart.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; LSR Register is just copied from Cotulla, because ; it's not in the spec. ; It's also not clear if we have FFUART,BTUART and STUART or ; just STUART1-3. (Compare Register Map to UART description.) ; State: preliminary ; -------------------------------------------------------------------------------- tree "UARTs" ; -------------------------------------------------------------------------------- ;tree "FFUART" ;%include xscale/Manitoba-uart-regs.ph 0x40100000 ;tree.end ;tree "BTUART" ;%include xscale/Manitoba-uart-regs.ph 0x40200000 ;tree.end tree "STUART-1" ;begin include file xscale/manitoba-uart-regs.ph ;parameters: 0x40700000 width 8. 18. group asd:0x40700000++0x23 line.long 0x08 "IIR ,Interrupt Identification Register" bitfld.long 0x08 6.--7. "FIFOES ,Fifo Mode Enable Status" "dis,res,res,ena" bitfld.long 0x08 3.--3. " TOD ,Time Out Detected" "no,yes" bitfld.long 0x08 1.--2. " IID ,Interrupt Source Encoding" "Modem Status,Transmit FIFO request data,Received data available,Receive error" textline " " bitfld.long 0x08 0.--0. "IP ,Interrupt Pending" "yes,no" width 8. 8. group asd:0x40700000++0x23 line.long 0x08 "FCR ,Fifo Control Register" bitfld.long 0x08 6.--7. "ITL ,Interrupt Trigger Level" "1,8,16,32" bitfld.long 0x08 2.--2. " RESETTF ,Reset Transmitter Fifo" "no,yes" bitfld.long 0x08 1.--1. " RESETRF ,Reset Receiver Fifo" "no,yes" bitfld.long 0x08 0.--0. " TRFIFO ,Transmit and Receive Fifo Enable" "dis,ena" line.long 0x0C "LCR ,Line Control Register" bitfld.long 0x0C 7.--7. "DLAB ,Divisor Register Access is" "dis,ena" bitfld.long 0x0C 6.--6. " SB ,Set Break" "no,yes" bitfld.long 0x0C 5.--5. " STKYP ,Sticky Parity" "no,yes" textline " " bitfld.long 0x0C 4.--4. "EPS ,Even Parity Select" "odd,even" bitfld.long 0x0C 3.--3. " PEN ,Parity Enable" "dis,ena" bitfld.long 0x0C 2.--2. " STB ,Number of Stop Bits" "1,2" bitfld.long 0x0C 0.--1. " WLS ,Word Length Select" "5,6,7,8" line.long 0x10 "MCR ,Modem Control Register" bitfld.long 0x10 4.--4. "LOOP ,Loop back testmode is" "dis,ena" bitfld.long 0x10 3.--3. " OUT2 ,OUT2# signal is set to" "1,0" bitfld.long 0x10 2.--2. " OUT1 ,Out1 Test Bit" "0,1" bitfld.long 0x10 1.--1. " RTS ,RTS# pin is" "1,0" bitfld.long 0x10 0.--0. " DTS ,DTS# pin is" "1,0" line.long 0x14 "LSR ,Line Status Register" bitfld.long 0x14 7.--7. "FIFOE ,FIFO Error Status" "no,yes" bitfld.long 0x14 6.--6. " TEMT ,Transmitter Empty" "no,yes" bitfld.long 0x14 5.--5. " TDRQ ,Transmit Data Request" "no,yes" bitfld.long 0x14 4.--4. " BI ,Break Interrupt" "no,yes" textline " " bitfld.long 0x14 3.--3. "FE ,Framing Error" "no,yes" bitfld.long 0x14 2.--2. " PE ,Parity Error" "no,yes" bitfld.long 0x14 1.--1. " OE ,Overrun Error" "no,yes" bitfld.long 0x14 0.--0. " DR ,Data Ready" "no,yes" line.long 0x18 "MSR ,Modem Status Register" bitfld.long 0x18 7.--7. "DCD ,DCD# pin is" "1,0" bitfld.long 0x18 6.--6. " RI ,RI# pin is" "1,0" bitfld.long 0x18 5.--5. " DSR ,DSR# pin is" "1,0" bitfld.long 0x18 4.--4. " CTS ,CTS# pin is" "1,0" textline " " bitfld.long 0x18 3.--3. "DDCD ,DCD# pin has changed" "no,yes" bitfld.long 0x18 2.--2. " TERI ,RI# pin has changed" "no,yes" bitfld.long 0x18 1.--1. " DDSR ,DSR# pin has changed" "no,yes" bitfld.long 0x18 0.--0. " DCTS ,CTS# pin has changed" "no,yes" line.long 0x1C "SCR ,Scratchpad Register" hexfld.byte 0x1C "SCR ,Scratchpad Register" if (d.l(asd:0x40700000+0x0C)&0x80)==0x80 group asd:0x40700000++0x23 line.long 0x0 "DLL ,Divisor Latch Register Low" hexfld.byte 0x0 "DLL ,Low byte compare value to generate baud rate" line.long 0x4 "DLH ,Divisor Latch Register High" hexfld.byte 0x0 "DLH ,High byte compare value to generate baud rate" else group asd:0x40700000++0x23 line.long 0x20 "IRDASEL ,Infrared Selection Register" bitfld.long 0x20 4.--4. "RXPL ,Receive Data Polarity" "pos,neg" bitfld.long 0x20 3.--3. " TXPL ,Transmit Data Polarity" "pos,neg" bitfld.long 0x20 2.--2. " XMODE ,Transmit Pulse Witdh select" "3/16,1.6us" bitfld.long 0x20 1.--1. " RCVEIR ,Receiver SIR Enable" "dis,ena" bitfld.long 0x20 0.--0. " XMITIR ,Transmitter SIR Enable" "dis,ena" line.long 0x04 "IER ,Interrupt Enable Register" bitfld.long 0x04 7.--7. "DMAE ,DMA Request Enable" "dis,ena" bitfld.long 0x04 6.--6. " UUE ,UART Unit Enable" "dis,ena" bitfld.long 0x04 5.--5. " NRZE ,NRZ coding Enable" "dis,ena" bitfld.long 0x04 4.--4. " RTOIE ,Receiver data Time out interrupt is" "dis,ena" textline " " bitfld.long 0x04 3.--3. "MIE ,Modem Status interrupt is" "dis,ena" bitfld.long 0x04 2.--2. " RLSE ,Receiver Line Status interrupt is" "dis,ena" bitfld.long 0x04 1.--1. " TIE ,Transmit FIFO Data request Interrupt Enable is" "dis,ena" bitfld.long 0x04 0.--0. " RAVIE ,Receiver Data Available interrupt is" "dis,ena" hide.byte 0x0 "THR, Transmit Holding Register" hide.byte 0x0 "RBR, Receive Buffer Register" in endif ;end include file xscale/manitoba-uart-regs.ph tree.end tree "STUART-2" ;begin include file xscale/manitoba-uart-regs.ph ;parameters: 0x42002000 width 8. 18. group asd:0x42002000++0x23 line.long 0x08 "IIR ,Interrupt Identification Register" bitfld.long 0x08 6.--7. "FIFOES ,Fifo Mode Enable Status" "dis,res,res,ena" bitfld.long 0x08 3.--3. " TOD ,Time Out Detected" "no,yes" bitfld.long 0x08 1.--2. " IID ,Interrupt Source Encoding" "Modem Status,Transmit FIFO request data,Received data available,Receive error" textline " " bitfld.long 0x08 0.--0. "IP ,Interrupt Pending" "yes,no" width 8. 8. group asd:0x42002000++0x23 line.long 0x08 "FCR ,Fifo Control Register" bitfld.long 0x08 6.--7. "ITL ,Interrupt Trigger Level" "1,8,16,32" bitfld.long 0x08 2.--2. " RESETTF ,Reset Transmitter Fifo" "no,yes" bitfld.long 0x08 1.--1. " RESETRF ,Reset Receiver Fifo" "no,yes" bitfld.long 0x08 0.--0. " TRFIFO ,Transmit and Receive Fifo Enable" "dis,ena" line.long 0x0C "LCR ,Line Control Register" bitfld.long 0x0C 7.--7. "DLAB ,Divisor Register Access is" "dis,ena" bitfld.long 0x0C 6.--6. " SB ,Set Break" "no,yes" bitfld.long 0x0C 5.--5. " STKYP ,Sticky Parity" "no,yes" textline " " bitfld.long 0x0C 4.--4. "EPS ,Even Parity Select" "odd,even" bitfld.long 0x0C 3.--3. " PEN ,Parity Enable" "dis,ena" bitfld.long 0x0C 2.--2. " STB ,Number of Stop Bits" "1,2" bitfld.long 0x0C 0.--1. " WLS ,Word Length Select" "5,6,7,8" line.long 0x10 "MCR ,Modem Control Register" bitfld.long 0x10 4.--4. "LOOP ,Loop back testmode is" "dis,ena" bitfld.long 0x10 3.--3. " OUT2 ,OUT2# signal is set to" "1,0" bitfld.long 0x10 2.--2. " OUT1 ,Out1 Test Bit" "0,1" bitfld.long 0x10 1.--1. " RTS ,RTS# pin is" "1,0" bitfld.long 0x10 0.--0. " DTS ,DTS# pin is" "1,0" line.long 0x14 "LSR ,Line Status Register" bitfld.long 0x14 7.--7. "FIFOE ,FIFO Error Status" "no,yes" bitfld.long 0x14 6.--6. " TEMT ,Transmitter Empty" "no,yes" bitfld.long 0x14 5.--5. " TDRQ ,Transmit Data Request" "no,yes" bitfld.long 0x14 4.--4. " BI ,Break Interrupt" "no,yes" textline " " bitfld.long 0x14 3.--3. "FE ,Framing Error" "no,yes" bitfld.long 0x14 2.--2. " PE ,Parity Error" "no,yes" bitfld.long 0x14 1.--1. " OE ,Overrun Error" "no,yes" bitfld.long 0x14 0.--0. " DR ,Data Ready" "no,yes" line.long 0x18 "MSR ,Modem Status Register" bitfld.long 0x18 7.--7. "DCD ,DCD# pin is" "1,0" bitfld.long 0x18 6.--6. " RI ,RI# pin is" "1,0" bitfld.long 0x18 5.--5. " DSR ,DSR# pin is" "1,0" bitfld.long 0x18 4.--4. " CTS ,CTS# pin is" "1,0" textline " " bitfld.long 0x18 3.--3. "DDCD ,DCD# pin has changed" "no,yes" bitfld.long 0x18 2.--2. " TERI ,RI# pin has changed" "no,yes" bitfld.long 0x18 1.--1. " DDSR ,DSR# pin has changed" "no,yes" bitfld.long 0x18 0.--0. " DCTS ,CTS# pin has changed" "no,yes" line.long 0x1C "SCR ,Scratchpad Register" hexfld.byte 0x1C "SCR ,Scratchpad Register" if (d.l(asd:0x42002000+0x0C)&0x80)==0x80 group asd:0x42002000++0x23 line.long 0x0 "DLL ,Divisor Latch Register Low" hexfld.byte 0x0 "DLL ,Low byte compare value to generate baud rate" line.long 0x4 "DLH ,Divisor Latch Register High" hexfld.byte 0x0 "DLH ,High byte compare value to generate baud rate" else group asd:0x42002000++0x23 line.long 0x20 "IRDASEL ,Infrared Selection Register" bitfld.long 0x20 4.--4. "RXPL ,Receive Data Polarity" "pos,neg" bitfld.long 0x20 3.--3. " TXPL ,Transmit Data Polarity" "pos,neg" bitfld.long 0x20 2.--2. " XMODE ,Transmit Pulse Witdh select" "3/16,1.6us" bitfld.long 0x20 1.--1. " RCVEIR ,Receiver SIR Enable" "dis,ena" bitfld.long 0x20 0.--0. " XMITIR ,Transmitter SIR Enable" "dis,ena" line.long 0x04 "IER ,Interrupt Enable Register" bitfld.long 0x04 7.--7. "DMAE ,DMA Request Enable" "dis,ena" bitfld.long 0x04 6.--6. " UUE ,UART Unit Enable" "dis,ena" bitfld.long 0x04 5.--5. " NRZE ,NRZ coding Enable" "dis,ena" bitfld.long 0x04 4.--4. " RTOIE ,Receiver data Time out interrupt is" "dis,ena" textline " " bitfld.long 0x04 3.--3. "MIE ,Modem Status interrupt is" "dis,ena" bitfld.long 0x04 2.--2. " RLSE ,Receiver Line Status interrupt is" "dis,ena" bitfld.long 0x04 1.--1. " TIE ,Transmit FIFO Data request Interrupt Enable is" "dis,ena" bitfld.long 0x04 0.--0. " RAVIE ,Receiver Data Available interrupt is" "dis,ena" hide.byte 0x0 "THR, Transmit Holding Register" hide.byte 0x0 "RBR, Receive Buffer Register" in endif ;end include file xscale/manitoba-uart-regs.ph tree.end tree "STUART-3" ;begin include file xscale/manitoba-uart-regs.ph ;parameters: 0x42002100 width 8. 18. group asd:0x42002100++0x23 line.long 0x08 "IIR ,Interrupt Identification Register" bitfld.long 0x08 6.--7. "FIFOES ,Fifo Mode Enable Status" "dis,res,res,ena" bitfld.long 0x08 3.--3. " TOD ,Time Out Detected" "no,yes" bitfld.long 0x08 1.--2. " IID ,Interrupt Source Encoding" "Modem Status,Transmit FIFO request data,Received data available,Receive error" textline " " bitfld.long 0x08 0.--0. "IP ,Interrupt Pending" "yes,no" width 8. 8. group asd:0x42002100++0x23 line.long 0x08 "FCR ,Fifo Control Register" bitfld.long 0x08 6.--7. "ITL ,Interrupt Trigger Level" "1,8,16,32" bitfld.long 0x08 2.--2. " RESETTF ,Reset Transmitter Fifo" "no,yes" bitfld.long 0x08 1.--1. " RESETRF ,Reset Receiver Fifo" "no,yes" bitfld.long 0x08 0.--0. " TRFIFO ,Transmit and Receive Fifo Enable" "dis,ena" line.long 0x0C "LCR ,Line Control Register" bitfld.long 0x0C 7.--7. "DLAB ,Divisor Register Access is" "dis,ena" bitfld.long 0x0C 6.--6. " SB ,Set Break" "no,yes" bitfld.long 0x0C 5.--5. " STKYP ,Sticky Parity" "no,yes" textline " " bitfld.long 0x0C 4.--4. "EPS ,Even Parity Select" "odd,even" bitfld.long 0x0C 3.--3. " PEN ,Parity Enable" "dis,ena" bitfld.long 0x0C 2.--2. " STB ,Number of Stop Bits" "1,2" bitfld.long 0x0C 0.--1. " WLS ,Word Length Select" "5,6,7,8" line.long 0x10 "MCR ,Modem Control Register" bitfld.long 0x10 4.--4. "LOOP ,Loop back testmode is" "dis,ena" bitfld.long 0x10 3.--3. " OUT2 ,OUT2# signal is set to" "1,0" bitfld.long 0x10 2.--2. " OUT1 ,Out1 Test Bit" "0,1" bitfld.long 0x10 1.--1. " RTS ,RTS# pin is" "1,0" bitfld.long 0x10 0.--0. " DTS ,DTS# pin is" "1,0" line.long 0x14 "LSR ,Line Status Register" bitfld.long 0x14 7.--7. "FIFOE ,FIFO Error Status" "no,yes" bitfld.long 0x14 6.--6. " TEMT ,Transmitter Empty" "no,yes" bitfld.long 0x14 5.--5. " TDRQ ,Transmit Data Request" "no,yes" bitfld.long 0x14 4.--4. " BI ,Break Interrupt" "no,yes" textline " " bitfld.long 0x14 3.--3. "FE ,Framing Error" "no,yes" bitfld.long 0x14 2.--2. " PE ,Parity Error" "no,yes" bitfld.long 0x14 1.--1. " OE ,Overrun Error" "no,yes" bitfld.long 0x14 0.--0. " DR ,Data Ready" "no,yes" line.long 0x18 "MSR ,Modem Status Register" bitfld.long 0x18 7.--7. "DCD ,DCD# pin is" "1,0" bitfld.long 0x18 6.--6. " RI ,RI# pin is" "1,0" bitfld.long 0x18 5.--5. " DSR ,DSR# pin is" "1,0" bitfld.long 0x18 4.--4. " CTS ,CTS# pin is" "1,0" textline " " bitfld.long 0x18 3.--3. "DDCD ,DCD# pin has changed" "no,yes" bitfld.long 0x18 2.--2. " TERI ,RI# pin has changed" "no,yes" bitfld.long 0x18 1.--1. " DDSR ,DSR# pin has changed" "no,yes" bitfld.long 0x18 0.--0. " DCTS ,CTS# pin has changed" "no,yes" line.long 0x1C "SCR ,Scratchpad Register" hexfld.byte 0x1C "SCR ,Scratchpad Register" if (d.l(asd:0x42002100+0x0C)&0x80)==0x80 group asd:0x42002100++0x23 line.long 0x0 "DLL ,Divisor Latch Register Low" hexfld.byte 0x0 "DLL ,Low byte compare value to generate baud rate" line.long 0x4 "DLH ,Divisor Latch Register High" hexfld.byte 0x0 "DLH ,High byte compare value to generate baud rate" else group asd:0x42002100++0x23 line.long 0x20 "IRDASEL ,Infrared Selection Register" bitfld.long 0x20 4.--4. "RXPL ,Receive Data Polarity" "pos,neg" bitfld.long 0x20 3.--3. " TXPL ,Transmit Data Polarity" "pos,neg" bitfld.long 0x20 2.--2. " XMODE ,Transmit Pulse Witdh select" "3/16,1.6us" bitfld.long 0x20 1.--1. " RCVEIR ,Receiver SIR Enable" "dis,ena" bitfld.long 0x20 0.--0. " XMITIR ,Transmitter SIR Enable" "dis,ena" line.long 0x04 "IER ,Interrupt Enable Register" bitfld.long 0x04 7.--7. "DMAE ,DMA Request Enable" "dis,ena" bitfld.long 0x04 6.--6. " UUE ,UART Unit Enable" "dis,ena" bitfld.long 0x04 5.--5. " NRZE ,NRZ coding Enable" "dis,ena" bitfld.long 0x04 4.--4. " RTOIE ,Receiver data Time out interrupt is" "dis,ena" textline " " bitfld.long 0x04 3.--3. "MIE ,Modem Status interrupt is" "dis,ena" bitfld.long 0x04 2.--2. " RLSE ,Receiver Line Status interrupt is" "dis,ena" bitfld.long 0x04 1.--1. " TIE ,Transmit FIFO Data request Interrupt Enable is" "dis,ena" bitfld.long 0x04 0.--0. " RAVIE ,Receiver Data Available interrupt is" "dis,ena" hide.byte 0x0 "THR, Transmit Holding Register" hide.byte 0x0 "RBR, Receive Buffer Register" in endif ;end include file xscale/manitoba-uart-regs.ph tree.end tree.end ;end include file xscale/manitoba-uart.ph ;begin include file xscale/manitoba-ssp.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; Copied from Cotulla; Should be ok ; State: preliminary ; -------------------------------------------------------------------------------- tree "SSP" ; -------------------------------------------------------------------------------- group asd:0x41000000++0x07 line.long 0x00 "SSCR0,SSP Control Register 0" hexmask.long 0x00 8.--15. 0x01 "SCR ,Serial Clock Rate" bitfld.long 0x00 7.--7. " SSE ,Synchronous Serial Port Enable" "dis,ena" bitfld.long 0x00 6.--6. " ECS ,External Clock Select" "On-chip clock,SSPEXTCLK" textline " " bitfld.long 0x00 4.--5. "FRF ,Frame Format" "Motorola SPI,TI SSP,National Microwire,res" bitfld.long 0x00 0.--3. " DSS ,Data Size Select in bit" "res,res,res,4,5,6,7,8,9,10,11,12,13,14,15,16" line.long 0x04 "SSCR1,SSP Control Register 1" bitfld.long 0x04 10.--13. "RFT ,Receive FIFO Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 6.--9. " TFT ,Transmit FIFO Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5.--5. " MWDS ,Microwire Transmit Data Size" "8 bit,16 bit" bitfld.long 0x04 4.--4. " SPH ,Motorola SPI SSPSCLK phase setting" "start 1 - end 1/2,start 1/2 - end 1" textline " " bitfld.long 0x04 3.--3. "SPO ,Motorola SPI SSPSCLK polarity setting" "inactive low,inactive high" bitfld.long 0x04 2.--2. " LBM ,Loop-Back Mode" "no,yes" bitfld.long 0x04 1.--1. " TIE ,Transmit FIFO Interrupt Enable" "dis,ena" bitfld.long 0x04 0.--0. " RIE ,Receive FIFO Interrupt Enable" "dis,ena" group asd:0x41000008++0x03 line.long 0x00 "SSSR,SSP Status Register" bitfld.long 0x00 12.--15. "RFL ,Receive FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TFL ,Transmit FIFO Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7.--7. " ROR ,Receive FIFO Overrun" "no,yes" bitfld.long 0x00 6.--6. " RFS ,Receive FIFO Service Request" "no,yes" bitfld.long 0x00 5.--5. " TFS ,Transmit FIFO Service Request" "no,yes" bitfld.long 0x00 4.--4. " BSY ,SSP Busy" "no,yes" textline " " bitfld.long 0x00 3.--3. "RNE ,Receive FIFO not empty" "empty,not empty" bitfld.long 0x00 2.--2. " TNF ,Transmit FIFO not full" "full,not full" group asd:0x4100000c++0x03 line.long 0x00 "SSITR,SSP Interrupt Test Register" bitfld.long 0x00 7.--7. "TROR ,Test Receive Fifo overun" "no,yes" bitfld.long 0x00 6.--6. "TRFS ,Test Reveive Fifo request" "no,yes" bitfld.long 0x00 5.--5. "TTFS ,Test Transmit Fifo request" "no,yes" group asd:0x41000010++0x03 hide.long 0x00 "SSDR,SSP Data Write Register / SSP Data Read Register" in tree.end ;end include file xscale/manitoba-ssp.ph ;begin include file xscale/manitoba-i2c.ph ;parameters: ; -------------------------------------------------------------------------------- ; Manitoba ; Should be ok. ; State: preliminary ; -------------------------------------------------------------------------------- tree "I2C" ; -------------------------------------------------------------------------------- group asd:0x40301680++0x03 line.long 0x00 "IBMR,I2C Bus Monitor Register" bitfld.long 0x00 1.--1. "SCLS ,SCL Pin Status" "low,high" bitfld.long 0x00 0.--0. "SDAS ,SDA Pin Status" "low,high" group asd:0x40301688++0x03 line.long 0x00 "IDBR,I2C Data Buffer Register" hexmask.long 0x00 0.--7. 0x01 "IDB ,I2C Data Buffer for I2C bus send/receive data" group asd:0x40301690++0x03 line.long 0x00 "ICR,I2C Control Register" bitfld.long 0x00 15.--15. "FM ,Fast Mode" "100 kBit/s,400 kBit/s" bitfld.long 0x00 14.--14. " UR ,Unit Reset" "no,yes" bitfld.long 0x00 13.--13. " SADIE ,Slave Address Detected Interrupt Enable" "dis,ena" bitfld.long 0x00 12.--12. " ALDIE ,Arbitration Loss Detected Interrupt Enable" "dis,ena" bitfld.long 0x00 11.--11. " SSDIE ,Slave STOP Detected Interrupt Enable" "dis,ena" textline " " bitfld.long 0x00 10.--10. "BEIE ,Bus Error Interrupt Enable" "dis,ena" bitfld.long 0x00 9.--9. " IRFIE ,IDBR Reveice Full Interrupt Enable" "dis,ena" bitfld.long 0x00 8.--8. " ITEIE ,IDBR Tranmit Empty Interrupt Enable" "dis,ena" bitfld.long 0x00 7.--7. " GCD ,General Call Disable" "ena,dis" bitfld.long 0x00 6.--6. " IUE ,I2C Unit Enable" "dis,ena" bitfld.long 0x00 5.--5. " SCLE ,SCL Enable" "dis,ena" textline " " bitfld.long 0x00 4.--4. "MA ,Master Abort" "STOP ICR bit,STOP without data" bitfld.long 0x00 3.--3. " TB ,Transfer Byte" "no,yes" bitfld.long 0x00 2.--2. " ACKNAK ,ACK/NAK Control" "ACK,NAK" bitfld.long 0x00 1.--1. " STOP ,STOP" "no,yes" bitfld.long 0x00 0.--0. " START ,START" "no,yes" group asd:0x40301698++0x03 line.long 0x00 "ISR,I2C Status Register" bitfld.long 0x00 10.--10. "BED ,Bus Error Detected" "no,yes" bitfld.long 0x00 9.--9. " SAD ,Slave Address Detected" "no,yes" bitfld.long 0x00 8.--8. " GCAD ,General Call address Detected" "no,yes" bitfld.long 0x00 7.--7. " IRF ,IDBR Reveice Full" "no,yes" bitfld.long 0x00 6.--6. " ITE ,IDBR Tranmit Empty" "no,yes" bitfld.long 0x00 5.--5. " ALD ,Arbitration Loss Detected" "no,yes" bitfld.long 0x00 4.--4. " SSD ,Slave STOP Detected" "no,yes" textline " " bitfld.long 0x00 3.--3. "IBB ,I2C Bus Busy" "no,yes" bitfld.long 0x00 2.--2. " UB ,Unit Busy" "no,yes" bitfld.long 0x00 1.--1. " ACKNAK ,ACK/NAK Status" "ACK,NAK" bitfld.long 0x00 0.--0. " RWM ,Read/Write Mode" "master transmit/slave receive,master receive/slave transmit" group asd:0x403016a0++0x03 line.long 0x00 "ISAR,I2C Slave Address Register" hexmask.long 0x00 0.--6. 0x01 "ISA ,I2C Slave Address" group asd:0x403016a8++0x03 line.long 0x00 "ICCR,I2C Clock Count Register" hexmask.long 0x00 0.--8. 0x01 "ICC ,I2C Clock Count" tree.end ;end include file xscale/manitoba-i2c.ph ; %include xscale/manitoba-dai.ph ; %include xscale/manitoba-dutycycle.ph 0x42002200 0 ; %include xscale/manitoba-dutycycle.ph 0x42002210 1 ; %include xscale/manitoba-dutycycle.ph 0x42002220 2 ; %include xscale/manitoba-sim.ph ; %include xscale/manitoba-lcd.ph ; %include xscale/manitoba-keypad.ph ; %include xscale/manitoba-msi.ph ; %include xscale/manitoba-bmi.ph ; following may be included above ;%include xscale/manitoba-boot.ph ;%include xscale/manitoba-pcmcia.ph ;%include xscale/manitoba-wd.ph ;%include xscale/manitoba-dsp.ph ;%include xscale/manitoba-bb.ph ; access to MSA register is probably not allowed! ;%include xscale/msa-bus.ph ;%include xscale/msa-gasket.ph ;%include xscale/msa-perbus.ph ;%include xscale/msa-dma.ph ;%include xscale/msa-ipc.ph ;%include xscale/msa-int.ph ;%include xscale/msa-clock.ph ;%include xscale/msa-power.ph ;%include xscale/msa-pll.ph ;%include xscale/msa-siq.ph ;%include xscale/msa-codec.ph ;%include xscale/msa-aux.ph ;%include xscale/msa-cipher.ph ;%include xscale/msa-timer.ph ;%include xscale/msa-i2s.ph ;%include xscale/msa-spi.ph ;%include xscale/msa-gsm.ph ;%include xscale/msa-viterbi.ph ;%include xscale/msa-hsl.ph